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ahmedheakl
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cass-instruct-os-v2

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int64
2
114k
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422
72.4k
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output_tokens
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z17constructQuadTreeP12QuadTreeNodei .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; @P0 EXIT ; SHF.L.U32 R7, R5, 0x2, RZ ; IMAD.MOV.U32 R2, RZ, RZ, 0x14 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R9, RZ, RZ, -0x1 ; ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R9 ; STG.E [R2.64+0x8], R9 ; STG.E [R2.64+0xc], R9 ; STG.E [R2.64+0x10], R9 ; @P0 EXIT ; IADD3 R5, R7.reuse, 0x1, RZ ; STG.E [R2.64+0x4], R7 ; IADD3 R9, R7, 0x2, RZ ; IADD3 R11, R7, 0x3, RZ ; STG.E [R2.64+0x8], R5 ; STG.E [R2.64+0xc], R9 ; STG.E [R2.64+0x10], R11 ; EXIT ; BRA 0x1a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z17constructQuadTreeP12QuadTreeNodei ; -- Begin function _Z17constructQuadTreeP12QuadTreeNodei .globl _Z17constructQuadTreeP12QuadTreeNodei .p2align 8 .type _Z17constructQuadTreeP12QuadTreeNodei,@function _Z17constructQuadTreeP12QuadTreeNodei: ; @_Z17constructQuadTreeP12QuadTreeNodei ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x1c s_load_b32 s2, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mul_i32 s15, s15, s3 s_mov_b32 s3, exec_lo v_add_nc_u32_e32 v1, s15, v0 v_cmpx_gt_i32_e64 s2, v1 s_cbranch_execz .LBB0_4 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v2, -1 :: v_dual_lshlrev_b32 v7, 2, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mov_b32_e32 v3, v2 v_mov_b32_e32 v4, v2 v_cmp_gt_i32_e32 vcc_lo, s2, v7 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[5:6], null, v1, 20, s[0:1] s_clause 0x1 global_store_b128 v[5:6], v[1:4], off global_store_b32 v[5:6], v2, off offset:16 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_4 ; %bb.2: ; %.preheader.preheader v_lshlrev_b32_e32 v0, 2, v0 s_mov_b32 s0, 0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v2, s15, 2, v0 v_add_co_u32 v0, vcc_lo, v5, 4 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v6, vcc_lo .LBB0_3: ; %.preheader ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s0, v2 s_add_i32 s0, s0, 1 s_cmp_lg_u32 s0, 4 global_store_b32 v[0:1], v3, off v_add_co_u32 v0, vcc_lo, v0, 4 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_cbranch_scc1 .LBB0_3 .LBB0_4: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z17constructQuadTreeP12QuadTreeNodei .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z17constructQuadTreeP12QuadTreeNodei, .Lfunc_end0-_Z17constructQuadTreeP12QuadTreeNodei ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 216 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z17constructQuadTreeP12QuadTreeNodei .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z17constructQuadTreeP12QuadTreeNodei.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0007001a_00000000-6_cuda_code_008760.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3635: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3635: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei .type _Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei, @function _Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei: .LFB3661: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z17constructQuadTreeP12QuadTreeNodei(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei, .-_Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei .globl _Z17constructQuadTreeP12QuadTreeNodei .type _Z17constructQuadTreeP12QuadTreeNodei, @function _Z17constructQuadTreeP12QuadTreeNodei: .LFB3662: .cfi_startproc endbr64 jmp _Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei .cfi_endproc .LFE3662: .size _Z17constructQuadTreeP12QuadTreeNodei, .-_Z17constructQuadTreeP12QuadTreeNodei .section .rodata.str1.1 .LC3: .string "Failed to allocate device memory" .LC4: .string "Kernel launch failed" .LC5: .string "Failed to synchronize device" .LC6: .string "Failed to copy memory from device to host" .LC7: .string "Node " .LC8: .string ": value = " .LC9: .string ", children = " .LC10: .string " " .LC11: .string "Failed to free device memory" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $10240, %esi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $2147483649, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi addq %rdi, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L14 movq 8(%rsp), %rdi movl $512, %esi call _Z51__device_stub__Z17constructQuadTreeP12QuadTreeNodeiP12QuadTreeNodei .L14: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi xorl %ebp, %ebp leaq .LC7(%rip), %r14 movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $10240, %edi call _Znam@PLT movq 8(%rsp), %rsi movl $2, %ecx movl $10240, %edx movq %rax, %rdi movq %rax, %rbx call cudaMemcpy@PLT leaq .LC6(%rip), %rsi movq %rbx, %r12 movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc .L16: movq %r14, %rsi leaq _ZSt4cout(%rip), %rdi movl $1, %r13d call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %esi leaq .LC10(%rip), %r15 movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC8(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl (%r12), %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC9(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L15: movl (%r12,%r13,4), %esi leaq _ZSt4cout(%rip), %rdi incq %r13 call _ZNSolsEi@PLT movq %r15, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $5, %r13 jne .L15 leaq _ZSt4cout(%rip), %rdi incl %ebp addq $20, %r12 call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT cmpl $10, %ebp jne .L16 movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC11(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq %rbx, %rdi call _ZdaPv@PLT movq 40(%rsp), %rax subq %fs:40, %rax je .L17 call __stack_chk_fail@PLT .L17: addq $56, %rsp .cfi_def_cfa_offset 56 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z17constructQuadTreeP12QuadTreeNodei" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rax, %rdi leaq _Z17constructQuadTreeP12QuadTreeNodei(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_008760.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z32__device_stub__constructQuadTreeP12QuadTreeNodei # -- Begin function _Z32__device_stub__constructQuadTreeP12QuadTreeNodei .type _Z32__device_stub__constructQuadTreeP12QuadTreeNodei,@function _Z32__device_stub__constructQuadTreeP12QuadTreeNodei: # @_Z32__device_stub__constructQuadTreeP12QuadTreeNodei .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z17constructQuadTreeP12QuadTreeNodei, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z32__device_stub__constructQuadTreeP12QuadTreeNodei, .Lfunc_end0-_Z32__device_stub__constructQuadTreeP12QuadTreeNodei .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $16, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 8(%rsp), %rdi movl $10240, %esi # imm = 0x2800 callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $4294967298, %rdi # imm = 0x100000002 leaq 254(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movq 8(%rsp), %rdi movl $512, %esi # imm = 0x200 callq _Z32__device_stub__constructQuadTreeP12QuadTreeNodei .LBB2_2: callq hipGetLastError movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $10240, %edi # imm = 0x2800 callq _Znam movq %rax, %rbx movq 8(%rsp), %rsi movl $10240, %edx # imm = 0x2800 movq %rax, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %r12 addq $4, %r12 xorl %r14d, %r14d movl $_ZSt4cout, %r13d .LBB2_3: # =>This Loop Header: Depth=1 # Child Loop BB2_4 Depth 2 movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $5, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r14d, %esi callq _ZNSolsEi movq %rax, %r15 movl $.L.str.8, %esi movl $10, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq (%r14,%r14,4), %rax movl (%rbx,%rax,4), %esi movq %r15, %rdi callq _ZNSolsEi movl $.L.str.9, %esi movl $13, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %r15d, %r15d .LBB2_4: # Parent Loop BB2_3 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r12,%r15,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str.10, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r15 cmpq $4, %r15 jne .LBB2_4 # %bb.5: # in Loop: Header=BB2_3 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %r13, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r14 addq $20, %r12 cmpq $10, %r14 jne .LBB2_3 # %bb.6: movq 8(%rsp), %rdi callq hipFree movl $.L.str.11, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi callq _ZdaPv xorl %eax, %eax addq $16, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z17constructQuadTreeP12QuadTreeNodei, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z17constructQuadTreeP12QuadTreeNodei,@object # @_Z17constructQuadTreeP12QuadTreeNodei .section .rodata,"a",@progbits .globl _Z17constructQuadTreeP12QuadTreeNodei .p2align 3, 0x0 _Z17constructQuadTreeP12QuadTreeNodei: .quad _Z32__device_stub__constructQuadTreeP12QuadTreeNodei .size _Z17constructQuadTreeP12QuadTreeNodei, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate device memory" .size .L.str.3, 33 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed" .size .L.str.4, 21 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to synchronize device" .size .L.str.5, 29 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy memory from device to host" .size .L.str.6, 42 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Node " .size .L.str.7, 6 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz ": value = " .size .L.str.8, 11 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz ", children = " .size .L.str.9, 14 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz " " .size .L.str.10, 2 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Failed to free device memory" .size .L.str.11, 29 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z17constructQuadTreeP12QuadTreeNodei" .size .L__unnamed_1, 38 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z32__device_stub__constructQuadTreeP12QuadTreeNodei .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z17constructQuadTreeP12QuadTreeNodei .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,127
4,958
113,382
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z19crankNicolsonKernelPfS_S_fff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R9, SR_CTAID.X ; ULDC.64 UR6, c[0x0][0x118] ; BSSY B0, 0x310 ; S2R R2, SR_TID.X ; IMAD R0, R9, c[0x0][0x0], R2 ; ISETP.GT.AND P0, PT, R0, 0xfff, PT ; @P0 BRA 0x300 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; ISETP.NE.OR P0, PT, R2, RZ, !P0 ; IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; LDG.E R5, [R4.64] ; @!P0 IADD3 R6, R0, -c[0x0][0x0], RZ ; @!P0 IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x168] ; @!P0 LDG.E R6, [R6.64] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; IADD3 R3, R10, -0x1, RZ ; STS [R2.X4+0x4], R5 ; @!P0 STS [RZ], R6 ; ISETP.NE.AND P0, PT, R2, R3, PT ; @P0 BRA 0x300 ; I2F.U32.RP R6, c[0x0][0x0] ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; MUFU.RCP R6, R6 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IADD3 R3, RZ, -R5, RZ ; IMAD R3, R3, c[0x0][0x0], RZ ; IMAD.HI.U32 R8, R5, R3, R4 ; IADD3 R3, R10, 0xfff, RZ ; IMAD.HI.U32 R8, R8, R3, RZ ; IMAD.MOV R10, RZ, RZ, -R8 ; IMAD R3, R10, c[0x0][0x0], R3 ; ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x0], PT ; @P0 IADD3 R3, R3, -c[0x0][0x0], RZ ; @P0 IADD3 R8, R8, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x0], PT ; @P1 IADD3 R8, R8, 0x1, RZ ; @!P2 LOP3.LUT R8, RZ, c[0x0][0x0], RZ, 0x33, !PT ; IADD3 R8, R8, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R9, R8, PT ; @P0 BRA 0x300 ; IADD3 R4, R0, c[0x0][0x0], RZ ; IMAD.WIDE.U32 R4, R4, R11, c[0x0][0x168] ; LDG.E R4, [R4.64] ; STS [0x404], R4 ; BSYNC B0 ; IADD3 R3, R0, -0x1, RZ ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GT.U32.AND P2, PT, R3, 0xffd, PT ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; BSSY B0, 0x520 ; IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; @P2 BRA 0x510 ; LDS R6, [R2.X4+0x4] ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x17c] ; BSSY B1, 0x4e0 ; LDS R7, [R2.X4] ; FMUL R12, R12, c[0x0][0x17c] ; LDS R10, [R2.X4+0x8] ; MUFU.RCP R9, R12 ; FADD R8, R6, R6 ; FADD R7, R7, -R8 ; FFMA R8, -R12, R9, 1 ; FADD R7, R7, R10 ; FFMA R8, R9, R8, R9 ; FCHK P0, R7, R12 ; FFMA R9, R7, R8, RZ ; FFMA R10, -R12, R9, R7 ; FFMA R8, R8, R10, R9 ; @!P0 BRA 0x4d0 ; MOV R8, 0x4c0 ; CALL.REL.NOINC 0xb50 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; BSYNC B1 ; FMUL R7, R8, c[0x0][0x180] ; FFMA R7, R7, c[0x0][0x178], R6 ; STG.E [R4.64], R7 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P2 EXIT ; MOV R6, c[0x0][0x17c] ; FMUL R12, R6, c[0x0][0x17c] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; MUFU.RCP R7, R12 ; FADD R6, R6, c[0x0][0x180] ; FMUL R6, R6, c[0x0][0x178] ; FCHK P0, R6, R12 ; FFMA R8, -R12, R7, 1 ; FFMA R9, R7, R8, R7 ; FFMA R7, R9, R6, RZ ; FFMA R8, -R12, R7, R6 ; FFMA R7, R9, R8, R7 ; @!P0 BRA 0x650 ; IMAD.MOV.U32 R7, RZ, RZ, R6 ; MOV R8, 0x640 ; CALL.REL.NOINC 0xb50 ; MOV R7, R10 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; FADD R6, R6, c[0x0][0x17c] ; FMUL R8, R8, c[0x0][0x178] ; FMUL R9, R6, c[0x0][0x17c] ; MUFU.RCP R6, R9 ; FCHK P0, -R8, R9 ; FFMA R11, -R9, R6, 1 ; FFMA R11, R6, R11, R6 ; FADD R6, R7, 1 ; FFMA R10, -R8, R11, RZ ; FFMA R12, -R9, R10, -R8 ; FFMA R7, R11, R12, R10 ; @!P0 BRA 0x780 ; FADD R7, -R8, -RZ ; MOV R12, R9 ; MOV R8, 0x770 ; CALL.REL.NOINC 0xb50 ; IMAD.MOV.U32 R7, RZ, RZ, R10 ; LDG.E R5, [R4.64] ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; BSSY B0, 0x8d0 ; @!P0 BRA 0x8c0 ; MUFU.RCP R9, R6 ; BSSY B1, 0x8a0 ; FCHK P0, R7, R6 ; FFMA R4, -R6, R9, 1 ; FFMA R4, R9, R4, R9 ; FFMA R9, R4, R7, RZ ; FFMA R8, -R6, R9, R7 ; FFMA R4, R4, R8, R9 ; @!P0 BRA 0x890 ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; MOV R8, 0x880 ; CALL.REL.NOINC 0xb50 ; MOV R4, R10 ; BSYNC B1 ; FFMA R6, R4, -R7, R6 ; FFMA R5, R5, -R4, R5 ; BSYNC B0 ; ULDC UR4, c[0x0][0x0] ; BSSY B0, 0xa20 ; UIADD3 UR4, UR4, -0x1, URZ ; ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; @P0 BRA 0xa10 ; MUFU.RCP R9, R6 ; BSSY B1, 0xa00 ; FCHK P0, R7, R6 ; FFMA R2, R9, -R6, 1 ; FFMA R2, R9, R2, R9 ; FFMA R9, R2, R7, RZ ; FFMA R4, R9, -R6, R7 ; FFMA R2, R2, R4, R9 ; @!P0 BRA 0x9f0 ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; MOV R8, 0x9e0 ; CALL.REL.NOINC 0xb50 ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; BSYNC B1 ; FFMA R5, R5, -R2, R5 ; BSYNC B0 ; MUFU.RCP R7, R6 ; BSSY B0, 0xb30 ; FCHK P0, R5, R6 ; FFMA R2, R7, -R6, 1 ; FFMA R8, R7, R2, R7 ; LEA R2, P1, R0, c[0x0][0x160], 0x2 ; FFMA R4, R8, R5, RZ ; LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; FFMA R7, R4, -R6, R5 ; FFMA R7, R8, R7, R4 ; @!P0 BRA 0xb20 ; MOV R7, R5 ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; MOV R8, 0xb10 ; CALL.REL.NOINC 0xb50 ; IMAD.MOV.U32 R7, RZ, RZ, R10 ; BSYNC B0 ; STG.E [R2.64], R7 ; EXIT ; SHF.R.U32.HI R11, RZ, 0x17, R12.reuse ; BSSY B2, 0x11b0 ; SHF.R.U32.HI R9, RZ, 0x17, R7 ; IMAD.MOV.U32 R13, RZ, RZ, R12 ; LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R14, R9, 0xff, RZ, 0xc0, !PT ; IADD3 R16, R11, -0x1, RZ ; IADD3 R15, R14, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; MOV R10, R7 ; ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0xd90 ; FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x1190 ; LOP3.LUT P0, RZ, R13, 0x7fffffff, R10, 0xc8, !PT ; @!P0 BRA 0x1170 ; FSETP.NEU.FTZ.AND P3, PT, |R7|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; @!P1 BRA !P3, 0x1170 ; LOP3.LUT P3, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; @P1 BRA 0x1150 ; LOP3.LUT P1, RZ, R13, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x1120 ; ISETP.GE.AND P0, PT, R15, RZ, PT ; ISETP.GE.AND P1, PT, R16, RZ, PT ; @P0 MOV R9, RZ ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; @!P0 FFMA R10, R7, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R13, R12, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R9, R9, 0x40, RZ ; LEA R12, R11, 0xc0800000, 0x17 ; BSSY B3, 0x1110 ; IADD3 R14, R14, -0x7f, RZ ; IMAD.IADD R15, R13, 0x1, -R12 ; IMAD R10, R14.reuse, -0x800000, R10 ; IADD3 R14, R14, 0x7f, -R11 ; MUFU.RCP R12, R15 ; FADD.FTZ R17, -R15, -RZ ; IADD3 R14, R14, R9, RZ ; FFMA R13, R12, R17, 1 ; FFMA R12, R12, R13, R12 ; FFMA R13, R10, R12, RZ ; FFMA R16, R17, R13, R10 ; FFMA R13, R12, R16, R13 ; FFMA R17, R17, R13, R10 ; FFMA R10, R12, R17, R13 ; SHF.R.U32.HI R11, RZ, 0x17, R10 ; LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R15, R11, 0x1, R14 ; IADD3 R9, R15, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; @!P0 BRA 0x10f0 ; ISETP.GT.AND P0, PT, R15, 0xfe, PT ; @P0 BRA 0x10c0 ; ISETP.GE.AND P0, PT, R15, 0x1, PT ; @P0 BRA 0x1100 ; ISETP.GE.AND P0, PT, R15, -0x18, PT ; LOP3.LUT R10, R10, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x1100 ; FFMA.RZ R9, R12.reuse, R17.reuse, R13.reuse ; IADD3 R14, R15.reuse, 0x20, RZ ; ISETP.NE.AND P3, PT, R15, RZ, PT ; LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R9, R12.reuse, R17.reuse, R13.reuse ; ISETP.NE.AND P1, PT, R15, RZ, PT ; FFMA.RM R12, R12, R17, R13 ; LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; IMAD.MOV R13, RZ, RZ, -R15 ; SHF.L.U32 R14, R11, R14, RZ ; FSETP.NEU.FTZ.AND P0, PT, R9, R12, PT ; SEL R12, R13, RZ, P3 ; ISETP.NE.AND P1, PT, R14, RZ, P1 ; SHF.R.U32.HI R12, RZ, R12, R11 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R14, RZ, 0x1, R12 ; SEL R9, RZ, 0x1, !P0 ; LOP3.LUT R9, R9, 0x1, R14, 0xf8, !PT ; LOP3.LUT R9, R9, R12, RZ, 0xc0, !PT ; IADD3 R9, R14, R9, RZ ; LOP3.LUT R10, R9, R10, RZ, 0xfc, !PT ; BRA 0x1100 ; LOP3.LUT R10, R10, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R10, R10, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1100 ; IMAD R10, R14, 0x800000, R10 ; BSYNC B3 ; BRA 0x11a0 ; LOP3.LUT R10, R13, 0x80000000, R10, 0x48, !PT ; LOP3.LUT R10, R10, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x11a0 ; LOP3.LUT R10, R13, 0x80000000, R10, 0x48, !PT ; BRA 0x11a0 ; MUFU.RSQ R10, -QNAN ; BRA 0x11a0 ; FADD.FTZ R10, R7, R12 ; BSYNC B2 ; HFMA2.MMA R9, -RZ, RZ, 0, 0 ; RET.REL.NODEC R8 0x0 ; BRA 0x11d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19crankNicolsonKernelPfS_S_fff ; -- Begin function _Z19crankNicolsonKernelPfS_S_fff .globl _Z19crankNicolsonKernelPfS_S_fff .p2align 8 .type _Z19crankNicolsonKernelPfS_S_fff,@function _Z19crankNicolsonKernelPfS_S_fff: ; @_Z19crankNicolsonKernelPfS_S_fff ; %bb.0: s_clause 0x2 s_load_b32 s8, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_lshlrev_b32_e32 v4, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s12, s8, 0xffff s_mov_b32 s8, exec_lo v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e32 0x1000, v1 s_cbranch_execz .LBB0_6 ; %bb.1: v_ashrrev_i32_e32 v2, 31, v1 s_cmp_lg_u32 s15, 0 s_cselect_b32 s9, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v0 global_load_b32 v2, v[2:3], off s_and_b32 s10, vcc_lo, s9 s_waitcnt vmcnt(0) ds_store_b32 v4, v2 offset:4 s_and_saveexec_b32 s9, s10 s_cbranch_execz .LBB0_3 ; %bb.2: v_subrev_nc_u32_e32 v2, s12, v1 v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[2:3] v_add_co_u32 v5, vcc_lo, s6, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo global_load_b32 v2, v[5:6], off s_waitcnt vmcnt(0) ds_store_b32 v3, v2 .LBB0_3: s_or_b32 exec_lo, exec_lo, s9 s_add_i32 s9, s12, -1 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_eq_u32_e32 vcc_lo, s9, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_6 ; %bb.4: v_cvt_f32_u32_e32 v2, s12 s_add_i32 s9, s12, 0xfff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s9, s9, 0xffff v_cvt_f32_u32_e32 v5, s9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v3, v2 s_waitcnt_depctr 0xfff v_mul_f32_e32 v3, v5, v3 v_trunc_f32_e32 v3, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v5, -v3, v2, v5 v_cvt_u32_f32_e32 v3, v3 v_cmp_ge_f32_e64 s9, |v5|, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_readfirstlane_b32 s10, v3 s_cmp_lg_u32 s9, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_addc_u32 s9, s10, 0 s_and_b32 s9, s9, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s9, s9, -1 s_cmp_ge_u32 s15, s9 s_cbranch_scc1 .LBB0_6 ; %bb.5: v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s12, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[2:3] v_add_co_u32 v5, vcc_lo, s6, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo global_load_b32 v2, v[5:6], off s_waitcnt vmcnt(0) ds_store_b32 v3, v2 offset:1028 .LBB0_6: ; %Flow84 s_or_b32 exec_lo, exec_lo, s8 s_load_b128 s[8:11], s[0:1], 0x18 v_add_nc_u32_e32 v2, -1, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmp_gt_u32_e64 s0, 0xffe, v2 v_mul_f32_e64 v3, s9, s9 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_8 ; %bb.7: ds_load_2addr_b32 v[5:6], v4 offset1:1 ds_load_b32 v2, v4 offset:8 s_waitcnt lgkmcnt(1) v_fma_f32 v4, -2.0, v6, v5 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v2, v2, v4 v_div_scale_f32 v4, null, v3, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v5, v4 s_waitcnt_depctr 0xfff v_fma_f32 v7, -v4, v5, 1.0 v_fmac_f32_e32 v5, v7, v5 v_div_scale_f32 v8, vcc_lo, v2, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v7, v8, v5 v_fma_f32 v9, -v4, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v7, v9, v5 v_fma_f32 v4, -v4, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v4, v4, v5, v7 v_div_fixup_f32 v4, v4, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v2, 0 :: v_dual_mul_f32 v7, s10, v4 v_lshlrev_b64 v[4:5], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v6, s8, v7 v_add_co_u32 v4, vcc_lo, s2, v4 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo global_store_b32 v[4:5], v6, off .LBB0_8: s_or_b32 exec_lo, exec_lo, s1 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_14 ; %bb.9: v_mov_b32_e32 v2, 0 v_add_f32_e64 v6, s9, s9 v_mul_f32_e64 v8, -s10, s8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v4, vcc_lo, s2, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo global_load_b32 v4, v[4:5], off v_add_f32_e64 v5, s10, s10 v_mul_f32_e32 v5, s8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f32 v7, null, v3, v3, v5 v_rcp_f32_e32 v9, v7 s_waitcnt_depctr 0xfff v_fma_f32 v12, -v7, v9, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mul_f32 v6, s9, v6 :: v_dual_fmac_f32 v9, v12, v9 v_div_scale_f32 v10, null, v6, v6, v8 v_div_scale_f32 v12, vcc_lo, v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v11, v10 s_waitcnt_depctr 0xfff v_fma_f32 v13, -v10, v11, 1.0 v_dual_mul_f32 v14, v12, v9 :: v_dual_fmac_f32 v11, v13, v11 v_div_scale_f32 v13, s0, v8, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v15, -v7, v14, v12 v_mul_f32_e32 v16, v13, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v14, v15, v9 v_fma_f32 v15, -v10, v16, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v7, -v7, v14, v12 v_fmac_f32_e32 v16, v15, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f32 v7, v7, v9, v14 s_mov_b32 vcc_lo, s0 s_mov_b32 s0, exec_lo v_fma_f32 v9, -v10, v16, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f32 v3, v7, v3, v5 v_div_fmas_f32 v5, v9, v11, v16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v3, 1.0, v3 v_div_fixup_f32 v5, v5, v6, v8 v_cmpx_ne_u32_e32 0, v0 s_cbranch_execz .LBB0_11 ; %bb.10: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v6, null, v3, v3, v5 v_div_scale_f32 v9, vcc_lo, v5, v3, v5 v_rcp_f32_e32 v7, v6 s_waitcnt_depctr 0xfff v_fma_f32 v8, -v6, v7, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v7, v8, v7 v_mul_f32_e32 v8, v9, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v10, -v6, v8, v9 v_fmac_f32_e32 v8, v10, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v6, -v6, v8, v9 v_div_fmas_f32 v6, v6, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f32 v6, v6, v3, v5 v_fma_f32 v3, -v5, v6, v3 s_waitcnt vmcnt(0) v_fma_f32 v4, -v6, v4, v4 .LBB0_11: s_or_b32 exec_lo, exec_lo, s0 s_add_i32 s12, s12, -1 s_mov_b32 s0, exec_lo v_cmpx_gt_u32_e64 s12, v0 s_cbranch_execz .LBB0_13 ; %bb.12: v_div_scale_f32 v0, null, v3, v3, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v6, v0 s_waitcnt_depctr 0xfff v_fma_f32 v7, -v0, v6, 1.0 v_fmac_f32_e32 v6, v7, v6 v_div_scale_f32 v7, vcc_lo, v5, v3, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v8, v7, v6 v_fma_f32 v9, -v0, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v8, v9, v6 v_fma_f32 v0, -v0, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v0, v0, v6, v8 v_div_fixup_f32 v0, v0, v3, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_fma_f32 v4, -v4, v0, v4 .LBB0_13: s_or_b32 exec_lo, exec_lo, s0 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v0, null, v3, v3, v4 v_div_scale_f32 v7, vcc_lo, v4, v3, v4 v_rcp_f32_e32 v5, v0 s_waitcnt_depctr 0xfff v_fma_f32 v6, -v0, v5, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v5, v6, v5 v_mul_f32_e32 v6, v7, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v8, -v0, v6, v7 v_fmac_f32_e32 v6, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v0, -v0, v6, v7 v_div_fmas_f32 v0, v0, v5, v6 s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f32 v3, v0, v3, v4 v_add_co_u32 v0, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo global_store_b32 v[0:1], v3, off .LBB0_14: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19crankNicolsonKernelPfS_S_fff .amdhsa_group_segment_fixed_size 1032 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 17 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19crankNicolsonKernelPfS_S_fff, .Lfunc_end0-_Z19crankNicolsonKernelPfS_S_fff ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1340 ; NumSgprs: 18 ; NumVgprs: 17 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 1032 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 17 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 1032 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19crankNicolsonKernelPfS_S_fff .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z19crankNicolsonKernelPfS_S_fff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 17 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00053779_00000000-6_cuda_code_037231.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff .type _Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff, @function _Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff: .LFB3660: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) leaq 64(%rsp), %rcx leaq 72(%rsp), %rdi movq %rsi, 32(%rsp) leaq 84(%rsp), %rsi movq %rdx, 24(%rsp) leaq 56(%rsp), %rdx movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movss %xmm2, 12(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 80(%rsp) movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) movq %rax, 84(%rsp) movl $1, 92(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 64(%rsp) .cfi_def_cfa_offset 200 leaq _Z19crankNicolsonKernelPfS_S_fff(%rip), %rdi pushq 64(%rsp) .cfi_def_cfa_offset 208 movq 100(%rsp), %rcx movl 108(%rsp), %r8d movq 88(%rsp), %rsi movl 96(%rsp), %edx leaq 136(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 200 popq %rdx .cfi_def_cfa_offset 192 .L2: movq 168(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $184, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff, .-_Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff .globl _Z19crankNicolsonKernelPfS_S_fff .type _Z19crankNicolsonKernelPfS_S_fff, @function _Z19crankNicolsonKernelPfS_S_fff: .LFB3661: .cfi_startproc endbr64 jmp _Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff .cfi_endproc .LFE3661: .size _Z19crankNicolsonKernelPfS_S_fff, .-_Z19crankNicolsonKernelPfS_S_fff .section .rodata.str1.1,"aMS",@progbits,1 .LC4: .string "CUDA error: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $16384, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 xorl %ebx, %ebx subq $72, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call malloc@PLT movl $16384, %edi movq %rax, %r13 call malloc@PLT movl $16384, %edi movq %rax, %rbp call malloc@PLT movq %rax, %r12 .L9: cvtsi2sdl %ebx, %xmm0 mulsd .LC0(%rip), %xmm0 divsd .LC1(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 call sinf@PLT movss %xmm0, 0(%r13,%rbx,4) incq %rbx cmpq $4096, %rbx jne .L9 xorl %eax, %eax movq %rbp, %rdi movq %rbx, %rcx movl $16384, %esi rep stosl movq %r12, %rdi movq %rbx, %rcx rep stosl leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $16384, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $16384, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $16384, %edx call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $268435457, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $4, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L10 movss .LC2(%rip), %xmm2 movss .LC3(%rip), %xmm1 movq 24(%rsp), %rdx movq 8(%rsp), %rsi movq 16(%rsp), %rdi movaps %xmm2, %xmm0 call _Z46__device_stub__Z19crankNicolsonKernelPfS_S_fffPfS_S_fff .L10: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L11 leaq .LC4(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L11: movq 16(%rsp), %rsi movl $2, %ecx movl $16384, %edx movq %rbp, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %r12, %rdi call free@PLT xorl %eax, %eax .L8: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L13 call __stack_chk_fail@PLT .L13: addq $72, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z19crankNicolsonKernelPfS_S_fff" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC5(%rip), %rdx movq %rax, %rdi leaq _Z19crankNicolsonKernelPfS_S_fff(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 1413754136 .long 1075388923 .align 8 .LC1: .long 0 .long 1085275648 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1008981770 .align 4 .LC3: .long 964691969 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_037231.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z34__device_stub__crankNicolsonKernelPfS_S_fff # -- Begin function _Z34__device_stub__crankNicolsonKernelPfS_S_fff .type _Z34__device_stub__crankNicolsonKernelPfS_S_fff,@function _Z34__device_stub__crankNicolsonKernelPfS_S_fff: # @_Z34__device_stub__crankNicolsonKernelPfS_S_fff .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rcx movq %rsi, (%rcx) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 20(%rsp), %rdx movss %xmm0, (%rdx) leaq 16(%rsp), %rdi movss %xmm1, (%rdi) leaq 12(%rsp), %r8 movss %xmm2, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rdi, 32(%rbx) movq %r8, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 32(%rsp), %r12 leaq 24(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z19crankNicolsonKernelPfS_S_fff, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z34__device_stub__crankNicolsonKernelPfS_S_fff, .Lfunc_end0-_Z34__device_stub__crankNicolsonKernelPfS_S_fff .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI1_0: .quad 0x401921fb54442d18 # double 6.2831853071795862 .LCPI1_1: .quad 0x40affe0000000000 # double 4095 .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 .LCPI1_2: .long 0x39800801 # float 2.44200259E-4 .LCPI1_3: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %rbx movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r14 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r15 xorl %r12d, %r12d xorl %r13d, %r13d .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2sd %r13d, %xmm0 mulsd .LCPI1_0(%rip), %xmm0 divsd .LCPI1_1(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 callq sinf movss %xmm0, (%rbx,%r13,4) movl %r12d, (%r14,%r13,4) movl %r12d, (%r15,%r13,4) incq %r13 cmpq $4096, %r13 # imm = 0x1000 jne .LBB1_1 # %bb.2: leaq 16(%rsp), %r12 movl $16384, %esi # imm = 0x4000 movq %r12, %rdi callq hipMalloc movq %rsp, %r13 movl $16384, %esi # imm = 0x4000 movq %r13, %rdi callq hipMalloc leaq 8(%rsp), %rbp movl $16384, %esi # imm = 0x4000 movq %rbp, %rdi callq hipMalloc movq (%r12), %rdi movl $16384, %edx # imm = 0x4000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq (%r13), %rdi movl $16384, %edx # imm = 0x4000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq (%rbp), %rdi movl $16384, %edx # imm = 0x4000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967312, %rdi # imm = 0x100000010 leaq 240(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq (%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movss .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero movss .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movaps %xmm0, %xmm2 callq _Z34__device_stub__crankNicolsonKernelPfS_S_fff .LBB1_4: callq hipGetLastError testl %eax, %eax je .LBB1_9 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_6 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_8 .LBB1_9: movq (%rsp), %rsi movl $16384, %edx # imm = 0x4000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax jmp .LBB1_10 .LBB1_6: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_10: addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19crankNicolsonKernelPfS_S_fff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z19crankNicolsonKernelPfS_S_fff,@object # @_Z19crankNicolsonKernelPfS_S_fff .section .rodata,"a",@progbits .globl _Z19crankNicolsonKernelPfS_S_fff .p2align 3, 0x0 _Z19crankNicolsonKernelPfS_S_fff: .quad _Z34__device_stub__crankNicolsonKernelPfS_S_fff .size _Z19crankNicolsonKernelPfS_S_fff, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z19crankNicolsonKernelPfS_S_fff" .size .L__unnamed_1, 33 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__crankNicolsonKernelPfS_S_fff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z19crankNicolsonKernelPfS_S_fff .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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4,665
113,384
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z11lbfgsUpdatePfS_S_S_S_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; ULDC.64 UR12, c[0x0][0x118] ; UMOV UR9, 0x1 ; ULDC.64 UR6, c[0x2][0x0] ; ULDC.64 UR10, c[0x0][0x180] ; IMAD.WIDE R6, R0, R15, c[0x0][0x168] ; IMAD.WIDE R2, R0.reuse, R15.reuse, c[0x0][0x160] ; LDG.E R9, [R6.64] ; LDG.E R11, [R2.64] ; UIMAD.WIDE.U32 UR4, UR9, UR10, UR6 ; ISETP.GT.AND P2, PT, R0.reuse, 0xff, PT ; UIMAD UR8, UR9, UR11, URZ ; IMAD.WIDE R6, R0, R15, c[0x0][0x178] ; UIADD3 UR8, UR5, UR8, URZ ; MOV R4, UR4 ; ULDC.64 UR10, c[0x0][0x188] ; IMAD.U32 R5, RZ, RZ, UR5 ; MOV R5, UR8 ; STS [R0.X4], R9 ; STS [R0.X4+0x400], R11 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P2 LDG.E R13, [R4.64] ; @!P2 LDG.E R8, [R6.64+0x1000] ; UIMAD.WIDE.U32 UR4, UR9, UR10, UR6 ; UIMAD UR6, UR9, UR11, URZ ; @!P2 LDS R12, [R0.X4] ; UIADD3 UR6, UR5, UR6, URZ ; MOV R11, UR5 ; IMAD.U32 R10, RZ, RZ, UR4 ; IMAD.U32 R11, RZ, RZ, UR6 ; @!P2 FMUL R13, R12, R13 ; @!P2 FMUL R13, R13, R8 ; IMAD.WIDE R8, R0, R15, c[0x0][0x170] ; @!P2 STG.E [R10.64], R13 ; @!P2 LDG.E R14, [R8.64+0x1000] ; BSSY B0, 0x340 ; @!P2 FFMA R15, -R13, R14, R12 ; @!P2 STS [R0.X4], R15 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P2 BRA 0x330 ; LDG.E R13, [R4.64+-0x4] ; LDG.E R14, [R6.64+0xc00] ; LDS R12, [R0.X4] ; FMUL R13, R12, R13 ; FMUL R13, R13, R14 ; STG.E [R10.64+-0x4], R13 ; LDG.E R14, [R8.64+0xc00] ; FFMA R15, -R13, R14, R12 ; STS [R0.X4], R15 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x410 ; @P2 BRA 0x400 ; LDG.E R13, [R4.64+-0x8] ; LDG.E R14, [R6.64+0x800] ; LDS R12, [R0.X4] ; FMUL R13, R12, R13 ; FMUL R13, R13, R14 ; STG.E [R10.64+-0x8], R13 ; LDG.E R14, [R8.64+0x800] ; FFMA R15, -R13, R14, R12 ; STS [R0.X4], R15 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x4e0 ; @P2 BRA 0x4d0 ; LDG.E R13, [R4.64+-0xc] ; LDG.E R14, [R6.64+0x400] ; LDS R12, [R0.X4] ; FMUL R13, R12, R13 ; FMUL R13, R13, R14 ; STG.E [R10.64+-0xc], R13 ; LDG.E R14, [R8.64+0x400] ; FFMA R15, -R13, R14, R12 ; STS [R0.X4], R15 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x5b0 ; @P2 BRA 0x5a0 ; LDG.E R12, [R4.64+-0x10] ; LDG.E R15, [R6.64] ; LDS R13, [R0.X4] ; FMUL R12, R12, R13 ; FMUL R12, R12, R15 ; STG.E [R10.64+-0x10], R12 ; LDG.E R14, [R8.64] ; FFMA R13, -R12, R14, R13 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x730 ; @P2 BRA 0x720 ; LDG.E R12, [R6.64+0x1000] ; BSSY B1, 0x6f0 ; LDS R13, [R0.X4+0x400] ; FMUL R15, R12, R12 ; FMUL R16, R12, R13 ; MUFU.RCP R14, R15 ; FCHK P0, R16, R15 ; FFMA R17, -R15, R14, 1 ; FFMA R17, R14, R17, R14 ; FFMA R12, R16, R17, RZ ; FFMA R13, -R15, R12, R16 ; FFMA R12, R17, R13, R12 ; @!P0 BRA 0x6e0 ; MOV R12, 0x6d0 ; CALL.REL.NOINC 0xbb0 ; MOV R12, R15 ; BSYNC B1 ; LDS R13, [R0.X4] ; FMUL R13, R13, R12 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x800 ; @P2 BRA 0x7f0 ; LDG.E R12, [R4.64+-0x10] ; LDG.E R15, [R8.64] ; LDG.E R14, [R10.64+-0x10] ; LDG.E R16, [R6.64] ; LDS R13, [R0.X4] ; FMUL R12, R12, R13 ; FFMA R12, -R12, R15, R14 ; FFMA R13, R12, R16, R13 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x8d0 ; @P2 BRA 0x8c0 ; LDG.E R13, [R4.64+-0xc] ; LDG.E R14, [R8.64+0x400] ; LDG.E R15, [R10.64+-0xc] ; LDG.E R16, [R6.64+0x400] ; LDS R12, [R0.X4] ; FMUL R13, R12, R13 ; FFMA R13, -R13, R14, R15 ; FFMA R13, R13, R16, R12 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x9a0 ; @P2 BRA 0x990 ; LDG.E R13, [R4.64+-0x8] ; LDG.E R14, [R8.64+0x800] ; LDG.E R15, [R10.64+-0x8] ; LDG.E R16, [R6.64+0x800] ; LDS R12, [R0.X4] ; FMUL R13, R12, R13 ; FFMA R13, -R13, R14, R15 ; FFMA R13, R13, R16, R12 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xa70 ; @P2 BRA 0xa60 ; LDG.E R13, [R4.64+-0x4] ; LDG.E R14, [R8.64+0xc00] ; LDG.E R15, [R10.64+-0x4] ; LDG.E R16, [R6.64+0xc00] ; LDS R12, [R0.X4] ; FMUL R13, R12, R13 ; FFMA R13, -R13, R14, R15 ; FFMA R13, R13, R16, R12 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xb40 ; @P2 BRA 0xb30 ; LDG.E R5, [R4.64] ; LDG.E R8, [R8.64+0x1000] ; LDG.E R10, [R10.64] ; LDG.E R6, [R6.64+0x1000] ; LDS R12, [R0.X4] ; FMUL R13, R12, R5 ; FFMA R13, -R13, R8, R10 ; FFMA R13, R13, R6, R12 ; STS [R0.X4], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P2 EXIT ; LDG.E R5, [R2.64] ; LDS R0, [R0.X4] ; FADD R5, -R0, R5 ; STG.E [R2.64], R5 ; EXIT ; SHF.R.U32.HI R13, RZ, 0x17, R15 ; BSSY B2, 0x1210 ; SHF.R.U32.HI R14, RZ, 0x17, R16.reuse ; IMAD.MOV.U32 R18, RZ, RZ, R16 ; LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R17, R14, 0xff, RZ, 0xc0, !PT ; IADD3 R21, R13, -0x1, RZ ; IADD3 R20, R17, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R21, 0xfd, PT ; MOV R19, R15 ; ISETP.GT.U32.OR P0, PT, R20, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; @!P0 BRA 0xdf0 ; FSETP.GTU.FTZ.AND P0, PT, |R16|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R15|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x11f0 ; LOP3.LUT P0, RZ, R19, 0x7fffffff, R18, 0xc8, !PT ; @!P0 BRA 0x11d0 ; FSETP.NEU.FTZ.AND P3, PT, |R16|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R15|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R16|, +INF , PT ; @!P1 BRA !P3, 0x11d0 ; LOP3.LUT P3, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; @P1 BRA 0x11b0 ; LOP3.LUT P1, RZ, R19, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x1180 ; ISETP.GE.AND P0, PT, R20, RZ, PT ; ISETP.GE.AND P1, PT, R21, RZ, PT ; @P0 MOV R14, RZ ; @!P0 IMAD.MOV.U32 R14, RZ, RZ, -0x40 ; @!P0 FFMA R18, R16, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R19, R15, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R14, R14, 0x40, RZ ; LEA R16, R13, 0xc0800000, 0x17 ; BSSY B3, 0x1170 ; IADD3 R20, -R16, R19, RZ ; IADD3 R19, R17, -0x7f, RZ ; MUFU.RCP R16, R20 ; FADD.FTZ R15, -R20, -RZ ; IMAD R18, R19.reuse, -0x800000, R18 ; IADD3 R19, R19, 0x7f, -R13 ; IMAD.IADD R14, R19, 0x1, R14 ; FFMA R17, R16, R15, 1 ; FFMA R16, R16, R17, R16 ; FFMA R17, R18, R16, RZ ; FFMA R21, R15, R17, R18 ; FFMA R17, R16, R21, R17 ; FFMA R18, R15, R17, R18 ; FFMA R15, R16, R18, R17 ; SHF.R.U32.HI R13, RZ, 0x17, R15 ; LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; IADD3 R19, R13, R14, RZ ; IADD3 R13, R19, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R13, 0xfe, PT ; @!P0 BRA 0x1150 ; ISETP.GT.AND P0, PT, R19, 0xfe, PT ; @P0 BRA 0x1120 ; ISETP.GE.AND P0, PT, R19, 0x1, PT ; @P0 BRA 0x1160 ; ISETP.GE.AND P0, PT, R19, -0x18, PT ; LOP3.LUT R15, R15, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x1160 ; FFMA.RZ R13, R16.reuse, R18.reuse, R17.reuse ; ISETP.NE.AND P3, PT, R19.reuse, RZ, PT ; ISETP.NE.AND P1, PT, R19, RZ, PT ; LOP3.LUT R14, R13, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R13, R16.reuse, R18.reuse, R17.reuse ; FFMA.RM R16, R16, R18, R17 ; IADD3 R17, R19, 0x20, RZ ; LOP3.LUT R14, R14, 0x800000, RZ, 0xfc, !PT ; IADD3 R18, -R19, RZ, RZ ; SHF.L.U32 R17, R14, R17, RZ ; FSETP.NEU.FTZ.AND P0, PT, R13, R16, PT ; SEL R13, R18, RZ, P3 ; ISETP.NE.AND P1, PT, R17, RZ, P1 ; SHF.R.U32.HI R13, RZ, R13, R14 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R17, RZ, 0x1, R13 ; SEL R14, RZ, 0x1, !P0 ; LOP3.LUT R14, R14, 0x1, R17, 0xf8, !PT ; LOP3.LUT R14, R14, R13, RZ, 0xc0, !PT ; IMAD.IADD R14, R17, 0x1, R14 ; LOP3.LUT R15, R14, R15, RZ, 0xfc, !PT ; BRA 0x1160 ; LOP3.LUT R15, R15, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R15, R15, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1160 ; LEA R15, R14, R15, 0x17 ; BSYNC B3 ; BRA 0x1200 ; LOP3.LUT R15, R19, 0x80000000, R18, 0x48, !PT ; LOP3.LUT R15, R15, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1200 ; LOP3.LUT R15, R19, 0x80000000, R18, 0x48, !PT ; BRA 0x1200 ; MUFU.RSQ R15, -QNAN ; BRA 0x1200 ; FADD.FTZ R15, R16, R15 ; BSYNC B2 ; HFMA2.MMA R13, -RZ, RZ, 0, 0 ; RET.REL.NODEC R12 0x0 ; BRA 0x1230; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z15computeGradientPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R4, 0xff, PT ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; LDG.E R2, [R2.64] ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; FADD R7, R2, R2 ; STG.E [R4.64], R7 ; EXIT ; BRA 0xe0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15computeGradientPfS_ ; -- Begin function _Z15computeGradientPfS_ .globl _Z15computeGradientPfS_ .p2align 8 .type _Z15computeGradientPfS_,@function _Z15computeGradientPfS_: ; @_Z15computeGradientPfS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x1c s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x100, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[0:3], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15computeGradientPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15computeGradientPfS_, .Lfunc_end0-_Z15computeGradientPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 140 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z11lbfgsUpdatePfS_S_S_S_S_ ; -- Begin function _Z11lbfgsUpdatePfS_S_S_S_S_ .globl _Z11lbfgsUpdatePfS_S_S_S_S_ .p2align 8 .type _Z11lbfgsUpdatePfS_S_S_S_S_,@function _Z11lbfgsUpdatePfS_S_S_S_S_: ; @_Z11lbfgsUpdatePfS_S_S_S_S_ ; %bb.0: s_load_b256 s[4:11], s[0:1], 0x0 v_dual_mov_b32 v9, 0 :: v_dual_lshlrev_b32 v8, 2, v0 s_load_b128 s[12:15], s[0:1], 0x20 v_mov_b32_e32 v10, -5 v_cmp_gt_u32_e64 s0, 0x100, v0 s_delay_alu instid0(VALU_DEP_3) v_add_nc_u32_e32 v7, 0, v8 v_or_b32_e32 v5, 0x1000, v8 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v11, v8, s[6:7] global_load_b32 v12, v8, s[4:5] v_add_co_u32 v1, s1, s4, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v2, null, s5, 0, s1 v_add_co_u32 v3, s1, s10, v5 v_add_co_ci_u32_e64 v4, null, s11, 0, s1 v_add_co_u32 v5, s1, s8, v5 s_add_u32 s2, s12, 16 v_add_co_ci_u32_e64 v6, null, s9, 0, s1 s_addc_u32 s3, s13, 0 s_add_u32 s4, s14, 16 s_addc_u32 s5, s15, 0 s_waitcnt vmcnt(0) ds_store_2addr_stride64_b32 v7, v11, v12 offset1:4 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB1_1: ; =>This Inner Loop Header: Depth=1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB1_3 ; %bb.2: ; in Loop: Header=BB1_1 Depth=1 global_load_b32 v11, v9, s[2:3] global_load_b32 v12, v[3:4], off ds_load_b32 v13, v7 s_waitcnt vmcnt(1) lgkmcnt(0) v_mul_f32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f32_e32 v11, v11, v12 global_store_b32 v9, v11, s[4:5] global_load_b32 v12, v[5:6], off s_waitcnt vmcnt(0) v_fma_f32 v11, -v11, v12, v13 ds_store_b32 v7, v11 .LBB1_3: ; in Loop: Header=BB1_1 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v3, vcc_lo, 0xfffffc00, v3 v_add_co_ci_u32_e32 v4, vcc_lo, -1, v4, vcc_lo v_add_co_u32 v5, vcc_lo, 0xfffffc00, v5 v_add_co_u32 v10, s1, v10, 1 s_add_u32 s2, s2, -4 v_add_co_ci_u32_e32 v6, vcc_lo, -1, v6, vcc_lo s_addc_u32 s3, s3, -1 s_add_u32 s4, s4, -4 s_addc_u32 s5, s5, -1 s_and_b32 vcc_lo, exec_lo, s1 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_vccz .LBB1_1 ; %bb.4: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB1_6 ; %bb.5: v_lshl_or_b32 v0, v0, 2, 0x1000 ds_load_2addr_stride64_b32 v[3:4], v7 offset1:4 global_load_b32 v0, v0, s[10:11] s_waitcnt vmcnt(0) lgkmcnt(0) v_mul_f32_e32 v4, v4, v0 v_mul_f32_e32 v0, v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f32 v5, null, v0, v0, v4 v_rcp_f32_e32 v6, v5 s_waitcnt_depctr 0xfff v_fma_f32 v9, -v5, v6, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v9, v6 v_div_scale_f32 v9, vcc_lo, v4, v0, v4 v_mul_f32_e32 v10, v9, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v11, -v5, v10, v9 v_fmac_f32_e32 v10, v11, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v5, -v5, v10, v9 v_div_fmas_f32 v5, v5, v6, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f32 v0, v5, v0, v4 v_mul_f32_e32 v0, v3, v0 ds_store_b32 v7, v0 .LBB1_6: s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v3, s1, s8, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v4, null, s9, 0, s1 v_add_co_u32 v5, s1, s10, v8 v_add_co_ci_u32_e64 v6, null, s11, 0, s1 v_mov_b32_e32 v0, 0 s_mov_b64 s[2:3], 0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB1_7: ; =>This Inner Loop Header: Depth=1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB1_9 ; %bb.8: ; in Loop: Header=BB1_7 Depth=1 s_add_u32 s4, s12, s2 s_addc_u32 s5, s13, s3 global_load_b32 v8, v0, s[4:5] s_add_u32 s4, s14, s2 s_addc_u32 s5, s15, s3 global_load_b32 v9, v[3:4], off global_load_b32 v10, v0, s[4:5] global_load_b32 v11, v[5:6], off ds_load_b32 v12, v7 s_waitcnt vmcnt(3) lgkmcnt(0) v_mul_f32_e32 v8, v8, v12 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f32 v8, -v8, v9, v10 s_waitcnt vmcnt(0) v_fmac_f32_e32 v12, v8, v11 ds_store_b32 v7, v12 .LBB1_9: ; in Loop: Header=BB1_7 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v3, vcc_lo, 0x400, v3 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo v_add_co_u32 v5, vcc_lo, 0x400, v5 v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmp_eq_u32 s2, 20 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB1_7 ; %bb.10: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB1_12 ; %bb.11: global_load_b32 v0, v[1:2], off ds_load_b32 v3, v7 s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_f32_e32 v0, v0, v3 global_store_b32 v[1:2], v0, off .LBB1_12: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11lbfgsUpdatePfS_S_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 48 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z11lbfgsUpdatePfS_S_S_S_S_, .Lfunc_end1-_Z11lbfgsUpdatePfS_S_S_S_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 796 ; NumSgprs: 18 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15computeGradientPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15computeGradientPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 48 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11lbfgsUpdatePfS_S_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11lbfgsUpdatePfS_S_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0001bf2f_00000000-6_cuda_code_055531.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3852: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3852: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z37__device_stub__Z15computeGradientPfS_PfS_ .type _Z37__device_stub__Z15computeGradientPfS_PfS_, @function _Z37__device_stub__Z15computeGradientPfS_PfS_: .LFB3874: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z15computeGradientPfS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L2: movq 104(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3874: .size _Z37__device_stub__Z15computeGradientPfS_PfS_, .-_Z37__device_stub__Z15computeGradientPfS_PfS_ .globl _Z15computeGradientPfS_ .type _Z15computeGradientPfS_, @function _Z15computeGradientPfS_: .LFB3875: .cfi_startproc endbr64 jmp _Z37__device_stub__Z15computeGradientPfS_PfS_ .cfi_endproc .LFE3875: .size _Z15computeGradientPfS_, .-_Z15computeGradientPfS_ .globl _Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_ .type _Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_, @function _Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_: .LFB3876: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) leaq 72(%rsp), %rdi movq %rsi, 32(%rsp) leaq 84(%rsp), %rsi movq %rdx, 24(%rsp) leaq 56(%rsp), %rdx movq %rcx, 16(%rsp) leaq 64(%rsp), %rcx movq %r8, 8(%rsp) movq %r9, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 80(%rsp) movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movq %rsp, %rax movq %rax, 160(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) movq %rax, 84(%rsp) movl $1, 92(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 64(%rsp) .cfi_def_cfa_offset 200 leaq _Z11lbfgsUpdatePfS_S_S_S_S_(%rip), %rdi pushq 64(%rsp) .cfi_def_cfa_offset 208 movq 100(%rsp), %rcx movl 108(%rsp), %r8d movq 88(%rsp), %rsi movl 96(%rsp), %edx leaq 136(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 200 popq %rdx .cfi_def_cfa_offset 192 .L8: movq 168(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $184, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3876: .size _Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_, .-_Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_ .globl _Z11lbfgsUpdatePfS_S_S_S_S_ .type _Z11lbfgsUpdatePfS_S_S_S_S_, @function _Z11lbfgsUpdatePfS_S_S_S_S_: .LFB3877: .cfi_startproc endbr64 jmp _Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_ .cfi_endproc .LFE3877: .size _Z11lbfgsUpdatePfS_S_S_S_S_, .-_Z11lbfgsUpdatePfS_S_S_S_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Error in computeGradient: " .LC2: .string "Error in lbfgsUpdate: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3849: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $1024, %edi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax call _Znam@PLT movl $5120, %edi movq %rax, %r14 call _Znam@PLT movl $5120, %edi movq %rax, %r13 call _Znam@PLT movl $20, %edi movq %rax, %r12 call _Znam@PLT movl $20, %edi movq %rax, %rbp call _Znam@PLT movss .LC0(%rip), %xmm0 movq %rax, %rbx xorl %eax, %eax .L14: movss %xmm0, (%r14,%rax,4) incq %rax cmpq $256, %rax jne .L14 xorl %eax, %eax movl $1280, %ecx movq %r13, %rdi movl $1024, %esi rep stosl movl $1280, %ecx movq %r12, %rdi rep stosl movl $5, %ecx movq %rbp, %rdi rep stosl movl $5, %ecx movq %rbx, %rdi rep stosl movq %rsp, %rdi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $1024, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $5120, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $5120, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $20, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $20, %esi call cudaMalloc@PLT movq (%rsp), %rdi movl $1, %ecx movq %r14, %rsi movl $1024, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $5120, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $5120, %edx call cudaMemcpy@PLT movq 32(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $20, %edx call cudaMemcpy@PLT movq 40(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $20, %edx call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx movl $1, %ecx movabsq $4294967297, %rdi movl $1, %esi movq %rdx, 48(%rsp) movl $1, 56(%rsp) movq %rdi, 60(%rsp) movl $1, 68(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L15 movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z37__device_stub__Z15computeGradientPfS_PfS_ .L15: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT leaq .LC1(%rip), %rsi movl %eax, %r15d testl %eax, %eax jne .L24 movl 56(%rsp), %ecx movq 48(%rsp), %rdx xorl %r9d, %r9d movl $2048, %r8d movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movq 40(%rsp), %r9 movq 32(%rsp), %r8 movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z41__device_stub__Z11lbfgsUpdatePfS_S_S_S_S_PfS_S_S_S_S_ .L18: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %r15d testl %eax, %eax je .L19 leaq .LC2(%rip), %rsi .L24: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r15d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L13 .L19: movq (%rsp), %rsi movl $2, %ecx movl $1024, %edx movq %r14, %rdi call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r14, %rdi call _ZdaPv@PLT movq %r13, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT xorl %eax, %eax .L13: movq 72(%rsp), %rdx subq %fs:40, %rdx je .L21 call __stack_chk_fail@PLT .L21: addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3849: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z11lbfgsUpdatePfS_S_S_S_S_" .LC4: .string "_Z15computeGradientPfS_" .LC5: .string "precalc_xorwow_matrix" .LC6: .string "precalc_xorwow_offset_matrix" .LC7: .string "mrg32k3aM1" .LC8: .string "mrg32k3aM2" .LC9: .string "mrg32k3aM1SubSeq" .LC10: .string "mrg32k3aM2SubSeq" .LC11: .string "mrg32k3aM1Seq" .LC12: .string "mrg32k3aM2Seq" .LC13: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3879: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC3(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z11lbfgsUpdatePfS_S_S_S_S_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC4(%rip), %rdx orl $-1, %r8d leaq _Z15computeGradientPfS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC5(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC9(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3879: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_055531.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__computeGradientPfS_ # -- Begin function _Z30__device_stub__computeGradientPfS_ .type _Z30__device_stub__computeGradientPfS_,@function _Z30__device_stub__computeGradientPfS_: # @_Z30__device_stub__computeGradientPfS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15computeGradientPfS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__computeGradientPfS_, .Lfunc_end0-_Z30__device_stub__computeGradientPfS_ .cfi_endproc # -- End function .globl _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ # -- Begin function _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ .type _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_,@function _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_: # @_Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 16(%rsp), %r8 movq %r9, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z11lbfgsUpdatePfS_S_S_S_S_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_, .Lfunc_end1-_Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $1024, %edi # imm = 0x400 callq _Znam movq %rax, %rbx movl $5120, %edi # imm = 0x1400 callq _Znam movq %rax, %r15 movl $5120, %edi # imm = 0x1400 callq _Znam movq %rax, %r12 movl $20, %edi callq _Znam movq %rax, %r13 movl $20, %edi callq _Znam movq %rax, 40(%rsp) # 8-byte Spill xorl %eax, %eax .LBB2_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 incq %rax cmpq $256, %rax # imm = 0x100 jne .LBB2_1 # %bb.2: # %.preheader62.preheader xorl %r14d, %r14d movl $5120, %edx # imm = 0x1400 movq %r15, %rdi xorl %esi, %esi callq memset@PLT movl $5120, %edx # imm = 0x1400 movq %r12, %rdi xorl %esi, %esi callq memset@PLT xorps %xmm0, %xmm0 movups %xmm0, (%r13) movl %r14d, 16(%r13) movq 40(%rsp), %rbp # 8-byte Reload movl %r14d, 16(%rbp) movups %xmm0, (%rbp) movq %rsp, %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc leaq 32(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc leaq 48(%rsp), %r14 movl $5120, %esi # imm = 0x1400 movq %r14, %rdi callq hipMalloc leaq 24(%rsp), %rdi movl $5120, %esi # imm = 0x1400 callq hipMalloc leaq 16(%rsp), %rdi movl $20, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $20, %esi callq hipMalloc movq %rsp, %rax movq (%rax), %rdi movl $1024, %edx # imm = 0x400 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq (%r14), %rdi movl $5120, %edx # imm = 0x1400 movq %r15, %rsi movl $1, %ecx callq hipMemcpy leaq 24(%rsp), %rax movq (%rax), %rdi movl $5120, %edx # imm = 0x1400 movq %r12, %rsi movl $1, %ecx callq hipMemcpy leaq 16(%rsp), %rax movq (%rax), %rdi movl $20, %edx movq %r13, %rsi movl $1, %ecx callq hipMemcpy leaq 8(%rsp), %rax movq (%rax), %rdi movl $20, %edx movq %rbp, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rbp movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: movq 32(%rsp), %rdi movq (%rsp), %rsi callq _Z30__device_stub__computeGradientPfS_ .LBB2_4: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB2_10 # %bb.5: movl %eax, %r14d movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %r14d, %edi jmp .LBB2_6 .LBB2_10: movl $2048, %r8d # imm = 0x800 movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_12 # %bb.11: movq (%rsp), %rdi movq 32(%rsp), %rsi movq 48(%rsp), %rdx movq 24(%rsp), %rcx movq 16(%rsp), %r8 movq 8(%rsp), %r9 callq _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ .LBB2_12: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB2_14 # %bb.13: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi .LBB2_6: callq hipGetErrorString testq %rax, %rax je .LBB2_7 # %bb.8: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_9 .LBB2_7: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB2_15: addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_14: .cfi_def_cfa_offset 112 movq (%rsp), %rsi movl $1024, %edx # imm = 0x400 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq (%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %r12, %rdi callq _ZdaPv movq %r13, %rdi callq _ZdaPv movq 40(%rsp), %rdi # 8-byte Reload callq _ZdaPv xorl %eax, %eax jmp .LBB2_15 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15computeGradientPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11lbfgsUpdatePfS_S_S_S_S_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z15computeGradientPfS_,@object # @_Z15computeGradientPfS_ .section .rodata,"a",@progbits .globl _Z15computeGradientPfS_ .p2align 3, 0x0 _Z15computeGradientPfS_: .quad _Z30__device_stub__computeGradientPfS_ .size _Z15computeGradientPfS_, 8 .type _Z11lbfgsUpdatePfS_S_S_S_S_,@object # @_Z11lbfgsUpdatePfS_S_S_S_S_ .globl _Z11lbfgsUpdatePfS_S_S_S_S_ .p2align 3, 0x0 _Z11lbfgsUpdatePfS_S_S_S_S_: .quad _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ .size _Z11lbfgsUpdatePfS_S_S_S_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error in computeGradient: " .size .L.str, 27 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error in lbfgsUpdate: " .size .L.str.1, 23 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15computeGradientPfS_" .size .L__unnamed_1, 24 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z11lbfgsUpdatePfS_S_S_S_S_" .size .L__unnamed_2, 28 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__computeGradientPfS_ .addrsig_sym _Z26__device_stub__lbfgsUpdatePfS_S_S_S_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15computeGradientPfS_ .addrsig_sym _Z11lbfgsUpdatePfS_S_S_S_S_ .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
7,366
6,386
113,386
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z18insertIntoSkipListP4Nodeiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; BSSY B0, 0xe0 ; S2R R7, SR_CTAID.X ; ISETP.GT.AND P0, PT, R0, 0xf, PT ; IMAD R7, R7, c[0x0][0x0], R0 ; ISETP.GE.AND P1, PT, R7, c[0x0][0x168], PT ; @P0 BRA 0xd0 ; IMAD.MOV.U32 R3, RZ, RZ, -0x1 ; STS [R0.X4], R3 ; IADD3 R0, R0, c[0x0][0x0], RZ ; ISETP.GE.AND P0, PT, R0, 0x10, PT ; @!P0 BRA 0x90 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P1 EXIT ; MOV R0, c[0x0][0x170] ; ULDC.64 UR6, c[0x0][0x118] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 BRA 0x360 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; HFMA2.MMA R3, -RZ, RZ, 0, 4.291534423828125e-06 ; IADD3 R9, R4, -0x1, RZ ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; IMAD.WIDE R2, R9, 0x4, R2 ; LDG.E R2, [R2.64+0x8] ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; ISETP.NE.AND P0, PT, R2, -0x1, PT ; @!P0 BRA 0x320 ; SHF.R.S32.HI R8, RZ, 0x1f, R9 ; IMAD.SHL.U32 R11, R9.reuse, 0x4, RZ ; MOV R5, R2 ; SHF.L.U64.HI R8, R9, 0x2, R8 ; IMAD.MOV.U32 R12, RZ, RZ, 0x48 ; IMAD.WIDE R2, R5, R12, c[0x0][0x160] ; LDG.E R2, [R2.64] ; MOV R10, R5 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; @P0 BRA 0x320 ; SHF.R.S32.HI R0, RZ, 0x1f, R5 ; IMAD.WIDE.U32 R2, R5, R12, c[0x0][0x160] ; IMAD R5, R0, 0x48, RZ ; IADD3 R2, P0, R11, R2, RZ ; IADD3.X R3, R8, R3, R5, P0, !PT ; LDG.E R5, [R2.64+0x8] ; IMAD.MOV.U32 R0, RZ, RZ, R10 ; ISETP.NE.AND P0, PT, R5, -0x1, PT ; @P0 BRA 0x230 ; SHF.L.U32 R3, R9, 0x2, RZ ; ISETP.GT.AND P0, PT, R6, 0x1, PT ; STS [R3], R0 ; @P0 BRA 0x160 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; IADD3 R7, R7, c[0x0][0x168], RZ ; @!P0 BRA 0x1140 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; HFMA2.MMA R2, -RZ, RZ, 0, 0 ; IADD3 R0, R5.reuse, -0x1, RZ ; LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; SHF.R.S32.HI R0, RZ, 0x1f, R7 ; @!P0 BRA 0xf50 ; IADD3 R4, -R5, c[0x0][0x170], RZ ; ULDC.64 UR4, c[0x0][0x160] ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; UIADD3 UR4, UP0, UR4, 0x14, URZ ; ISETP.GT.AND P0, PT, R4, RZ, PT ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; MOV R6, UR4 ; UMOV UR4, URZ ; IMAD.U32 R3, RZ, RZ, UR5 ; @!P0 BRA 0xd80 ; ISETP.GT.AND P1, PT, R4, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0xa50 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDS.128 R8, [UR4] ; MOV R14, R6 ; IMAD.MOV.U32 R15, RZ, RZ, R3 ; IMAD.WIDE R16, R8, 0x48, R14 ; LDG.E R25, [R16.64+-0xc] ; IMAD R19, R0, 0x48, RZ ; IMAD.WIDE.U32 R12, R7, 0x48, R14 ; IADD3 R13, R13, R19, RZ ; IMAD.WIDE R18, R9, 0x48, R14 ; STG.E [R12.64+-0xc], R25 ; STG.E [R16.64+-0xc], R7 ; LDG.E R27, [R18.64+-0x8] ; IMAD.WIDE R20, R10, 0x48, R14 ; STG.E [R12.64+-0x8], R27 ; STG.E [R18.64+-0x8], R7 ; LDG.E R29, [R20.64+-0x4] ; IMAD.WIDE R22, R11, 0x48, R14 ; LDS.128 R8, [UR4+0x10] ; IADD3 R14, P1, R6, 0x10, RZ ; STG.E [R12.64+-0x4], R29 ; STG.E [R20.64+-0x4], R7 ; LDG.E R24, [R22.64] ; IMAD.X R15, RZ, RZ, R3, P1 ; IMAD.WIDE R16, R8, 0x48, R14.reuse ; STG.E [R12.64], R24 ; STG.E [R22.64], R7 ; LDG.E R27, [R16.64+-0xc] ; IMAD.WIDE R18, R9, 0x48, R14 ; STG.E [R12.64+0x4], R27 ; STG.E [R16.64+-0xc], R7 ; LDG.E R29, [R18.64+-0x8] ; IMAD.WIDE R20, R10, 0x48, R14 ; STG.E [R12.64+0x8], R29 ; STG.E [R18.64+-0x8], R7 ; LDG.E R26, [R20.64+-0x4] ; IMAD.WIDE R24, R11, 0x48, R14 ; LDS.128 R8, [UR4+0x20] ; IADD3 R14, P1, R6, 0x20, RZ ; STG.E [R12.64+0xc], R26 ; STG.E [R20.64+-0x4], R7 ; LDG.E R23, [R24.64] ; IADD3.X R15, RZ, R3, RZ, P1, !PT ; IMAD.WIDE R16, R8, 0x48, R14.reuse ; STG.E [R12.64+0x10], R23 ; STG.E [R24.64], R7 ; LDG.E R27, [R16.64+-0xc] ; IMAD.WIDE R18, R9, 0x48, R14 ; STG.E [R12.64+0x14], R27 ; STG.E [R16.64+-0xc], R7 ; LDG.E R29, [R18.64+-0x8] ; IMAD.WIDE R20, R10, 0x48, R14 ; STG.E [R12.64+0x18], R29 ; STG.E [R18.64+-0x8], R7 ; LDG.E R26, [R20.64+-0x4] ; IMAD.WIDE R22, R11, 0x48, R14 ; LDS.128 R8, [UR4+0x30] ; IADD3 R14, P1, R6, 0x30, RZ ; STG.E [R12.64+0x1c], R26 ; STG.E [R20.64+-0x4], R7 ; LDG.E R25, [R22.64] ; IMAD.X R15, RZ, RZ, R3, P1 ; IMAD.WIDE R16, R8, 0x48, R14.reuse ; STG.E [R12.64+0x20], R25 ; STG.E [R22.64], R7 ; LDG.E R27, [R16.64+-0xc] ; IMAD.WIDE R8, R9, 0x48, R14 ; STG.E [R12.64+0x24], R27 ; STG.E [R16.64+-0xc], R7 ; LDG.E R21, [R8.64+-0x8] ; IMAD.WIDE R18, R10, 0x48, R14 ; STG.E [R12.64+0x28], R21 ; STG.E [R8.64+-0x8], R7 ; LDG.E R29, [R18.64+-0x4] ; IMAD.WIDE R14, R11, 0x48, R14 ; IADD3 R4, R4, -0x10, RZ ; ISETP.GT.AND P1, PT, R4, 0xc, PT ; STG.E [R12.64+0x2c], R29 ; STG.E [R18.64+-0x4], R7 ; LDG.E R11, [R14.64] ; IADD3 R6, P2, R6, 0x40, RZ ; UIADD3 UR4, UR4, 0x40, URZ ; IADD3 R2, R2, 0x10, RZ ; IADD3.X R3, RZ, R3, RZ, P2, !PT ; STG.E [R12.64+0x30], R11 ; STG.E [R14.64], R7 ; @P1 BRA 0x4f0 ; ISETP.GT.AND P1, PT, R4, 0x4, PT ; @!P1 BRA 0xd60 ; LDS.128 R8, [UR4] ; MOV R15, R3 ; IMAD.MOV.U32 R14, RZ, RZ, R6 ; IMAD.WIDE R16, R8, 0x48, R14 ; LDG.E R25, [R16.64+-0xc] ; IMAD R19, R0, 0x48, RZ ; IMAD.WIDE.U32 R12, R7, 0x48, R14 ; IMAD.IADD R13, R19, 0x1, R13 ; IMAD.WIDE R18, R9, 0x48, R14 ; STG.E [R12.64+-0xc], R25 ; STG.E [R16.64+-0xc], R7 ; LDG.E R27, [R18.64+-0x8] ; IMAD.WIDE R20, R10, 0x48, R14 ; STG.E [R12.64+-0x8], R27 ; STG.E [R18.64+-0x8], R7 ; LDG.E R29, [R20.64+-0x4] ; IMAD.WIDE R22, R11, 0x48, R14 ; LDS.128 R8, [UR4+0x10] ; IADD3 R14, P0, R6, 0x10, RZ ; STG.E [R12.64+-0x4], R29 ; STG.E [R20.64+-0x4], R7 ; LDG.E R24, [R22.64] ; IADD3.X R15, RZ, R3, RZ, P0, !PT ; IMAD.WIDE R16, R8, 0x48, R14.reuse ; STG.E [R12.64], R24 ; STG.E [R22.64], R7 ; LDG.E R25, [R16.64+-0xc] ; IMAD.WIDE R8, R9, 0x48, R14 ; STG.E [R12.64+0x4], R25 ; STG.E [R16.64+-0xc], R7 ; LDG.E R21, [R8.64+-0x8] ; IMAD.WIDE R18, R10, 0x48, R14 ; STG.E [R12.64+0x8], R21 ; STG.E [R8.64+-0x8], R7 ; LDG.E R27, [R18.64+-0x4] ; IMAD.WIDE R14, R11, 0x48, R14 ; STG.E [R12.64+0xc], R27 ; STG.E [R18.64+-0x4], R7 ; LDG.E R11, [R14.64] ; IADD3 R6, P1, R6, 0x20, RZ ; UIADD3 UR4, UR4, 0x20, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R2, R2, 0x8, RZ ; IMAD.X R3, RZ, RZ, R3, P1 ; IADD3 R4, R4, -0x8, RZ ; STG.E [R12.64+0x10], R11 ; STG.E [R14.64], R7 ; ISETP.NE.OR P0, PT, R4, RZ, P0 ; @!P0 BRA 0xf50 ; LDS.128 R8, [UR4] ; MOV R12, R6 ; IMAD.MOV.U32 R13, RZ, RZ, R3 ; IMAD.WIDE R16, R8, 0x48, R12 ; LDG.E R3, [R16.64+-0xc] ; IMAD R19, R0, 0x48, RZ ; IMAD.WIDE.U32 R14, R7, 0x48, R12 ; IMAD.WIDE R8, R9, 0x48, R12 ; IADD3 R15, R19, R15, RZ ; STG.E [R14.64+-0xc], R3 ; STG.E [R16.64+-0xc], R7 ; LDG.E R21, [R8.64+-0x8] ; IMAD.WIDE R18, R10, 0x48, R12 ; STG.E [R14.64+-0x8], R21 ; STG.E [R8.64+-0x8], R7 ; LDG.E R23, [R18.64+-0x4] ; IMAD.WIDE R10, R11, 0x48, R12 ; IADD3 R4, R4, -0x4, RZ ; ISETP.NE.AND P0, PT, R4, RZ, PT ; STG.E [R14.64+-0x4], R23 ; STG.E [R18.64+-0x4], R7 ; LDG.E R25, [R10.64] ; IADD3 R6, P1, R12, 0x10, RZ ; UIADD3 UR4, UR4, 0x10, URZ ; IADD3 R2, R2, 0x4, RZ ; IMAD.X R3, RZ, RZ, R13, P1 ; STG.E [R14.64], R25 ; STG.E [R10.64], R7 ; @P0 BRA 0xd80 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 BRA 0x1140 ; HFMA2.MMA R8, -RZ, RZ, 0, 4.291534423828125e-06 ; IMAD R3, R0, 0x48, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IMAD.SHL.U32 R0, R2.reuse, 0x4, RZ ; IMAD.WIDE R10, R2, R11, c[0x0][0x160] ; IMAD.WIDE.U32 R8, R7, R8, c[0x0][0x160] ; IADD3 R4, P1, R10, 0x8, RZ ; IADD3 R9, R3, R9, RZ ; IADD3.X R13, RZ, R11, RZ, P1, !PT ; IMAD.WIDE R8, R2, 0x4, R8 ; IADD3 R6, P0, R8, 0x8, RZ ; IMAD.X R15, RZ, RZ, R9, P0 ; LDS R9, [R0] ; MOV R2, R4 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; IMAD.WIDE R2, R9, 0x48, R2 ; LDG.E R11, [R2.64] ; IADD3 R5, R5, -0x1, RZ ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; MOV R8, R6 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IADD3 R4, P2, R4, 0x4, RZ ; IADD3 R6, P1, R6, 0x4, RZ ; IADD3 R0, R0, 0x4, RZ ; IMAD.X R13, RZ, RZ, R13, P2 ; IADD3.X R15, RZ, R15, RZ, P1, !PT ; STG.E [R8.64], R11 ; STG.E [R2.64], R7 ; @P0 BRA 0x1030 ; MOV R2, 0x48 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; MOV R7, c[0x0][0x170] ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R7 ; EXIT ; BRA 0x11b0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z12initSkipListP4Nodei .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; @P0 EXIT ; HFMA2.MMA R2, -RZ, RZ, 0, 4.291534423828125e-06 ; MOV R7, 0x1 ; ULDC.64 UR4, c[0x0][0x118] ; MOV R9, 0xffffffff ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R7 ; STG.E [R2.64+0x8], R9 ; STG.E [R2.64+0xc], R9 ; STG.E [R2.64+0x10], R9 ; STG.E [R2.64+0x14], R9 ; STG.E [R2.64+0x18], R9 ; STG.E [R2.64+0x1c], R9 ; STG.E [R2.64+0x20], R9 ; STG.E [R2.64+0x24], R9 ; STG.E [R2.64+0x28], R9 ; STG.E [R2.64+0x2c], R9 ; STG.E [R2.64+0x30], R9 ; STG.E [R2.64+0x34], R9 ; STG.E [R2.64+0x38], R9 ; STG.E [R2.64+0x3c], R9 ; STG.E [R2.64+0x40], R9 ; STG.E [R2.64+0x44], R9 ; EXIT ; BRA 0x1e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12initSkipListP4Nodei ; -- Begin function _Z12initSkipListP4Nodei .globl _Z12initSkipListP4Nodei .p2align 8 .type _Z12initSkipListP4Nodei,@function _Z12initSkipListP4Nodei: ; @_Z12initSkipListP4Nodei ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_3 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_mov_b32_e32 v2, 1 v_mov_b32_e32 v4, -1 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[5:6], null, 0x48, v1, s[0:1] s_mov_b64 s[0:1], 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v5, 8 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo global_store_b64 v[5:6], v[1:2], off .LBB0_2: ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v1, vcc_lo, v0, s0 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v3, vcc_lo s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s0, 64 global_store_b32 v[1:2], v4, off s_cbranch_scc1 .LBB0_2 .LBB0_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12initSkipListP4Nodei .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12initSkipListP4Nodei, .Lfunc_end0-_Z12initSkipListP4Nodei ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 168 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z18insertIntoSkipListP4Nodeiii ; -- Begin function _Z18insertIntoSkipListP4Nodeiii .globl _Z18insertIntoSkipListP4Nodeiii .p2align 8 .type _Z18insertIntoSkipListP4Nodeiii,@function _Z18insertIntoSkipListP4Nodeiii: ; @_Z18insertIntoSkipListP4Nodeiii ; %bb.0: s_load_b32 s2, s[0:1], 0x24 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff v_cmpx_gt_u32_e32 16, v0 s_cbranch_execz .LBB1_3 ; %bb.1: ; %.lr.ph.preheader v_lshl_add_u32 v1, v0, 2, 0 v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v3, v0 s_mov_b32 s4, 0 s_lshl_b32 s5, s2, 2 .LBB1_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s2, v3 ds_store_b32 v1, v2 v_add_nc_u32_e32 v1, s5, v1 v_cmp_lt_u32_e32 vcc_lo, 15, v3 s_or_b32 s4, vcc_lo, s4 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB1_2 .LBB1_3: ; %Flow84 s_or_b32 exec_lo, exec_lo, s3 s_load_b128 s[4:7], s[0:1], 0x8 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s4, v1 s_cbranch_execz .LBB1_16 ; %bb.4: ; %.preheader49 s_load_b64 s[0:1], s[0:1], 0x0 s_cmp_gt_i32 s6, 0 s_mov_b32 s3, 0 s_cselect_b32 s7, -1, 0 s_cmp_lt_i32 s6, 1 s_cbranch_scc1 .LBB1_12 ; %bb.5: ; %.preheader.preheader s_mov_b32 s10, s6 s_mov_b32 s11, 0 .LBB1_6: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB1_7 Depth 2 s_add_i32 s2, s10, -1 s_mov_b32 s12, s11 s_lshl_b64 s[8:9], s[2:3], 2 .LBB1_7: ; Parent Loop BB1_6 Depth=1 ; => This Inner Loop Header: Depth=2 s_mov_b32 s11, s12 s_mulk_i32 s12, 0x48 s_mul_hi_i32 s13, s11, 0x48 s_waitcnt lgkmcnt(0) s_add_u32 s12, s0, s12 s_addc_u32 s13, s1, s13 s_add_u32 s12, s12, s8 s_addc_u32 s13, s13, s9 s_load_b32 s12, s[12:13], 0x8 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s12, -1 s_cbranch_scc1 .LBB1_9 ; %bb.8: ; in Loop: Header=BB1_7 Depth=2 s_mul_i32 s13, s12, 0x48 s_mul_hi_i32 s15, s12, 0x48 s_add_u32 s14, s0, s13 s_addc_u32 s15, s1, s15 s_load_b32 s13, s[14:15], 0x0 s_waitcnt lgkmcnt(0) s_cmp_ge_i32 s13, s5 s_cselect_b32 s13, -1, 0 s_branch .LBB1_10 .LBB1_9: ; in Loop: Header=BB1_7 Depth=2 s_mov_b32 s13, -1 ; implicit-def: $sgpr12 .LBB1_10: ; %Flow79 ; in Loop: Header=BB1_7 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB1_7 ; %bb.11: ; %.critedge ; in Loop: Header=BB1_6 Depth=1 s_lshl_b32 s8, s2, 2 v_mov_b32_e32 v2, s11 s_add_i32 s8, s8, 0 s_cmp_lt_i32 s10, 2 v_mov_b32_e32 v0, s8 s_mov_b32 s10, s2 ds_store_b32 v0, v2 s_cbranch_scc0 .LBB1_6 .LBB1_12: ; %._crit_edge54 v_add_nc_u32_e32 v2, s4, v1 s_and_not1_b32 vcc_lo, exec_lo, s7 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_vccnz .LBB1_15 ; %bb.13: ; %.lr.ph57.preheader v_mad_i64_i32 v[0:1], null, 0x48, v2, 0 s_add_u32 s2, s0, 8 s_addc_u32 s3, s1, 0 s_mov_b32 s4, 0 s_mov_b32 s7, s6 .LBB1_14: ; %.lr.ph57 ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v3, s4 s_add_i32 s7, s7, -1 ds_load_b32 v3, v3 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v4, 0x48, v3 v_mul_hi_i32 v5, 0x48, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v5, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo global_load_b32 v7, v[3:4], off s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_add_i32 s4, s4, 4 s_cmp_eq_u32 s7, 0 s_waitcnt vmcnt(0) s_clause 0x1 global_store_b32 v[5:6], v7, off global_store_b32 v[3:4], v2, off s_cbranch_scc0 .LBB1_14 .LBB1_15: ; %._crit_edge58 v_mad_i64_i32 v[0:1], null, 0x48, v2, s[0:1] v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s6 global_store_b64 v[0:1], v[2:3], off .LBB1_16: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18insertIntoSkipListP4Nodeiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z18insertIntoSkipListP4Nodeiii, .Lfunc_end1-_Z18insertIntoSkipListP4Nodeiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 568 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12initSkipListP4Nodei .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12initSkipListP4Nodei.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims - .offset: 144 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18insertIntoSkipListP4Nodeiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18insertIntoSkipListP4Nodeiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00090631_00000000-6_cuda_code_074578.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3853: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3853: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error during " .LC1: .string ": " .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3849: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3849: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .type _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei, @function _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei: .LFB3875: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z12initSkipListP4Nodei(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3875: .size _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei, .-_Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .globl _Z12initSkipListP4Nodei .type _Z12initSkipListP4Nodei, @function _Z12initSkipListP4Nodei: .LFB3876: .cfi_startproc endbr64 jmp _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .cfi_endproc .LFE3876: .size _Z12initSkipListP4Nodei, .-_Z12initSkipListP4Nodei .globl _Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii .type _Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii, @function _Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii: .LFB3877: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movl %esi, 20(%rsp) leaq 68(%rsp), %rsi movl %edx, 16(%rsp) leaq 40(%rsp), %rdx movl %ecx, 12(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L13 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z18insertIntoSkipListP4Nodeiii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L13: movq 136(%rsp), %rax subq %fs:40, %rax je .L15 call __stack_chk_fail@PLT .L15: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3877: .size _Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii, .-_Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii .globl _Z18insertIntoSkipListP4Nodeiii .type _Z18insertIntoSkipListP4Nodeiii, @function _Z18insertIntoSkipListP4Nodeiii: .LFB3878: .cfi_startproc endbr64 jmp _Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii .cfi_endproc .LFE3878: .size _Z18insertIntoSkipListP4Nodeiii, .-_Z18insertIntoSkipListP4Nodeiii .section .rodata.str1.1 .LC2: .string "memory allocation" .LC3: .string "initSkipList kernel launch" .LC4: .string "initSkipList kernel execution" .LC5: .string "insertIntoSkipList kernel launch" .LC6: .string "insertIntoSkipList kernel execution" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3850: .cfi_startproc endbr64 subq $56, %rsp .cfi_def_cfa_offset 64 movl $589824, %esi movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq .LC2(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $268435457, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $4, %rdi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L19 movq 8(%rsp), %rdi movl $4096, %esi call _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .L19: call cudaGetLastError@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx movl $268435457, %edi xorl %r9d, %r9d salq $8, %rdx salq $4, %rdi movl $64, %r8d movl $1, %ecx movl $1, %esi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L20 movq 8(%rsp), %rdi movl $4, %ecx movl $2048, %edx movl $4096, %esi call _Z45__device_stub__Z18insertIntoSkipListP4NodeiiiP4Nodeiii .L20: call cudaGetLastError@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax je .L21 call __stack_chk_fail@PLT .L21: xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3850: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z18insertIntoSkipListP4Nodeiii" .LC8: .string "_Z12initSkipListP4Nodei" .LC9: .string "precalc_xorwow_matrix" .LC10: .string "precalc_xorwow_offset_matrix" .LC11: .string "mrg32k3aM1" .LC12: .string "mrg32k3aM2" .LC13: .string "mrg32k3aM1SubSeq" .LC14: .string "mrg32k3aM2SubSeq" .LC15: .string "mrg32k3aM1Seq" .LC16: .string "mrg32k3aM2Seq" .LC17: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3880: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z18insertIntoSkipListP4Nodeiii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC8(%rip), %rdx orl $-1, %r8d leaq _Z12initSkipListP4Nodei(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC9(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC15(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3880: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_074578.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z27__device_stub__initSkipListP4Nodei # -- Begin function _Z27__device_stub__initSkipListP4Nodei .type _Z27__device_stub__initSkipListP4Nodei,@function _Z27__device_stub__initSkipListP4Nodei: # @_Z27__device_stub__initSkipListP4Nodei .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z12initSkipListP4Nodei, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z27__device_stub__initSkipListP4Nodei, .Lfunc_end0-_Z27__device_stub__initSkipListP4Nodei .cfi_endproc # -- End function .globl _Z33__device_stub__insertIntoSkipListP4Nodeiii # -- Begin function _Z33__device_stub__insertIntoSkipListP4Nodeiii .type _Z33__device_stub__insertIntoSkipListP4Nodeiii,@function _Z33__device_stub__insertIntoSkipListP4Nodeiii: # @_Z33__device_stub__insertIntoSkipListP4Nodeiii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 20(%rsp), %rdi movl %esi, (%rdi) leaq 16(%rsp), %rsi movl %edx, (%rsi) leaq 12(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 32(%rsp), %r12 leaq 24(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z18insertIntoSkipListP4Nodeiii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z33__device_stub__insertIntoSkipListP4Nodeiii, .Lfunc_end1-_Z33__device_stub__insertIntoSkipListP4Nodeiii .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB2_2 # %bb.1: retq .LBB2_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end2: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end2-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movabsq $4294967312, %rbx # imm = 0x100000010 movq %rsp, %rdi movl $589824, %esi # imm = 0x90000 callq hipMalloc movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 240(%rbx), %r14 movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq (%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq _Z27__device_stub__initSkipListP4Nodei .LBB3_2: callq hipGetLastError movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $64, %r8d movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq (%rsp), %rdi movl $4096, %esi # imm = 0x1000 movl $2048, %edx # imm = 0x800 movl $4, %ecx callq _Z33__device_stub__insertIntoSkipListP4Nodeiii .LBB3_4: callq hipGetLastError movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12initSkipListP4Nodei, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18insertIntoSkipListP4Nodeiii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z12initSkipListP4Nodei,@object # @_Z12initSkipListP4Nodei .section .rodata,"a",@progbits .globl _Z12initSkipListP4Nodei .p2align 3, 0x0 _Z12initSkipListP4Nodei: .quad _Z27__device_stub__initSkipListP4Nodei .size _Z12initSkipListP4Nodei, 8 .type _Z18insertIntoSkipListP4Nodeiii,@object # @_Z18insertIntoSkipListP4Nodeiii .globl _Z18insertIntoSkipListP4Nodeiii .p2align 3, 0x0 _Z18insertIntoSkipListP4Nodeiii: .quad _Z33__device_stub__insertIntoSkipListP4Nodeiii .size _Z18insertIntoSkipListP4Nodeiii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error during " .size .L.str, 19 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz ": " .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "memory allocation" .size .L.str.2, 18 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "initSkipList kernel launch" .size .L.str.3, 27 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "initSkipList kernel execution" .size .L.str.4, 30 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "insertIntoSkipList kernel launch" .size .L.str.5, 33 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "insertIntoSkipList kernel execution" .size .L.str.6, 36 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12initSkipListP4Nodei" .size .L__unnamed_1, 24 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z18insertIntoSkipListP4Nodeiii" .size .L__unnamed_2, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__initSkipListP4Nodei .addrsig_sym _Z33__device_stub__insertIntoSkipListP4Nodeiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12initSkipListP4Nodei .addrsig_sym _Z18insertIntoSkipListP4Nodeiii .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
6,540
5,070
113,388
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z10stencil64DPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR6, c[0x0][0x118] ; BSSY B0, 0x150 ; S2R R7, SR_TID.X ; S2R R3, SR_CTAID.Y ; S2R R4, SR_TID.Y ; IMAD R0, R0, c[0x0][0x0], R7 ; IADD3 R2, R0, -0xb, RZ ; IMAD R3, R3, c[0x0][0x4], R4 ; IMAD R4, R4, 0x56, R7 ; HFMA2.MMA R7, -RZ, RZ, 0, 0 ; IADD3 R5, R3, -0xb, RZ ; LOP3.LUT P0, RZ, R5, 0xffffffc0, R2, 0xc8, !PT ; @P0 BRA 0x140 ; LEA R2, R3, R0, 0x6 ; MOV R7, 0x4 ; IADD3 R2, R2, -0x2cb, RZ ; IMAD.WIDE R6, R2, R7, c[0x0][0x160] ; LDG.E R7, [R6.64] ; BSYNC B0 ; STS [R4.X4], R7 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; LDS R2, [R4.X4+-0xef4] ; UMOV UR4, 0xfffff10c ; LDS R7, [R4.X4+-0xef0] ; LDS R8, [R4.X4+-0xeec] ; LDS R9, [R4.X4+-0xee8] ; LDS R10, [R4.X4+-0xee4] ; LDS R11, [R4.X4+-0xee0] ; LDS R12, [R4.X4+-0xedc] ; LDS R14, [R4.X4+-0xed8] ; LDS R16, [R4.X4+-0xed4] ; LDS R5, [R4.X4+-0xed0] ; FADD R6, RZ, R2 ; LDS R18, [R4.X4+-0xeac] ; FADD R7, R6, R7 ; LDS R2, [R4.X4+-0xecc] ; FADD R8, R7, R8 ; LDS R6, [R4.X4+-0xec8] ; FADD R9, R8, R9 ; LDS R7, [R4.X4+-0xec4] ; FADD R10, R9, R10 ; LDS R8, [R4.X4+-0xec0] ; FADD R11, R10, R11 ; LDS R9, [R4.X4+-0xebc] ; FADD R11, R11, R12 ; LDS R10, [R4.X4+-0xeb8] ; FADD R11, R11, R14 ; LDS R12, [R4.X4+-0xeb4] ; FADD R16, R11, R16 ; LDS R14, [R4.X4+-0xeb0] ; FADD R5, R16, R5 ; LDS R20, [R4.X4+-0xea0] ; LDS R16, [R4.X4+-0xea8] ; FADD R5, R5, R2 ; LDS R2, [R4.X4+-0xea4] ; FADD R6, R5, R6 ; FADD R7, R6, R7 ; LDS R6, [R4.X4+-0xe9c] ; FADD R8, R7, R8 ; FADD R9, R8, R9 ; FADD R9, R9, R10 ; FADD R9, R9, R12 ; FADD R9, R9, R14 ; FADD R9, R9, R18 ; FADD R9, R9, R16 ; FADD R9, R9, R2 ; SHF.L.U32 R2, R4, 0x2, RZ ; FADD R9, R9, R20 ; IADD3 R4, R2, -0xef4, RZ ; FADD R8, R9, R6 ; LDS R7, [R4+0x158] ; UMOV UR5, UR4 ; UIADD3 UR4, UR4, 0x2b0, URZ ; LDS R9, [R4+0x15c] ; UISETP.NE.AND UP0, UPT, UR4, 0xe9c, UPT ; LDS R10, [R4+0x160] ; LDS R11, [R4+0x164] ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; LDS R12, [R4+0x168] ; LDS R13, [R4+0x16c] ; LDS R14, [R4+0x170] ; LDS R15, [R4+0x174] ; LDS R6, [R4+0x178] ; LDS R5, [R4+0x17c] ; FADD R8, R7, R8 ; LDS R18, [R2+UR5+0x300] ; FADD R9, R8, R9 ; LDS R7, [R4+0x180] ; FADD R10, R9, R10 ; LDS R8, [R4+0x184] ; FADD R11, R10, R11 ; LDS R9, [R4+0x188] ; FADD R12, R11, R12 ; LDS R10, [R4+0x18c] ; FADD R13, R12, R13 ; LDS R11, [R4+0x190] ; FADD R14, R13, R14 ; LDS R12, [R4+0x194] ; FADD R15, R14, R15 ; LDS R13, [R4+0x198] ; FADD R16, R15, R6 ; LDS R14, [R4+0x19c] ; FADD R16, R16, R5 ; LDS R6, [R4+0x1a0] ; LDS R5, [R4+0x1a4] ; FADD R15, R16, R7 ; LDS R20, [R2+UR5+0x308] ; FADD R16, R15, R8 ; LDS R7, [R4+0x1a8] ; FADD R15, R16, R9 ; LDS R8, [R4+0x1ac] ; FADD R16, R15, R10 ; LDS R9, [R4+0x1b0] ; FADD R15, R16, R11 ; LDS R10, [R2+UR5+0x2b0] ; FADD R16, R15, R12 ; LDS R11, [R2+UR5+0x2b4] ; FADD R15, R16, R13 ; LDS R12, [R2+UR5+0x2b8] ; FADD R15, R15, R14 ; LDS R13, [R2+UR5+0x2bc] ; FADD R14, R15, R6 ; LDS R4, [R2+UR5+0x2c0] ; FADD R14, R14, R5 ; LDS R6, [R2+UR5+0x2c4] ; LDS R5, [R2+UR5+0x2c8] ; FADD R15, R14, R7 ; LDS R16, [R2+UR5+0x2f8] ; FADD R14, R15, R8 ; LDS R7, [R2+UR5+0x2cc] ; FADD R15, R14, R9 ; LDS R8, [R2+UR5+0x2d0] ; FADD R14, R15, R10 ; LDS R9, [R2+UR5+0x2d4] ; FADD R15, R14, R11 ; LDS R10, [R2+UR5+0x2d8] ; FADD R14, R15, R12 ; LDS R11, [R2+UR5+0x2dc] ; FADD R15, R14, R13 ; LDS R12, [R2+UR5+0x2e0] ; FADD R15, R15, R4 ; LDS R13, [R2+UR5+0x2e4] ; FADD R14, R15, R6 ; LDS R4, [R2+UR5+0x2e8] ; FADD R14, R14, R5 ; LDS R6, [R2+UR5+0x2ec] ; LDS R5, [R2+UR5+0x2f0] ; FADD R7, R14, R7 ; LDS R14, [R2+UR5+0x2f4] ; FADD R8, R7, R8 ; FADD R9, R8, R9 ; LDS R8, [R2+UR5+0x2fc] ; FADD R10, R9, R10 ; FADD R11, R10, R11 ; LDS R10, [R2+UR5+0x304] ; FADD R12, R11, R12 ; FADD R13, R12, R13 ; FADD R13, R13, R4 ; IADD3 R4, R2, UR5, RZ ; FADD R6, R13, R6 ; IADD3 R4, R4, 0x2b0, RZ ; FADD R5, R6, R5 ; FADD R5, R5, R14 ; FADD R5, R5, R16 ; FADD R5, R5, R8 ; FADD R5, R5, R18 ; FADD R5, R5, R10 ; FADD R8, R5, R20 ; @P0 BRA 0x490 ; LEA R0, R3, R0, 0x6 ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R0, R0, -0x2cb, RZ ; IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; STG.E [R2.64], R8 ; EXIT ; BRA 0xb20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10stencil64DPfS_ ; -- Begin function _Z10stencil64DPfS_ .globl _Z10stencil64DPfS_ .p2align 8 .type _Z10stencil64DPfS_,@function _Z10stencil64DPfS_: ; @_Z10stencil64DPfS_ ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b128 s[0:3], s[0:1], 0x0 v_and_b32_e32 v3, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 v_mov_b32_e32 v1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s5, s4, 0xffff s_lshr_b32 s4, s4, 16 s_mul_i32 s14, s14, s5 s_mul_i32 s15, s15, s4 v_add3_u32 v0, v3, s14, -11 v_add3_u32 v4, v2, s15, -11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_or_b32_e32 v5, v4, v0 v_lshl_add_u32 v0, v4, 6, v0 v_cmp_gt_u32_e32 vcc_lo, 64, v5 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: v_mov_b32_e32 v1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[0:1] v_add_co_u32 v4, s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, s1, v5, s0 global_load_b32 v1, v[4:5], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s4 v_lshlrev_b32_e32 v3, 2, v3 s_delay_alu instid0(VALU_DEP_1) v_mad_u32_u24 v4, 0x158, v2, v3 s_waitcnt vmcnt(0) ds_store_b32 v4, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB0_8 ; %bb.3: ; %.preheader.preheader v_mul_u32_u24_e32 v1, 0x158, v2 v_mov_b32_e32 v2, 0 s_mov_b32 s0, -11 s_delay_alu instid0(VALU_DEP_2) v_add3_u32 v1, v1, v3, 0xfffff10c .LBB0_4: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_5 Depth 2 s_mov_b32 s1, 0 .LBB0_5: ; Parent Loop BB0_4 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s1, v1 s_add_i32 s1, s1, 4 s_delay_alu instid0(SALU_CYCLE_1) s_cmpk_eq_i32 s1, 0x5c ds_load_b32 v3, v3 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v2, v3 s_cbranch_scc0 .LBB0_5 ; %bb.6: ; in Loop: Header=BB0_4 Depth=1 v_add_nc_u32_e32 v1, 0x158, v1 s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, 12 s_cbranch_scc0 .LBB0_4 ; %bb.7: v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10stencil64DPfS_ .amdhsa_group_segment_fixed_size 29584 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10stencil64DPfS_, .Lfunc_end0-_Z10stencil64DPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 364 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 29584 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 29584 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10stencil64DPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10stencil64DPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
2,836
3,207
113,389
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000daa7c_00000000-6_cuda_code_075722.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4293: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4293: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z32__device_stub__Z10stencil64DPfS_PfS_ .type _Z32__device_stub__Z10stencil64DPfS_PfS_, @function _Z32__device_stub__Z10stencil64DPfS_PfS_: .LFB3660: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z10stencil64DPfS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z32__device_stub__Z10stencil64DPfS_PfS_, .-_Z32__device_stub__Z10stencil64DPfS_PfS_ .globl _Z10stencil64DPfS_ .type _Z10stencil64DPfS_, @function _Z10stencil64DPfS_: .LFB3661: .cfi_startproc endbr64 jmp _Z32__device_stub__Z10stencil64DPfS_PfS_ .cfi_endproc .LFE3661: .size _Z10stencil64DPfS_, .-_Z10stencil64DPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Error allocating d_input: " .LC2: .string "Error allocating d_output: " .LC4: .string "Error copying input data to device: " .LC5: .string "Kernel launch error: " .LC6: .string "Error copying output data to host: " .LC7: .string "Stencil computation completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $16384, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $56, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $16384, %edi movq %rax, %rbp call _Znam@PLT movss .LC0(%rip), %xmm0 movq %rax, %r12 xorl %eax, %eax .L10: movss %xmm0, 0(%rbp,%rax,4) incq %rax cmpq $4096, %rax jne .L10 movq %rsp, %rdi movl $29584, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L11 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L12 .L11: leaq 8(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT .L12: movl $1, %eax jmp .L9 .L13: movl $29584, %edi call _Znam@PLT movq %rax, %rbx xorl %eax, %eax .L15: imull $86, %eax, %ecx movl $-11, %edx leal -11(%rax), %edi .L18: cmpl $63, %edi movslq %ecx, %rsi ja .L16 cmpl $63, %edx ja .L16 movl %eax, %r8d sall $6, %r8d leal -704(%rdx,%r8), %r8d movss 0(%rbp,%r8,4), %xmm0 movss %xmm0, (%rbx,%rsi,4) jmp .L17 .L16: movl $0x00000000, (%rbx,%rsi,4) .L17: incl %edx incl %ecx cmpl $75, %edx jne .L18 incl %eax cmpl $86, %eax jne .L15 movq (%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $29584, %edx call cudaMemcpy@PLT leaq .LC4(%rip), %rsi movl %eax, %r13d testl %eax, %eax jne .L28 xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movl $1, %esi movabsq $68719476752, %rdx movabsq $17179869188, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L21 movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z32__device_stub__Z10stencil64DPfS_PfS_ .L21: call cudaGetLastError@PLT leaq .LC5(%rip), %rsi movl %eax, %r13d testl %eax, %eax jne .L28 movq 8(%rsp), %rsi movl $2, %ecx movl $16384, %edx movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %r13d testl %eax, %eax je .L23 leaq .LC6(%rip), %rsi .L28: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r13d, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT jmp .L12 .L23: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L9: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L24 call __stack_chk_fail@PLT .L24: addq $56, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z10stencil64DPfS_" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi leaq _Z10stencil64DPfS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_075722.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z25__device_stub__stencil64DPfS_ # -- Begin function _Z25__device_stub__stencil64DPfS_ .type _Z25__device_stub__stencil64DPfS_,@function _Z25__device_stub__stencil64DPfS_: # @_Z25__device_stub__stencil64DPfS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z10stencil64DPfS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z25__device_stub__stencil64DPfS_, .Lfunc_end0-_Z25__device_stub__stencil64DPfS_ .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $24, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $16384, %edi # imm = 0x4000 callq _Znam movq %rax, %r14 movl $16384, %edi # imm = 0x4000 callq _Znam movq %rax, %r15 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $29584, %esi # imm = 0x7390 callq hipMalloc testl %eax, %eax je .LBB1_5 # %bb.3: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_8 # %bb.4: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_9 .LBB1_5: leaq 16(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB1_10 # %bb.6: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $27, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_18 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_19 .LBB1_8: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_29 .LBB1_10: movl $29584, %edi # imm = 0x7390 callq _Znam movq %rax, %rbx movq %r14, %rax addq $-2860, %rax # imm = 0xF4D4 xorl %ecx, %ecx movq %rbx, %rdx .LBB1_11: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_12 Depth 2 leal -11(%rcx), %esi xorl %edi, %edi .LBB1_12: # Parent Loop BB1_11 Depth=1 # => This Inner Loop Header: Depth=2 leal -11(%rdi), %r8d orl %esi, %r8d xorps %xmm0, %xmm0 cmpl $63, %r8d ja .LBB1_14 # %bb.13: # in Loop: Header=BB1_12 Depth=2 movss (%rax,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero .LBB1_14: # in Loop: Header=BB1_12 Depth=2 movss %xmm0, (%rdx,%rdi,4) incq %rdi cmpq $86, %rdi jne .LBB1_12 # %bb.15: # in Loop: Header=BB1_11 Depth=1 incq %rcx addq $344, %rdx # imm = 0x158 addq $256, %rax # imm = 0x100 cmpq $86, %rcx jne .LBB1_11 # %bb.16: movq 8(%rsp), %rdi movl $29584, %edx # imm = 0x7390 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_20 # %bb.17: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $36, %edx jmp .LBB1_24 .LBB1_18: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree jmp .LBB1_29 .LBB1_20: movabsq $17179869188, %rdi # imm = 0x400000004 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_22 # %bb.21: movq 8(%rsp), %rdi movq 16(%rsp), %rsi callq _Z25__device_stub__stencil64DPfS_ .LBB1_22: callq hipGetLastError testl %eax, %eax je .LBB1_31 # %bb.23: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $21, %edx .LBB1_24: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_26 # %bb.25: movq %rax, %r14 movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_27 .LBB1_26: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit66 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_28: movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv .LBB1_29: movl $1, %eax .LBB1_30: addq $24, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_31: .cfi_def_cfa_offset 64 movq 16(%rsp), %rsi movl $16384, %edx # imm = 0x4000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_33 # %bb.32: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_28 .LBB1_33: movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %rbx, %rdi callq _ZdaPv movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $43, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB1_30 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10stencil64DPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10stencil64DPfS_,@object # @_Z10stencil64DPfS_ .section .rodata,"a",@progbits .globl _Z10stencil64DPfS_ .p2align 3, 0x0 _Z10stencil64DPfS_: .quad _Z25__device_stub__stencil64DPfS_ .size _Z10stencil64DPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error allocating d_input: " .size .L.str, 27 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error allocating d_output: " .size .L.str.1, 28 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Error copying input data to device: " .size .L.str.2, 37 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Kernel launch error: " .size .L.str.3, 22 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error copying output data to host: " .size .L.str.4, 36 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Stencil computation completed successfully." .size .L.str.5, 44 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10stencil64DPfS_" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__stencil64DPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10stencil64DPfS_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,290
6,014
113,390
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z19graphColoringKernelPiS_S_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R4, 0x1f, PT ; @P0 EXIT ; IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; LDG.E R0, [R2.64] ; IMAD.SHL.U32 R6, R4.reuse, 0x20, RZ ; PRMT R10, RZ, 0x7610, R10 ; IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; IMAD.WIDE R8, R11, 0x4, R6 ; LDG.E R8, [R8.64] ; BSSY B0, 0xe90 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0xe80 ; SHF.R.S32.HI R12, RZ, 0x1f, R11 ; LEA R8, P0, R11, c[0x0][0x168], 0x2 ; LEA.HI.X R9, R11, c[0x0][0x16c], R12, 0x2, P0 ; LDG.E R9, [R8.64] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @P0 BRA 0xe80 ; LDG.E R8, [R6.64] ; IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; BSSY B1, 0xe10 ; @!P0 BRA 0x240 ; LDG.E R12, [R8.64] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x4] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x2a0 ; LDG.E R12, [R8.64+0x4] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x8] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x300 ; LDG.E R12, [R8.64+0x8] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0xc] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x360 ; LDG.E R12, [R8.64+0xc] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x10] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x3c0 ; LDG.E R12, [R8.64+0x10] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x14] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x420 ; LDG.E R12, [R8.64+0x14] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x18] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x480 ; LDG.E R12, [R8.64+0x18] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x1c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x4e0 ; LDG.E R12, [R8.64+0x1c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x20] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x540 ; LDG.E R12, [R8.64+0x20] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x24] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x5a0 ; LDG.E R12, [R8.64+0x24] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x28] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x600 ; LDG.E R12, [R8.64+0x28] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x2c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x660 ; LDG.E R12, [R8.64+0x2c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x30] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x6c0 ; LDG.E R12, [R8.64+0x30] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x34] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x720 ; LDG.E R12, [R8.64+0x34] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x38] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x780 ; LDG.E R12, [R8.64+0x38] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x3c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x7e0 ; LDG.E R12, [R8.64+0x3c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x40] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x840 ; LDG.E R12, [R8.64+0x40] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x44] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x8a0 ; LDG.E R12, [R8.64+0x44] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x48] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x900 ; LDG.E R12, [R8.64+0x48] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x4c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x960 ; LDG.E R12, [R8.64+0x4c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x50] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0x9c0 ; LDG.E R12, [R8.64+0x50] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x54] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xa20 ; LDG.E R12, [R8.64+0x54] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x58] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xa80 ; LDG.E R12, [R8.64+0x58] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x5c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xae0 ; LDG.E R12, [R8.64+0x5c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x60] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xb40 ; LDG.E R12, [R8.64+0x60] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x64] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xba0 ; LDG.E R12, [R8.64+0x64] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x68] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xc00 ; LDG.E R12, [R8.64+0x68] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x6c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xc60 ; LDG.E R12, [R8.64+0x6c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x70] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xcc0 ; LDG.E R12, [R8.64+0x70] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x74] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xd20 ; LDG.E R12, [R8.64+0x74] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x78] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BRA 0xd80 ; LDG.E R12, [R8.64+0x78] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @!P1 BRA 0xe00 ; LDG.E R12, [R6.64+0x7c] ; ISETP.NE.AND P1, PT, R12, RZ, PT ; @!P1 BREAK B1 ; @!P1 BRA 0xe60 ; LDG.E R12, [R8.64+0x7c] ; ISETP.NE.AND P1, PT, R12, R13, PT ; @P1 BREAK B1 ; @P1 BRA 0xe60 ; BSYNC B1 ; IADD3 R13, R13, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R13, 0x21, PT ; @P1 CALL.REL.NOINC 0xe50 ; BRA 0x1f0 ; BRA 0xe80 ; STG.E [R4.64], R13 ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; BSYNC B0 ; WARPSYNC 0xffffffff ; IADD3 R11, R11, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R11, 0x20, PT ; @P0 CALL.REL.NOINC 0xee0 ; BRA 0xf0 ; LOP3.LUT P0, RZ, R10, 0xff, RZ, 0xc0, !PT ; @!P0 BRA 0xf30 ; LDG.E R5, [R4.64] ; STG.E [R2.64], R5 ; EXIT ; S2R R0, SR_LANEID ; VOTEU.ANY UR6, UPT, PT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; UFLO.U32 UR7, UR6 ; POPC R5, UR6 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; EXIT ; BRA 0xfc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19graphColoringKernelPiS_S_S_ ; -- Begin function _Z19graphColoringKernelPiS_S_S_ .globl _Z19graphColoringKernelPiS_S_S_ .p2align 8 .type _Z19graphColoringKernelPiS_S_S_,@function _Z19graphColoringKernelPiS_S_S_: ; @_Z19graphColoringKernelPiS_S_S_ ; %bb.0: s_load_b32 s2, s[0:1], 0x2c s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 32, v2 s_cbranch_execz .LBB0_27 ; %bb.1: s_load_b256 s[0:7], s[0:1], 0x0 v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b32_e32 v4, 5, v2 s_mov_b32 s11, 0 ; implicit-def: $sgpr10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[6:7], 2, v[2:3] v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b64 v[10:11], 2, v[4:5] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s2, v6 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v2, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo global_load_b32 v9, v[0:1], off v_add_co_u32 v5, vcc_lo, s0, v10 v_add_co_ci_u32_e32 v6, vcc_lo, s1, v11, vcc_lo v_mov_b32_e32 v10, 0 s_mov_b32 s5, 0 s_mov_b32 s4, 0 .LBB0_2: ; =>This Loop Header: Depth=1 ; Child Loop BB0_5 Depth 2 ; Child Loop BB0_7 Depth 3 s_delay_alu instid0(SALU_CYCLE_1) v_or_b32_e32 v7, s4, v4 s_and_not1_b32 s8, s10, exec_lo s_and_b32 s9, s11, exec_lo s_mov_b32 s12, exec_lo s_or_b32 s10, s8, s9 v_ashrrev_i32_e32 v8, 31, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[7:8] v_add_co_u32 v7, vcc_lo, s0, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo global_load_b32 v7, v[7:8], off s_waitcnt vmcnt(0) v_cmpx_ne_u32_e32 0, v7 s_cbranch_execz .LBB0_20 ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 s_lshl_b64 s[8:9], s[4:5], 2 s_mov_b32 s13, exec_lo s_add_u32 s8, s2, s8 s_addc_u32 s9, s3, s9 global_load_b32 v7, v10, s[8:9] s_waitcnt vmcnt(0) v_cmpx_eq_u32_e64 v7, v9 s_cbranch_execz .LBB0_19 ; %bb.4: ; %.preheader51.preheader ; in Loop: Header=BB0_2 Depth=1 v_mov_b32_e32 v11, 1 s_mov_b32 s14, 0 s_mov_b32 s19, s11 ; implicit-def: $sgpr15 ; implicit-def: $sgpr16 ; implicit-def: $sgpr17 ; implicit-def: $sgpr18 .LBB0_5: ; %.preheader51 ; Parent Loop BB0_2 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_7 Depth 3 s_and_not1_b32 s8, s18, exec_lo s_and_b32 s9, s19, exec_lo s_and_not1_b32 s17, s17, exec_lo s_or_b32 s18, s8, s9 s_or_b32 s16, s16, exec_lo s_mov_b32 s20, exec_lo v_cmpx_gt_i32_e32 33, v11 s_cbranch_execz .LBB0_17 ; %bb.6: ; %.preheader.preheader ; in Loop: Header=BB0_5 Depth=2 v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5 s_mov_b32 s24, -1 s_mov_b32 s23, 0 s_mov_b64 s[8:9], s[2:3] s_mov_b32 s29, 0 ; implicit-def: $sgpr22 ; implicit-def: $sgpr21 ; implicit-def: $sgpr25 ; implicit-def: $sgpr27 ; implicit-def: $sgpr28 ; implicit-def: $sgpr26 .LBB0_7: ; %.preheader ; Parent Loop BB0_2 Depth=1 ; Parent Loop BB0_5 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b32 v12, v[7:8], off s_mov_b32 s33, -1 s_mov_b32 s31, exec_lo ; implicit-def: $sgpr30 s_waitcnt vmcnt(0) v_cmpx_ne_u32_e32 0, v12 s_cbranch_execz .LBB0_9 ; %bb.8: ; in Loop: Header=BB0_7 Depth=3 global_load_b32 v12, v10, s[8:9] s_mov_b32 s30, -1 s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, v12, v11 s_or_not1_b32 s33, vcc_lo, exec_lo .LBB0_9: ; %Flow87 ; in Loop: Header=BB0_7 Depth=3 s_or_b32 exec_lo, exec_lo, s31 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 s26, s26, exec_lo s_and_b32 s30, s30, exec_lo s_and_not1_b32 s28, s28, exec_lo s_or_b32 s26, s26, s30 s_and_b32 s30, s24, exec_lo s_and_not1_b32 s27, s27, exec_lo s_and_b32 s34, s0, exec_lo s_mov_b32 s31, -1 s_or_b32 s28, s28, s30 s_or_b32 s27, s27, s34 s_and_saveexec_b32 s30, s33 s_cbranch_execz .LBB0_11 ; %bb.10: ; in Loop: Header=BB0_7 Depth=3 s_add_i32 s33, s29, 1 s_cmp_lt_u32 s29, 31 v_add_co_u32 v7, vcc_lo, v7, 4 s_cselect_b32 s34, -1, 0 s_add_u32 s8, s8, 4 s_addc_u32 s9, s9, 0 s_cmp_eq_u32 s33, 32 v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo s_cselect_b32 s29, -1, 0 s_and_not1_b32 s28, s28, exec_lo s_and_b32 s24, s24, exec_lo s_and_not1_b32 s27, s27, exec_lo s_and_b32 s31, s34, exec_lo s_and_not1_b32 s26, s26, exec_lo s_or_b32 s28, s28, s24 s_or_b32 s27, s27, s31 s_or_not1_b32 s31, s29, exec_lo s_mov_b32 s29, s33 s_mov_b32 s24, s34 .LBB0_11: ; %Flow88 ; in Loop: Header=BB0_7 Depth=3 s_or_b32 exec_lo, exec_lo, s30 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s30, exec_lo, s31 s_or_b32 s23, s30, s23 s_and_not1_b32 s25, s25, exec_lo s_and_b32 s30, s26, exec_lo s_and_not1_b32 s21, s21, exec_lo s_or_b32 s25, s25, s30 s_and_b32 s30, s28, exec_lo s_and_not1_b32 s22, s22, exec_lo s_and_b32 s31, s27, exec_lo s_or_b32 s21, s21, s30 s_or_b32 s22, s22, s31 s_and_not1_b32 exec_lo, exec_lo, s23 s_cbranch_execnz .LBB0_7 ; %bb.12: ; %loop.exit.guard ; in Loop: Header=BB0_5 Depth=2 s_or_b32 exec_lo, exec_lo, s23 s_xor_b32 s23, s25, -1 ; implicit-def: $sgpr9 ; implicit-def: $sgpr8 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s24, s23 s_xor_b32 s23, exec_lo, s24 s_cbranch_execz .LBB0_14 ; %bb.13: ; %.critedge ; in Loop: Header=BB0_5 Depth=2 s_mov_b32 s8, -1 s_and_b32 s9, s22, exec_lo global_store_b32 v[2:3], v11, off .LBB0_14: ; %Flow86 ; in Loop: Header=BB0_5 Depth=2 s_and_not1_saveexec_b32 s22, s23 ; %bb.15: ; in Loop: Header=BB0_5 Depth=2 v_add_nc_u32_e32 v11, 1, v11 s_and_not1_b32 s9, s9, exec_lo s_and_b32 s21, s21, exec_lo s_and_not1_b32 s8, s8, exec_lo s_and_b32 s19, s19, exec_lo s_or_b32 s9, s9, s21 s_or_b32 s8, s8, s19 ; %bb.16: ; in Loop: Header=BB0_5 Depth=2 s_or_b32 exec_lo, exec_lo, s22 s_xor_b32 s9, s9, -1 s_and_not1_b32 s18, s18, exec_lo s_and_b32 s8, s8, exec_lo s_and_not1_b32 s17, s17, exec_lo s_and_not1_b32 s16, s16, exec_lo s_and_b32 s9, s9, exec_lo s_or_b32 s18, s18, s8 s_or_b32 s17, s17, s8 s_or_b32 s16, s16, s9 ; implicit-def: $sgpr19 .LBB0_17: ; %Flow89 ; in Loop: Header=BB0_5 Depth=2 s_or_b32 exec_lo, exec_lo, s20 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s8, exec_lo, s16 s_or_b32 s14, s8, s14 s_and_not1_b32 s8, s19, exec_lo s_and_b32 s9, s17, exec_lo s_and_not1_b32 s15, s15, exec_lo s_and_b32 s20, s18, exec_lo s_or_b32 s19, s8, s9 s_or_b32 s15, s15, s20 s_and_not1_b32 exec_lo, exec_lo, s14 s_cbranch_execnz .LBB0_5 ; %bb.18: ; %Flow90 ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s14 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s8, s11, exec_lo s_and_b32 s9, s15, exec_lo s_or_b32 s11, s8, s9 .LBB0_19: ; %Flow91 ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s13 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s8, s10, exec_lo s_and_b32 s9, s11, exec_lo ; implicit-def: $sgpr11 s_or_b32 s10, s8, s9 .LBB0_20: ; %.loopexit ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 s8, s11, exec_lo s_and_b32 s9, s10, exec_lo s_add_i32 s4, s4, 1 s_or_b32 s11, s8, s9 s_cmp_eq_u32 s4, 32 s_cbranch_scc0 .LBB0_2 ; %bb.21: s_xor_b32 s0, s10, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s1, s0 s_xor_b32 s0, exec_lo, s1 s_cbranch_execz .LBB0_25 ; %bb.22: s_mov_b32 s2, exec_lo s_mov_b32 s1, exec_lo v_mbcnt_lo_u32_b32 v0, s2, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_24 ; %bb.23: s_bcnt1_i32_b32 s2, s2 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 global_atomic_add_u32 v0, v1, s[6:7] .LBB0_24: ; %Flow s_or_b32 exec_lo, exec_lo, s1 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $vgpr0_vgpr1 .LBB0_25: ; %Flow84 s_and_not1_saveexec_b32 s0, s0 s_cbranch_execz .LBB0_27 ; %bb.26: global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) global_store_b32 v[0:1], v2, off .LBB0_27: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19graphColoringKernelPiS_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 35 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19graphColoringKernelPiS_S_S_, .Lfunc_end0-_Z19graphColoringKernelPiS_S_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 936 ; NumSgprs: 37 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 4 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 37 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19graphColoringKernelPiS_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 37 .sgpr_spill_count: 0 .symbol: _Z19graphColoringKernelPiS_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00041583_00000000-6_cuda_code_017022.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4002: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE4002: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3998: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3998: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_ .type _Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_, @function _Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_: .LFB4024: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movq %rcx, (%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z19graphColoringKernelPiS_S_S_(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L8: movq 136(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4024: .size _Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_, .-_Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_ .globl _Z19graphColoringKernelPiS_S_S_ .type _Z19graphColoringKernelPiS_S_S_, @function _Z19graphColoringKernelPiS_S_S_: .LFB4025: .cfi_startproc endbr64 jmp _Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_ .cfi_endproc .LFE4025: .size _Z19graphColoringKernelPiS_S_S_, .-_Z19graphColoringKernelPiS_S_S_ .section .rodata.str1.1 .LC3: .string "_Z19graphColoringKernelPiS_S_S_" .section .text.startup,"ax",@progbits .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4027: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC3(%rip), %rdx movq %rax, %rdi leaq _Z19graphColoringKernelPiS_S_S_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE4027: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .rodata._ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.str1.1,"aMS",@progbits,1 .LC4: .string "cannot create std::vector larger than max_size()" .section .text._ZNSt6vectorIiSaIiEEC2EmRKiRKS0_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC5EmRKiRKS0_,comdat .align 2 .weak _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_ .type _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_, @function _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_: .LFB4337: .cfi_startproc endbr64 movabsq $2305843009213693951, %rax pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 pushq %rcx .cfi_def_cfa_offset 48 cmpq %rsi, %rax jnb .L16 leaq .LC4(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L16: movq %rdx, %r13 xorl %edx, %edx movq %rdi, %rbx movq %rsi, %rbp movq %rdx, (%rdi) leaq 0(,%rsi,4), %r12 xorl %eax, %eax movq %rdx, 8(%rdi) movq %rdx, 16(%rdi) testq %rsi, %rsi je .L17 movq %r12, %rdi call _Znwm@PLT .L17: addq %rax, %r12 movq %rax, (%rbx) movq %r12, 16(%rbx) testq %rbp, %rbp je .L18 movl 0(%r13), %edx .L19: cmpq %rax, %r12 je .L18 movl %edx, (%rax) addq $4, %rax jmp .L19 .L18: movq %rax, 8(%rbx) popq %rax .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4337: .size _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_, .-_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_ .weak _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .set _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_,_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_ .section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat .align 2 .weak _ZNSt6vectorIiSaIiEED2Ev .type _ZNSt6vectorIiSaIiEED2Ev, @function _ZNSt6vectorIiSaIiEED2Ev: .LFB4340: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L27 movq 16(%rdi), %rsi movq %rax, %rdi subq %rax, %rsi jmp _ZdlPvm@PLT .L27: ret .cfi_endproc .LFE4340: .size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev .weak _ZNSt6vectorIiSaIiEED1Ev .set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev .section .rodata.str1.1 .LC5: .string "cudaMalloc d_adjMatrix" .LC6: .string "cudaMalloc d_colors" .LC7: .string "cudaMalloc d_nextColors" .LC8: .string "cudaMalloc d_done" .LC9: .string "cudaMemcpy d_adjMatrix" .LC10: .string "cudaMemcpy d_colors" .LC11: .string "cudaMemcpy d_nextColors" .LC12: .string "cudaMemcpy d_done" .LC13: .string "cudaStreamCreate" .LC14: .string "cudaMemcpyAsync d_done" .LC15: .string "graphColoringKernel launch" .LC16: .string "cudaStreamSynchronize" .LC17: .string "cudaMemcpy colors" .LC18: .string "Graph coloring result:" .LC19: .string "Node " .LC20: .string ": Color " .LC21: .string "cudaFree d_adjMatrix" .LC22: .string "cudaFree d_colors" .LC23: .string "cudaFree d_nextColors" .LC24: .string "cudaFree d_done" .LC25: .string "cudaStreamDestroy" .section .text.startup .globl main .type main, @function main: .LFB3999: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA3999 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 xorl %edi, %edi movl $1024, %esi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $184, %rsp .cfi_def_cfa_offset 240 movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 120(%rsp), %rax movl %edi, 144(%rsp) leaq 144(%rsp), %rbp movq %rax, (%rsp) leaq 96(%rsp), %rax movq (%rsp), %rcx movq %rbp, %rdx movq %rax, %rdi movq %rax, 8(%rsp) .LEHB0: call _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .LEHE0: movq 96(%rsp), %rbx xorl %edx, %edx .L30: movl %edx, %esi movl %edx, %eax incl %edx movl %edx, %ecx addl $31, %eax sall $5, %esi andl $31, %ecx andl $31, %eax addl %esi, %ecx addl %esi, %eax movslq %ecx, %rcx cltq movl $1, (%rbx,%rcx,4) movl $1, (%rbx,%rax,4) cmpl $32, %edx jne .L30 xorl %esi, %esi leaq 84(%rsp), %r12 movq (%rsp), %rdi movq %rbp, %rdx movl %esi, 144(%rsp) movq %r12, %rcx movl $32, %esi .LEHB1: call _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .LEHE1: xorl %ecx, %ecx movq %r12, %rdx movl $32, %esi movq %rbp, %rdi movl %ecx, 84(%rsp) leaq 72(%rsp), %rcx .LEHB2: call _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .LEHE2: xorl %edx, %edx leaq 32(%rsp), %rdi movl $4096, %esi movl %edx, 28(%rsp) .LEHB3: call cudaMalloc@PLT movl %eax, %edi leaq .LC5(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc leaq 40(%rsp), %rdi movl $128, %esi call cudaMalloc@PLT movl %eax, %edi leaq .LC6(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc leaq 48(%rsp), %rdi movl $128, %esi call cudaMalloc@PLT movl %eax, %edi leaq .LC7(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc leaq 56(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl %eax, %edi leaq .LC8(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 32(%rsp), %rdi movl $1, %ecx movl $4096, %edx movq %rbx, %rsi call cudaMemcpy@PLT movl %eax, %edi leaq .LC9(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 120(%rsp), %r12 movq 40(%rsp), %rdi movl $1, %ecx movl $128, %edx movq %r12, %rsi call cudaMemcpy@PLT movl %eax, %edi leaq .LC10(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 48(%rsp), %rdi movl $1, %ecx movl $128, %edx movq 144(%rsp), %rsi call cudaMemcpy@PLT movl %eax, %edi leaq .LC11(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc leaq 28(%rsp), %rbx movq 56(%rsp), %rdi movl $1, %ecx movl $4, %edx movq %rbx, %rsi call cudaMemcpy@PLT movl %eax, %edi leaq .LC12(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movabsq $4294967297, %rax leaq 64(%rsp), %rdi movl $1, 92(%rsp) movq %rax, 76(%rsp) movq %rax, 84(%rsp) call cudaStreamCreate@PLT movl %eax, %edi leaq .LC13(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc leaq .LC14(%rip), %r13 .L31: cmpl $31, 28(%rsp) jg .L50 movq 64(%rsp), %r8 movq 56(%rsp), %rdi xorl %eax, %eax movq %rbx, %rsi movl $1, %ecx movl $4, %edx movl %eax, 28(%rsp) call cudaMemcpyAsync@PLT movl %eax, %edi movq %r13, %rsi call _Z14checkCudaError9cudaErrorPKc movl $256, 72(%rsp) movl 80(%rsp), %ecx xorl %r8d, %r8d movq 64(%rsp), %r9 movq 72(%rsp), %rdx movq 84(%rsp), %rdi movl 92(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L32 .L34: call cudaGetLastError@PLT movl %eax, %edi leaq .LC15(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc jmp .L51 .L32: movq 56(%rsp), %rcx movq 48(%rsp), %rdx movq 40(%rsp), %rsi movq 32(%rsp), %rdi call _Z45__device_stub__Z19graphColoringKernelPiS_S_S_PiS_S_S_ jmp .L34 .L51: movq 64(%rsp), %r8 movq 56(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi movl $4, %edx call cudaMemcpyAsync@PLT movl %eax, %edi movq %r13, %rsi call _Z14checkCudaError9cudaErrorPKc movq 64(%rsp), %rdi call cudaStreamSynchronize@PLT movl %eax, %edi leaq .LC16(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc jmp .L31 .L50: movq 40(%rsp), %rsi movl $2, %ecx movl $128, %edx movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %edi leaq .LC17(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc leaq _ZSt4cout(%rip), %r13 leaq .LC18(%rip), %rsi movq %r13, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT xorl %ebx, %ebx leaq .LC19(%rip), %r14 .L36: movq %r14, %rsi movq %r13, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebx, %esi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC20(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl (%r12,%rbx,4), %esi movq %rax, %rdi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT incq %rbx cmpq $32, %rbx jne .L36 movq 32(%rsp), %rdi call cudaFree@PLT movl %eax, %edi leaq .LC21(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 40(%rsp), %rdi call cudaFree@PLT movl %eax, %edi leaq .LC22(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 48(%rsp), %rdi call cudaFree@PLT movl %eax, %edi leaq .LC23(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 56(%rsp), %rdi call cudaFree@PLT movl %eax, %edi leaq .LC24(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc movq 64(%rsp), %rdi call cudaStreamDestroy@PLT movl %eax, %edi leaq .LC25(%rip), %rsi call _Z14checkCudaError9cudaErrorPKc .LEHE3: leaq 144(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev leaq 120(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev leaq 96(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 168(%rsp), %rax subq %fs:40, %rax je .L41 jmp .L48 .L44: endbr64 movq %rax, %rbx .L37: movq %rbp, %rdi call _ZNSt6vectorIiSaIiEED1Ev jmp .L38 .L43: endbr64 movq %rax, %rbx .L38: movq (%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev jmp .L39 .L42: endbr64 movq %rax, %rbx .L39: movq 8(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 168(%rsp), %rax subq %fs:40, %rax jne .L48 movq %rbx, %rdi .LEHB4: call _Unwind_Resume@PLT .LEHE4: .L48: call __stack_chk_fail@PLT .L41: addq $184, %rsp .cfi_def_cfa_offset 56 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3999: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA3999: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE3999-.LLSDACSB3999 .LLSDACSB3999: .uleb128 .LEHB0-.LFB3999 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB3999 .uleb128 .LEHE1-.LEHB1 .uleb128 .L42-.LFB3999 .uleb128 0 .uleb128 .LEHB2-.LFB3999 .uleb128 .LEHE2-.LEHB2 .uleb128 .L43-.LFB3999 .uleb128 0 .uleb128 .LEHB3-.LFB3999 .uleb128 .LEHE3-.LEHB3 .uleb128 .L44-.LFB3999 .uleb128 0 .uleb128 .LEHB4-.LFB3999 .uleb128 .LEHE4-.LEHB4 .uleb128 0 .uleb128 0 .LLSDACSE3999: .section .text.startup .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_017022.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z34__device_stub__graphColoringKernelPiS_S_S_ # -- Begin function _Z34__device_stub__graphColoringKernelPiS_S_S_ .type _Z34__device_stub__graphColoringKernelPiS_S_S_,@function _Z34__device_stub__graphColoringKernelPiS_S_S_: # @_Z34__device_stub__graphColoringKernelPiS_S_S_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 16(%rsp), %rdx movq %rcx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z19graphColoringKernelPiS_S_S_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z34__device_stub__graphColoringKernelPiS_S_S_, .Lfunc_end0-_Z34__device_stub__graphColoringKernelPiS_S_S_ .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: # %.noexc pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4096, %edi # imm = 0x1000 callq _Znwm movq %rax, %rbx xorl %ebp, %ebp movl $4096, %edx # imm = 0x1000 movq %rax, %rdi xorl %esi, %esi callq memset@PLT movl $31, %eax movb $1, %cl movl $1, %edx .LBB2_1: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit # =>This Inner Loop Header: Depth=1 movl %eax, %esi andl $31, %esi addl %ebp, %esi movzbl %cl, %ecx movl %ecx, %edi andl $31, %edi addl %ebp, %edi movl %edx, (%rbx,%rdi,4) movl %edx, (%rbx,%rsi,4) incl %eax addl $32, %ebp incb %cl cmpl $63, %eax jne .LBB2_1 # %bb.2: .Ltmp0: movl $128, %edi callq _Znwm .Ltmp1: # %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i30.preheader movq %rax, %r14 xorps %xmm0, %xmm0 movups %xmm0, 112(%rax) movups %xmm0, 96(%rax) movups %xmm0, 80(%rax) movups %xmm0, 64(%rax) movups %xmm0, 48(%rax) movups %xmm0, 32(%rax) movups %xmm0, 16(%rax) movups %xmm0, (%rax) .Ltmp3: movl $128, %edi callq _Znwm .Ltmp4: # %bb.4: # %.lr.ph.i.i.i.i.i.i.i.i.i35.preheader movq %rax, %r15 xorps %xmm0, %xmm0 movups %xmm0, 112(%rax) movups %xmm0, 96(%rax) movups %xmm0, 80(%rax) movups %xmm0, 64(%rax) movups %xmm0, 48(%rax) movups %xmm0, 32(%rax) movups %xmm0, 16(%rax) movups %xmm0, (%rax) movl $0, 12(%rsp) .Ltmp6: leaq 48(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc .Ltmp7: # %bb.5: .Ltmp8: movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp9: # %bb.6: .Ltmp10: leaq 32(%rsp), %rdi movl $128, %esi callq hipMalloc .Ltmp11: # %bb.7: .Ltmp12: movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp13: # %bb.8: .Ltmp14: leaq 40(%rsp), %rdi movl $128, %esi callq hipMalloc .Ltmp15: # %bb.9: .Ltmp16: movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp17: # %bb.10: .Ltmp18: leaq 24(%rsp), %rdi movl $4, %esi callq hipMalloc .Ltmp19: # %bb.11: .Ltmp20: movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp21: # %bb.12: movq 48(%rsp), %rdi .Ltmp22: movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy .Ltmp23: # %bb.13: .Ltmp24: movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp25: # %bb.14: movq 32(%rsp), %rdi .Ltmp26: movl $128, %edx movq %r14, %rsi movl $1, %ecx callq hipMemcpy .Ltmp27: # %bb.15: .Ltmp28: movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp29: # %bb.16: movq 40(%rsp), %rdi .Ltmp30: movl $128, %edx movq %r15, %rsi movl $1, %ecx callq hipMemcpy .Ltmp31: # %bb.17: .Ltmp32: movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp33: # %bb.18: movq 24(%rsp), %rdi .Ltmp34: leaq 12(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy .Ltmp35: # %bb.19: .Ltmp36: movl $.L.str.10, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp37: # %bb.20: .Ltmp39: leaq 16(%rsp), %rdi callq hipStreamCreate .Ltmp40: # %bb.21: .Ltmp41: movl $.L.str.11, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp42: # %bb.22: # %.preheader.preheader leaq 12(%rsp), %r12 movabsq $4294967297, %r13 # imm = 0x100000001 movabsq $4294967552, %rbp # imm = 0x100000100 .LBB2_23: # %.preheader # =>This Inner Loop Header: Depth=1 cmpl $31, 12(%rsp) jg .LBB2_39 # %bb.24: # in Loop: Header=BB2_23 Depth=1 movl $0, 12(%rsp) movq 24(%rsp), %rdi movq 16(%rsp), %r8 .Ltmp91: movl $4, %edx movq %r12, %rsi movl $1, %ecx callq hipMemcpyAsync .Ltmp92: # %bb.25: # in Loop: Header=BB2_23 Depth=1 .Ltmp93: movl $.L.str.12, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp94: # %bb.26: # in Loop: Header=BB2_23 Depth=1 movq 16(%rsp), %r9 .Ltmp95: movq %r13, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d callq __hipPushCallConfiguration .Ltmp96: # %bb.27: # in Loop: Header=BB2_23 Depth=1 testl %eax, %eax jne .LBB2_29 # %bb.28: # in Loop: Header=BB2_23 Depth=1 movq 48(%rsp), %rdi movq 32(%rsp), %rsi movq 40(%rsp), %rdx movq 24(%rsp), %rcx .Ltmp97: callq _Z34__device_stub__graphColoringKernelPiS_S_S_ .Ltmp98: .LBB2_29: # in Loop: Header=BB2_23 Depth=1 .Ltmp99: callq hipGetLastError .Ltmp100: # %bb.30: # in Loop: Header=BB2_23 Depth=1 .Ltmp101: movl $.L.str.13, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp102: # %bb.31: # in Loop: Header=BB2_23 Depth=1 movq 24(%rsp), %rsi movq 16(%rsp), %r8 .Ltmp103: movl $4, %edx movq %r12, %rdi movl $2, %ecx callq hipMemcpyAsync .Ltmp104: # %bb.32: # in Loop: Header=BB2_23 Depth=1 .Ltmp105: movl $.L.str.12, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp106: # %bb.33: # in Loop: Header=BB2_23 Depth=1 movq 16(%rsp), %rdi .Ltmp107: callq hipStreamSynchronize .Ltmp108: # %bb.34: # in Loop: Header=BB2_23 Depth=1 .Ltmp109: movl $.L.str.14, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp110: jmp .LBB2_23 .LBB2_39: movq 32(%rsp), %rsi .Ltmp43: movl $128, %edx movq %r14, %rdi movl $2, %ecx callq hipMemcpy .Ltmp44: # %bb.40: .Ltmp45: movl $.L.str.15, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp46: # %bb.41: .Ltmp47: movl $_ZSt4cout, %r12d movl $_ZSt4cout, %edi movl $.L.str.16, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp48: # %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cout(%rip), %rax addq -24(%rax), %r12 .Ltmp49: movq %r12, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc .Ltmp50: # %bb.43: # %.noexc63 .Ltmp51: movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .Ltmp52: # %bb.44: # %.noexc64 .Ltmp53: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp54: # %bb.45: # %_ZNSolsEPFRSoS_E.exit.preheader.preheader xorl %r12d, %r12d .LBB2_46: # %_ZNSolsEPFRSoS_E.exit.preheader # =>This Inner Loop Header: Depth=1 .Ltmp55: movl $_ZSt4cout, %edi movl $.L.str.17, %esi movl $5, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp56: # %bb.47: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit43 # in Loop: Header=BB2_46 Depth=1 .Ltmp57: movl $_ZSt4cout, %edi movl %r12d, %esi callq _ZNSolsEi .Ltmp58: # %bb.48: # in Loop: Header=BB2_46 Depth=1 .Ltmp59: movq %rax, %r13 movl $.L.str.18, %esi movl $8, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp60: # %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45 # in Loop: Header=BB2_46 Depth=1 movl (%r14,%r12,4), %esi .Ltmp61: movq %r13, %rdi callq _ZNSolsEi .Ltmp62: # %bb.50: # in Loop: Header=BB2_46 Depth=1 movq %rax, %r13 movq (%rax), %rax movq -24(%rax), %rdi addq %r13, %rdi .Ltmp63: movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc .Ltmp64: # %bb.51: # %.noexc66 # in Loop: Header=BB2_46 Depth=1 .Ltmp65: movsbl %al, %esi movq %r13, %rdi callq _ZNSo3putEc .Ltmp66: # %bb.52: # %.noexc67 # in Loop: Header=BB2_46 Depth=1 .Ltmp67: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp68: # %bb.53: # %_ZNSolsEPFRSoS_E.exit47 # in Loop: Header=BB2_46 Depth=1 incq %r12 cmpq $32, %r12 jne .LBB2_46 # %bb.54: movq 48(%rsp), %rdi .Ltmp70: callq hipFree .Ltmp71: # %bb.55: .Ltmp72: movl $.L.str.19, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp73: # %bb.56: movq 32(%rsp), %rdi .Ltmp74: callq hipFree .Ltmp75: # %bb.57: .Ltmp76: movl $.L.str.20, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp77: # %bb.58: movq 40(%rsp), %rdi .Ltmp78: callq hipFree .Ltmp79: # %bb.59: .Ltmp80: movl $.L.str.21, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp81: # %bb.60: movq 24(%rsp), %rdi .Ltmp82: callq hipFree .Ltmp83: # %bb.61: .Ltmp84: movl $.L.str.22, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp85: # %bb.62: movq 16(%rsp), %rdi .Ltmp86: callq hipStreamDestroy .Ltmp87: # %bb.63: .Ltmp88: movl $.L.str.23, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .Ltmp89: # %bb.64: # %_ZNSt6vectorIiSaIiEED2Ev.exit51 movq %r15, %rdi callq _ZdlPv movq %r14, %rdi callq _ZdlPv movq %rbx, %rdi callq _ZdlPv xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_36: .cfi_def_cfa_offset 112 .Ltmp5: movq %rax, %r12 jmp .LBB2_67 .LBB2_35: .Ltmp2: movq %rax, %r12 jmp .LBB2_68 .LBB2_37: .Ltmp38: jmp .LBB2_66 .LBB2_38: # %.loopexit.split-lp .Ltmp90: jmp .LBB2_66 .LBB2_69: .Ltmp69: jmp .LBB2_66 .LBB2_65: # %.loopexit .Ltmp111: .LBB2_66: # %_ZNSt6vectorIiSaIiEED2Ev.exit53 movq %rax, %r12 movq %r15, %rdi callq _ZdlPv .LBB2_67: # %_ZNSt6vectorIiSaIiEED2Ev.exit55 movq %r14, %rdi callq _ZdlPv .LBB2_68: # %_ZNSt6vectorIiSaIiEED2Ev.exit57 movq %rbx, %rdi callq _ZdlPv movq %r12, %rdi callq _Unwind_Resume@PLT .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table2: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5 .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp37-.Ltmp6 # Call between .Ltmp6 and .Ltmp37 .uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38 .byte 0 # On action: cleanup .uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp42-.Ltmp39 # Call between .Ltmp39 and .Ltmp42 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp91-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp110-.Ltmp91 # Call between .Ltmp91 and .Ltmp110 .uleb128 .Ltmp111-.Lfunc_begin0 # jumps to .Ltmp111 .byte 0 # On action: cleanup .uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp54-.Ltmp43 # Call between .Ltmp43 and .Ltmp54 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp68-.Ltmp55 # Call between .Ltmp55 and .Ltmp68 .uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69 .byte 0 # On action: cleanup .uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp89-.Ltmp70 # Call between .Ltmp70 and .Ltmp89 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp89-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Lfunc_end2-.Ltmp89 # Call between .Ltmp89 and .Lfunc_end2 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19graphColoringKernelPiS_S_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z19graphColoringKernelPiS_S_S_,@object # @_Z19graphColoringKernelPiS_S_S_ .section .rodata,"a",@progbits .globl _Z19graphColoringKernelPiS_S_S_ .p2align 3, 0x0 _Z19graphColoringKernelPiS_S_S_: .quad _Z34__device_stub__graphColoringKernelPiS_S_S_ .size _Z19graphColoringKernelPiS_S_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMalloc d_adjMatrix" .size .L.str.3, 22 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipMalloc d_colors" .size .L.str.4, 19 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipMalloc d_nextColors" .size .L.str.5, 23 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "hipMalloc d_done" .size .L.str.6, 17 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipMemcpy d_adjMatrix" .size .L.str.7, 22 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "hipMemcpy d_colors" .size .L.str.8, 19 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipMemcpy d_nextColors" .size .L.str.9, 23 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "hipMemcpy d_done" .size .L.str.10, 17 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "hipStreamCreate" .size .L.str.11, 16 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "hipMemcpyAsync d_done" .size .L.str.12, 22 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "graphColoringKernel launch" .size .L.str.13, 27 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "hipStreamSynchronize" .size .L.str.14, 21 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "hipMemcpy colors" .size .L.str.15, 17 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "Graph coloring result:" .size .L.str.16, 23 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "Node " .size .L.str.17, 6 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz ": Color " .size .L.str.18, 9 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "hipFree d_adjMatrix" .size .L.str.19, 20 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "hipFree d_colors" .size .L.str.20, 17 .type .L.str.21,@object # @.str.21 .L.str.21: .asciz "hipFree d_nextColors" .size .L.str.21, 21 .type .L.str.22,@object # @.str.22 .L.str.22: .asciz "hipFree d_done" .size .L.str.22, 15 .type .L.str.23,@object # @.str.23 .L.str.23: .asciz "hipStreamDestroy" .size .L.str.23, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z19graphColoringKernelPiS_S_S_" .size .L__unnamed_1, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__graphColoringKernelPiS_S_S_ .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z19graphColoringKernelPiS_S_S_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z13infoMapKernelPiPfS0_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R30, SR_CTAID.X ; IMAD.MOV.U32 R31, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R7, SR_TID.X ; IMAD R30, R30, c[0x0][0x0], R7 ; IMAD.WIDE R32, R30, R31, c[0x0][0x160] ; LDG.E R0, [R32.64] ; STS [R7.X4], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R4, [R32.64] ; IMAD.WIDE R4, R4, R31, c[0x0][0x170] ; LDG.E R5, [R4.64] ; IMAD.WIDE R30, R30, R31, c[0x0][0x168] ; LDG.E R2, [R30.64] ; BSSY B0, 0x1b0 ; MUFU.RCP R6, R5 ; FCHK P0, R2, R5 ; FFMA R3, -R5, R6, 1 ; FFMA R3, R6, R3, R6 ; FFMA R6, R2, R3, RZ ; FFMA R7, -R5, R6, R2 ; FFMA R26, R3, R7, R6 ; @!P0 BRA 0x1a0 ; MOV R4, 0x1a0 ; CALL.REL.NOINC 0xf30 ; BSYNC B0 ; FSETP.GEU.AND P1, PT, R26, 1.175494350822287508e-38, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x3e055027 ; IMAD.MOV.U32 R28, RZ, RZ, 0x20 ; FSEL R27, RZ, -23, P1 ; @!P1 FMUL R26, R26, 8388608 ; IADD3 R3, R26.reuse, -0x3f2aaaab, RZ ; ISETP.GE.U32.AND P0, PT, R26.reuse, 0x7f800000, PT ; LOP3.LUT R3, R3, 0xff800000, RZ, 0xc0, !PT ; FSETP.NEU.AND P1, PT, R26, RZ, PT ; IMAD.IADD R4, R26, 0x1, -R3 ; FADD R8, R4, -1 ; I2F R4, R3 ; @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x7f800000 ; @P0 MOV R19, 0x7f800000 ; FFMA R5, R8.reuse, -R5, 0.14084610342979431152 ; @P0 MOV R37, 0x7f800000 ; @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x7f800000 ; @P0 MOV R9, 0x7f800000 ; FFMA R5, R8, R5, -0.12148627638816833496 ; @P0 IMAD.MOV.U32 R21, RZ, RZ, 0x7f800000 ; FFMA R5, R8.reuse, R5, 0.13980610668659210205 ; @P0 IMAD.MOV.U32 R23, RZ, RZ, 0x7f800000 ; FFMA R5, R8, R5, -0.16684235632419586182 ; FFMA R27, R4, 1.1920928955078125e-07, R27 ; FFMA R5, R8, R5, 0.20012299716472625732 ; @P0 IMAD.MOV.U32 R13, RZ, RZ, 0x7f800000 ; FFMA R5, R8.reuse, R5, -0.24999669194221496582 ; @P0 IMAD.MOV.U32 R15, RZ, RZ, 0x7f800000 ; FFMA R5, R8.reuse, R5, 0.33333182334899902344 ; @P0 IMAD.MOV.U32 R29, RZ, RZ, 0x7f800000 ; FFMA R5, R8, R5, -0.5 ; @P0 IMAD.MOV.U32 R35, RZ, RZ, 0x7f800000 ; FMUL R5, R8.reuse, R5 ; @P0 IMAD.MOV.U32 R22, RZ, RZ, 0x7f800000 ; FFMA R8, R8, R5, R8 ; @P0 MOV R5, 0x7f800000 ; @P0 IMAD.MOV.U32 R10, RZ, RZ, 0x7f800000 ; @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x7f800000 ; @P0 IMAD.MOV.U32 R25, RZ, RZ, 0x7f800000 ; @P0 FFMA R4, R26.reuse, R7, +INF ; @P0 FFMA R7, R26.reuse, R17, +INF ; @P0 FFMA R3, R26.reuse, R5, +INF ; @P0 FFMA R16, R26.reuse, R19, +INF ; @P0 FFMA R17, R26.reuse, R21, +INF ; @P0 FFMA R18, R26, R23, +INF ; @P0 FFMA R5, R26.reuse, R13, +INF ; @P0 FFMA R6, R26.reuse, R15, +INF ; @P0 FFMA R19, R26.reuse, R29, +INF ; @P0 FFMA R20, R26.reuse, R35, +INF ; @P0 FFMA R21, R26.reuse, R37, +INF ; @P0 FFMA R22, R26, R22, +INF ; @P0 FFMA R23, R26.reuse, R10, +INF ; @P0 FFMA R24, R26.reuse, R11, +INF ; @P0 FFMA R25, R26.reuse, R25, +INF ; FFMA R27, R27, 0.69314718246459960938, R8 ; @P0 FFMA R26, R26, R9, +INF ; IMAD.MOV.U32 R8, RZ, RZ, -0x319194d8 ; IMAD.MOV.U32 R11, RZ, RZ, R0 ; IMAD.MOV.U32 R9, RZ, RZ, R27.reuse ; @P0 MOV R9, R3 ; IMAD.MOV.U32 R10, RZ, RZ, R27.reuse ; @P0 IMAD.MOV.U32 R10, RZ, RZ, R4 ; FADD R9, R9, -1 ; FADD R10, R10, -1 ; IMAD.MOV.U32 R12, RZ, RZ, R27 ; FSEL R9, R9, -INF , P1 ; @P0 IMAD.MOV.U32 R12, RZ, RZ, R5 ; FSEL R13, R10, -INF , P1 ; MOV R10, R27 ; FMUL R9, R2.reuse, R9 ; FMUL R13, R2, R13 ; @P0 IMAD.MOV.U32 R10, RZ, RZ, R6 ; FSETP.GT.AND P5, PT, R9, R8, PT ; FSEL R14, R9, R8, P5 ; FADD R8, R12, -1 ; FSETP.GT.AND P3, PT, R13.reuse, R14.reuse, PT ; FSEL R9, R8, -INF , P1 ; FADD R8, R10, -1 ; FSEL R34, R13, R14, P3 ; IMAD.MOV.U32 R10, RZ, RZ, R27 ; LDS.128 R12, [R28+-0x20] ; FMUL R9, R2, R9 ; FSEL R29, R8, -INF , P1 ; @P0 IMAD.MOV.U32 R10, RZ, RZ, R7 ; FSETP.GT.AND P4, PT, R9.reuse, R34.reuse, PT ; FADD R8, R10, -1 ; FMUL R29, R2, R29 ; FSEL R34, R9, R34, P4 ; IMAD.MOV.U32 R10, RZ, RZ, R27 ; @P0 MOV R10, R16 ; FSEL R9, R8, -INF , P1 ; FSETP.GT.AND P2, PT, R29, R34, PT ; FADD R8, R10, -1 ; FMUL R9, R2, R9 ; FSEL R34, R29, R34, P2 ; IMAD.MOV.U32 R10, RZ, RZ, R27 ; FSEL R29, R8, -INF , P1 ; @P0 IMAD.MOV.U32 R10, RZ, RZ, R17 ; FSETP.GT.AND P6, PT, R9, R34, PT ; FADD R8, R10, -1 ; FSEL R34, R9, R34, P6 ; FMUL R29, R2, R29 ; FSEL R9, R8, -INF , P1 ; IMAD.MOV.U32 R8, RZ, RZ, R27 ; @P0 IMAD.MOV.U32 R8, RZ, RZ, R18 ; FMUL R9, R2, R9 ; FADD R8, R8, -1 ; SEL R12, R12, R11, P5 ; FSETP.GT.AND P5, PT, R29, R34, PT ; SEL R13, R13, R12, P3 ; FSEL R34, R29, R34, P5 ; FSEL R29, R8, -INF , P1 ; FSETP.GT.AND P3, PT, R9.reuse, R34.reuse, PT ; SEL R14, R14, R13, P4 ; FMUL R29, R2, R29 ; FSEL R12, R9, R34, P3 ; LDS.128 R8, [R28+-0x10] ; MOV R34, R27 ; @P0 IMAD.MOV.U32 R34, RZ, RZ, R19 ; FSETP.GT.AND P4, PT, R29, R12, PT ; SEL R15, R15, R14, P2 ; FADD R34, R34, -1 ; FSEL R12, R29, R12, P4 ; IMAD.MOV.U32 R14, RZ, RZ, R27 ; @P0 IMAD.MOV.U32 R14, RZ, RZ, R20 ; FSEL R13, R34, -INF , P1 ; FMUL R13, R2, R13 ; FSETP.GT.AND P2, PT, R13, R12, PT ; FSEL R12, R13, R12, P2 ; FADD R13, R14, -1 ; IMAD.MOV.U32 R14, RZ, RZ, R27 ; @P0 MOV R14, R21 ; FSEL R13, R13, -INF , P1 ; FMUL R13, R2, R13 ; SEL R34, R8, R15, P6 ; FADD R8, R14, -1 ; FSETP.GT.AND P6, PT, R13, R12, PT ; IMAD.MOV.U32 R14, RZ, RZ, R27.reuse ; SEL R9, R9, R34, P5 ; @P0 IMAD.MOV.U32 R14, RZ, RZ, R22 ; FSEL R15, R8, -INF , P1 ; FSEL R8, R13, R12, P6 ; FADD R34, R14, -1 ; SEL R10, R10, R9, P3 ; FMUL R29, R2, R15 ; LDS.128 R12, [R28] ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; @P0 MOV R9, R23 ; FSEL R35, R34, -INF , P1 ; FSETP.GT.AND P5, PT, R29, R8, PT ; FADD R9, R9, -1 ; SEL R11, R11, R10, P4 ; FMUL R35, R2, R35 ; FSEL R8, R29, R8, P5 ; IMAD.MOV.U32 R10, RZ, RZ, R27 ; FSEL R9, R9, -INF , P1 ; @P0 IMAD.MOV.U32 R10, RZ, RZ, R24 ; FSETP.GT.AND P3, PT, R35, R8, PT ; FMUL R9, R2, R9 ; FSEL R8, R35, R8, P3 ; FADD R10, R10, -1 ; FSETP.GT.AND P4, PT, R9.reuse, R8.reuse, PT ; FSEL R29, R10, -INF , P1 ; FSEL R34, R9, R8, P4 ; FMUL R29, R2, R29 ; SEL R12, R12, R11, P2 ; LDS.128 R8, [R28+0x10] ; FSETP.GT.AND P2, PT, R29, R34, PT ; SEL R13, R13, R12, P6 ; FSEL R12, R29, R34, P2 ; SEL R14, R14, R13, P5 ; IMAD.MOV.U32 R13, RZ, RZ, R27 ; @P0 MOV R13, R25 ; SEL R29, R15, R14, P3 ; IMAD.MOV.U32 R14, RZ, RZ, R27 ; IADD3 R28, R28, 0x40, RZ ; FADD R13, R13, -1 ; @P0 IMAD.MOV.U32 R14, RZ, RZ, R26 ; FSEL R13, R13, -INF , P1 ; FADD R14, R14, -1 ; FMUL R13, R2, R13 ; FSEL R15, R14, -INF , P1 ; FSETP.GT.AND P3, PT, R13, R12, PT ; FMUL R15, R2, R15 ; FSEL R12, R13, R12, P3 ; SEL R8, R8, R29, P4 ; ISETP.NE.AND P4, PT, R28, 0x1020, PT ; SEL R9, R9, R8, P2 ; FSETP.GT.AND P2, PT, R15, R12, PT ; SEL R10, R10, R9, P3 ; FSEL R8, R15, R12, P2 ; SEL R11, R11, R10, P2 ; @P4 BRA 0x550 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P0, PT, R11, R0, PT ; @!P0 EXIT ; LDG.E R2, [R30.64] ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; LEA R6, P0, R0, c[0x0][0x170], 0x2 ; LEA.HI.X R7, R0, c[0x0][0x174], R3, 0x2, P0 ; S2R R0, SR_LANEID ; VOTEU.ANY UR6, UPT, PT ; FADD R15, -R2, -RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R15 ; LDG.E R9, [R30.64] ; UFLO.U32 UR7, UR6 ; POPC R13, UR6 ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; MOV R4, c[0x0][0x178] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; IMAD.WIDE R2, R11, R2, c[0x0][0x170] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R9 ; STG.E [R32.64], R11 ; @P0 RED.E.ADD.STRONG.GPU [R4.64], R13 ; EXIT ; SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; BSSY B1, 0x1590 ; SHF.R.U32.HI R3, RZ, 0x17, R2.reuse ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R5 ; LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; IADD3 R11, R6, -0x1, RZ ; IADD3 R10, R3, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; @!P0 MOV R9, RZ ; @!P0 BRA 0x1170 ; FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x1570 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; @!P0 BRA 0x1550 ; FSETP.NEU.FTZ.AND P2, PT, |R2|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; @!P0 BRA !P2, 0x1550 ; LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P2, PT, 0x2a, 0x0 ; @P0 BRA 0x1530 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P1, P0, PT, 0x2a, 0x0 ; @P0 BRA 0x1500 ; ISETP.GE.AND P0, PT, R10, RZ, PT ; ISETP.GE.AND P1, PT, R11, RZ, PT ; @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; @!P0 FFMA R7, R2, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R9, R9, 0x40, RZ ; LEA R5, R6, 0xc0800000, 0x17 ; BSSY B2, 0x14f0 ; IADD3 R3, R3, -0x7f, RZ ; IMAD.IADD R8, R8, 0x1, -R5 ; IADD3 R6, R3.reuse, 0x7f, -R6 ; IMAD R5, R3, -0x800000, R7 ; MUFU.RCP R10, R8 ; FADD.FTZ R12, -R8, -RZ ; IADD3 R6, R6, R9, RZ ; FFMA R11, R10, R12, 1 ; FFMA R14, R10, R11, R10 ; FFMA R7, R5, R14, RZ ; FFMA R10, R12, R7, R5 ; FFMA R11, R14, R10, R7 ; FFMA R12, R12, R11, R5 ; FFMA R5, R14, R12, R11 ; SHF.R.U32.HI R3, RZ, 0x17, R5 ; LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R9, R3, 0x1, R6 ; IADD3 R3, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; @!P0 BRA 0x14d0 ; ISETP.GT.AND P0, PT, R9, 0xfe, PT ; @P0 BRA 0x14a0 ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; @P0 BRA 0x14e0 ; ISETP.GE.AND P0, PT, R9, -0x18, PT ; LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x14e0 ; FFMA.RZ R3, R14.reuse, R12.reuse, R11.reuse ; IADD3 R8, R9.reuse, 0x20, RZ ; FFMA.RM R6, R14.reuse, R12.reuse, R11.reuse ; ISETP.NE.AND P2, PT, R9, RZ, PT ; LOP3.LUT R7, R3, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R3, R14, R12, R11 ; ISETP.NE.AND P1, PT, R9, RZ, PT ; IMAD.MOV R9, RZ, RZ, -R9 ; LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R3, R6, PT ; SHF.L.U32 R8, R7, R8, RZ ; SEL R6, R9, RZ, P2 ; ISETP.NE.AND P1, PT, R8, RZ, P1 ; SHF.R.U32.HI R6, RZ, R6, R7 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R8, RZ, 0x1, R6 ; SEL R3, RZ, 0x1, !P0 ; LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ; LOP3.LUT R3, R3, R6, RZ, 0xc0, !PT ; IMAD.IADD R8, R8, 0x1, R3 ; LOP3.LUT R5, R8, R5, RZ, 0xfc, !PT ; BRA 0x14e0 ; LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x14e0 ; LEA R5, R6, R5, 0x17 ; BSYNC B2 ; BRA 0x1580 ; LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1580 ; LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; BRA 0x1580 ; MUFU.RSQ R5, -QNAN ; BRA 0x1580 ; FADD.FTZ R5, R2, R5 ; BSYNC B1 ; IMAD.MOV.U32 R26, RZ, RZ, R5 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0x15c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13infoMapKernelPiPfS0_S_ ; -- Begin function _Z13infoMapKernelPiPfS0_S_ .globl _Z13infoMapKernelPiPfS0_S_ .p2align 8 .type _Z13infoMapKernelPiPfS0_S_,@function _Z13infoMapKernelPiPfS0_S_: ; @_Z13infoMapKernelPiPfS0_S_ ; %bb.0: s_clause 0x1 s_load_b32 s8, s[0:1], 0x2c s_load_b256 s[0:7], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s8, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] v_lshl_add_u32 v0, v0, 2, 0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s0, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo global_load_b32 v6, v[1:2], off s_mov_b32 s0, 0 s_waitcnt vmcnt(0) ds_store_b32 v0, v6 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv global_load_b32 v7, v[1:2], off s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v8, 31, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[7:8] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo global_load_b32 v5, v[3:4], off global_load_b32 v0, v[7:8], off s_waitcnt vmcnt(0) v_div_scale_f32 v7, null, v0, v0, v5 v_div_scale_f32 v10, vcc_lo, v5, v0, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v8, v7 s_waitcnt_depctr 0xfff v_fma_f32 v9, -v7, v8, 1.0 v_fmac_f32_e32 v8, v9, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v9, v10, v8 v_fma_f32 v11, -v7, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v9, v11, v8 v_fma_f32 v7, -v7, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v7, v7, v8, v9 v_div_fixup_f32 v0, v7, v0, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 v_cndmask_b32_e64 v7, 1.0, 0x4f800000, vcc_lo v_mul_f32_e32 v0, v0, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_log_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v7, 0x3f317217, v0 v_fma_f32 v8, 0x3f317217, v0, -v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v8, v0, 0x3377d1cf, v8 v_add_f32_e32 v7, v7, v8 v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v0, v0, v7, vcc_lo v_sub_f32_e32 v0, v0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v7, -1.0, v0 :: v_dual_mov_b32 v0, 0xce6e6b28 v_mul_f32_e32 v7, v5, v7 v_mov_b32_e32 v5, v6 .LBB0_1: ; =>This Inner Loop Header: Depth=1 s_add_i32 s1, s0, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_f32_e32 vcc_lo, v7, v0 v_mov_b32_e32 v8, s1 s_add_i32 s0, s0, 4 s_cmpk_eq_i32 s0, 0x1000 v_cndmask_b32_e32 v0, v0, v7, vcc_lo ds_load_b32 v8, v8 s_waitcnt lgkmcnt(0) v_cndmask_b32_e32 v5, v5, v8, vcc_lo s_cbranch_scc0 .LBB0_1 ; %bb.2: s_barrier buffer_gl0_inv s_mov_b32 s0, exec_lo v_cmpx_ne_u32_e64 v5, v6 s_cbranch_execz .LBB0_9 ; %bb.3: v_ashrrev_i32_e32 v7, 31, v6 s_mov_b32 s0, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[6:7] v_add_co_u32 v6, vcc_lo, s4, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_load_b32 v0, v[3:4], off global_load_b32 v9, v[6:7], off .LBB0_4: ; %atomicrmw.start ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_sub_f32_e32 v8, v9, v0 global_atomic_cmpswap_b32 v8, v[6:7], v[8:9], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v8, v9 v_mov_b32_e32 v9, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_4 ; %bb.5: ; %atomicrmw.end s_or_b32 exec_lo, exec_lo, s0 v_ashrrev_i32_e32 v6, 31, v5 s_mov_b32 s0, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[5:6] v_add_co_u32 v6, vcc_lo, s4, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_load_b32 v0, v[3:4], off global_load_b32 v4, v[6:7], off .LBB0_6: ; %atomicrmw.start42 ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_add_f32_e32 v3, v4, v0 global_atomic_cmpswap_b32 v3, v[6:7], v[3:4], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v3, v4 v_mov_b32_e32 v4, v3 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_6 ; %bb.7: ; %atomicrmw.end41 s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mov_b32 s0, exec_lo global_store_b32 v[1:2], v5, off v_mbcnt_lo_u32_b32 v0, s0, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_and_b32 s1, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s1 s_cbranch_execz .LBB0_9 ; %bb.8: s_bcnt1_i32_b32 s0, s0 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 global_atomic_add_u32 v0, v1, s[6:7] .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13infoMapKernelPiPfS0_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13infoMapKernelPiPfS0_S_, .Lfunc_end0-_Z13infoMapKernelPiPfS0_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 784 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13infoMapKernelPiPfS0_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13infoMapKernelPiPfS0_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0008f241_00000000-6_cuda_code_016724.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6836: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6836: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z23calculateModularQualityPiPfS0_i .type _Z23calculateModularQualityPiPfS0_i, @function _Z23calculateModularQualityPiPfS0_i: .LFB6832: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE6832: .size _Z23calculateModularQualityPiPfS0_i, .-_Z23calculateModularQualityPiPfS0_i .globl _Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_ .type _Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_, @function _Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_: .LFB6858: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movq %rcx, (%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L4 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z13infoMapKernelPiPfS0_S_(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L4: movq 136(%rsp), %rax subq %fs:40, %rax je .L6 call __stack_chk_fail@PLT .L6: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6858: .size _Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_, .-_Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_ .globl _Z13infoMapKernelPiPfS0_S_ .type _Z13infoMapKernelPiPfS0_S_, @function _Z13infoMapKernelPiPfS0_S_: .LFB6859: .cfi_startproc endbr64 jmp _Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_ .cfi_endproc .LFE6859: .size _Z13infoMapKernelPiPfS0_S_, .-_Z13infoMapKernelPiPfS0_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "CUDA error: " .LC2: .string "Number of community changes: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6833: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 movl $4096, %edi pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $4096, %edi movq %rax, %rbp call _Znam@PLT movl $4096, %edi movq %rax, %r13 call _Znam@PLT movl $4, %edi movq %rax, %r12 call _Znwm@PLT movss .LC0(%rip), %xmm0 movl $1, (%rax) movq %rax, %rbx xorl %eax, %eax .L11: movl %eax, 0(%rbp,%rax,4) movss %xmm0, 0(%r13,%rax,4) movss %xmm0, (%r12,%rax,4) incq %rax cmpq $1024, %rax jne .L11 movq %rsp, %rdi movl $4096, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movq (%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $4, %edx call cudaMemcpy@PLT movl $16777217, %edx movl $1073741825, %edi xorl %r9d, %r9d salq $8, %rdx salq $2, %rdi movl $1024, %r8d movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L12 movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z40__device_stub__Z13infoMapKernelPiPfS0_S_PiPfS0_S_ .L12: call cudaGetLastError@PLT movl %eax, %r14d testl %eax, %eax je .L13 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r14d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L10 .L13: movq (%rsp), %rsi movl $2, %ecx movl $4096, %edx movq %rbp, %rdi call cudaMemcpy@PLT movq 24(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi movl $4, %edx call cudaMemcpy@PLT leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl (%rbx), %esi movq %rax, %rdi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %r13, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movl $4, %esi movq %rbx, %rdi call _ZdlPvm@PLT xorl %eax, %eax .L10: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L15 call __stack_chk_fail@PLT .L15: addq $64, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6833: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z13infoMapKernelPiPfS0_S_" .LC4: .string "_ZN50_INTERNAL_abc61e82_19_cuda_code_016724_cu_e854aca74cuda3std3__419piecewise_constructE" .LC5: .string "_ZN50_INTERNAL_abc61e82_19_cuda_code_016724_cu_e854aca74cuda3std6ranges3__45__cpo4swapE" .LC6: .string "_ZN50_INTERNAL_abc61e82_19_cuda_code_016724_cu_e854aca74cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6861: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC3(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z13infoMapKernelPiPfS0_S_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC4(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC5(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6861: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_016724.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z28__device_stub__infoMapKernelPiPfS0_S_ # -- Begin function _Z28__device_stub__infoMapKernelPiPfS0_S_ .type _Z28__device_stub__infoMapKernelPiPfS0_S_,@function _Z28__device_stub__infoMapKernelPiPfS0_S_: # @_Z28__device_stub__infoMapKernelPiPfS0_S_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 16(%rsp), %rdx movq %rcx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13infoMapKernelPiPfS0_S_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z28__device_stub__infoMapKernelPiPfS0_S_, .Lfunc_end0-_Z28__device_stub__infoMapKernelPiPfS0_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %r14 movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %r15 movl $4, %edi callq _Znwm movq %rax, 32(%rsp) # 8-byte Spill movl $1, (%rax) xorl %eax, %eax movl $1065353216, %ecx # imm = 0x3F800000 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %eax, (%rbx,%rax,4) movl %ecx, (%r14,%rax,4) movl %ecx, (%r15,%rax,4) incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB1_1 # %bb.2: leaq 8(%rsp), %r13 movl $4096, %esi # imm = 0x1000 movq %r13, %rdi callq hipMalloc leaq 24(%rsp), %r12 movl $4096, %esi # imm = 0x1000 movq %r12, %rdi callq hipMalloc leaq 16(%rsp), %rbp movl $4096, %esi # imm = 0x1000 movq %rbp, %rdi callq hipMalloc movq %rsp, %rdi movl $4, %esi callq hipMalloc movq (%r13), %rdi movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq (%r12), %rdi movl $4096, %edx # imm = 0x1000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq (%rbp), %rdi movl $4096, %edx # imm = 0x1000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq %rsp, %rax movq (%rax), %rdi movl $4, %edx movq 32(%rsp), %r13 # 8-byte Reload movq %r13, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967300, %rdi # imm = 0x100000004 leaq 252(%rdi), %rdx movl $1024, %r8d # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 8(%rsp), %rdi movq 24(%rsp), %rsi movq 16(%rsp), %rdx movq (%rsp), %rcx callq _Z28__device_stub__infoMapKernelPiPfS0_S_ .LBB1_4: callq hipGetLastError testl %eax, %eax je .LBB1_9 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_6 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_8 .LBB1_9: movq 8(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq (%rsp), %rsi movl $4, %edx movq %r13, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $29, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl (%r13), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rdi addq %r12, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r12, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %r13, %rdi callq _ZdlPv xorl %eax, %eax jmp .LBB1_10 .LBB1_6: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_10: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13infoMapKernelPiPfS0_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z13infoMapKernelPiPfS0_S_,@object # @_Z13infoMapKernelPiPfS0_S_ .section .rodata,"a",@progbits .globl _Z13infoMapKernelPiPfS0_S_ .p2align 3, 0x0 _Z13infoMapKernelPiPfS0_S_: .quad _Z28__device_stub__infoMapKernelPiPfS0_S_ .size _Z13infoMapKernelPiPfS0_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Number of community changes: " .size .L.str.1, 30 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13infoMapKernelPiPfS0_S_" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__infoMapKernelPiPfS0_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13infoMapKernelPiPfS0_S_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z19convolve2DSharedMemPKfS0_Pfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.Y ; ULDC.64 UR4, c[0x0][0x118] ; S2R R20, SR_TID.Y ; S2R R3, SR_TID.X ; S2R R0, SR_CTAID.X ; LEA R26, R5, R20, 0x4 ; ISETP.GE.AND P1, PT, R3, 0x400, PT ; ISETP.GE.AND P0, PT, R26, c[0x0][0x17c], PT ; LEA R25, R0, R3, 0x4 ; ISETP.LT.AND P1, PT, R20, 0x400, !P1 ; ISETP.LT.AND P0, PT, R25, c[0x0][0x178], !P0 ; @P1 LEA R6, R20, R3, 0xa ; @P1 MOV R7, 0x4 ; @P0 IMAD R4, R26, c[0x0][0x178], R25 ; @P0 MOV R5, 0x4 ; @P1 IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; @P1 LDG.E R7, [R6.64] ; @P0 LDG.E R5, [R4.64] ; SHF.L.U32 R9, R3, 0x2, RZ ; HFMA2.MMA R15, -RZ, RZ, 0, 0 ; MOV R23, RZ ; LEA R24, R20, R9, 0x6 ; @!P1 STS [R24+0x400], RZ ; @!P0 STS [R24], RZ ; @P1 STS [R24+0x400], R7 ; @P0 STS [R24], R5 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IADD3 R0, R20, R23.reuse, RZ ; IADD3 R2, R26, -R23, RZ ; IADD3 R23, R23, 0x10, RZ ; MOV R22, RZ ; ISETP.GE.U32.AND P3, PT, R23, 0x400, PT ; IADD3 R7, R25, -R22.reuse, RZ ; IADD3 R5, R3, R22, RZ ; LOP3.LUT R4, R7, R2, RZ, 0xfc, !PT ; ISETP.GT.AND P2, PT, R5, 0x3ff, PT ; ISETP.GE.AND P1, PT, R4, RZ, PT ; ISETP.GT.OR P2, PT, R0, 0x3ff, P2 ; ISETP.GE.OR P1, PT, R2, c[0x0][0x17c], !P1 ; MOV R27, RZ ; ISETP.GE.OR P1, PT, R7, c[0x0][0x178], P1 ; @!P2 LEA R12, R0, R5, 0xa ; HFMA2.MMA R5, -RZ, RZ, 0, 0 ; @!P2 MOV R13, 0x4 ; @!P1 MOV R29, 0x4 ; @!P1 IMAD R28, R2, c[0x0][0x178], R7 ; @!P2 IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; @!P1 IMAD.WIDE R28, R28, R29, c[0x0][0x160] ; @!P2 LDG.E R5, [R12.64] ; @!P1 LDG.E R27, [R28.64] ; IADD3 R22, R22, 0x10, RZ ; ISETP.GE.U32.AND P1, PT, R22, 0x400, PT ; STS [R24+0x400], R5 ; STS [R24], R27 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R21, [R24] ; LDS.128 R4, [0x400] ; LDS.128 R16, [0x410] ; LDS.128 R8, [0x420] ; FFMA R4, R21, R4, R15 ; LDS.128 R12, [0x430] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x440] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x450] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x460] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x470] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x480] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x490] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x4a0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x4b0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x4c0] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x4d0] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x4e0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x4f0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x500] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x510] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x520] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x530] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x540] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x550] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x560] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x570] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x580] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x590] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x5a0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x5b0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x5c0] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x5d0] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x5e0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x5f0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x600] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x610] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x620] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x630] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x640] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x650] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x660] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x670] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x680] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x690] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x6a0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x6b0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x6c0] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x6d0] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x6e0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x6f0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x700] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x710] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x720] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x730] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x740] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x750] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x760] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x770] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x780] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x790] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x7a0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x7b0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R18, R21.reuse, R18, R4 ; LDS.128 R4, [0x7c0] ; FFMA R18, R21, R19, R18 ; FFMA R8, R21.reuse, R8, R18 ; LDS.128 R16, [0x7d0] ; FFMA R8, R21, R9, R8 ; FFMA R8, R21, R10, R8 ; FFMA R8, R21, R11, R8 ; FFMA R8, R21, R12, R8 ; FFMA R8, R21, R13, R8 ; FFMA R14, R21.reuse, R14, R8 ; LDS.128 R8, [0x7e0] ; FFMA R14, R21, R15, R14 ; FFMA R4, R21.reuse, R4, R14 ; LDS.128 R12, [0x7f0] ; FFMA R4, R21, R5, R4 ; FFMA R4, R21, R6, R4 ; FFMA R4, R21, R7, R4 ; FFMA R4, R21, R16, R4 ; FFMA R4, R21, R17, R4 ; FFMA R4, R21, R18, R4 ; FFMA R4, R21, R19, R4 ; FFMA R4, R21, R8, R4 ; FFMA R4, R21, R9, R4 ; FFMA R4, R21, R10, R4 ; FFMA R4, R21, R11, R4 ; FFMA R4, R21, R12, R4 ; FFMA R4, R21, R13, R4 ; FFMA R4, R21, R14, R4 ; FFMA R15, R21, R15, R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P1 CALL.REL.NOINC 0x17d0 ; BRA 0x220 ; @P3 CALL.REL.NOINC 0x17f0 ; BRA 0x1d0 ; @!P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R2, R26, c[0x0][0x178], R25 ; IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; STG.E [R2.64], R15 ; EXIT ; BRA 0x1850; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19convolve2DSharedMemPKfS0_Pfii ; -- Begin function _Z19convolve2DSharedMemPKfS0_Pfii .globl _Z19convolve2DSharedMemPKfS0_Pfii .p2align 8 .type _Z19convolve2DSharedMemPKfS0_Pfii,@function _Z19convolve2DSharedMemPKfS0_Pfii: ; @_Z19convolve2DSharedMemPKfS0_Pfii ; %bb.0: s_load_b256 s[4:11], s[0:1], 0x0 v_bfe_u32 v4, v0, 10, 10 v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v5, 0x3ff, v0 v_mov_b32_e32 v1, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshl_add_u32 v3, s15, 4, v4 v_lshl_add_u32 v0, s14, 4, v5 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s11, v3 v_cmp_gt_i32_e64 s0, s10, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s12, vcc_lo, s0 s_and_saveexec_b32 s0, s12 s_cbranch_execz .LBB0_2 ; %bb.1: v_mad_u64_u32 v[6:7], null, v3, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[6:7], 2, v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_load_b32 v1, v[6:7], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s0 v_lshlrev_b32_e32 v6, 2, v5 s_mov_b32 s13, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_lshl_or_b32 v7, v4, 12, v6 global_load_b32 v9, v7, s[6:7] v_lshl_add_u32 v7, v4, 6, v6 v_mov_b32_e32 v6, 0 v_add_nc_u32_e32 v8, 0x400, v7 s_waitcnt vmcnt(0) ds_store_2addr_stride64_b32 v7, v9, v1 offset1:4 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_3: ; %.preheader106 ; =>This Loop Header: Depth=1 ; Child Loop BB0_4 Depth 2 ; Child Loop BB0_11 Depth 3 ; Child Loop BB0_12 Depth 4 v_subrev_nc_u32_e32 v11, s13, v3 v_add_nc_u32_e32 v1, s13, v4 s_mov_b32 s14, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v9, v11, s10 v_cmp_gt_u32_e32 vcc_lo, 0x400, v1 v_cmp_lt_i32_e64 s0, -1, v11 v_lshlrev_b32_e32 v10, 10, v1 v_cmp_gt_i32_e64 s1, s11, v11 .LBB0_4: ; Parent Loop BB0_3 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_11 Depth 3 ; Child Loop BB0_12 Depth 4 v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v1, s14, v5 v_mov_b32_e32 v11, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u32_e64 s2, 0x400, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_6 ; %bb.5: ; in Loop: Header=BB0_4 Depth=2 v_add_nc_u32_e32 v1, v1, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], 2, v[1:2] v_add_co_u32 v12, s2, s6, v12 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v13, s2, s7, v13, s2 global_load_b32 v12, v[12:13], off .LBB0_6: ; in Loop: Header=BB0_4 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) ds_store_b32 v7, v12 s_and_saveexec_b32 s15, s0 s_cbranch_execz .LBB0_10 ; %bb.7: ; in Loop: Header=BB0_4 Depth=2 v_subrev_nc_u32_e32 v1, s14, v0 v_mov_b32_e32 v11, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cmp_lt_i32_e64 s2, -1, v1 v_cmp_gt_i32_e64 s3, s10, v1 s_and_b32 s2, s1, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_9 ; %bb.8: ; in Loop: Header=BB0_4 Depth=2 v_add_nc_u32_e32 v11, v1, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v12, 31, v11 v_lshlrev_b64 v[11:12], 2, v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v11, s2, s4, v11 v_add_co_ci_u32_e64 v12, s2, s5, v12, s2 global_load_b32 v11, v[11:12], off .LBB0_9: ; %Flow ; in Loop: Header=BB0_4 Depth=2 s_or_b32 exec_lo, exec_lo, s3 .LBB0_10: ; in Loop: Header=BB0_4 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s15 s_waitcnt vmcnt(0) ds_store_b32 v8, v11 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_b32 v1, v8 s_mov_b32 s2, 0 s_mov_b32 s3, 0 .LBB0_11: ; %.preheader ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_4 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB0_12 Depth 4 s_mov_b32 s15, 0 .LBB0_12: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_4 Depth=2 ; Parent Loop BB0_11 Depth=3 ; => This Inner Loop Header: Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s16, s2, s15 s_add_i32 s15, s15, 4 v_mov_b32_e32 v11, s16 s_cmp_eq_u32 s15, 64 ds_load_b32 v11, v11 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v6, v1, v11 s_cbranch_scc0 .LBB0_12 ; %bb.13: ; in Loop: Header=BB0_11 Depth=3 s_add_i32 s3, s3, 1 s_add_i32 s2, s2, 64 s_cmp_eq_u32 s3, 16 s_cbranch_scc0 .LBB0_11 ; %bb.14: ; in Loop: Header=BB0_4 Depth=2 s_add_i32 s2, s14, 16 s_cmpk_gt_u32 s14, 0x3ef s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_16 ; %bb.15: ; in Loop: Header=BB0_4 Depth=2 s_mov_b32 s14, s2 s_branch .LBB0_4 .LBB0_16: ; in Loop: Header=BB0_3 Depth=1 s_add_i32 s0, s13, 16 s_cmpk_gt_u32 s13, 0x3ef s_cbranch_scc1 .LBB0_18 ; %bb.17: ; in Loop: Header=BB0_3 Depth=1 s_mov_b32 s13, s0 s_branch .LBB0_3 .LBB0_18: s_and_saveexec_b32 s0, s12 s_cbranch_execz .LBB0_20 ; %bb.19: v_mad_u64_u32 v[1:2], null, v3, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo global_store_b32 v[0:1], v6, off .LBB0_20: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19convolve2DSharedMemPKfS0_Pfii .amdhsa_group_segment_fixed_size 2048 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 17 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19convolve2DSharedMemPKfS0_Pfii, .Lfunc_end0-_Z19convolve2DSharedMemPKfS0_Pfii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 716 ; NumSgprs: 19 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 2048 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 19 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value .group_segment_fixed_size: 2048 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19convolve2DSharedMemPKfS0_Pfii .private_segment_fixed_size: 0 .sgpr_count: 19 .sgpr_spill_count: 0 .symbol: _Z19convolve2DSharedMemPKfS0_Pfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0008d965_00000000-6_cuda_code_017902.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4012: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE4012: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii .type _Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii, @function _Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii: .LFB4034: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movq %rdx, 8(%rsp) leaq 32(%rsp), %rdx movl %ecx, 4(%rsp) leaq 40(%rsp), %rcx movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 40(%rsp) .cfi_def_cfa_offset 168 leaq _Z19convolve2DSharedMemPKfS0_Pfii(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 176 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L2: movq 136(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4034: .size _Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii, .-_Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii .globl _Z19convolve2DSharedMemPKfS0_Pfii .type _Z19convolve2DSharedMemPKfS0_Pfii, @function _Z19convolve2DSharedMemPKfS0_Pfii: .LFB4035: .cfi_startproc endbr64 jmp _Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii .cfi_endproc .LFE4035: .size _Z19convolve2DSharedMemPKfS0_Pfii, .-_Z19convolve2DSharedMemPKfS0_Pfii .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "convolve2DSharedMem launch failed: %s\n" .LC3: .string "cudaDeviceReset failed!" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB4009: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $4194304, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call malloc@PLT movl $4194304, %edi movq %rax, %rbp call malloc@PLT movl $4194304, %edi movq %rax, %rbx call malloc@PLT movss .LC0(%rip), %xmm0 movq %rax, %r12 xorl %eax, %eax .L9: movss %xmm0, 0(%rbp,%rax,4) incq %rax cmpq $1048576, %rax jne .L9 movss .LC1(%rip), %xmm0 xorl %eax, %eax .L10: movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $1048576, %rax jne .L10 leaq 8(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $4194304, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $4194304, %edx call cudaMemcpy@PLT xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movabsq $137438953504, %rdi movl $1, %esi movq %rdi, %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L11 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $1024, %ecx movl $1024, %r8d movq 8(%rsp), %rdi call _Z47__device_stub__Z19convolve2DSharedMemPKfS0_PfiiPKfS0_Pfii .L11: movq 24(%rsp), %rsi movl $2, %ecx movl $4194304, %edx movq %r12, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r12, %rdi call free@PLT call cudaGetLastError@PLT movl %eax, %edi testl %eax, %eax je .L12 call cudaGetErrorString@PLT movq stderr(%rip), %rdi movl $2, %esi leaq .LC2(%rip), %rdx movq %rax, %rcx xorl %eax, %eax call __fprintf_chk@PLT jmp .L13 .L12: call cudaDeviceReset@PLT movl %eax, %edx xorl %eax, %eax testl %edx, %edx je .L8 movq stderr(%rip), %rdi leaq .LC3(%rip), %rdx movl $2, %esi call __fprintf_chk@PLT .L13: movl $1, %eax .L8: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L15 call __stack_chk_fail@PLT .L15: addq $64, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4009: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z19convolve2DSharedMemPKfS0_Pfii" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4037: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC4(%rip), %rdx movq %rax, %rdi leaq _Z19convolve2DSharedMemPKfS0_Pfii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE4037: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .align 4 .LC1: .long 897581056 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_017902.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii # -- Begin function _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii .type _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii,@function _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii: # @_Z34__device_stub__convolve2DSharedMemPKfS0_Pfii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) movq %rsp, %rcx movl %r8d, (%rcx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z19convolve2DSharedMemPKfS0_Pfii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $144, %rsp .cfi_adjust_cfa_offset -144 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii, .Lfunc_end0-_Z34__device_stub__convolve2DSharedMemPKfS0_Pfii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $32, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $4194304, %edi # imm = 0x400000 callq malloc movq %rax, %rbx movl $4194304, %edi # imm = 0x400000 callq malloc movq %rax, %r14 movl $4194304, %edi # imm = 0x400000 callq malloc movq %rax, %r15 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 incq %rax cmpq $1048576, %rax # imm = 0x100000 jne .LBB1_1 # %bb.2: # %.preheader.preheader xorl %eax, %eax .LBB1_3: # %.preheader # =>This Inner Loop Header: Depth=1 movl $897581056, (%r14,%rax,4) # imm = 0x35800000 incq %rax cmpq $1048576, %rax # imm = 0x100000 jne .LBB1_3 # %bb.4: leaq 24(%rsp), %r12 movl $4194304, %esi # imm = 0x400000 movq %r12, %rdi callq hipMalloc leaq 16(%rsp), %r13 movl $4194304, %esi # imm = 0x400000 movq %r13, %rdi callq hipMalloc leaq 8(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc movq (%r12), %rdi movl $4194304, %edx # imm = 0x400000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq (%r13), %rdi movl $4194304, %edx # imm = 0x400000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $137438953504, %rdi # imm = 0x2000000020 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 24(%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movl $1024, %ecx # imm = 0x400 movl $1024, %r8d # imm = 0x400 callq _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii .LBB1_6: movq 8(%rsp), %rsi movl $4194304, %edx # imm = 0x400000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.8: callq hipDeviceReset movl %eax, %ecx xorl %eax, %eax testl %ecx, %ecx jne .LBB1_9 .LBB1_11: addq $32, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_7: .cfi_def_cfa_offset 80 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movq %rbx, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf jmp .LBB1_10 .LBB1_9: movq stderr(%rip), %rcx movl $.L.str.1, %edi movl $22, %esi movl $1, %edx callq fwrite@PLT .LBB1_10: movl $1, %eax jmp .LBB1_11 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19convolve2DSharedMemPKfS0_Pfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z19convolve2DSharedMemPKfS0_Pfii,@object # @_Z19convolve2DSharedMemPKfS0_Pfii .section .rodata,"a",@progbits .globl _Z19convolve2DSharedMemPKfS0_Pfii .p2align 3, 0x0 _Z19convolve2DSharedMemPKfS0_Pfii: .quad _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii .size _Z19convolve2DSharedMemPKfS0_Pfii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "convolve2DSharedMem launch failed: %s\n" .size .L.str, 39 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "hipDeviceReset failed!" .size .L.str.1, 23 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z19convolve2DSharedMemPKfS0_Pfii" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__convolve2DSharedMemPKfS0_Pfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z19convolve2DSharedMemPKfS0_Pfii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
3,441
4,061
113,398
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z11mine_blocksPjS_j .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; BSSY B0, 0x200 ; S2R R0, SR_TID.X ; IMAD R3, R3, c[0x0][0x0], R0 ; SHF.R.U32.HI R2, RZ, 0x8, R3.reuse ; LOP3.LUT R0, R3, 0xff, RZ, 0xc0, !PT ; SHF.R.U32.HI R4, RZ, 0x10, R3 ; LOP3.LUT R5, R2, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R7, R4, 0xff, RZ, 0xc0, !PT ; IMAD R0, R0, 0x83, R5 ; SHF.R.U32.HI R5, RZ, 0x18, R3 ; IMAD R0, R0, 0x83, R7 ; IMAD R0, R0, 0x83, R5 ; IMAD R0, R0, 0x78153931, RZ ; ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; @!P0 BRA 0x1f0 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; IMAD R3, R6, c[0x0][0x0], R3 ; SHF.R.U32.HI R2, RZ, 0x8, R3.reuse ; LOP3.LUT R0, R3, 0xff, RZ, 0xc0, !PT ; SHF.R.U32.HI R4, RZ, 0x10, R3 ; LOP3.LUT R5, R2, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R7, R4, 0xff, RZ, 0xc0, !PT ; IMAD R0, R0, 0x83, R5 ; SHF.R.U32.HI R5, RZ, 0x18, R3 ; IMAD R0, R0, 0x83, R7 ; IMAD R0, R0, 0x83, R5 ; IMAD R0, R0, 0x78153931, RZ ; ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; @P0 BRA 0x120 ; BSYNC B0 ; ULDC.64 UR4, c[0x0][0x168] ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; MOV R6, UR4 ; IMAD.U32 R7, RZ, RZ, UR5 ; ATOMG.E.CAS.STRONG.GPU PT, R2, [R6], R2, R3 ; ULDC.64 UR4, c[0x0][0x118] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; @!P0 MOV R5, c[0x0][0x164] ; @!P0 STG.E [R4.64], R3 ; BAR.SYNC 0x0 ; EXIT ; BRA 0x2c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11mine_blocksPjS_j ; -- Begin function _Z11mine_blocksPjS_j .globl _Z11mine_blocksPjS_j .p2align 8 .type _Z11mine_blocksPjS_j,@function _Z11mine_blocksPjS_j: ; @_Z11mine_blocksPjS_j ; %bb.0: s_clause 0x2 s_load_b32 s3, s[0:1], 0x24 s_load_b32 s4, s[0:1], 0x18 s_load_b32 s2, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1] s_mul_i32 s4, s4, s3 s_mov_b32 s3, 0 .LBB0_1: ; =>This Loop Header: Depth=1 ; Child Loop BB0_2 Depth 2 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v0, v1 v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v1 s_mov_b32 s5, 32 .LBB0_2: ; Parent Loop BB0_1 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_and_b32_e32 v5, 0xff, v3 v_lshrrev_b32_e32 v3, 8, v3 s_add_i32 s5, s5, -1 s_cmp_lg_u32 s5, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, 0x83, v4, v[5:6] v_mov_b32_e32 v4, v1 s_cbranch_scc1 .LBB0_2 ; %bb.3: ; %_Z11simple_hashj.exit ; in Loop: Header=BB0_1 Depth=1 v_cmp_gt_u32_e32 vcc_lo, s2, v1 v_add_nc_u32_e32 v1, s4, v0 s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_1 ; %bb.4: s_or_b32 exec_lo, exec_lo, s3 s_load_b128 s[0:3], s[0:1], 0x0 v_mov_b32_e32 v1, 0 s_waitcnt lgkmcnt(0) global_atomic_cmpswap_b32 v2, v1, v[0:1], s[2:3] glc s_mov_b32 s2, exec_lo s_waitcnt vmcnt(0) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_6 ; %bb.5: global_store_b32 v1, v0, s[0:1] .LBB0_6: s_or_b32 exec_lo, exec_lo, s2 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11mine_blocksPjS_j .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11mine_blocksPjS_j, .Lfunc_end0-_Z11mine_blocksPjS_j ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 228 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11mine_blocksPjS_j .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11mine_blocksPjS_j.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
978
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000c54a8_00000000-6_cuda_code_036537.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6836: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6836: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB7720: .cfi_startproc jmp *%rsi .cfi_endproc .LFE7720: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z11simple_hashj .type _Z11simple_hashj, @function _Z11simple_hashj: .LFB6832: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE6832: .size _Z11simple_hashj, .-_Z11simple_hashj .globl _Z34__device_stub__Z11mine_blocksPjS_jPjS_j .type _Z34__device_stub__Z11mine_blocksPjS_jPjS_j, @function _Z34__device_stub__Z11mine_blocksPjS_jPjS_j: .LFB6858: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movl %edx, 12(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L5 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z11mine_blocksPjS_j(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L5: movq 120(%rsp), %rax subq %fs:40, %rax je .L7 call __stack_chk_fail@PLT .L7: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6858: .size _Z34__device_stub__Z11mine_blocksPjS_jPjS_j, .-_Z34__device_stub__Z11mine_blocksPjS_jPjS_j .globl _Z11mine_blocksPjS_j .type _Z11mine_blocksPjS_j, @function _Z11mine_blocksPjS_j: .LFB6859: .cfi_startproc endbr64 jmp _Z34__device_stub__Z11mine_blocksPjS_jPjS_j .cfi_endproc .LFE6859: .size _Z11mine_blocksPjS_j, .-_Z11mine_blocksPjS_j .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate device memory for nonce: " .LC1: .string "Failed to allocate device memory for result: " .LC2: .string "Failed to initialize device memory for nonce: " .LC3: .string "Failed to initialize device memory for result: " .LC4: .string "Kernel launch failed: " .LC5: .string "Failed to copy nonce from device to host: " .LC6: .string "Failed to copy result from device to host: " .LC7: .string "Found nonce: " .LC8: .string " with hash less than difficulty " .LC9: .string "No nonce found with hash less than difficulty " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6833: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movl $4, %esi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 16(%rsp), %rdi xorl %eax, %eax movl %eax, 8(%rsp) movl %eax, 12(%rsp) call cudaMalloc@PLT testl %eax, %eax je .L12 movl %eax, %ebx leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L13 .L12: leaq 24(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L14 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 16(%rsp), %rdi .L26: call cudaFree@PLT .L13: orl $-1, %eax jmp .L11 .L14: movq 16(%rsp), %rdi xorl %esi, %esi movl $4, %edx call cudaMemset@PLT leaq .LC2(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L28 movq 24(%rsp), %rdi xorl %esi, %esi movl $4, %edx call cudaMemset@PLT leaq .LC3(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L28 movl $16777217, %edx movl $4194305, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx salq $10, %rdi movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movq 24(%rsp), %rsi movq 16(%rsp), %rdi movl $16384, %edx call _Z34__device_stub__Z11mine_blocksPjS_jPjS_j .L18: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L28 movq 16(%rsp), %rsi leaq 8(%rsp), %rdi movl $2, %ecx movl $4, %edx call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L28 movq 24(%rsp), %rsi leaq 12(%rsp), %rdi movl $2, %ecx movl $4, %edx call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax je .L21 leaq .LC6(%rip), %rsi .L28: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi jmp .L26 .L21: cmpl $0, 12(%rsp) leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rdi je .L27 leaq .LC7(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl 8(%rsp), %esi movq %rax, %rdi call _ZNSo9_M_insertImEERSoT_@PLT leaq .LC8(%rip), %rsi movq %rax, %rdi .L27: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $16384, %esi movq %rax, %rdi call _ZNSo9_M_insertImEERSoT_@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L11: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L24 call __stack_chk_fail@PLT .L24: addq $72, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6833: .size main, .-main .section .rodata.str1.1 .LC10: .string "_Z11mine_blocksPjS_j" .LC11: .string "_ZN50_INTERNAL_8bfe3eaa_19_cuda_code_036537_cu_dc6124754cuda3std3__419piecewise_constructE" .LC12: .string "_ZN50_INTERNAL_8bfe3eaa_19_cuda_code_036537_cu_dc6124754cuda3std6ranges3__45__cpo4swapE" .LC13: .string "_ZN50_INTERNAL_8bfe3eaa_19_cuda_code_036537_cu_dc6124754cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6861: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z11mine_blocksPjS_j(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC11(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6861: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_036537.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__mine_blocksPjS_j # -- Begin function _Z26__device_stub__mine_blocksPjS_j .type _Z26__device_stub__mine_blocksPjS_j,@function _Z26__device_stub__mine_blocksPjS_j: # @_Z26__device_stub__mine_blocksPjS_j .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z11mine_blocksPjS_j, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z26__device_stub__mine_blocksPjS_j, .Lfunc_end0-_Z26__device_stub__mine_blocksPjS_j .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 xorl %eax, %eax movl %eax, 28(%rsp) movl %eax, 24(%rsp) leaq 8(%rsp), %rdi movl $4, %esi callq hipMalloc testl %eax, %eax je .LBB1_3 # %bb.1: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $44, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_6 # %bb.2: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_7 .LBB1_3: leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc testl %eax, %eax je .LBB1_8 # %bb.4: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $45, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_10 # %bb.5: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_11 .LBB1_6: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_20 .LBB1_8: movq 8(%rsp), %rdi movl $4, %edx xorl %esi, %esi callq hipMemset testl %eax, %eax je .LBB1_12 # %bb.9: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $46, %edx jmp .LBB1_14 .LBB1_10: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit33 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi jmp .LBB1_19 .LBB1_12: movq 16(%rsp), %rdi movl $4, %edx xorl %esi, %esi callq hipMemset testl %eax, %eax je .LBB1_22 # %bb.13: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $47, %edx .LBB1_14: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_16 # %bb.15: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_17 .LBB1_16: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_18: movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi .LBB1_19: callq hipFree .LBB1_20: movl $-1, %eax .LBB1_21: addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_22: .cfi_def_cfa_offset 48 movabsq $4294967552, %rdx # imm = 0x100000100 leaq 768(%rdx), %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_24 # %bb.23: movq 8(%rsp), %rdi movq 16(%rsp), %rsi movl $16384, %edx # imm = 0x4000 callq _Z26__device_stub__mine_blocksPjS_j .LBB1_24: callq hipGetLastError testl %eax, %eax je .LBB1_26 # %bb.25: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $22, %edx jmp .LBB1_30 .LBB1_26: movq 8(%rsp), %rsi leaq 28(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_28 # %bb.27: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $42, %edx jmp .LBB1_30 .LBB1_28: movq 16(%rsp), %rsi leaq 24(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_31 # %bb.29: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.6, %esi movl $43, %edx .LBB1_30: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_18 .LBB1_31: cmpl $0, 24(%rsp) je .LBB1_33 # %bb.32: movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $13, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 28(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSo9_M_insertImEERSoT_ movq %rax, %rbx movl $.L.str.8, %esi movl $32, %edx movq %rax, %rdi jmp .LBB1_34 .LBB1_33: movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $46, %edx .LBB1_34: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $16384, %esi # imm = 0x4000 movq %rbx, %rdi callq _ZNSo9_M_insertImEERSoT_ movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_21 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11mine_blocksPjS_j, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11mine_blocksPjS_j,@object # @_Z11mine_blocksPjS_j .section .rodata,"a",@progbits .globl _Z11mine_blocksPjS_j .p2align 3, 0x0 _Z11mine_blocksPjS_j: .quad _Z26__device_stub__mine_blocksPjS_j .size _Z11mine_blocksPjS_j, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory for nonce: " .size .L.str, 45 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate device memory for result: " .size .L.str.1, 46 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to initialize device memory for nonce: " .size .L.str.2, 47 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to initialize device memory for result: " .size .L.str.3, 48 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed: " .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy nonce from device to host: " .size .L.str.5, 43 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy result from device to host: " .size .L.str.6, 44 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Found nonce: " .size .L.str.7, 14 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz " with hash less than difficulty " .size .L.str.8, 33 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "No nonce found with hash less than difficulty " .size .L.str.9, 47 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11mine_blocksPjS_j" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__mine_blocksPjS_j .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11mine_blocksPjS_j .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
5,428
5,820
113,402
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z6mutateP17curandStateXORWOWPff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R2, 0x3f, PT ; @P0 EXIT ; IMAD.SHL.U32 R20, R2, 0x400, RZ ; HFMA2.MMA R3, -RZ, RZ, 0, 2.86102294921875e-06 ; IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R22, R20.reuse, 0x1, RZ ; IMAD.WIDE R20, R20, R23, c[0x0][0x168] ; IMAD.WIDE R22, R22, R23, c[0x0][0x168] ; IMAD.MOV.U32 R0, RZ, RZ, R20 ; IMAD.MOV.U32 R20, RZ, RZ, R22 ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; LDG.E.64 R10, [R2.64] ; LDG.E.64 R4, [R2.64+0x10] ; LDG.E.64 R6, [R2.64+0x8] ; IMAD.MOV.U32 R24, RZ, RZ, 0x2f800000 ; SHF.R.U32.HI R8, RZ, 0x2, R11 ; IADD3 R18, R10, 0x587c5, RZ ; LOP3.LUT R8, R8, R11, RZ, 0x3c, !PT ; IMAD.SHL.U32 R15, R5.reuse, 0x10, RZ ; MOV R16, R18 ; SHF.L.U32 R9, R8, 0x1, RZ ; IMAD.MOV.U32 R17, RZ, RZ, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R7 ; LOP3.LUT R8, R5, R9, R8, 0x96, !PT ; STG.E.64 [R2.64], R16 ; LOP3.LUT R15, R8, R15, RZ, 0x3c, !PT ; IMAD.IADD R8, R15, 0x1, R18 ; I2F.U32 R9, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R7 ; FFMA R9, R9, R24, 1.1641532182693481445e-10 ; FSETP.GEU.AND P1, PT, R9, c[0x0][0x170], PT ; @!P1 SHF.R.U32.HI R9, RZ, 0x2, R6 ; @!P1 IMAD.SHL.U32 R14, R15, 0x10, RZ ; @!P1 IADD3 R10, R10, 0xb0f8a, RZ ; @!P1 LOP3.LUT R12, R9, R6, RZ, 0x3c, !PT ; @!P1 STG.E.64 [R2.64], R10 ; @!P1 SHF.L.U32 R9, R12, 0x1, RZ ; @!P1 LOP3.LUT R9, R15, R9, R12, 0x96, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R15 ; @!P1 LOP3.LUT R13, R9, R14, RZ, 0x3c, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R5 ; MOV R9, R4 ; @!P1 IMAD.IADD R19, R13, 0x1, R10 ; STG.E.64 [R2.64+0x10], R14 ; STG.E.64 [R2.64+0x8], R8 ; @!P1 I2F.U32 R19, R19 ; @!P1 STG.E.64 [R2.64+0x10], R12 ; @!P1 STG.E.64 [R2.64+0x8], R4 ; @!P1 MOV R8, R0 ; @!P1 IMAD.MOV.U32 R9, RZ, RZ, R21 ; @!P1 FFMA R25, R19, R24, 1.1641532182693481445e-10 ; @!P1 STG.E [R8.64], R25 ; @!P1 LDG.E.64 R18, [R2.64] ; @!P1 LDG.E.64 R14, [R2.64+0x10] ; @!P1 LDG.E.64 R26, [R2.64+0x8] ; IADD3 R22, R22, 0x2, RZ ; BSSY B0, 0x690 ; IADD3 R0, P2, R0, 0x8, RZ ; @!P1 IMAD.MOV.U32 R6, RZ, RZ, R19 ; IMAD.SHL.U32 R11, R15, 0x10, RZ ; SHF.R.U32.HI R17, RZ, 0x2, R6 ; IMAD.MOV.U32 R8, RZ, RZ, R15 ; @!P1 MOV R5, R14 ; @!P1 IMAD.MOV.U32 R4, RZ, RZ, R27 ; LOP3.LUT R6, R17, R6, RZ, 0x3c, !PT ; @!P1 MOV R7, R26 ; SHF.L.U32 R10, R6, 0x1, RZ ; STG.E.64 [R2.64+0x8], R4 ; ISETP.NE.AND P1, PT, R22, 0x400, PT ; LOP3.LUT R10, R15, R10, R6, 0x96, !PT ; IADD3 R6, R18, 0x587c5, RZ ; LOP3.LUT R9, R10, R11, RZ, 0x3c, !PT ; STG.E.64 [R2.64], R6 ; IMAD.IADD R10, R9, 0x1, R6 ; STG.E.64 [R2.64+0x10], R8 ; I2F.U32 R11, R10 ; FFMA R11, R11, R24, 1.1641532182693481445e-10 ; FSETP.GEU.AND P0, PT, R11, c[0x0][0x170], PT ; @P0 BRA 0x680 ; SHF.R.U32.HI R6, RZ, 0x2, R7 ; IMAD.SHL.U32 R8, R9.reuse, 0x10, RZ ; IADD3 R18, R18, 0xb0f8a, RZ ; IMAD.MOV.U32 R14, RZ, RZ, R5 ; LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; IMAD.MOV.U32 R19, RZ, RZ, R4 ; IMAD.MOV.U32 R4, RZ, RZ, R20 ; STG.E.64 [R2.64+0x8], R14 ; IMAD.SHL.U32 R7, R6, 0x2, RZ ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; STG.E.64 [R2.64], R18 ; LOP3.LUT R7, R9, R7, R6, 0x96, !PT ; MOV R6, R9 ; LOP3.LUT R7, R7, R8, RZ, 0x3c, !PT ; IADD3 R8, R7, R18, RZ ; STG.E.64 [R2.64+0x10], R6 ; I2F.U32 R11, R8 ; FFMA R11, R11, R24, 1.1641532182693481445e-10 ; STG.E [R4.64], R11 ; BSYNC B0 ; IADD3 R20, P0, R20, 0x8, RZ ; IADD3.X R21, RZ, R21, RZ, P2, !PT ; IMAD.X R23, RZ, RZ, R23, P0 ; @P1 BRA 0x110 ; EXIT ; BRA 0x6e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9crossoverPfS_Pii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R10, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R10, R10, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R10, 0x3f, PT ; @P0 EXIT ; IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.SHL.U32 R3, R10, 0x2, RZ ; IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; ISETP.GE.AND P0, PT, R14, 0x1, PT ; IMAD.WIDE R2, R3, R12, c[0x0][0x170] ; MOV R0, c[0x0][0x168] ; LDG.E R13, [R2.64+0x4] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; @!P0 BRA 0x9f0 ; IADD3 R4, R14.reuse, -0x1, RZ ; LDG.E R15, [R2.64] ; UMOV UR4, URZ ; LOP3.LUT R16, R14, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; @!P0 BRA 0x890 ; IADD3 R18, -R16, c[0x0][0x178], RZ ; IMAD.SHL.U32 R19, R10, 0x400, RZ ; UMOV UR4, URZ ; IMAD.SHL.U32 R3, R15, 0x400, RZ ; ISETP.GT.AND P0, PT, R18, RZ, PT ; IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x168] ; MOV R21, c[0x0][0x16c] ; IMAD.WIDE R2, R3, R12, c[0x0][0x160] ; IADD3 R17, R19, 0x1, RZ ; @!P0 BRA 0x730 ; ISETP.GT.AND P1, PT, R18, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x520 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R23, [R2.64] ; IMAD.MOV.U32 R4, RZ, RZ, R20 ; IMAD.MOV.U32 R5, RZ, RZ, R21 ; IMAD.WIDE R6, R19, 0x4, R4 ; STG.E [R6.64], R23 ; LDG.E R21, [R2.64+0x4] ; IMAD.WIDE R8, R17, 0x4, R4 ; STG.E [R8.64], R21 ; LDG.E R25, [R2.64+0x8] ; STG.E [R8.64+0x4], R25 ; LDG.E R27, [R2.64+0xc] ; STG.E [R8.64+0x8], R27 ; LDG.E R29, [R2.64+0x10] ; STG.E [R6.64+0x10], R29 ; LDG.E R20, [R2.64+0x14] ; STG.E [R8.64+0x10], R20 ; LDG.E R23, [R2.64+0x18] ; STG.E [R8.64+0x14], R23 ; LDG.E R21, [R2.64+0x1c] ; STG.E [R8.64+0x18], R21 ; LDG.E R25, [R2.64+0x20] ; STG.E [R6.64+0x20], R25 ; LDG.E R27, [R2.64+0x24] ; STG.E [R8.64+0x20], R27 ; LDG.E R29, [R2.64+0x28] ; STG.E [R8.64+0x24], R29 ; LDG.E R20, [R2.64+0x2c] ; STG.E [R8.64+0x28], R20 ; LDG.E R23, [R2.64+0x30] ; STG.E [R6.64+0x30], R23 ; LDG.E R21, [R2.64+0x34] ; STG.E [R8.64+0x30], R21 ; LDG.E R25, [R2.64+0x38] ; IADD3 R18, R18, -0x10, RZ ; ISETP.GT.AND P1, PT, R18, 0xc, PT ; STG.E [R8.64+0x34], R25 ; LDG.E R27, [R2.64+0x3c] ; IADD3 R22, P3, R2, 0x40, RZ ; UIADD3 UR4, UR4, 0x10, URZ ; IADD3 R20, P2, R4, 0x40, RZ ; IMAD.X R23, RZ, RZ, R3, P3 ; IMAD.X R21, RZ, RZ, R5, P2 ; MOV R2, R22 ; IMAD.MOV.U32 R3, RZ, RZ, R23 ; STG.E [R8.64+0x38], R27 ; @P1 BRA 0x240 ; ISETP.GT.AND P1, PT, R18, 0x4, PT ; @!P1 BRA 0x710 ; LDG.E R9, [R2.64] ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; IMAD.WIDE R4, R19, 0x4, R6 ; STG.E [R4.64], R9 ; LDG.E R23, [R2.64+0x4] ; IMAD.WIDE R6, R17, 0x4, R6 ; STG.E [R6.64], R23 ; LDG.E R25, [R2.64+0x8] ; STG.E [R6.64+0x4], R25 ; LDG.E R27, [R2.64+0xc] ; STG.E [R6.64+0x8], R27 ; LDG.E R29, [R2.64+0x10] ; STG.E [R4.64+0x10], R29 ; LDG.E R8, [R2.64+0x14] ; STG.E [R6.64+0x10], R8 ; LDG.E R9, [R2.64+0x18] ; STG.E [R6.64+0x14], R9 ; LDG.E R23, [R2.64+0x1c] ; IADD3 R22, P2, R2, 0x20, RZ ; UIADD3 UR4, UR4, 0x8, URZ ; IADD3 R20, P1, R20, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.X R5, RZ, RZ, R3, P2 ; IADD3 R18, R18, -0x8, RZ ; IADD3.X R21, RZ, R21, RZ, P1, !PT ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; IMAD.MOV.U32 R3, RZ, RZ, R5 ; STG.E [R6.64+0x18], R23 ; ISETP.NE.OR P0, PT, R18, RZ, P0 ; @!P0 BRA 0x890 ; LDG.E R23, [R2.64] ; IMAD.MOV.U32 R4, RZ, RZ, R20 ; IMAD.MOV.U32 R5, RZ, RZ, R21 ; IMAD.WIDE R6, R19, 0x4, R4 ; STG.E [R6.64], R23 ; LDG.E R21, [R2.64+0x4] ; IMAD.WIDE R8, R17, 0x4, R4 ; STG.E [R8.64], R21 ; LDG.E R25, [R2.64+0x8] ; IADD3 R18, R18, -0x4, RZ ; ISETP.NE.AND P0, PT, R18, RZ, PT ; STG.E [R8.64+0x4], R25 ; LDG.E R27, [R2.64+0xc] ; IADD3 R22, P2, R2, 0x10, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R20, P1, R4, 0x10, RZ ; IADD3.X R23, RZ, R3, RZ, P2, !PT ; IMAD.X R21, RZ, RZ, R5, P1 ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; IMAD.MOV.U32 R3, RZ, RZ, R23 ; STG.E [R8.64+0x8], R27 ; @P0 BRA 0x730 ; ISETP.NE.AND P0, PT, R16, RZ, PT ; @!P0 BRA 0x9f0 ; LEA R3, R10, UR4, 0xa ; LEA R5, R15, UR4, 0xa ; IMAD.WIDE R2, R3, R12, c[0x0][0x168] ; IMAD.WIDE R4, R5, R12, c[0x0][0x160] ; MOV R9, R3 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; IMAD.MOV.U32 R2, RZ, RZ, R4 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; LDG.E R5, [R2.64] ; IADD3 R16, R16, -0x1, RZ ; IADD3 R4, P2, R4, 0x4, RZ ; ISETP.NE.AND P0, PT, R16, RZ, PT ; IMAD.X R7, RZ, RZ, R7, P2 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; MOV R3, R9 ; IADD3 R6, P1, R6, 0x4, RZ ; IMAD.X R9, RZ, RZ, R9, P1 ; STG.E [R2.64], R5 ; @P0 BRA 0x920 ; ISETP.GT.AND P0, PT, R14, 0x3ff, PT ; @P0 EXIT ; IMAD.MOV R6, RZ, RZ, -c[0x0][0x178] ; IADD3 R14, -R14, 0x3ff, RZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; LOP3.LUT P1, R6, R6, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R14, 0x3, PT ; @!P1 BRA 0xbe0 ; LEA R3, R10, c[0x0][0x178], 0xa ; LEA R5, R13, c[0x0][0x178], 0xa ; IMAD.WIDE R2, R3, R12, c[0x0][0x168] ; IMAD.WIDE R4, R5, R12, c[0x0][0x160] ; MOV R9, R2 ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; MOV R4, c[0x0][0x178] ; IMAD.MOV.U32 R14, RZ, RZ, R3 ; IMAD.MOV.U32 R8, RZ, RZ, R5 ; IMAD.MOV.U32 R2, RZ, RZ, R7 ; IMAD.MOV.U32 R3, RZ, RZ, R8 ; LDG.E R5, [R2.64] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R7, P3, R7, 0x4, RZ ; ISETP.NE.AND P1, PT, R6, RZ, PT ; IADD3 R4, R4, 0x1, RZ ; IMAD.X R8, RZ, RZ, R8, P3 ; IMAD.MOV.U32 R2, RZ, RZ, R9 ; MOV R3, R14 ; IADD3 R9, P2, R9, 0x4, RZ ; IMAD.X R14, RZ, RZ, R14, P2 ; STG.E [R2.64], R5 ; @P1 BRA 0xb00 ; @!P0 EXIT ; IADD3 R3, R4, -0x4, RZ ; IMAD R13, R13, 0x400, R4 ; LEA R10, R10, R4, 0xa ; IADD3 R2, -R3, 0x3fc, RZ ; IMAD.WIDE R12, R13, R12, c[0x0][0x160] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; ISETP.GT.AND P1, PT, R2, 0xc, PT ; IADD3 R2, R10, 0x1, RZ ; @!P1 BRA 0xf60 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R15, [R12.64] ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, R11 ; IMAD.WIDE R6, R10, 0x4, R4 ; STG.E [R6.64], R15 ; LDG.E R11, [R12.64+0x4] ; IMAD.WIDE R8, R2, 0x4, R4 ; STG.E [R8.64], R11 ; LDG.E R17, [R12.64+0x8] ; STG.E [R8.64+0x4], R17 ; LDG.E R19, [R12.64+0xc] ; STG.E [R8.64+0x8], R19 ; LDG.E R21, [R12.64+0x10] ; STG.E [R6.64+0x10], R21 ; LDG.E R23, [R12.64+0x14] ; STG.E [R8.64+0x10], R23 ; LDG.E R15, [R12.64+0x18] ; STG.E [R8.64+0x14], R15 ; LDG.E R11, [R12.64+0x1c] ; STG.E [R8.64+0x18], R11 ; LDG.E R17, [R12.64+0x20] ; STG.E [R6.64+0x20], R17 ; LDG.E R19, [R12.64+0x24] ; STG.E [R8.64+0x20], R19 ; LDG.E R21, [R12.64+0x28] ; STG.E [R8.64+0x24], R21 ; LDG.E R23, [R12.64+0x2c] ; STG.E [R8.64+0x28], R23 ; LDG.E R15, [R12.64+0x30] ; STG.E [R6.64+0x30], R15 ; LDG.E R25, [R12.64+0x34] ; STG.E [R8.64+0x30], R25 ; LDG.E R17, [R12.64+0x38] ; IADD3 R3, R3, 0x10, RZ ; ISETP.GE.AND P1, PT, R3, 0x3f0, PT ; STG.E [R8.64+0x34], R17 ; LDG.E R19, [R12.64+0x3c] ; IADD3 R14, P3, R12, 0x40, RZ ; IADD3 R0, P2, R4, 0x40, RZ ; IMAD.X R15, RZ, RZ, R13, P3 ; IADD3.X R11, RZ, R5, RZ, P2, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; IMAD.MOV.U32 R13, RZ, RZ, R15 ; STG.E [R8.64+0x38], R19 ; @!P1 BRA 0xc90 ; IADD3 R4, -R3, 0x3fc, RZ ; ISETP.GT.AND P1, PT, R4, 0x4, PT ; @!P1 BRA 0x1150 ; LDG.E R9, [R12.64] ; MOV R5, R11 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.WIDE R6, R10, 0x4, R4 ; STG.E [R6.64], R9 ; LDG.E R15, [R12.64+0x4] ; IMAD.WIDE R4, R2, 0x4, R4 ; STG.E [R4.64], R15 ; LDG.E R17, [R12.64+0x8] ; STG.E [R4.64+0x4], R17 ; LDG.E R19, [R12.64+0xc] ; STG.E [R4.64+0x8], R19 ; LDG.E R21, [R12.64+0x10] ; STG.E [R6.64+0x10], R21 ; LDG.E R23, [R12.64+0x14] ; STG.E [R4.64+0x10], R23 ; LDG.E R9, [R12.64+0x18] ; STG.E [R4.64+0x14], R9 ; LDG.E R15, [R12.64+0x1c] ; IADD3 R8, P2, R12, 0x20, RZ ; IADD3 R0, P1, R0, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.X R17, RZ, RZ, R13, P2 ; IADD3 R3, R3, 0x8, RZ ; IMAD.X R11, RZ, RZ, R11, P1 ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; MOV R13, R17 ; STG.E [R4.64+0x18], R15 ; ISETP.LT.OR P0, PT, R3, 0x3fc, P0 ; @!P0 EXIT ; LDG.E R7, [R12.64] ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, R11 ; IMAD.WIDE R10, R10, 0x4, R4 ; STG.E [R10.64], R7 ; LDG.E R9, [R12.64+0x4] ; IMAD.WIDE R2, R2, 0x4, R4 ; STG.E [R2.64], R9 ; LDG.E R5, [R12.64+0x8] ; STG.E [R2.64+0x4], R5 ; LDG.E R15, [R12.64+0xc] ; STG.E [R2.64+0x8], R15 ; EXIT ; BRA 0x1240; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z20initializePopulationP17curandStateXORWOWPf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R2, 0x3f, PT ; @P0 EXIT ; IMAD.SHL.U32 R4, R2, 0x400, RZ ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD.MOV.U32 R3, RZ, RZ, 0x30 ; IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IADD3 R16, P0, R4, 0x8, RZ ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; IMAD.X R17, RZ, RZ, R5, P0 ; LDG.E R4, [R2.64+0x4] ; LDG.E R8, [R2.64+0x14] ; LDG.E R6, [R2.64] ; LDG.E R7, [R2.64+0x8] ; LDG.E R9, [R2.64+0xc] ; LDG.E R11, [R2.64+0x10] ; SHF.R.U32.HI R5, RZ, 0x2, R4 ; LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ; STG.E [R2.64+0x10], R8 ; IMAD.SHL.U32 R4, R5, 0x2, RZ ; STG.E [R2.64+0x4], R7 ; LOP3.LUT R5, R8, R4, R5, 0x96, !PT ; SHF.L.U32 R4, R8, 0x4, RZ ; STG.E [R2.64+0x8], R9 ; LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ; STG.E [R2.64+0xc], R11 ; IADD3 R4, R6, 0x587c5, RZ ; IMAD.MOV.U32 R6, RZ, RZ, 0x2f800000 ; STG.E [R2.64+0x14], R5 ; IMAD.IADD R10, R5, 0x1, R4 ; STG.E [R2.64], R4 ; I2F.U32 R13, R10 ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; IMAD.MOV.U32 R4, RZ, RZ, R16 ; FFMA R13, R13, R6, 1.1641532182693481445e-10 ; STG.E [R4.64+-0x8], R13 ; LDG.E R10, [R2.64+0x4] ; LDG.E R12, [R2.64+0x14] ; LDG.E R14, [R2.64] ; LDG.E R9, [R2.64+0x8] ; LDG.E R11, [R2.64+0xc] ; LDG.E R15, [R2.64+0x10] ; SHF.R.U32.HI R7, RZ, 0x2, R10 ; LOP3.LUT R7, R7, R10, RZ, 0x3c, !PT ; STG.E [R2.64+0x10], R12 ; IADD3 R14, R14, 0x587c5, RZ ; IMAD.SHL.U32 R8, R7, 0x2, RZ ; STG.E [R2.64+0x4], R9 ; LOP3.LUT R8, R12.reuse, R8, R7, 0x96, !PT ; SHF.L.U32 R7, R12, 0x4, RZ ; STG.E [R2.64+0x8], R11 ; LOP3.LUT R7, R8, R7, RZ, 0x3c, !PT ; STG.E [R2.64+0xc], R15 ; IMAD.IADD R8, R7, 0x1, R14 ; STG.E [R2.64+0x14], R7 ; I2F.U32 R13, R8 ; STG.E [R2.64], R14 ; FFMA R13, R13, R6, 1.1641532182693481445e-10 ; STG.E [R4.64+-0x4], R13 ; LDG.E R10, [R2.64+0x4] ; LDG.E R16, [R2.64+0x14] ; LDG.E R18, [R2.64] ; LDG.E R17, [R2.64+0x8] ; LDG.E R19, [R2.64+0xc] ; LDG.E R21, [R2.64+0x10] ; SHF.R.U32.HI R7, RZ, 0x2, R10 ; LOP3.LUT R7, R7, R10, RZ, 0x3c, !PT ; STG.E [R2.64+0x10], R16 ; IADD3 R18, R18, 0x587c5, RZ ; IMAD.SHL.U32 R8, R7, 0x2, RZ ; STG.E [R2.64+0x4], R17 ; LOP3.LUT R8, R16.reuse, R8, R7, 0x96, !PT ; IMAD.SHL.U32 R7, R16, 0x10, RZ ; STG.E [R2.64+0x8], R19 ; LOP3.LUT R7, R8, R7, RZ, 0x3c, !PT ; STG.E [R2.64+0xc], R21 ; IMAD.IADD R8, R7, 0x1, R18 ; STG.E [R2.64+0x14], R7 ; I2F.U32 R9, R8 ; STG.E [R2.64], R18 ; FFMA R9, R9, R6, 1.1641532182693481445e-10 ; STG.E [R4.64], R9 ; LDG.E R10, [R2.64+0x4] ; LDG.E R12, [R2.64+0x14] ; LDG.E R14, [R2.64] ; LDG.E R11, [R2.64+0x8] ; LDG.E R13, [R2.64+0xc] ; LDG.E R15, [R2.64+0x10] ; IADD3 R0, R0, 0x4, RZ ; IADD3 R16, P1, R4, 0x10, RZ ; ISETP.NE.AND P0, PT, R0, 0x400, PT ; IMAD.X R17, RZ, RZ, R5, P1 ; SHF.R.U32.HI R7, RZ, 0x2, R10 ; LOP3.LUT R7, R7, R10, RZ, 0x3c, !PT ; STG.E [R2.64+0x10], R12 ; SHF.L.U32 R8, R7, 0x1, RZ ; IADD3 R14, R14, 0x587c5, RZ ; LOP3.LUT R8, R12.reuse, R8, R7, 0x96, !PT ; IMAD.SHL.U32 R7, R12, 0x10, RZ ; STG.E [R2.64+0x4], R11 ; LOP3.LUT R7, R8, R7, RZ, 0x3c, !PT ; STG.E [R2.64+0x8], R13 ; IMAD.IADD R8, R7, 0x1, R14 ; STG.E [R2.64+0x14], R7 ; I2F.U32 R9, R8 ; STG.E [R2.64+0xc], R15 ; STG.E [R2.64], R14 ; FFMA R9, R9, R6, 1.1641532182693481445e-10 ; STG.E [R4.64+0x4], R9 ; @P0 BRA 0xf0 ; EXIT ; BRA 0x740; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z20initializePopulationP12hiprandStatePf ; -- Begin function _Z20initializePopulationP12hiprandStatePf .globl _Z20initializePopulationP12hiprandStatePf .p2align 8 .type _Z20initializePopulationP12hiprandStatePf,@function _Z20initializePopulationP12hiprandStatePf: ; @_Z20initializePopulationP12hiprandStatePf ; %bb.0: s_load_b32 s2, s[0:1], 0x1c s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 64, v4 s_cbranch_execz .LBB0_4 ; %bb.1: ; %.preheader s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[8:9], null, v4, 48, s[0:1] v_lshlrev_b32_e32 v4, 10, v4 s_mov_b64 s[0:1], 0 s_clause 0x2 global_load_b32 v11, v[8:9], off offset:40 global_load_b128 v[0:3], v[8:9], off offset:24 global_load_b32 v10, v[8:9], off v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[4:5] v_add_co_u32 v12, vcc_lo, s2, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v13, vcc_lo, s3, v5, vcc_lo .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(1) v_lshrrev_b32_e32 v4, 2, v0 s_waitcnt vmcnt(0) v_dual_mov_b32 v7, v11 :: v_dual_add_nc_u32 v10, 0x587c5, v10 v_add_co_u32 v14, vcc_lo, v12, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v0, v4, v0 v_lshlrev_b32_e32 v4, 4, v7 v_add_co_ci_u32_e32 v15, vcc_lo, s1, v13, vcc_lo s_add_u32 s0, s0, 4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_dual_mov_b32 v6, v3 :: v_dual_lshlrev_b32 v5, 1, v0 s_addc_u32 s1, s1, 0 s_cmpk_lg_i32 s0, 0x1000 v_xor_b32_e32 v4, v5, v4 v_mov_b32_e32 v5, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor3_b32 v11, v4, v0, v7 v_mov_b32_e32 v4, v1 v_add_nc_u32_e32 v0, v10, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cvt_f32_u32_e32 v3, v0 v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v2 v_mov_b32_e32 v2, v6 v_dual_fmaak_f32 v16, 0x2f800000, v3, 0x2f800000 :: v_dual_mov_b32 v3, v7 global_store_b32 v[14:15], v16, off s_cbranch_scc1 .LBB0_2 ; %bb.3: ; %.loopexit s_clause 0x2 global_store_b32 v[8:9], v11, off offset:40 global_store_b128 v[8:9], v[4:7], off offset:24 global_store_b32 v[8:9], v10, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z20initializePopulationP12hiprandStatePf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 17 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z20initializePopulationP12hiprandStatePf, .Lfunc_end0-_Z20initializePopulationP12hiprandStatePf ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 316 ; NumSgprs: 18 ; NumVgprs: 17 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 17 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z9crossoverPfS_Pii ; -- Begin function _Z9crossoverPfS_Pii .globl _Z9crossoverPfS_Pii .p2align 8 .type _Z9crossoverPfS_Pii,@function _Z9crossoverPfS_Pii: ; @_Z9crossoverPfS_Pii ; %bb.0: s_load_b32 s2, s[0:1], 0x2c s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 64, v1 s_cbranch_execz .LBB1_7 ; %bb.1: s_load_b64 s[2:3], s[0:1], 0x10 v_lshlrev_b32_e32 v2, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v0, v[2:3], off offset:4 s_clause 0x1 s_load_b32 s4, s[0:1], 0x18 s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s4, 1 s_cbranch_scc1 .LBB1_4 ; %bb.2: ; %.lr.ph global_load_b32 v3, v[2:3], off v_lshlrev_b32_e32 v2, 10, v1 s_mov_b32 s5, s4 s_waitcnt vmcnt(0) v_lshlrev_b32_e32 v4, 10, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[2:3] v_lshlrev_b64 v[4:5], 2, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo .LBB1_3: ; =>This Inner Loop Header: Depth=1 global_load_b32 v6, v[4:5], off v_add_co_u32 v4, vcc_lo, v4, 4 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_add_i32 s5, s5, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s5, 0 s_waitcnt vmcnt(0) global_store_b32 v[2:3], v6, off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_cbranch_scc0 .LBB1_3 .LBB1_4: ; %.preheader s_cmpk_gt_i32 s4, 0x3ff s_cbranch_scc1 .LBB1_7 ; %bb.5: ; %.lr.ph30 v_lshl_add_u32 v1, v1, 10, s4 s_waitcnt vmcnt(0) v_lshl_add_u32 v3, v0, 10, s4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v2, 31, v1 v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[1:2] v_lshlrev_b64 v[2:3], 2, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo s_add_i32 s0, s4, -1 .LBB1_6: ; =>This Inner Loop Header: Depth=1 global_load_b32 v4, v[2:3], off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmpk_lt_i32 s0, 0x3ff s_waitcnt vmcnt(0) global_store_b32 v[0:1], v4, off v_add_co_u32 v0, vcc_lo, v0, 4 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_cbranch_scc1 .LBB1_6 .LBB1_7: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9crossoverPfS_Pii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z9crossoverPfS_Pii, .Lfunc_end1-_Z9crossoverPfS_Pii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 448 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z6mutateP12hiprandStatePff ; -- Begin function _Z6mutateP12hiprandStatePff .globl _Z6mutateP12hiprandStatePff .p2align 8 .type _Z6mutateP12hiprandStatePff,@function _Z6mutateP12hiprandStatePff: ; @_Z6mutateP12hiprandStatePff ; %bb.0: s_load_b32 s2, s[0:1], 0x24 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 64, v4 s_cbranch_execz .LBB2_7 ; %bb.1: ; %.preheader s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s2, s[0:1], 0x10 s_mov_b64 s[0:1], 0 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[7:8], null, v4, 48, s[4:5] v_lshlrev_b32_e32 v4, 10, v4 s_clause 0x2 global_load_b32 v11, v[7:8], off offset:40 global_load_b128 v[0:3], v[7:8], off offset:24 global_load_b32 v13, v[7:8], off v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[4:5] v_add_co_u32 v9, vcc_lo, s6, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v10, vcc_lo, s7, v5, vcc_lo .LBB2_2: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(1) v_lshrrev_b32_e32 v4, 2, v0 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v12, 0x587c5, v13 v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v0, v4, v0 v_lshlrev_b32_e32 v4, 4, v11 v_lshlrev_b32_e32 v5, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v4, v5, v4 v_mov_b32_e32 v5, v3 v_xor3_b32 v0, v4, v0, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, v12, v0 v_mov_b32_e32 v14, v0 v_cvt_f32_u32_e32 v4, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmaak_f32 v4, 0x2f800000, v4, 0x2f800000 v_cmp_gt_f32_e32 vcc_lo, s2, v4 v_mov_b32_e32 v4, v2 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB2_4 ; %bb.3: ; in Loop: Header=BB2_2 Depth=1 v_lshrrev_b32_e32 v4, 2, v1 v_add_nc_u32_e32 v12, 0xb0f8a, v13 v_add_co_u32 v15, vcc_lo, v9, s0 v_add_co_ci_u32_e32 v16, vcc_lo, s1, v10, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v1, v4, v1 v_lshlrev_b32_e32 v4, 4, v0 v_dual_mov_b32 v6, v0 :: v_dual_lshlrev_b32 v5, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v4, v5, v4 v_mov_b32_e32 v5, v11 v_xor3_b32 v14, v4, v1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v4, v3 :: v_dual_add_nc_u32 v1, v14, v12 v_cvt_f32_u32_e32 v1, v1 s_delay_alu instid0(VALU_DEP_1) v_dual_fmaak_f32 v0, 0x2f800000, v1, 0x2f800000 :: v_dual_mov_b32 v1, v2 global_store_b32 v[15:16], v0, off .LBB2_4: ; in Loop: Header=BB2_2 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmpk_lg_i32 s0, 0x1000 s_cbranch_scc0 .LBB2_6 ; %bb.5: ; in Loop: Header=BB2_2 Depth=1 v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v4 v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v3, v6 v_mov_b32_e32 v11, v14 v_mov_b32_e32 v13, v12 s_branch .LBB2_2 .LBB2_6: ; %.loopexit v_mov_b32_e32 v3, v1 s_clause 0x2 global_store_b32 v[7:8], v14, off offset:40 global_store_b128 v[7:8], v[3:6], off offset:24 global_store_b32 v[7:8], v12, off .LBB2_7: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6mutateP12hiprandStatePff .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 17 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z6mutateP12hiprandStatePff, .Lfunc_end2-_Z6mutateP12hiprandStatePff ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 444 ; NumSgprs: 18 ; NumVgprs: 17 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 17 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z20initializePopulationP12hiprandStatePf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z20initializePopulationP12hiprandStatePf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 17 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9crossoverPfS_Pii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9crossoverPfS_Pii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6mutateP12hiprandStatePff .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6mutateP12hiprandStatePff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 17 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
10,473
10,124
113,403
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000c2923_00000000-6_cuda_code_034402.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3853: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3853: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " failed: " .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3849: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3849: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf .type _Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf, @function _Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf: .LFB3875: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z20initializePopulationP17curandStateXORWOWPf(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3875: .size _Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf, .-_Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf .globl _Z20initializePopulationP17curandStateXORWOWPf .type _Z20initializePopulationP17curandStateXORWOWPf, @function _Z20initializePopulationP17curandStateXORWOWPf: .LFB3876: .cfi_startproc endbr64 jmp _Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf .cfi_endproc .LFE3876: .size _Z20initializePopulationP17curandStateXORWOWPf, .-_Z20initializePopulationP17curandStateXORWOWPf .globl _Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii .type _Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii, @function _Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii: .LFB3877: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L13 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z9crossoverPfS_Pii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L13: movq 136(%rsp), %rax subq %fs:40, %rax je .L15 call __stack_chk_fail@PLT .L15: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3877: .size _Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii, .-_Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii .globl _Z9crossoverPfS_Pii .type _Z9crossoverPfS_Pii, @function _Z9crossoverPfS_Pii: .LFB3878: .cfi_startproc endbr64 jmp _Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii .cfi_endproc .LFE3878: .size _Z9crossoverPfS_Pii, .-_Z9crossoverPfS_Pii .globl _Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff .type _Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff, @function _Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff: .LFB3879: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx movq %rsi, 16(%rsp) leaq 48(%rsp), %rdi leaq 60(%rsp), %rsi movss %xmm0, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L18 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z6mutateP17curandStateXORWOWPff(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L18: movq 120(%rsp), %rax subq %fs:40, %rax je .L20 call __stack_chk_fail@PLT .L20: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3879: .size _Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff, .-_Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff .globl _Z6mutateP17curandStateXORWOWPff .type _Z6mutateP17curandStateXORWOWPff, @function _Z6mutateP17curandStateXORWOWPff: .LFB3880: .cfi_startproc endbr64 jmp _Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff .cfi_endproc .LFE3880: .size _Z6mutateP17curandStateXORWOWPff, .-_Z6mutateP17curandStateXORWOWPff .section .rodata.str1.1 .LC2: .string "cudaMalloc" .LC3: .string "cudaMemcpy" .LC4: .string "initializePopulation" .LC5: .string "cudaDeviceSynchronize" .LC6: .string "crossover" .LC8: .string "mutate" .LC9: .string "GPU " .LC10: .string " Final individual genes: " .LC11: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3850: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 xorl %r15d, %r15d pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $168, %rsp .cfi_def_cfa_offset 224 movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 136(%rsp), %rax movq %rax, 16(%rsp) .L25: movl $512, %edi call _Znam@PLT movq 16(%rsp), %rcx xorl %edx, %edx movq %rax, (%rcx,%r15,8) .L24: leal 1(%rdx), %ecx movl %edx, (%rax,%rdx,4) andl $63, %ecx movl %ecx, 4(%rax,%rdx,4) addq $2, %rdx cmpq $128, %rdx jne .L24 testq %r15, %r15 jne .L53 movl $1, %r15d jmp .L25 .L53: xorl %ebx, %ebx xorl %r14d, %r14d leaq .LC2(%rip), %rbp .L27: movl %r14d, %edi leaq 72(%rsp), %r12 leaq 120(%rsp), %r13 call cudaSetDevice@PLT leaq (%r12,%rbx), %rdi movl $262144, %esi call cudaMalloc@PLT movq %rbp, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 104(%rsp), %rax movl $262144, %esi leaq (%rbx,%rax), %rdi movq %rax, 8(%rsp) call cudaMalloc@PLT movq %rbp, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 0(%r13,%rbx), %rdi movl $512, %esi call cudaMalloc@PLT movq %rbp, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 88(%rsp,%rbx), %rdi movl $3072, %esi call cudaMalloc@PLT movq %rbp, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rax movq 120(%rsp,%rbx), %rdi movl $1, %ecx movl $512, %edx movq (%rax,%rbx), %rsi call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx movl $1, %ecx movabsq $4294967297, %rdi movl $1, %esi movq %rdx, 44(%rsp) movl $1, 52(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L26 movq 72(%rsp,%rbx), %rsi movq 88(%rsp,%rbx), %rdi call _Z60__device_stub__Z20initializePopulationP17curandStateXORWOWPfP17curandStateXORWOWPf .L26: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi addq $8, %rbx movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc testl %r14d, %r14d jne .L54 movl $1, %r14d jmp .L27 .L54: movl $100, 28(%rsp) .L28: movq 8(%rsp), %rbx xorl %ebp, %ebp movabsq $4294967552, %r14 .L31: movl %ebp, %edi call cudaSetDevice@PLT xorl %r9d, %r9d xorl %r8d, %r8d movq %r14, %rdx movl $1, %ecx movl $1, %esi movabsq $4294967297, %rax movq %r14, 44(%rsp) movq %rax, %rdi movl $1, 52(%rsp) movq %rax, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L29 movq 0(%r13,%rbp,8), %rdx movq (%r12,%rbp,8), %rdi movl $512, %ecx movq (%rbx), %rsi call _Z33__device_stub__Z9crossoverPfS_PiiPfS_Pii .L29: call cudaGetLastError@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %r9d, %r9d xorl %r8d, %r8d movq %r14, %rdx movl $1, %ecx movl $1, %esi movabsq $4294967297, %rax movq %r14, 44(%rsp) movq %rax, %rdi movl $1, 52(%rsp) movq %rax, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L30 movq 88(%rsp,%rbp,8), %rdi movss .LC7(%rip), %xmm0 movq (%rbx), %rsi call _Z46__device_stub__Z6mutateP17curandStateXORWOWPffP17curandStateXORWOWPff .L30: call cudaGetLastError@PLT leaq .LC8(%rip), %rsi addq $8, %rbx movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq -8(%rbx), %rdx movq (%r12,%rbp,8), %rax movq %rdx, (%r12,%rbp,8) movq %rax, -8(%rbx) testq %rbp, %rbp jne .L55 movq %r15, %rbp jmp .L31 .L55: decl 28(%rsp) jne .L28 xorl %ebx, %ebx leaq .LC3(%rip), %r15 .L32: movl %ebx, %edi leaq 56(%rsp), %r14 call cudaSetDevice@PLT movl $262144, %edi call _Znam@PLT movq (%r12,%rbx,8), %rsi movl $2, %ecx movl $262144, %edx movq %rax, %rdi movq %rax, (%r14,%rbx,8) call cudaMemcpy@PLT movq %r15, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%r12,%rbx,8), %rdi call cudaFree@PLT movq 8(%rsp), %rax movq (%rax,%rbx,8), %rdi call cudaFree@PLT movq 0(%r13,%rbx,8), %rdi call cudaFree@PLT movq 88(%rsp,%rbx,8), %rdi call cudaFree@PLT movq 16(%rsp), %rax movq (%rax,%rbx,8), %rdi testq %rdi, %rdi je .L33 call _ZdaPv@PLT .L33: testq %rbx, %rbx jne .L56 movq %rbp, %rbx jmp .L32 .L56: xorl %ebp, %ebp .L36: leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rdi xorl %r13d, %r13d call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %esi leaq .LC11(%rip), %r15 movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC10(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L34: movq (%r14,%rbp,8), %r12 leaq _ZSt4cout(%rip), %rdi cvtss2sd (%r12,%r13), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT addq $4, %r13 movq %r15, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $40, %r13 jne .L34 leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT testq %r12, %r12 je .L35 movq %r12, %rdi call _ZdaPv@PLT .L35: testq %rbp, %rbp jne .L57 movq %rbx, %rbp jmp .L36 .L57: movq 152(%rsp), %rax subq %fs:40, %rax je .L37 call __stack_chk_fail@PLT .L37: addq $168, %rsp .cfi_def_cfa_offset 56 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3850: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z6mutateP17curandStateXORWOWPff" .LC13: .string "_Z9crossoverPfS_Pii" .LC14: .string "_Z20initializePopulationP17curandStateXORWOWPf" .LC15: .string "precalc_xorwow_matrix" .LC16: .string "precalc_xorwow_offset_matrix" .LC17: .string "mrg32k3aM1" .LC18: .string "mrg32k3aM2" .LC19: .string "mrg32k3aM1SubSeq" .LC20: .string "mrg32k3aM2SubSeq" .LC21: .string "mrg32k3aM1Seq" .LC22: .string "mrg32k3aM2Seq" .LC23: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3882: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z6mutateP17curandStateXORWOWPff(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC13(%rip), %rdx orl $-1, %r8d leaq _Z9crossoverPfS_Pii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC14(%rip), %rdx orl $-1, %r8d leaq _Z20initializePopulationP17curandStateXORWOWPf(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC15(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC19(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC20(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC21(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC22(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC23(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3882: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC7: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_034402.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z35__device_stub__initializePopulationP12hiprandStatePf # -- Begin function _Z35__device_stub__initializePopulationP12hiprandStatePf .type _Z35__device_stub__initializePopulationP12hiprandStatePf,@function _Z35__device_stub__initializePopulationP12hiprandStatePf: # @_Z35__device_stub__initializePopulationP12hiprandStatePf .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z20initializePopulationP12hiprandStatePf, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z35__device_stub__initializePopulationP12hiprandStatePf, .Lfunc_end0-_Z35__device_stub__initializePopulationP12hiprandStatePf .cfi_endproc # -- End function .globl _Z24__device_stub__crossoverPfS_Pii # -- Begin function _Z24__device_stub__crossoverPfS_Pii .type _Z24__device_stub__crossoverPfS_Pii,@function _Z24__device_stub__crossoverPfS_Pii: # @_Z24__device_stub__crossoverPfS_Pii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z9crossoverPfS_Pii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z24__device_stub__crossoverPfS_Pii, .Lfunc_end1-_Z24__device_stub__crossoverPfS_Pii .cfi_endproc # -- End function .globl _Z21__device_stub__mutateP12hiprandStatePff # -- Begin function _Z21__device_stub__mutateP12hiprandStatePff .type _Z21__device_stub__mutateP12hiprandStatePff,@function _Z21__device_stub__mutateP12hiprandStatePff: # @_Z21__device_stub__mutateP12hiprandStatePff .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rdx movss %xmm0, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rdx, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z6mutateP12hiprandStatePff, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z21__device_stub__mutateP12hiprandStatePff, .Lfunc_end2-_Z21__device_stub__mutateP12hiprandStatePff .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB3_2 # %bb.1: retq .LBB3_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end3: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end3-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI4_0: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $120, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movb $1, %bl xorl %r14d, %r14d .LBB4_1: # =>This Loop Header: Depth=1 # Child Loop BB4_2 Depth 2 movl $512, %edi # imm = 0x200 callq _Znam movq %rax, 48(%rsp,%r14,8) movl $1, %ecx .LBB4_2: # Parent Loop BB4_1 Depth=1 # => This Inner Loop Header: Depth=2 leaq -1(%rcx), %rdx movl %edx, -4(%rax,%rcx,4) movl %ecx, %esi andl $63, %esi movl %esi, (%rax,%rcx,4) addq $2, %rcx cmpq $126, %rdx jb .LBB4_2 # %bb.3: # in Loop: Header=BB4_1 Depth=1 movl $1, %r14d testb $1, %bl movl $0, %ebx jne .LBB4_1 # %bb.4: # %.preheader105.preheader movb $1, %r15b movabsq $4294967297, %rbx # imm = 0x100000001 xorl %r12d, %r12d leaq 255(%rbx), %r14 .LBB4_5: # %.preheader105 # =>This Inner Loop Header: Depth=1 movl %r12d, %edi callq hipSetDevice leaq (%rsp,%r12,8), %rdi addq $16, %rdi movl $262144, %esi # imm = 0x40000 movq %rdi, 40(%rsp) # 8-byte Spill callq hipMalloc movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq (%rsp,%r12,8), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq (%rsp,%r12,8), %rbp addq $64, %rbp movl $512, %esi # imm = 0x200 movq %rbp, %rdi callq hipMalloc movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq (%rsp,%r12,8), %r13 addq $80, %r13 movl $3072, %esi # imm = 0xC00 movq %r13, %rdi callq hipMalloc movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rbp), %rdi movq 48(%rsp,%r12,8), %rsi movl $512, %edx # imm = 0x200 movl $1, %ecx callq hipMemcpy movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_7 # %bb.6: # in Loop: Header=BB4_5 Depth=1 movq (%r13), %rdi movq 40(%rsp), %rax # 8-byte Reload movq (%rax), %rsi callq _Z35__device_stub__initializePopulationP12hiprandStatePf .LBB4_7: # in Loop: Header=BB4_5 Depth=1 callq hipGetLastError movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $1, %r12d xorl %r13d, %r13d testb $1, %r15b movl $0, %r15d jne .LBB4_5 .LBB4_8: # %.preheader103 # =>This Loop Header: Depth=1 # Child Loop BB4_9 Depth 2 movb $1, %bpl xorl %r15d, %r15d .LBB4_9: # Parent Loop BB4_8 Depth=1 # => This Inner Loop Header: Depth=2 movl %r15d, %edi callq hipSetDevice movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_11 # %bb.10: # in Loop: Header=BB4_9 Depth=2 movq 16(%rsp,%r15,8), %rdi movq (%rsp,%r15,8), %rsi movq 64(%rsp,%r15,8), %rdx movl $512, %ecx # imm = 0x200 callq _Z24__device_stub__crossoverPfS_Pii .LBB4_11: # in Loop: Header=BB4_9 Depth=2 callq hipGetLastError movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_13 # %bb.12: # in Loop: Header=BB4_9 Depth=2 movq 80(%rsp,%r15,8), %rdi movq (%rsp,%r15,8), %rsi movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero callq _Z21__device_stub__mutateP12hiprandStatePff .LBB4_13: # in Loop: Header=BB4_9 Depth=2 callq hipGetLastError movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 16(%rsp,%r15,8), %rax movq (%rsp,%r15,8), %rcx movq %rcx, 16(%rsp,%r15,8) movq %rax, (%rsp,%r15,8) movl $1, %r15d testb $1, %bpl movl $0, %ebp jne .LBB4_9 # %bb.14: # in Loop: Header=BB4_8 Depth=1 incl %r13d cmpl $100, %r13d jne .LBB4_8 # %bb.15: # %.preheader102.preheader movb $1, %bpl xorl %ebx, %ebx .LBB4_16: # %.preheader102 # =>This Inner Loop Header: Depth=1 movl %ebx, %edi callq hipSetDevice movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, 96(%rsp,%rbx,8) movq 16(%rsp,%rbx,8), %rsi movl $262144, %edx # imm = 0x40000 movq %rax, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 16(%rsp,%rbx,8), %rdi callq hipFree movq (%rsp,%rbx,8), %rdi callq hipFree movq 64(%rsp,%rbx,8), %rdi callq hipFree movq 80(%rsp,%rbx,8), %rdi callq hipFree movq 48(%rsp,%rbx,8), %rdi testq %rdi, %rdi je .LBB4_18 # %bb.17: # in Loop: Header=BB4_16 Depth=1 callq _ZdaPv .LBB4_18: # in Loop: Header=BB4_16 Depth=1 movl $1, %ebx testb $1, %bpl movl $0, %ebp jne .LBB4_16 # %bb.19: # %.preheader.preheader movb $1, %bpl xorl %ebx, %ebx movl $_ZSt4cout, %r14d .LBB4_20: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_21 Depth 2 movl $_ZSt4cout, %edi movl $.L.str.8, %esi movl $4, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebx, %esi callq _ZNSolsEi movl $.L.str.9, %esi movl $25, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 96(%rsp,%rbx,8), %rbx xorl %r15d, %r15d .LBB4_21: # Parent Loop BB4_20 Depth=1 # => This Inner Loop Header: Depth=2 xorps %xmm0, %xmm0 cvtss2sd (%rbx,%r15,4), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.10, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r15 cmpq $10, %r15 jne .LBB4_21 # %bb.22: # in Loop: Header=BB4_20 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %r14, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq %rbx, %rdi callq _ZdaPv movl $1, %ebx testb $1, %bpl movl $0, %ebp jne .LBB4_20 # %bb.23: xorl %eax, %eax addq $120, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z20initializePopulationP12hiprandStatePf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9crossoverPfS_Pii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6mutateP12hiprandStatePff, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type _Z20initializePopulationP12hiprandStatePf,@object # @_Z20initializePopulationP12hiprandStatePf .section .rodata,"a",@progbits .globl _Z20initializePopulationP12hiprandStatePf .p2align 3, 0x0 _Z20initializePopulationP12hiprandStatePf: .quad _Z35__device_stub__initializePopulationP12hiprandStatePf .size _Z20initializePopulationP12hiprandStatePf, 8 .type _Z9crossoverPfS_Pii,@object # @_Z9crossoverPfS_Pii .globl _Z9crossoverPfS_Pii .p2align 3, 0x0 _Z9crossoverPfS_Pii: .quad _Z24__device_stub__crossoverPfS_Pii .size _Z9crossoverPfS_Pii, 8 .type _Z6mutateP12hiprandStatePff,@object # @_Z6mutateP12hiprandStatePff .globl _Z6mutateP12hiprandStatePff .p2align 3, 0x0 _Z6mutateP12hiprandStatePff: .quad _Z21__device_stub__mutateP12hiprandStatePff .size _Z6mutateP12hiprandStatePff, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " failed: " .size .L.str.1, 10 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "hipMalloc" .size .L.str.2, 10 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMemcpy" .size .L.str.3, 10 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "initializePopulation" .size .L.str.4, 21 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipDeviceSynchronize" .size .L.str.5, 21 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "crossover" .size .L.str.6, 10 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "mutate" .size .L.str.7, 7 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "GPU " .size .L.str.8, 5 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz " Final individual genes: " .size .L.str.9, 26 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz " " .size .L.str.10, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z20initializePopulationP12hiprandStatePf" .size .L__unnamed_1, 42 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z9crossoverPfS_Pii" .size .L__unnamed_2, 20 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z6mutateP12hiprandStatePff" .size .L__unnamed_3, 28 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z35__device_stub__initializePopulationP12hiprandStatePf .addrsig_sym _Z24__device_stub__crossoverPfS_Pii .addrsig_sym _Z21__device_stub__mutateP12hiprandStatePff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z20initializePopulationP12hiprandStatePf .addrsig_sym _Z9crossoverPfS_Pii .addrsig_sym _Z6mutateP12hiprandStatePff .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15updateParticlesPfS_S_S_S_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R0, 0x3f, PT ; @P0 EXIT ; HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R8, R0, 0x3, RZ ; ULDC.64 UR6, c[0x0][0x118] ; MOV R2, c[0x0][0x178] ; MOV R3, c[0x0][0x17c] ; IMAD.WIDE R4, R8.reuse, R11.reuse, c[0x0][0x160] ; LDG.E R10, [R2.64] ; IMAD.WIDE R6, R8.reuse, R11.reuse, c[0x0][0x170] ; LDG.E R13, [R4.64] ; IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; LDG.E R12, [R6.64] ; LDG.E R14, [R8.64] ; LOP3.LUT R15, R0, 0xaad26b49, RZ, 0x3c, !PT ; IMAD R15, R15, 0x4182bed5, RZ ; IADD3 R16, R15, 0x75bcd15, RZ ; SHF.R.U32.HI R17, RZ, 0x2, R16 ; IADD3 R18, R15, 0x583f19, RZ ; LOP3.LUT R19, R17, R16, RZ, 0x3c, !PT ; LOP3.LUT R17, R15, 0x159a55e5, RZ, 0x3c, !PT ; SHF.R.S32.HI R16, RZ, 0x1f, R0 ; SHF.L.U32 R20, R18, 0x4, RZ ; SHF.R.U32.HI R22, RZ, 0x2, R17 ; LOP3.LUT R16, R16, 0xf7dcefdd, RZ, 0x3c, !PT ; LOP3.LUT R20, R19.reuse, R20, R18, 0x96, !PT ; SHF.L.U32 R19, R19, 0x1, RZ ; LOP3.LUT R22, R22, 0x159a55e5, R15.reuse, 0x96, !PT ; IMAD R16, R16, -0x658354e5, R15 ; LOP3.LUT R19, R20, R19, RZ, 0x3c, !PT ; SHF.L.U32 R15, R22, 0x1, RZ ; IADD3 R16, R16, 0x64f0c9, RZ ; LOP3.LUT R22, R19.reuse, R15, R22, 0x96, !PT ; SHF.L.U32 R15, R19, 0x4, RZ ; IADD3 R19, R16, 0x587c5, R19 ; LOP3.LUT R15, R22, R15, RZ, 0x3c, !PT ; IADD3 R16, R16, 0xb0f8a, R15 ; I2F.U32 R19, R19 ; HFMA2.MMA R20, -RZ, RZ, 0.1171875, 0 ; I2F.U32 R16, R16 ; FFMA R15, R19, R20.reuse, 1.1641532182693481445e-10 ; FADD R17, -R13, R12 ; FMUL R12, R15, 1.4944499731063842773 ; FMUL R18, R14, 0.72899997234344482422 ; FFMA R14, R16, R20, 1.1641532182693481445e-10 ; FADD R13, -R13, R10 ; LDG.E R16, [R8.64+0x4] ; FFMA R17, R12, R17, R18 ; FMUL R10, R14, 1.4944499731063842773 ; FFMA R13, R10, R13, R17 ; STG.E [R8.64], R13 ; LDG.E R14, [R4.64+0x4] ; LDG.E R15, [R6.64+0x4] ; LDG.E R17, [R2.64+0x4] ; FMUL R16, R16, 0.72899997234344482422 ; FADD R15, -R14.reuse, R15 ; FADD R17, -R14, R17 ; FFMA R15, R12, R15, R16 ; LDG.E R16, [R8.64+0x8] ; FFMA R15, R10, R17, R15 ; STG.E [R8.64+0x4], R15 ; LDG.E R14, [R4.64+0x8] ; LDG.E R17, [R6.64+0x8] ; LDG.E R19, [R2.64+0x8] ; FMUL R16, R16, 0.72899997234344482422 ; FADD R17, -R14.reuse, R17 ; FADD R19, -R14, R19 ; FFMA R16, R12, R17, R16 ; FFMA R19, R10, R19, R16 ; STG.E [R8.64+0x8], R19 ; LDG.E R10, [R4.64] ; FADD R13, R13, R10 ; LDG.E R10, [R4.64+0x4] ; STG.E [R4.64], R13 ; LDG.E R15, [R8.64+0x4] ; FADD R15, R10, R15 ; LDG.E R10, [R4.64+0x8] ; STG.E [R4.64+0x4], R15 ; LDG.E R17, [R8.64+0x8] ; FADD R17, R10, R17 ; IMAD.WIDE R10, R0, R11, c[0x0][0x180] ; STG.E [R4.64+0x8], R17 ; LDG.E R12, [R10.64] ; FFMA R0, R13, R13, RZ ; FFMA R0, R15, R15, R0 ; FFMA R13, R17, R17, R0 ; FSETP.GEU.AND P0, PT, R13, R12, PT ; @!P0 STG.E [R10.64], R13 ; @!P0 LDG.E R15, [R4.64] ; @!P0 STG.E [R6.64], R15 ; @!P0 LDG.E R19, [R4.64+0x4] ; MOV R8, c[0x0][0x188] ; MOV R9, c[0x0][0x18c] ; @!P0 STG.E [R6.64+0x4], R19 ; @!P0 LDG.E R17, [R4.64+0x8] ; @!P0 STG.E [R6.64+0x8], R17 ; LDG.E R0, [R8.64] ; FSETP.GEU.AND P0, PT, R13, R0, PT ; @P0 EXIT ; S2R R0, SR_LANEID ; REDUX.MIN UR5, R13 ; VOTEU.ANY UR4, UPT, PT ; UFLO.U32 UR4, UR4 ; ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; MOV R7, UR5 ; @P0 RED.E.MIN.STRONG.GPU [R8.64], R7 ; LDG.E R0, [R8.64] ; FSETP.NEU.AND P0, PT, R0, R13, PT ; @P0 EXIT ; LDG.E R7, [R4.64] ; STG.E [R2.64], R7 ; LDG.E R9, [R4.64+0x4] ; STG.E [R2.64+0x4], R9 ; LDG.E R11, [R4.64+0x8] ; STG.E [R2.64+0x8], R11 ; EXIT ; BRA 0x780; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15updateParticlesPfS_S_S_S_S_ ; -- Begin function _Z15updateParticlesPfS_S_S_S_S_ .globl _Z15updateParticlesPfS_S_S_S_S_ .p2align 8 .type _Z15updateParticlesPfS_S_S_S_S_,@function _Z15updateParticlesPfS_S_S_S_S_: ; @_Z15updateParticlesPfS_S_S_S_S_ ; %bb.0: s_load_b32 s2, s[0:1], 0x3c s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 64, v1 s_cbranch_execz .LBB0_18 ; %bb.1: v_xor_b32_e32 v0, 0x2c7f967f, v1 v_cmp_lt_i32_e32 vcc_lo, -1, v1 s_clause 0x1 s_load_b256 s[4:11], s[0:1], 0x0 s_load_b128 s[0:3], s[0:1], 0x20 v_mul_lo_u32 v0, 0x493c4aa1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, 0x75bcd15, v0 v_add_nc_u32_e32 v4, 0x583f19, v0 v_lshrrev_b32_e32 v3, 2, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b32_e32 v5, 4, v4 v_xor_b32_e32 v2, v3, v2 v_xor_b32_e32 v3, 0x159a55e5, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b32_e32 v6, 1, v2 v_lshrrev_b32_e32 v7, 2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v5, v5, v6 v_xor_b32_e32 v6, v7, v3 v_mov_b32_e32 v3, 0x8a5d614f s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor3_b32 v4, v5, v4, v2 v_lshlrev_b32_e32 v5, 1, v6 v_lshl_add_u32 v2, v1, 1, v1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v8, 0xfa091aa4, v3 :: v_dual_lshlrev_b32 v7, 4, v4 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add3_u32 v0, v0, v8, 0x64f0c9 v_xor_b32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[7:8], 2, v[2:3] v_add3_u32 v2, v0, v4, 0x587c5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor3_b32 v5, v5, v6, v4 v_cvt_f32_u32_e32 v2, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_add3_u32 v0, v0, v5, 0xb0f8a s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s8, v7 v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo v_cvt_f32_u32_e32 v0, v0 v_add_co_u32 v3, vcc_lo, s4, v7 v_fmaak_f32 v9, 0x2f800000, v2, 0x2f800000 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmaak_f32 v10, 0x2f800000, v0, 0x2f800000 v_add_co_u32 v0, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v8, vcc_lo v_dual_mul_f32 v8, 0x3fbf4a23, v10 :: v_dual_mul_f32 v7, 0x3fbf4a23, v9 v_mov_b32_e32 v9, 0 s_mov_b64 s[4:5], 0 .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v10, vcc_lo, v5, s4 v_add_co_ci_u32_e32 v11, vcc_lo, s5, v6, vcc_lo v_add_co_u32 v12, vcc_lo, v3, s4 v_add_co_ci_u32_e32 v13, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v14, vcc_lo, v0, s4 v_add_co_ci_u32_e32 v15, vcc_lo, s5, v2, vcc_lo global_load_b32 v10, v[10:11], off global_load_b32 v11, v[12:13], off global_load_b32 v12, v[14:15], off s_add_u32 s6, s10, s4 s_addc_u32 s7, s11, s5 s_add_u32 s4, s4, 4 global_load_b32 v13, v9, s[6:7] s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s4, 12 s_waitcnt vmcnt(2) v_sub_f32_e32 v10, v10, v11 s_waitcnt vmcnt(0) v_dual_mul_f32 v12, 0x3f3a9fbe, v12 :: v_dual_sub_f32 v11, v13, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v12, v7, v10 v_fmac_f32_e32 v12, v8, v11 global_store_b32 v[14:15], v12, off s_cbranch_scc1 .LBB0_2 ; %bb.3: ; %.preheader89.preheader s_mov_b64 s[4:5], 0 .LBB0_4: ; %.preheader89 ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v7, vcc_lo, v0, s4 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v2, vcc_lo v_add_co_u32 v9, vcc_lo, v3, s4 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v4, vcc_lo s_add_u32 s4, s4, 4 global_load_b32 v7, v[7:8], off global_load_b32 v8, v[9:10], off s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s4, 12 s_waitcnt vmcnt(0) v_add_f32_e32 v7, v7, v8 global_store_b32 v[9:10], v7, off s_cbranch_scc1 .LBB0_4 ; %bb.5: ; %.preheader88.preheader v_mov_b32_e32 v7, 0 s_mov_b64 s[4:5], 0 .LBB0_6: ; %.preheader88 ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v8, vcc_lo, v3, s4 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v4, vcc_lo s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_cmp_eq_u32 s4, 12 global_load_b32 v0, v[8:9], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v7, v0, v0 s_cbranch_scc0 .LBB0_6 ; %bb.7: v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[0:1], off s_waitcnt vmcnt(0) v_cmpx_lt_f32_e32 v7, v2 s_cbranch_execz .LBB0_10 ; %bb.8: s_mov_b64 s[0:1], 0 global_store_b32 v[0:1], v7, off .LBB0_9: ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v0, vcc_lo, v3, s0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo global_load_b32 v2, v[0:1], off v_add_co_u32 v0, vcc_lo, v5, s0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s0, 12 s_waitcnt vmcnt(0) global_store_b32 v[0:1], v2, off s_cbranch_scc1 .LBB0_9 .LBB0_10: ; %Flow152 s_or_b32 exec_lo, exec_lo, s4 v_mov_b32_e32 v0, 0 global_load_b32 v0, v0, s[2:3] s_waitcnt vmcnt(0) v_cmp_lt_f32_e32 vcc_lo, v7, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_18 ; %bb.11: s_mov_b32 s1, exec_lo s_mov_b32 s0, -1 .LBB0_12: ; %ComputeLoop ; =>This Inner Loop Header: Depth=1 s_ctz_i32_b32 s4, s1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_readlane_b32 s5, v7, s4 s_lshl_b32 s4, 1, s4 s_and_not1_b32 s1, s1, s4 s_delay_alu instid0(VALU_DEP_1) s_min_u32 s0, s0, s5 s_cmp_lg_u32 s1, 0 s_cbranch_scc1 .LBB0_12 ; %bb.13: ; %ComputeEnd v_mbcnt_lo_u32_b32 v0, exec_lo, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_xor_b32 s1, exec_lo, s1 s_cbranch_execz .LBB0_15 ; %bb.14: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 global_atomic_min_u32 v0, v1, s[2:3] .LBB0_15: s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v0, 0 global_load_b32 v1, v0, s[2:3] s_waitcnt vmcnt(0) v_cmp_eq_f32_e32 vcc_lo, v1, v7 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_18 ; %bb.16: ; %.preheader.preheader s_mov_b64 s[0:1], 0 .LBB0_17: ; %.preheader ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v1, vcc_lo, v3, s0 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo s_add_u32 s2, s10, s0 s_addc_u32 s3, s11, s1 s_add_u32 s0, s0, 4 global_load_b32 v1, v[1:2], off s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s0, 12 s_waitcnt vmcnt(0) global_store_b32 v0, v1, s[2:3] s_cbranch_scc1 .LBB0_17 .LBB0_18: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15updateParticlesPfS_S_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15updateParticlesPfS_S_S_S_S_, .Lfunc_end0-_Z15updateParticlesPfS_S_S_S_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1004 ; NumSgprs: 18 ; NumVgprs: 16 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 16 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15updateParticlesPfS_S_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15updateParticlesPfS_S_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000643c1_00000000-6_cuda_code_056302.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3852: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3852: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_ .type _Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_, @function _Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_: .LFB3874: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) leaq 72(%rsp), %rdi movq %rsi, 32(%rsp) leaq 84(%rsp), %rsi movq %rdx, 24(%rsp) leaq 56(%rsp), %rdx movq %rcx, 16(%rsp) leaq 64(%rsp), %rcx movq %r8, 8(%rsp) movq %r9, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 80(%rsp) movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movq %rsp, %rax movq %rax, 160(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) movq %rax, 84(%rsp) movl $1, 92(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 64(%rsp) .cfi_def_cfa_offset 200 leaq _Z15updateParticlesPfS_S_S_S_S_(%rip), %rdi pushq 64(%rsp) .cfi_def_cfa_offset 208 movq 100(%rsp), %rcx movl 108(%rsp), %r8d movq 88(%rsp), %rsi movl 96(%rsp), %edx leaq 136(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 200 popq %rdx .cfi_def_cfa_offset 192 .L2: movq 168(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $184, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3874: .size _Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_, .-_Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_ .globl _Z15updateParticlesPfS_S_S_S_S_ .type _Z15updateParticlesPfS_S_S_S_S_, @function _Z15updateParticlesPfS_S_S_S_S_: .LFB3875: .cfi_startproc endbr64 jmp _Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_ .cfi_endproc .LFE3875: .size _Z15updateParticlesPfS_S_S_S_S_, .-_Z15updateParticlesPfS_S_S_S_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "CUDA error: " .LC6: .string "Global best position: (" .LC7: .string ", " .LC8: .string ")" .LC9: .string "Global best value: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3849: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $768, %esi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 xorl %ebp, %ebp pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $2680, %rsp .cfi_def_cfa_offset 2736 movq %fs:40, %rax movq %rax, 2664(%rsp) xorl %eax, %eax leaq 16(%rsp), %rdi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $768, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $768, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 48(%rsp), %rdi movl $12, %esi call cudaMalloc@PLT leaq 56(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl $0x7f7fffff, 12(%rsp) .L9: imulq $12, %rbp, %rbx xorl %r15d, %r15d .L10: call rand@PLT incl %r15d movl $0x00000000, 1128(%rsp,%rbx) leaq 360(%rsp), %r12 cvtsi2ssl %eax, %xmm0 mulss .LC1(%rip), %xmm0 leaq 1128(%rsp), %r14 mulss .LC2(%rip), %xmm0 leaq 1896(%rsp), %r13 subss .LC3(%rip), %xmm0 movss %xmm0, 360(%rsp,%rbx) movss %xmm0, 1896(%rsp,%rbx) addq $4, %rbx cmpl $3, %r15d jne .L10 leaq 104(%rsp), %rbx movl $0x7f7fffff, (%rbx,%rbp,4) incq %rbp cmpq $64, %rbp jne .L9 movq 16(%rsp), %rdi movl $1, %ecx movl $768, %edx movq %r12, %rsi movl $100, %ebp call cudaMemcpy@PLT movq 24(%rsp), %rdi movq %r14, %rsi movl $1, %ecx movl $768, %edx leaq 92(%rsp), %r14 call cudaMemcpy@PLT movq 32(%rsp), %rdi movq %r13, %rsi movl $1, %ecx movl $768, %edx leaq 12(%rsp), %r13 call cudaMemcpy@PLT movq 40(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $256, %edx call cudaMemcpy@PLT movq 48(%rsp), %rdi movl $1, %ecx movq %r14, %rsi movl $12, %edx call cudaMemcpy@PLT movq 56(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $4, %edx call cudaMemcpy@PLT movl $1, 88(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) addq $3, %rax movq %rax, 80(%rsp) .L15: movl 76(%rsp), %ecx movq 80(%rsp), %rdi xorl %r9d, %r9d xorl %r8d, %r8d movl $16, 68(%rsp) movl 88(%rsp), %esi movq 68(%rsp), %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L12 movq 56(%rsp), %r9 movq 40(%rsp), %r8 movq 48(%rsp), %rcx movq 32(%rsp), %rdx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z45__device_stub__Z15updateParticlesPfS_S_S_S_S_PfS_S_S_S_S_ .L12: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L13 leaq .LC5(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L13: decl %ebp jne .L15 movq 16(%rsp), %rsi movl $2, %ecx movl $768, %edx movq %r12, %rdi leaq _ZSt4cout(%rip), %rbx leaq .LC7(%rip), %rbp call cudaMemcpy@PLT movq 48(%rsp), %rsi movl $2, %ecx movq %r14, %rdi movl $12, %edx call cudaMemcpy@PLT movq 56(%rsp), %rsi movl $2, %ecx movq %r13, %rdi movl $4, %edx call cudaMemcpy@PLT leaq .LC6(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd 92(%rsp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd 96(%rsp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd 100(%rsp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT leaq .LC8(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC9(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd 12(%rsp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L8: movq 2664(%rsp), %rdx subq %fs:40, %rdx je .L16 call __stack_chk_fail@PLT .L16: addq $2680, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3849: .size main, .-main .section .rodata.str1.1 .LC10: .string "_Z15updateParticlesPfS_S_S_S_S_" .LC11: .string "precalc_xorwow_matrix" .LC12: .string "precalc_xorwow_offset_matrix" .LC13: .string "mrg32k3aM1" .LC14: .string "mrg32k3aM2" .LC15: .string "mrg32k3aM1SubSeq" .LC16: .string "mrg32k3aM2SubSeq" .LC17: .string "mrg32k3aM1Seq" .LC18: .string "mrg32k3aM2Seq" .LC19: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3877: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z15updateParticlesPfS_S_S_S_S_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC11(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC15(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC19(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3877: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 805306368 .align 4 .LC2: .long 1092616192 .align 4 .LC3: .long 1084227584 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_056302.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__updateParticlesPfS_S_S_S_S_ # -- Begin function _Z30__device_stub__updateParticlesPfS_S_S_S_S_ .type _Z30__device_stub__updateParticlesPfS_S_S_S_S_,@function _Z30__device_stub__updateParticlesPfS_S_S_S_S_: # @_Z30__device_stub__updateParticlesPfS_S_S_S_S_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 16(%rsp), %r8 movq %r9, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15updateParticlesPfS_S_S_S_S_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__updateParticlesPfS_S_S_S_S_, .Lfunc_end0-_Z30__device_stub__updateParticlesPfS_S_S_S_S_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x30000000 # float 4.65661287E-10 .LCPI1_1: .long 0x41200000 # float 10 .LCPI1_2: .long 0xc0a00000 # float -5 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $2648, %rsp # imm = 0xA58 .cfi_def_cfa_offset 2704 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 32(%rsp), %rdi movl $768, %esi # imm = 0x300 callq hipMalloc leaq 56(%rsp), %rdi movl $768, %esi # imm = 0x300 callq hipMalloc leaq 48(%rsp), %rdi movl $768, %esi # imm = 0x300 callq hipMalloc leaq 40(%rsp), %rdi movl $256, %esi # imm = 0x100 callq hipMalloc leaq 24(%rsp), %rdi movl $12, %esi callq hipMalloc leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc movl $2139095039, 12(%rsp) # imm = 0x7F7FFFFF leaq 1104(%rsp), %rbx leaq 1872(%rsp), %r14 leaq 336(%rsp), %r15 xorl %r12d, %r12d .LBB1_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 xorl %r13d, %r13d .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 callq rand movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss %xmm1, %xmm0 movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm0 movss .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero addss %xmm1, %xmm0 movss %xmm0, (%r15,%r13,4) movl $0, (%r14,%r13,4) movss %xmm0, (%rbx,%r13,4) incq %r13 cmpq $3, %r13 jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 movl $2139095039, 80(%rsp,%r12,4) # imm = 0x7F7FFFFF incq %r12 addq $12, %rbx addq $12, %r14 addq $12, %r15 cmpq $64, %r12 jne .LBB1_1 # %bb.4: movabsq $4294967300, %rbx # imm = 0x100000004 movq 32(%rsp), %rdi leaq 336(%rsp), %rsi movl $768, %edx # imm = 0x300 movl $1, %ecx callq hipMemcpy movq 56(%rsp), %rdi leaq 1872(%rsp), %rsi movl $768, %edx # imm = 0x300 movl $1, %ecx callq hipMemcpy movq 48(%rsp), %rdi leaq 1104(%rsp), %rsi movl $768, %edx # imm = 0x300 movl $1, %ecx callq hipMemcpy movq 40(%rsp), %rdi leaq 80(%rsp), %rsi movl $256, %edx # imm = 0x100 movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi leaq 68(%rsp), %rsi movl $12, %edx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi leaq 12(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movl $100, %r15d leaq 12(%rbx), %r14 .LBB1_6: # =>This Inner Loop Header: Depth=1 movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_8 # %bb.7: # in Loop: Header=BB1_6 Depth=1 movq 32(%rsp), %rdi movq 56(%rsp), %rsi movq 48(%rsp), %rdx movq 24(%rsp), %rcx movq 40(%rsp), %r8 movq 16(%rsp), %r9 callq _Z30__device_stub__updateParticlesPfS_S_S_S_S_ .LBB1_8: # in Loop: Header=BB1_6 Depth=1 callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB1_9 # %bb.5: # in Loop: Header=BB1_6 Depth=1 decl %r15d jne .LBB1_6 # %bb.13: movq 32(%rsp), %rsi leaq 336(%rsp), %rdi movl $768, %edx # imm = 0x300 movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rsi leaq 68(%rsp), %r14 movl $12, %edx movq %r14, %rdi movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rsi leaq 12(%rsp), %rbx movl $4, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $23, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cvtss2sd (%r14), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.2, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd 4(%r14), %xmm0 movq %r15, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.2, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd 8(%r14), %xmm0 movq %r15, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r14 movl $.L.str.3, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r14), %rax movq -24(%rax), %rdi addq %r14, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r14, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $19, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 32(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_14 .LBB1_9: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_10 # %bb.11: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_12 .LBB1_10: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_12: movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_14: addq $2648, %rsp # imm = 0xA58 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15updateParticlesPfS_S_S_S_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15updateParticlesPfS_S_S_S_S_,@object # @_Z15updateParticlesPfS_S_S_S_S_ .section .rodata,"a",@progbits .globl _Z15updateParticlesPfS_S_S_S_S_ .p2align 3, 0x0 _Z15updateParticlesPfS_S_S_S_S_: .quad _Z30__device_stub__updateParticlesPfS_S_S_S_S_ .size _Z15updateParticlesPfS_S_S_S_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Global best position: (" .size .L.str.1, 24 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ", " .size .L.str.2, 3 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz ")" .size .L.str.3, 2 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Global best value: " .size .L.str.4, 20 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15updateParticlesPfS_S_S_S_S_" .size .L__unnamed_1, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__updateParticlesPfS_S_S_S_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15updateParticlesPfS_S_S_S_S_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z14sum_of_squaresPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ULDC.64 UR6, c[0x0][0x118] ; MOV R4, c[0x0][0x168] ; S2R R8, SR_TID.X ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; LDG.E R4, [R4.64] ; IMAD R2, R6, c[0x0][0x0], R8 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; @!P0 MOV R3, 0x4 ; @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @!P0 LDG.E R0, [R2.64] ; ULDC UR4, c[0x0][0x0] ; USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; ISETP.NE.AND P1, PT, RZ, UR4, PT ; ISETP.NE.AND P0, PT, R8, RZ, PT ; FMUL R7, R0, -2 ; FMUL R7, R4, R7 ; FFMA R7, R0, R0, R7 ; FFMA R7, R4, R4, R7 ; STS [R8.X4], R7 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 BRA 0x240 ; SHF.L.U32 R0, R8, 0x2, RZ ; IMAD.U32 R3, RZ, RZ, UR4 ; ISETP.GE.AND P1, PT, R8, R3, PT ; @!P1 LEA R2, R3, R0, 0x2 ; @!P1 LDS R4, [R8.X4] ; SHF.R.U32.HI R3, RZ, 0x1, R3 ; @!P1 LDS R5, [R2] ; @!P1 FADD R4, R4, R5 ; @!P1 STS [R8.X4], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @P1 BRA 0x1a0 ; @P0 EXIT ; LDS R5, [RZ] ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x2a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13reduce_stddevPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ULDC.64 UR6, c[0x0][0x118] ; S2R R7, SR_TID.X ; IMAD R2, R6, c[0x0][0x0], R7 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; @!P0 MOV R3, 0x4 ; @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @!P0 LDG.E R0, [R2.64] ; ULDC UR4, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R7, RZ, PT ; USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; ISETP.NE.AND P1, PT, RZ, UR4, PT ; STS [R7.X4], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 BRA 0x1d0 ; SHF.L.U32 R0, R7, 0x2, RZ ; IMAD.U32 R3, RZ, RZ, UR4 ; ISETP.GE.AND P1, PT, R7, R3, PT ; @!P1 LEA R2, R3, R0, 0x2 ; @!P1 LDS R4, [R7.X4] ; SHF.R.U32.HI R3, RZ, 0x1, R3 ; @!P1 LDS R5, [R2] ; @!P1 FADD R4, R4, R5 ; @!P1 STS [R7.X4], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @P1 BRA 0x130 ; @P0 EXIT ; LDS R5, [RZ] ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x230; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13reduce_stddevPfS_i ; -- Begin function _Z13reduce_stddevPfS_i .globl _Z13reduce_stddevPfS_i .p2align 8 .type _Z13reduce_stddevPfS_i,@function _Z13reduce_stddevPfS_i: ; @_Z13reduce_stddevPfS_i ; %bb.0: s_clause 0x2 s_load_b32 s5, s[0:1], 0x24 s_load_b32 s6, s[0:1], 0x10 s_load_b128 s[0:3], s[0:1], 0x0 s_mov_b32 s4, s15 s_waitcnt lgkmcnt(0) s_and_b32 s5, s5, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1] v_mov_b32_e32 v2, 0 v_cmp_gt_i32_e32 vcc_lo, s6, v1 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_load_b32 v2, v[1:2], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s6 v_lshl_add_u32 v1, v0, 2, 0 s_cmp_lt_u32 s5, 2 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier .LBB0_3: ; =>This Inner Loop Header: Depth=1 buffer_gl0_inv s_cbranch_scc1 .LBB0_7 ; %bb.4: ; %.lr.ph ; in Loop: Header=BB0_3 Depth=1 s_lshr_b32 s0, s5, 1 s_mov_b32 s1, exec_lo v_cmpx_gt_u32_e64 s0, v0 s_cbranch_execz .LBB0_6 ; %bb.5: ; in Loop: Header=BB0_3 Depth=1 v_lshl_add_u32 v2, s0, 2, v1 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 .LBB0_6: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s5, 4 s_mov_b32 s5, s0 s_branch .LBB0_3 .LBB0_7: ; %._crit_edge s_mov_b32 s0, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_9 ; %bb.8: v_mov_b32_e32 v0, 0 s_mov_b32 s5, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[0:1], s[4:5], 2 s_add_u32 s0, s2, s0 ds_load_b32 v1, v0 s_addc_u32 s1, s3, s1 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13reduce_stddevPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13reduce_stddevPfS_i, .Lfunc_end0-_Z13reduce_stddevPfS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 312 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z14sum_of_squaresPfS_S_i ; -- Begin function _Z14sum_of_squaresPfS_S_i .globl _Z14sum_of_squaresPfS_S_i .p2align 8 .type _Z14sum_of_squaresPfS_S_i,@function _Z14sum_of_squaresPfS_S_i: ; @_Z14sum_of_squaresPfS_S_i ; %bb.0: s_clause 0x3 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s8, s[0:1], 0x18 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] v_mov_b32_e32 v2, 0 v_cmp_gt_i32_e32 vcc_lo, s8, v1 s_and_saveexec_b32 s8, vcc_lo s_cbranch_execz .LBB1_2 ; %bb.1: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s4, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo global_load_b32 v2, v[1:2], off .LBB1_2: s_or_b32 exec_lo, exec_lo, s8 s_load_b32 s4, s[6:7], 0x0 s_waitcnt vmcnt(0) v_add_f32_e32 v1, v2, v2 s_cmp_lt_u32 s3, 2 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v1, s4, v1 v_fma_f32 v2, v2, v2, -v1 v_lshl_add_u32 v1, v0, 2, 0 s_delay_alu instid0(VALU_DEP_2) v_fmac_f32_e64 v2, s4, s4 ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier .LBB1_3: ; =>This Inner Loop Header: Depth=1 buffer_gl0_inv s_cbranch_scc1 .LBB1_7 ; %bb.4: ; %.lr.ph ; in Loop: Header=BB1_3 Depth=1 s_lshr_b32 s4, s3, 1 s_mov_b32 s5, exec_lo v_cmpx_gt_u32_e64 s4, v0 s_cbranch_execz .LBB1_6 ; %bb.5: ; in Loop: Header=BB1_3 Depth=1 v_lshl_add_u32 v2, s4, 2, v1 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 .LBB1_6: ; in Loop: Header=BB1_3 Depth=1 s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s3, 4 s_mov_b32 s3, s4 s_branch .LBB1_3 .LBB1_7: ; %._crit_edge s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB1_9 ; %bb.8: v_mov_b32_e32 v0, 0 s_mov_b32 s3, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[2:3], s[2:3], 2 s_add_u32 s0, s0, s2 ds_load_b32 v1, v0 s_addc_u32 s1, s1, s3 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] .LBB1_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14sum_of_squaresPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z14sum_of_squaresPfS_S_i, .Lfunc_end1-_Z14sum_of_squaresPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 364 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims - .offset: 144 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13reduce_stddevPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13reduce_stddevPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14sum_of_squaresPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14sum_of_squaresPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00081d83_00000000-6_cuda_code_074140.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6835: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6835: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB7721: .cfi_startproc jmp *%rsi .cfi_endproc .LFE7721: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z36__device_stub__Z13reduce_stddevPfS_iPfS_i .type _Z36__device_stub__Z13reduce_stddevPfS_iPfS_i, @function _Z36__device_stub__Z13reduce_stddevPfS_iPfS_i: .LFB6857: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movl %edx, 12(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z13reduce_stddevPfS_i(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L3: movq 120(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6857: .size _Z36__device_stub__Z13reduce_stddevPfS_iPfS_i, .-_Z36__device_stub__Z13reduce_stddevPfS_iPfS_i .globl _Z13reduce_stddevPfS_i .type _Z13reduce_stddevPfS_i, @function _Z13reduce_stddevPfS_i: .LFB6858: .cfi_startproc endbr64 jmp _Z36__device_stub__Z13reduce_stddevPfS_iPfS_i .cfi_endproc .LFE6858: .size _Z13reduce_stddevPfS_i, .-_Z13reduce_stddevPfS_i .globl _Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i .type _Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i, @function _Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i: .LFB6859: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L9 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z14sum_of_squaresPfS_S_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L9: movq 136(%rsp), %rax subq %fs:40, %rax je .L11 call __stack_chk_fail@PLT .L11: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6859: .size _Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i .globl _Z14sum_of_squaresPfS_S_i .type _Z14sum_of_squaresPfS_S_i, @function _Z14sum_of_squaresPfS_S_i: .LFB6860: .cfi_startproc endbr64 jmp _Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i .cfi_endproc .LFE6860: .size _Z14sum_of_squaresPfS_S_i, .-_Z14sum_of_squaresPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "Failed to allocate d_data (error code " .LC3: .string ")" .LC4: .string "Failed to allocate d_intermediate (error code " .LC5: .string "Failed to allocate d_mean (error code " .LC6: .string "Failed to allocate d_variance (error code " .LC7: .string "Failed to copy data from host to device (error code " .LC8: .string "Failed to copy intermediate results from device to host (error code " .LC10: .string "Failed to copy mean from host to device (error code " .LC11: .string "Mean: " .LC12: .string "Variance: " .LC13: .string "Standard Deviation: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6832: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $4096, %rsp .cfi_def_cfa_offset 4120 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 8216 orq $0, (%rsp) subq $136, %rsp .cfi_def_cfa_offset 8352 xorl %ebx, %ebx movq %fs:40, %rax movq %rax, 8312(%rsp) xorl %eax, %eax .L15: call rand@PLT leaq 120(%rsp), %rbp cvtsi2ssl %eax, %xmm0 mulss .LC1(%rip), %xmm0 movss %xmm0, 0(%rbp,%rbx,4) incq %rbx cmpq $2048, %rbx jne .L15 movl $8192, %esi leaq 32(%rsp), %rdi call cudaMalloc@PLT leaq .LC2(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L39 leaq 40(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L18 leaq .LC4(%rip), %rsi .L39: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %esi movq %rax, %rdi .L40: call _ZNSolsEi@PLT leaq .LC3(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L14 .L18: movl $4, %esi leaq 48(%rsp), %rdi call cudaMalloc@PLT leaq .LC5(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L39 movl $4, %esi leaq 56(%rsp), %rdi call cudaMalloc@PLT leaq .LC6(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L39 movq 32(%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $8192, %edx call cudaMemcpy@PLT leaq .LC7(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L39 movl $16777217, %edx movl $536870913, %edi xorl %r9d, %r9d movl $1024, %r8d salq $8, %rdx salq $3, %rdi movl $1, %ecx movl $1, %esi movq %rdx, 76(%rsp) movl $1, 84(%rsp) movq %rdi, 64(%rsp) movl $1, 72(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L23 movq 40(%rsp), %rsi movq 32(%rsp), %rdi movl $2048, %edx call _Z36__device_stub__Z13reduce_stddevPfS_iPfS_i .L23: call cudaDeviceSynchronize@PLT leaq 88(%rsp), %rbx movq 40(%rsp), %rsi movl $32, %edx movl $2, %ecx movq %rbx, %rdi call cudaMemcpy@PLT xorl %edx, %edx xorps %xmm0, %xmm0 movl %eax, %ebp testl %eax, %eax jne .L41 .L24: addss (%rbx,%rdx,4), %xmm0 incq %rdx cmpq $8, %rdx jne .L24 movq 48(%rsp), %rdi leaq 28(%rsp), %rsi movl $1, %ecx movl $4, %edx mulss .LC9(%rip), %xmm0 movss %xmm0, 28(%rsp) call cudaMemcpy@PLT leaq .LC10(%rip), %rsi movl %eax, %ebp testl %eax, %eax jne .L42 movl $16777217, %edx movl $536870913, %edi xorl %r9d, %r9d movl $1024, %r8d salq $8, %rdx salq $3, %rdi movl $1, %ecx movl $1, %esi movq %rdx, 76(%rsp) movl $1, 84(%rsp) movq %rdi, 64(%rsp) movl $1, 72(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L26 movq 40(%rsp), %rdx movq 48(%rsp), %rsi movl $2048, %ecx movq 32(%rsp), %rdi call _Z39__device_stub__Z14sum_of_squaresPfS_S_iPfS_S_i .L26: call cudaDeviceSynchronize@PLT movq 40(%rsp), %rsi movl $32, %edx movq %rbx, %rdi movl $2, %ecx call cudaMemcpy@PLT xorl %edx, %edx xorps %xmm0, %xmm0 movl %eax, %ebp testl %eax, %eax je .L27 .L41: leaq .LC8(%rip), %rsi .L42: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %esi movq %rax, %rdi jmp .L40 .L27: addss (%rbx,%rdx,4), %xmm0 incq %rdx cmpq $8, %rdx jne .L27 movss .LC9(%rip), %xmm1 leaq _ZSt4cout(%rip), %rbx mulss %xmm0, %xmm1 movaps %xmm1, %xmm0 movss %xmm1, 12(%rsp) call sqrtf@PLT leaq .LC11(%rip), %rsi movq %rbx, %rdi movss %xmm0, 8(%rsp) call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd 28(%rsp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 leaq .LC12(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movss 12(%rsp), %xmm1 movq %rax, %rdi cvtss2sd %xmm1, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 leaq .LC13(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movss 8(%rsp), %xmm2 movq %rax, %rdi cvtss2sd %xmm2, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L14: movq 8312(%rsp), %rdx subq %fs:40, %rdx je .L28 call __stack_chk_fail@PLT .L28: addq $8328, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6832: .size main, .-main .section .rodata.str1.1 .LC14: .string "_Z14sum_of_squaresPfS_S_i" .LC15: .string "_Z13reduce_stddevPfS_i" .LC16: .string "_ZN50_INTERNAL_2c4d87c6_19_cuda_code_074140_cu_d677f6be4cuda3std3__419piecewise_constructE" .LC17: .string "_ZN50_INTERNAL_2c4d87c6_19_cuda_code_074140_cu_d677f6be4cuda3std6ranges3__45__cpo4swapE" .LC18: .string "_ZN50_INTERNAL_2c4d87c6_19_cuda_code_074140_cu_d677f6be4cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6862: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z14sum_of_squaresPfS_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC15(%rip), %rdx orl $-1, %r8d leaq _Z13reduce_stddevPfS_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC16(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6862: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 805306368 .align 4 .LC9: .long 973078528 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_074140.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z28__device_stub__reduce_stddevPfS_i # -- Begin function _Z28__device_stub__reduce_stddevPfS_i .type _Z28__device_stub__reduce_stddevPfS_i,@function _Z28__device_stub__reduce_stddevPfS_i: # @_Z28__device_stub__reduce_stddevPfS_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13reduce_stddevPfS_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z28__device_stub__reduce_stddevPfS_i, .Lfunc_end0-_Z28__device_stub__reduce_stddevPfS_i .cfi_endproc # -- End function .globl _Z29__device_stub__sum_of_squaresPfS_S_i # -- Begin function _Z29__device_stub__sum_of_squaresPfS_S_i .type _Z29__device_stub__sum_of_squaresPfS_S_i,@function _Z29__device_stub__sum_of_squaresPfS_S_i: # @_Z29__device_stub__sum_of_squaresPfS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z14sum_of_squaresPfS_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z29__device_stub__sum_of_squaresPfS_S_i, .Lfunc_end1-_Z29__device_stub__sum_of_squaresPfS_S_i .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x30000000 # float 4.65661287E-10 .LCPI2_1: .long 0x3a000000 # float 4.8828125E-4 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $8272, %rsp # imm = 0x2050 .cfi_def_cfa_offset 8304 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 xorl %ebx, %ebx .LBB2_1: # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI2_0(%rip), %xmm0 movss %xmm0, 80(%rsp,%rbx,4) incq %rbx cmpq $2048, %rbx # imm = 0x800 jne .LBB2_1 # %bb.2: leaq 16(%rsp), %rdi movl $8192, %esi # imm = 0x2000 callq hipMalloc testl %eax, %eax je .LBB2_5 # %bb.3: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi .LBB2_4: movl $38, %edx jmp .LBB2_7 .LBB2_5: movq %rsp, %rdi movl $32, %esi callq hipMalloc testl %eax, %eax je .LBB2_10 # %bb.6: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $46, %edx .LBB2_7: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebx, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB2_8: movl $-1, %eax .LBB2_9: addq $8272, %rsp # imm = 0x2050 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_10: .cfi_def_cfa_offset 8304 leaq 24(%rsp), %rdi movl $4, %esi callq hipMalloc testl %eax, %eax je .LBB2_12 # %bb.11: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi jmp .LBB2_4 .LBB2_12: leaq 40(%rsp), %rdi movl $4, %esi callq hipMalloc testl %eax, %eax je .LBB2_14 # %bb.13: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $42, %edx jmp .LBB2_7 .LBB2_14: movq 16(%rsp), %rdi leaq 80(%rsp), %rsi movl $8192, %edx # imm = 0x2000 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_17 # %bb.15: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $52, %edx .LBB2_16: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebx, %esi jmp .LBB2_26 .LBB2_17: movabsq $4294967304, %r14 # imm = 0x100000008 leaq 248(%r14), %rbx movl $1024, %r8d # imm = 0x400 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_19 # %bb.18: movq 16(%rsp), %rdi movq (%rsp), %rsi movl $2048, %edx # imm = 0x800 callq _Z28__device_stub__reduce_stddevPfS_i .LBB2_19: callq hipDeviceSynchronize movq (%rsp), %rsi leaq 48(%rsp), %rdi movl $32, %edx movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_21 # %bb.20: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.6, %esi movl $68, %edx jmp .LBB2_25 .LBB2_21: # %.preheader69.preheader xorps %xmm0, %xmm0 xorl %eax, %eax .LBB2_22: # %.preheader69 # =>This Inner Loop Header: Depth=1 addss 48(%rsp,%rax,4), %xmm0 incq %rax cmpq $8, %rax jne .LBB2_22 # %bb.23: mulss .LCPI2_1(%rip), %xmm0 leaq 36(%rsp), %rsi movss %xmm0, (%rsi) movq 24(%rsp), %rdi movl $4, %edx movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_27 # %bb.24: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.7, %esi movl $52, %edx .LBB2_25: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebp, %esi .LBB2_26: callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %rbx, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB2_8 .LBB2_27: movl $1024, %r8d # imm = 0x400 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_29 # %bb.28: movq 16(%rsp), %rdi movq 24(%rsp), %rsi movq (%rsp), %rdx movl $2048, %ecx # imm = 0x800 callq _Z29__device_stub__sum_of_squaresPfS_S_i .LBB2_29: callq hipDeviceSynchronize movq (%rsp), %rsi leaq 48(%rsp), %rdi movl $32, %edx movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_31 # %bb.30: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.6, %esi movl $68, %edx jmp .LBB2_16 .LBB2_31: # %.preheader.preheader xorps %xmm0, %xmm0 xorl %eax, %eax .LBB2_32: # %.preheader # =>This Inner Loop Header: Depth=1 addss 48(%rsp,%rax,4), %xmm0 incq %rax cmpq $8, %rax jne .LBB2_32 # %bb.33: mulss .LCPI2_1(%rip), %xmm0 xorps %xmm1, %xmm1 ucomiss %xmm1, %xmm0 movss %xmm0, 32(%rsp) # 4-byte Spill jb .LBB2_35 # %bb.34: sqrtss %xmm0, %xmm0 jmp .LBB2_36 .LBB2_35: # %call.sqrt callq sqrtf@PLT .LBB2_36: # %.split movss %xmm0, 12(%rsp) # 4-byte Spill movl $_ZSt4cout, %edi movl $.L.str.8, %esi movl $6, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd 36(%rsp), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $10, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd 32(%rsp), %xmm0 # 4-byte Folded Reload movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $20, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd 12(%rsp), %xmm0 # 4-byte Folded Reload movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 16(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB2_9 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13reduce_stddevPfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14sum_of_squaresPfS_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z13reduce_stddevPfS_i,@object # @_Z13reduce_stddevPfS_i .section .rodata,"a",@progbits .globl _Z13reduce_stddevPfS_i .p2align 3, 0x0 _Z13reduce_stddevPfS_i: .quad _Z28__device_stub__reduce_stddevPfS_i .size _Z13reduce_stddevPfS_i, 8 .type _Z14sum_of_squaresPfS_S_i,@object # @_Z14sum_of_squaresPfS_S_i .globl _Z14sum_of_squaresPfS_S_i .p2align 3, 0x0 _Z14sum_of_squaresPfS_S_i: .quad _Z29__device_stub__sum_of_squaresPfS_S_i .size _Z14sum_of_squaresPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate d_data (error code " .size .L.str, 39 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz ")" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate d_intermediate (error code " .size .L.str.2, 47 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate d_mean (error code " .size .L.str.3, 39 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate d_variance (error code " .size .L.str.4, 43 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy data from host to device (error code " .size .L.str.5, 53 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy intermediate results from device to host (error code " .size .L.str.6, 69 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to copy mean from host to device (error code " .size .L.str.7, 53 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Mean: " .size .L.str.8, 7 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Variance: " .size .L.str.9, 11 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Standard Deviation: " .size .L.str.10, 21 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13reduce_stddevPfS_i" .size .L__unnamed_1, 23 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z14sum_of_squaresPfS_S_i" .size .L__unnamed_2, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__reduce_stddevPfS_i .addrsig_sym _Z29__device_stub__sum_of_squaresPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13reduce_stddevPfS_i .addrsig_sym _Z14sum_of_squaresPfS_S_i .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z18heatEquationKernelPfS_fffi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR6, c[0x0][0x118] ; S2R R7, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R7 ; ISETP.GE.AND P1, PT, R0, c[0x0][0x17c], PT ; @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; @!P1 IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; @!P1 LDG.E R2, [R2.64] ; ULDC UR4, c[0x0][0x17c] ; UIADD3 UR4, UR4, -0x1, URZ ; ISETP.GE.AND P0, PT, R0, UR4, PT ; ISETP.LT.OR P0, PT, R0, 0x1, P0 ; @!P1 STS [R7.X4], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; LDS R2, [R7.X4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; BSSY B0, 0x250 ; LDS R3, [R7.X4+0x4] ; FMUL R8, R8, c[0x0][0x170] ; LDS R6, [R7.X4+-0x4] ; MUFU.RCP R5, R8 ; FADD R4, R2, R2 ; FADD R3, R3, -R4 ; FFMA R4, -R8, R5, 1 ; FADD R3, R3, R6 ; FFMA R4, R5, R4, R5 ; FCHK P0, R3, R8 ; FFMA R5, R3, R4, RZ ; FFMA R6, -R8, R5, R3 ; FFMA R7, R4, R6, R5 ; @!P0 BRA 0x240 ; MOV R4, 0x230 ; CALL.REL.NOINC 0x2c0 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSYNC B0 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; FMUL R3, R3, c[0x0][0x178] ; IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; FFMA R3, R3, R7, R2 ; STG.E [R4.64], R3 ; EXIT ; SHF.R.U32.HI R6, RZ, 0x17, R8.reuse ; BSSY B1, 0x920 ; SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R10, RZ, RZ, R8 ; LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; IADD3 R12, R6, -0x1, RZ ; IADD3 R11, R5, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0x500 ; FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x900 ; LOP3.LUT P0, RZ, R10, 0x7fffffff, R7, 0xc8, !PT ; @!P0 BRA 0x8e0 ; FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; @!P1 BRA !P2, 0x8e0 ; LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0x8c0 ; LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x890 ; ISETP.GE.AND P0, PT, R11, RZ, PT ; ISETP.GE.AND P1, PT, R12, RZ, PT ; @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R10, R8, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R9, R9, 0x40, RZ ; LEA R3, R6, 0xc0800000, 0x17 ; BSSY B2, 0x880 ; IADD3 R5, R5, -0x7f, RZ ; IMAD.IADD R10, R10, 0x1, -R3 ; IADD3 R6, R5.reuse, 0x7f, -R6 ; IMAD R7, R5, -0x800000, R7 ; MUFU.RCP R3, R10 ; FADD.FTZ R8, -R10, -RZ ; IMAD.IADD R6, R6, 0x1, R9 ; FFMA R12, R3, R8, 1 ; FFMA R14, R3, R12, R3 ; FFMA R3, R7, R14, RZ ; FFMA R12, R8, R3, R7 ; FFMA R11, R14, R12, R3 ; FFMA R8, R8, R11, R7 ; FFMA R3, R14, R8, R11 ; SHF.R.U32.HI R5, RZ, 0x17, R3 ; LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R9, R5, 0x1, R6 ; IADD3 R5, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; @!P0 BRA 0x860 ; ISETP.GT.AND P0, PT, R9, 0xfe, PT ; @P0 BRA 0x830 ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; @P0 BRA 0x870 ; ISETP.GE.AND P0, PT, R9, -0x18, PT ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x870 ; FFMA.RZ R5, R14.reuse, R8.reuse, R11.reuse ; ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; FFMA.RM R6, R14.reuse, R8.reuse, R11.reuse ; ISETP.NE.AND P1, PT, R9, RZ, PT ; LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R5, R14, R8, R11 ; IADD3 R8, R9, 0x20, RZ ; IMAD.MOV R9, RZ, RZ, -R9 ; LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; SHF.L.U32 R8, R7, R8, RZ ; SEL R6, R9, RZ, P2 ; ISETP.NE.AND P1, PT, R8, RZ, P1 ; SHF.R.U32.HI R6, RZ, R6, R7 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R8, RZ, 0x1, R6 ; SEL R5, RZ, 0x1, !P0 ; LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; IMAD.IADD R8, R8, 0x1, R5 ; LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; BRA 0x870 ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x870 ; IMAD R3, R6, 0x800000, R3 ; BSYNC B2 ; BRA 0x910 ; LOP3.LUT R3, R10, 0x80000000, R7, 0x48, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x910 ; LOP3.LUT R3, R10, 0x80000000, R7, 0x48, !PT ; BRA 0x910 ; MUFU.RSQ R3, -QNAN ; BRA 0x910 ; FADD.FTZ R3, R3, R8 ; BSYNC B1 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0x940; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18heatEquationKernelPfS_fffi ; -- Begin function _Z18heatEquationKernelPfS_fffi .globl _Z18heatEquationKernelPfS_fffi .p2align 8 .type _Z18heatEquationKernelPfS_fffi,@function _Z18heatEquationKernelPfS_fffi: ; @_Z18heatEquationKernelPfS_fffi ; %bb.0: s_clause 0x1 s_load_b32 s8, s[0:1], 0x2c s_load_b256 s[0:7], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s8, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] v_lshl_add_u32 v0, v0, 2, 0 s_mov_b32 s8, exec_lo v_cmpx_gt_i32_e64 s7, v1 s_cbranch_execz .LBB0_2 ; %bb.1: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) ds_store_b32 v0, v2 .LBB0_2: s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s0, s7, -1 v_cmp_lt_i32_e32 vcc_lo, 0, v1 v_cmp_gt_i32_e64 s0, s0, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_4 ; %bb.3: v_add_nc_u32_e32 v2, -4, v0 v_mul_f32_e64 v4, s4, s4 ds_load_b32 v0, v0 offset:4 ds_load_2addr_b32 v[2:3], v2 offset1:1 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v0, -2.0, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v0, v2, v0 v_div_scale_f32 v2, null, v4, v4, v0 v_div_scale_f32 v7, vcc_lo, v0, v4, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v5, v2 s_waitcnt_depctr 0xfff v_fma_f32 v6, -v2, v5, 1.0 v_fmac_f32_e32 v5, v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v6, v7, v5 v_fma_f32 v8, -v2, v6, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v8, v5 v_fma_f32 v2, -v2, v6, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_div_fmas_f32 v5, v2, v5, v6 v_mov_b32_e32 v2, 0 v_mul_f32_e64 v6, s5, s6 v_div_fixup_f32 v4, v5, v4, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[1:2] v_fmac_f32_e32 v3, v6, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v3, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18heatEquationKernelPfS_fffi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18heatEquationKernelPfS_fffi, .Lfunc_end0-_Z18heatEquationKernelPfS_fffi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 372 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18heatEquationKernelPfS_fffi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18heatEquationKernelPfS_fffi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0011bd87_00000000-6_cuda_code_076111.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4293: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4293: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi .type _Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi, @function _Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi: .LFB3660: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 24(%rsp) leaq 48(%rsp), %rcx leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movl %edx, (%rsp) leaq 40(%rsp), %rdx movss %xmm0, 12(%rsp) movss %xmm1, 8(%rsp) movss %xmm2, 4(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) leaq 4(%rsp), %rax movq %rax, 136(%rsp) movq %rsp, %rax movq %rax, 144(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 48(%rsp) .cfi_def_cfa_offset 184 leaq _Z18heatEquationKernelPfS_fffi(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 192 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 184 popq %rdx .cfi_def_cfa_offset 176 .L3: movq 152(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $168, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi, .-_Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi .globl _Z18heatEquationKernelPfS_fffi .type _Z18heatEquationKernelPfS_fffi, @function _Z18heatEquationKernelPfS_fffi: .LFB3661: .cfi_startproc endbr64 jmp _Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi .cfi_endproc .LFE3661: .size _Z18heatEquationKernelPfS_fffi, .-_Z18heatEquationKernelPfS_fffi .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "CUDA error: " .LC6: .string "u_new[" .LC7: .string "] = " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 movl $8192, %edi pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 xorl %r12d, %r12d pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $8192, %edi movq %rax, %rbp call _Znam@PLT movq %rax, %rbx .L10: cvtsi2sdl %r12d, %xmm0 mulsd .LC0(%rip), %xmm0 divsd .LC1(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 call sinf@PLT movss %xmm0, 0(%rbp,%r12,4) incq %r12 cmpq $2048, %r12 jne .L10 movq %rsp, %rdi movl $8192, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax jne .L25 leaq 8(%rsp), %rdi movl $8192, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L13 .L25: leaq _ZSt4cerr(%rip), %rdi leaq .LC2(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx .L26: call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L9 .L13: movq (%rsp), %rdi movl $1, %ecx movl $8192, %edx movq %rbp, %rsi call cudaMemcpy@PLT movl %eax, %r12d testl %eax, %eax jne .L25 movl $134217729, %edx movl $67108865, %edi xorl %r9d, %r9d movl $128, %r8d salq $5, %rdx salq $6, %rdi movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rsi movq (%rsp), %rdi movl $2048, %edx movss .LC3(%rip), %xmm2 movss .LC4(%rip), %xmm1 movss .LC5(%rip), %xmm0 call _Z44__device_stub__Z18heatEquationKernelPfS_fffiPfS_fffi .L16: call cudaGetLastError@PLT movl %eax, %r12d testl %eax, %eax jne .L25 movq 8(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi xorl %r12d, %r12d movl $8192, %edx leaq .LC6(%rip), %r14 call cudaMemcpy@PLT movl %eax, %r13d testl %eax, %eax je .L18 leaq _ZSt4cerr(%rip), %rdi leaq .LC2(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r13d, %edi movq %rax, %rbx jmp .L26 .L18: movq %r14, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC7(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd (%rbx,%r12,4), %xmm0 incq %r12 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 cmpq $10, %r12 jne .L18 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT xorl %eax, %eax .L9: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L19 call __stack_chk_fail@PLT .L19: addq $48, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z18heatEquationKernelPfS_fffi" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi leaq _Z18heatEquationKernelPfS_fffi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 1413754136 .long 1075388923 .align 8 .LC1: .long 0 .long 1084226560 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC3: .long 1008981770 .align 4 .LC4: .long 953267991 .align 4 .LC5: .long 973082626 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_076111.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z33__device_stub__heatEquationKernelPfS_fffi # -- Begin function _Z33__device_stub__heatEquationKernelPfS_fffi .type _Z33__device_stub__heatEquationKernelPfS_fffi,@function _Z33__device_stub__heatEquationKernelPfS_fffi: # @_Z33__device_stub__heatEquationKernelPfS_fffi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movss %xmm0, (%rsi) leaq 8(%rsp), %rdi movss %xmm1, (%rdi) leaq 4(%rsp), %r8 movss %xmm2, (%r8) movq %rsp, %r9 movl %edx, (%r9) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) movq %rdi, 24(%rbx) movq %r8, 32(%rbx) movq %r9, 40(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z18heatEquationKernelPfS_fffi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $144, %rsp .cfi_adjust_cfa_offset -144 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z33__device_stub__heatEquationKernelPfS_fffi, .Lfunc_end0-_Z33__device_stub__heatEquationKernelPfS_fffi .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI1_0: .quad 0x401921fb54442d18 # double 6.2831853071795862 .LCPI1_1: .quad 0x409ffc0000000000 # double 2047 .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 .LCPI1_2: .long 0x3a001002 # float 4.88519785E-4 .LCPI1_3: .long 0x38d1b717 # float 9.99999974E-5 .LCPI1_4: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $16, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $8192, %edi # imm = 0x2000 callq _Znam movq %rax, %rbx movl $8192, %edi # imm = 0x2000 callq _Znam movq %rax, %r14 xorl %r15d, %r15d .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2sd %r15d, %xmm0 mulsd .LCPI1_0(%rip), %xmm0 divsd .LCPI1_1(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 callq sinf movss %xmm0, (%rbx,%r15,4) incq %r15 cmpq $2048, %r15 # imm = 0x800 jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $8192, %esi # imm = 0x2000 callq hipMalloc testl %eax, %eax jne .LBB1_3 # %bb.7: movq %rsp, %rdi movl $8192, %esi # imm = 0x2000 callq hipMalloc testl %eax, %eax jne .LBB1_3 # %bb.8: movq 8(%rsp), %rdi movl $8192, %edx # imm = 0x2000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_3 # %bb.9: movabsq $4294967328, %rdx # imm = 0x100000020 leaq 32(%rdx), %rdi movl $128, %r8d movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_11 # %bb.10: movq 8(%rsp), %rdi movq (%rsp), %rsi movss .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero movss .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero movl $2048, %edx # imm = 0x800 callq _Z33__device_stub__heatEquationKernelPfS_fffi .LBB1_11: callq hipGetLastError testl %eax, %eax je .LBB1_12 .LBB1_3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_4 # %bb.5: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_6 .LBB1_4: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_17: movl $-1, %eax .LBB1_18: addq $16, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_12: .cfi_def_cfa_offset 64 movq (%rsp), %rsi movl $8192, %edx # imm = 0x2000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_13 # %bb.16: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_17 .LBB1_13: # %.preheader.preheader xorl %r15d, %r15d .LBB1_14: # %.preheader # =>This Inner Loop Header: Depth=1 movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $6, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r15d, %esi callq _ZNSolsEi movq %rax, %r12 movl $.L.str.2, %esi movl $4, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd (%r14,%r15,4), %xmm0 movq %r12, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rdi addq %r12, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r12, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r15 cmpq $10, %r15 jne .LBB1_14 # %bb.15: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB1_18 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18heatEquationKernelPfS_fffi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z18heatEquationKernelPfS_fffi,@object # @_Z18heatEquationKernelPfS_fffi .section .rodata,"a",@progbits .globl _Z18heatEquationKernelPfS_fffi .p2align 3, 0x0 _Z18heatEquationKernelPfS_fffi: .quad _Z33__device_stub__heatEquationKernelPfS_fffi .size _Z18heatEquationKernelPfS_fffi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "u_new[" .size .L.str.1, 7 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "] = " .size .L.str.2, 5 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z18heatEquationKernelPfS_fffi" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__heatEquationKernelPfS_fffi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18heatEquationKernelPfS_fffi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z19computeForcesKernelPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; @P0 EXIT ; IMAD R0, R3, c[0x0][0x168], R0 ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; MOV R5, 0xc11cf5c3 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R0, R0, 0x3, RZ ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; STG.E [R2.64+0x4], R5 ; STG.E [R2.64], RZ ; STG.E [R2.64+0x8], RZ ; EXIT ; BRA 0x140; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z21clothSimulationKernelPfS_S_fii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x17c], P0 ; @P0 EXIT ; IMAD R0, R3, c[0x0][0x17c], R0 ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; LEA R0, R0, R0, 0x1 ; IMAD.WIDE R6, R0, R5, c[0x0][0x170] ; IMAD.WIDE R2, R0.reuse, R5.reuse, c[0x0][0x168] ; LDG.E R8, [R6.64+0x4] ; IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; LDG.E R9, [R2.64] ; LDG.E R0, [R6.64] ; LDG.E R10, [R6.64+0x8] ; LDG.E R11, [R2.64+0x4] ; LDG.E R13, [R2.64+0x8] ; LDG.E R12, [R4.64] ; LDG.E R14, [R4.64+0x4] ; LDG.E R16, [R4.64+0x8] ; FFMA R9, R0, c[0x0][0x178], R9 ; FFMA R11, R8, c[0x0][0x178], R11 ; FFMA R13, R10, c[0x0][0x178], R13 ; FFMA R15, R9, c[0x0][0x178], R12 ; FFMA R7, R11, c[0x0][0x178], R14 ; FFMA R17, R13, c[0x0][0x178], R16 ; STG.E [R2.64], R9 ; STG.E [R2.64+0x4], R11 ; STG.E [R2.64+0x8], R13 ; STG.E [R4.64], R15 ; STG.E [R4.64+0x4], R7 ; STG.E [R4.64+0x8], R17 ; EXIT ; BRA 0x270; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21clothSimulationKernelPfS_S_fii ; -- Begin function _Z21clothSimulationKernelPfS_S_fii .globl _Z21clothSimulationKernelPfS_S_fii .p2align 8 .type _Z21clothSimulationKernelPfS_S_fii,@function _Z21clothSimulationKernelPfS_S_fii: ; @_Z21clothSimulationKernelPfS_S_fii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x18 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s5, v0 v_cmp_gt_i32_e64 s2, s6, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 ; %bb.1: v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1] s_clause 0x1 s_load_b64 s[6:7], s[0:1], 0x10 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v2, 1, v2 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v9, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v10, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v11, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v12, vcc_lo, s1, v1, vcc_lo global_load_b96 v[0:2], v[2:3], off global_load_b96 v[3:5], v[9:10], off global_load_b96 v[6:8], v[11:12], off s_waitcnt vmcnt(1) v_fma_f32 v3, s4, v0, v3 v_fma_f32 v4, s4, v1, v4 v_fmac_f32_e32 v5, s4, v2 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v6, s4, v3, v6 v_fma_f32 v7, s4, v4, v7 s_delay_alu instid0(VALU_DEP_3) v_fmac_f32_e32 v8, s4, v5 global_store_b96 v[9:10], v[3:5], off global_store_b96 v[11:12], v[6:8], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21clothSimulationKernelPfS_S_fii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21clothSimulationKernelPfS_S_fii, .Lfunc_end0-_Z21clothSimulationKernelPfS_S_fii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 312 ; NumSgprs: 18 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z19computeForcesKernelPfii ; -- Begin function _Z19computeForcesKernelPfii .globl _Z19computeForcesKernelPfii .p2align 8 .type _Z19computeForcesKernelPfii,@function _Z19computeForcesKernelPfii: ; @_Z19computeForcesKernelPfii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b64 s[4:5], s[0:1], 0x8 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s4, v0 v_cmp_gt_i32_e64 s2, s5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_2 ; %bb.1: v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_load_b64 s[0:1], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v2, 1, v2 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[0:1] v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xc11cf5c3 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo v_mov_b32_e32 v2, v0 global_store_b96 v[4:5], v[0:2], off .LBB1_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19computeForcesKernelPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z19computeForcesKernelPfii, .Lfunc_end1-_Z19computeForcesKernelPfii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 204 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21clothSimulationKernelPfS_S_fii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21clothSimulationKernelPfS_S_fii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19computeForcesKernelPfii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z19computeForcesKernelPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00100fd1_00000000-6_cuda_code_070086.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii .type _Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii, @function _Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii: .LFB3660: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) leaq 72(%rsp), %rdi movq %rsi, 32(%rsp) leaq 84(%rsp), %rsi movq %rdx, 24(%rsp) leaq 56(%rsp), %rdx movl %ecx, 16(%rsp) leaq 64(%rsp), %rcx movl %r8d, 12(%rsp) movss %xmm0, 20(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 80(%rsp) movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) movq %rax, 84(%rsp) movl $1, 92(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 64(%rsp) .cfi_def_cfa_offset 200 leaq _Z21clothSimulationKernelPfS_S_fii(%rip), %rdi pushq 64(%rsp) .cfi_def_cfa_offset 208 movq 100(%rsp), %rcx movl 108(%rsp), %r8d movq 88(%rsp), %rsi movl 96(%rsp), %edx leaq 136(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 200 popq %rdx .cfi_def_cfa_offset 192 .L2: movq 168(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $184, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii, .-_Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii .globl _Z21clothSimulationKernelPfS_S_fii .type _Z21clothSimulationKernelPfS_S_fii, @function _Z21clothSimulationKernelPfS_S_fii: .LFB3661: .cfi_startproc endbr64 jmp _Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii .cfi_endproc .LFE3661: .size _Z21clothSimulationKernelPfS_S_fii, .-_Z21clothSimulationKernelPfS_S_fii .globl _Z41__device_stub__Z19computeForcesKernelPfiiPfii .type _Z41__device_stub__Z19computeForcesKernelPfiiPfii, @function _Z41__device_stub__Z19computeForcesKernelPfiiPfii: .LFB3662: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 24(%rsp), %rcx leaq 32(%rsp), %rdi movl %esi, 4(%rsp) leaq 44(%rsp), %rsi movl %edx, (%rsp) leaq 16(%rsp), %rdx movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 40(%rsp) movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 32(%rsp) movq %rax, 44(%rsp) movl $1, 52(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 24(%rsp) .cfi_def_cfa_offset 136 leaq _Z19computeForcesKernelPfii(%rip), %rdi pushq 24(%rsp) .cfi_def_cfa_offset 144 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq 96(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3662: .size _Z41__device_stub__Z19computeForcesKernelPfiiPfii, .-_Z41__device_stub__Z19computeForcesKernelPfiiPfii .globl _Z19computeForcesKernelPfii .type _Z19computeForcesKernelPfii, @function _Z19computeForcesKernelPfii: .LFB3663: .cfi_startproc endbr64 jmp _Z41__device_stub__Z19computeForcesKernelPfiiPfii .cfi_endproc .LFE3663: .size _Z19computeForcesKernelPfii, .-_Z19computeForcesKernelPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Error in computeForcesKernel: " .LC2: .string "Error in clothSimulationKernel: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $201326592, %edi movabsq $1099511628032, %r15 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 movl $100, %r14d pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $201326592, %edi movq %rax, %r12 call _Znam@PLT movl $201326592, %edi movq %rax, %rbp call _Znam@PLT movl $50331648, %ecx movq %r12, %rdi movl $201326592, %esi movq %rax, %rbx xorl %eax, %eax rep stosl movl $50331648, %ecx movq %rbp, %rdi rep stosl movl $50331648, %ecx movq %rbx, %rdi rep stosl leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $201326592, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $201326592, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $201326592, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $201326592, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $201326592, %edx call cudaMemcpy@PLT movl $1, 40(%rsp) movabsq $68719476752, %rax movq %rax, 44(%rsp) movl $1, 52(%rsp) .L20: movl 40(%rsp), %ecx movq 44(%rsp), %rdi xorl %r9d, %r9d xorl %r8d, %r8d movl 52(%rsp), %esi movq %r15, %rdx movq %r15, 32(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L14 movq 24(%rsp), %rdi movl $4096, %edx movl $4096, %esi call _Z41__device_stub__Z19computeForcesKernelPfiiPfii .L14: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %r13d testl %eax, %eax je .L15 leaq .LC0(%rip), %rsi jmp .L24 .L15: movl 40(%rsp), %ecx movq 32(%rsp), %rdx xorl %r9d, %r9d xorl %r8d, %r8d movq 44(%rsp), %rdi movl 52(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L17 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $4096, %ecx movl $4096, %r8d movss .LC1(%rip), %xmm0 movq 8(%rsp), %rdi call _Z48__device_stub__Z21clothSimulationKernelPfS_S_fiiPfS_S_fii .L17: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %r13d testl %eax, %eax je .L18 leaq .LC2(%rip), %rsi .L24: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r13d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L13 .L18: decl %r14d jne .L20 movq 8(%rsp), %rsi movl $2, %ecx movl $201326592, %edx movq %r12, %rdi call cudaMemcpy@PLT movq 16(%rsp), %rsi movl $2, %ecx movq %rbp, %rdi movl $201326592, %edx call cudaMemcpy@PLT movq 24(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi movl $201326592, %edx call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT xorl %eax, %eax .L13: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L21 call __stack_chk_fail@PLT .L21: addq $72, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z19computeForcesKernelPfii" .LC4: .string "_Z21clothSimulationKernelPfS_S_fii" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3665: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC3(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z19computeForcesKernelPfii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC4(%rip), %rdx orl $-1, %r8d leaq _Z21clothSimulationKernelPfS_S_fii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3665: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_070086.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z36__device_stub__clothSimulationKernelPfS_S_fii # -- Begin function _Z36__device_stub__clothSimulationKernelPfS_S_fii .type _Z36__device_stub__clothSimulationKernelPfS_S_fii,@function _Z36__device_stub__clothSimulationKernelPfS_S_fii: # @_Z36__device_stub__clothSimulationKernelPfS_S_fii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 20(%rsp), %rdx movss %xmm0, (%rdx) leaq 16(%rsp), %r9 movl %ecx, (%r9) leaq 12(%rsp), %rcx movl %r8d, (%rcx) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %r9, 32(%rbx) movq %rcx, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 32(%rsp), %r12 leaq 24(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z21clothSimulationKernelPfS_S_fii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z36__device_stub__clothSimulationKernelPfS_S_fii, .Lfunc_end0-_Z36__device_stub__clothSimulationKernelPfS_S_fii .cfi_endproc # -- End function .globl _Z34__device_stub__computeForcesKernelPfii # -- Begin function _Z34__device_stub__computeForcesKernelPfii .type _Z34__device_stub__computeForcesKernelPfii,@function _Z34__device_stub__computeForcesKernelPfii: # @_Z34__device_stub__computeForcesKernelPfii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) movq %rsp, %rsi movl %edx, (%rsi) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z19computeForcesKernelPfii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $112, %rsp .cfi_adjust_cfa_offset -112 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z34__device_stub__computeForcesKernelPfii, .Lfunc_end1-_Z34__device_stub__computeForcesKernelPfii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movabsq $1099511628032, %r12 # imm = 0x10000000100 movabsq $68719476752, %r13 # imm = 0x1000000010 movl $201326592, %edi # imm = 0xC000000 callq _Znam movq %rax, %r15 movl $201326592, %edi # imm = 0xC000000 callq _Znam movq %rax, %rbx movl $201326592, %edi # imm = 0xC000000 callq _Znam movq %rax, %r14 movl $201326592, %edx # imm = 0xC000000 movq %r15, %rdi xorl %esi, %esi callq memset@PLT movl $201326592, %edx # imm = 0xC000000 movq %rbx, %rdi xorl %esi, %esi callq memset@PLT movl $201326592, %edx # imm = 0xC000000 movq %r14, %rdi xorl %esi, %esi callq memset@PLT leaq 24(%rsp), %rbp movl $201326592, %esi # imm = 0xC000000 movq %rbp, %rdi callq hipMalloc leaq 16(%rsp), %rdi movl $201326592, %esi # imm = 0xC000000 callq hipMalloc leaq 8(%rsp), %rdi movl $201326592, %esi # imm = 0xC000000 callq hipMalloc movq (%rbp), %rdi movl $201326592, %edx # imm = 0xC000000 movq %r15, 32(%rsp) # 8-byte Spill movq %r15, %rsi movq %rbx, %r15 movl $1, %ecx callq hipMemcpy leaq 16(%rsp), %rax movq (%rax), %rdi movl $201326592, %edx # imm = 0xC000000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy leaq 8(%rsp), %rax movq (%rax), %rdi movl $201326592, %edx # imm = 0xC000000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movl $100, %ebx .LBB2_2: # =>This Inner Loop Header: Depth=1 movq %r13, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: # in Loop: Header=BB2_2 Depth=1 movq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 movl $4096, %edx # imm = 0x1000 callq _Z34__device_stub__computeForcesKernelPfii .LBB2_4: # in Loop: Header=BB2_2 Depth=1 callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB2_5 # %bb.10: # in Loop: Header=BB2_2 Depth=1 movq %r13, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_12 # %bb.11: # in Loop: Header=BB2_2 Depth=1 movq 24(%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movl $4096, %ecx # imm = 0x1000 movl $4096, %r8d # imm = 0x1000 callq _Z36__device_stub__clothSimulationKernelPfS_S_fii .LBB2_12: # in Loop: Header=BB2_2 Depth=1 callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB2_13 # %bb.1: # in Loop: Header=BB2_2 Depth=1 decl %ebx jne .LBB2_2 # %bb.14: movq 24(%rsp), %rsi movl $201326592, %edx # imm = 0xC000000 movq 32(%rsp), %rbx # 8-byte Reload movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rsi movl $201326592, %edx # imm = 0xC000000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rsi movl $201326592, %edx # imm = 0xC000000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB2_15 .LBB2_5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $30, %edx jmp .LBB2_6 .LBB2_13: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $32, %edx .LBB2_6: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_7 # %bb.8: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_9 .LBB2_7: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB2_15: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21clothSimulationKernelPfS_S_fii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19computeForcesKernelPfii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z21clothSimulationKernelPfS_S_fii,@object # @_Z21clothSimulationKernelPfS_S_fii .section .rodata,"a",@progbits .globl _Z21clothSimulationKernelPfS_S_fii .p2align 3, 0x0 _Z21clothSimulationKernelPfS_S_fii: .quad _Z36__device_stub__clothSimulationKernelPfS_S_fii .size _Z21clothSimulationKernelPfS_S_fii, 8 .type _Z19computeForcesKernelPfii,@object # @_Z19computeForcesKernelPfii .globl _Z19computeForcesKernelPfii .p2align 3, 0x0 _Z19computeForcesKernelPfii: .quad _Z34__device_stub__computeForcesKernelPfii .size _Z19computeForcesKernelPfii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error in computeForcesKernel: " .size .L.str, 31 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error in clothSimulationKernel: " .size .L.str.1, 33 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z21clothSimulationKernelPfS_S_fii" .size .L__unnamed_1, 35 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z19computeForcesKernelPfii" .size .L__unnamed_2, 28 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__clothSimulationKernelPfS_S_fii .addrsig_sym _Z34__device_stub__computeForcesKernelPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21clothSimulationKernelPfS_S_fii .addrsig_sym _Z19computeForcesKernelPfii .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.Y ; S2R R3, SR_TID.Y ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R4, R4, c[0x0][0x4], R3 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x184], PT ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.OR P0, PT, R5, c[0x0][0x180], P0 ; @P0 EXIT ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; ULDC.64 UR8, c[0x0][0x118] ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ISETP.GE.AND P0, PT, R6, 0x1, PT ; @!P0 BRA 0x8a0 ; IADD3 R0, R6.reuse, -0x1, RZ ; UMOV UR4, URZ ; LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ISETP.NE.AND P4, PT, R6, RZ, PT ; @!P0 BRA 0x6b0 ; IADD3 R7, -R6, c[0x0][0x168], RZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; IMAD.MOV.U32 R3, RZ, RZ, R9 ; LDG.E.CONSTANT R22, [R2.64+0x4] ; LDG.E.CONSTANT R11, [R2.64] ; LDG.E.CONSTANT R14, [R2.64+0x10] ; LDG.E.CONSTANT R10, [R2.64+0x1c] ; LDG.E.CONSTANT R8, [R2.64+0x28] ; LDG.E.CONSTANT R13, [R2.64+0xc] ; LDG.E.CONSTANT R9, [R2.64+0x24] ; LDG.E.CONSTANT R12, [R2.64+0x18] ; IADD3 R16, R22, -0x40, RZ ; ISETP.GE.AND P0, PT, R5, R16, PT ; IADD3 R16, R22, 0x40, RZ ; IADD3 R17, R11, -0x40, RZ ; ISETP.GE.OR P0, PT, R5, R16, !P0 ; IADD3 R11, R11, 0x40, RZ ; ISETP.LT.OR P0, PT, R4, R17, P0 ; IADD3 R16, R14, -0x40, RZ ; ISETP.GE.OR P0, PT, R4, R11, P0 ; ISETP.GE.AND P1, PT, R5, R16, PT ; IADD3 R16, R14, 0x40, RZ ; IADD3 R18, R10, -0x40, RZ ; IADD3 R20, R8, -0x40, RZ ; ISETP.GE.OR P1, PT, R5, R16, !P1 ; IADD3 R11, R13, -0x40, RZ ; ISETP.GE.AND P3, PT, R5.reuse, R18, PT ; IADD3 R16, R10, 0x40, RZ ; ISETP.GE.AND P2, PT, R5, R20, PT ; IADD3 R13, R13, 0x40, RZ ; ISETP.LT.OR P1, PT, R4, R11, P1 ; IADD3 R18, R8, 0x40, RZ ; ISETP.GE.OR P3, PT, R5.reuse, R16, !P3 ; @!P0 IMAD.IADD R16, R4.reuse, 0x1, -R17 ; ISETP.GE.OR P1, PT, R4, R13, P1 ; ISETP.GE.OR P2, PT, R5, R18, !P2 ; IADD3 R17, R9, -0x40, RZ ; IADD3 R15, R12, -0x40, RZ ; IADD3 R9, R9, 0x40, RZ ; ISETP.LT.OR P2, PT, R4, R17, P2 ; IADD3 R19, R12, 0x40, RZ ; ISETP.LT.OR P3, PT, R4, R15, P3 ; @!P0 IADD3 R13, R5, 0x40, -R22 ; ISETP.GE.OR P2, PT, R4.reuse, R9, P2 ; ISETP.GE.OR P3, PT, R4, R19, P3 ; @!P0 IMAD R13, R16, 0x80, R13 ; @!P1 IADD3 R14, R5, 0x40, -R14 ; @!P0 IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; @!P1 IMAD.IADD R11, R4, 0x1, -R11 ; @!P0 IMAD.WIDE R12, R13, R12, c[0x0][0x170] ; @!P1 IMAD R9, R11, 0x80, R14 ; @!P2 LDG.E.CONSTANT R18, [R2.64+0x2c] ; @!P1 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; @!P2 IADD3 R11, R5, 0x40, -R8 ; @!P0 LDG.E.CONSTANT R13, [R12.64] ; @!P1 IMAD.WIDE R8, R9, R16, c[0x0][0x170] ; @!P3 IADD3 R10, R5, 0x40, -R10 ; @!P1 LDG.E.CONSTANT R16, [R2.64+0x14] ; @!P3 IMAD.IADD R15, R4, 0x1, -R15 ; @!P2 IMAD.IADD R14, R4, 0x1, -R17 ; @!P1 LDG.E.CONSTANT R9, [R8.64] ; @!P0 LDG.E.CONSTANT R12, [R2.64+0x8] ; @!P3 IMAD R10, R15, 0x80, R10 ; @!P3 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; @!P2 IMAD R14, R14, 0x80, R11 ; @!P2 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; @!P3 IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; @!P2 IMAD.WIDE R14, R14, R17, c[0x0][0x170] ; @!P3 LDG.E.CONSTANT R11, [R10.64] ; @!P3 LDG.E.CONSTANT R17, [R2.64+0x20] ; @!P2 LDG.E.CONSTANT R15, [R14.64] ; IADD3 R7, R7, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; @!P0 FFMA R0, R13, R12, R0 ; @!P1 FFMA R0, R9, R16, R0 ; ISETP.NE.AND P1, PT, R7, RZ, PT ; IADD3 R8, P0, R2, 0x30, RZ ; IMAD.X R9, RZ, RZ, R3, P0 ; @!P3 FFMA R0, R11, R17, R0 ; @!P2 FFMA R0, R15, R18, R0 ; @P1 BRA 0x1b0 ; @!P4 BRA 0x8a0 ; UMOV UR5, 0xc ; ULDC.64 UR6, c[0x0][0x160] ; UIMAD.WIDE UR4, UR4, UR5, UR6 ; UIADD3 UR6, UP0, UR4, 0x8, URZ ; UIADD3.X UR4, URZ, UR5, URZ, UP0, !UPT ; IMAD.U32 R2, RZ, RZ, UR6 ; IMAD.U32 R3, RZ, RZ, UR4 ; LDG.E.CONSTANT R12, [R2.64+-0x4] ; LDG.E.CONSTANT R7, [R2.64+-0x8] ; IADD3 R8, R12.reuse, -0x40, RZ ; IADD3 R10, R12, 0x40, RZ ; ISETP.GE.AND P0, PT, R5, R8, PT ; IADD3 R9, R7, -0x40, RZ ; ISETP.GE.OR P0, PT, R5, R10, !P0 ; IADD3 R7, R7, 0x40, RZ ; ISETP.LT.OR P0, PT, R4, R9, P0 ; ISETP.GE.OR P0, PT, R4, R7, P0 ; @!P0 IADD3 R7, R5, 0x40, -R12 ; @!P0 IMAD.IADD R8, R4, 0x1, -R9 ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; @!P0 IMAD R8, R8, 0x80, R7 ; @!P0 LDG.E.CONSTANT R7, [R2.64] ; @!P0 IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; @!P0 LDG.E.CONSTANT R9, [R8.64] ; IADD3 R6, R6, -0x1, RZ ; ISETP.NE.AND P1, PT, R6, RZ, PT ; IADD3 R2, P2, R2, 0xc, RZ ; IMAD.X R3, RZ, RZ, R3, P2 ; @!P0 FFMA R0, R9, R7, R0 ; @P1 BRA 0x730 ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD R2, R4, c[0x0][0x180], R5 ; IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; STG.E [R2.64], R0 ; EXIT ; BRA 0x8f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii ; -- Begin function _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .globl _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .p2align 8 .type _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii,@function _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii: ; @_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b64 s[4:5], s[0:1], 0x20 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s4, v0 v_cmp_gt_i32_e64 s2, s5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_10 ; %bb.1: ; %.preheader s_clause 0x1 s_load_b32 s5, s[0:1], 0x8 s_load_b64 s[2:3], s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s5, 1 s_cbranch_scc1 .LBB0_8 ; %bb.2: ; %.lr.ph.preheader s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x0 s_load_b64 s[6:7], s[0:1], 0x10 v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) s_add_u32 s8, s8, 4 s_addc_u32 s9, s9, 0 .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_load_b64 s[10:11], s[8:9], 0x0 s_waitcnt lgkmcnt(0) s_sub_i32 s0, s10, 64 s_add_i32 s1, s10, 64 v_cmp_le_i32_e32 vcc_lo, s0, v0 v_cmp_gt_i32_e64 s0, s1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, vcc_lo, s0 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_7 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 s_add_u32 s12, s8, -4 s_addc_u32 s13, s9, -1 s_load_b32 s0, s[12:13], 0x0 s_waitcnt lgkmcnt(0) s_sub_i32 s12, s0, 64 s_add_i32 s0, s0, 64 v_cmp_le_i32_e32 vcc_lo, s12, v1 v_cmp_gt_i32_e64 s0, s0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s13, vcc_lo, s0 s_and_saveexec_b32 s0, s13 s_cbranch_execz .LBB0_6 ; %bb.5: ; in Loop: Header=BB0_3 Depth=1 v_subrev_nc_u32_e32 v3, s12, v1 v_subrev_nc_u32_e32 v4, s10, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v3, 7, v3 v_add3_u32 v3, v4, v3, 64 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[3:4], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo global_load_b32 v3, v[3:4], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v2, s11, v3 .LBB0_6: ; %Flow ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s0 .LBB0_7: ; in Loop: Header=BB0_3 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_add_i32 s5, s5, -1 s_add_u32 s8, s8, 12 s_addc_u32 s9, s9, 0 s_cmp_eq_u32 s5, 0 s_cbranch_scc0 .LBB0_3 s_branch .LBB0_9 .LBB0_8: v_mov_b32_e32 v2, 0 .LBB0_9: ; %Flow66 v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii, .Lfunc_end0-_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 448 ; NumSgprs: 18 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .actual_access: read_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0015637a_00000000-6_cuda_code_036453.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii .type _Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii, @function _Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii: .LFB3661: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movl %esi, 12(%rsp) leaq 68(%rsp), %rsi movl %r8d, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 16(%rsp), %rax movq %rdi, 16(%rsp) leaq 56(%rsp), %rdi movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rdx, 24(%rsp) leaq 40(%rsp), %rdx movq %rcx, 32(%rsp) leaq 48(%rsp), %rcx movq %rax, 144(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movl $1, 64(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 48(%rsp) .cfi_def_cfa_offset 184 leaq _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 192 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 184 popq %rdx .cfi_def_cfa_offset 176 .L2: movq 152(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $168, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii, .-_Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii .globl _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .type _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii, @function _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii: .LFB3662: .cfi_startproc endbr64 jmp _Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii .cfi_endproc .LFE3662: .size _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii, .-_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "CUDA error: " .text .globl _Z23launchSparseConvolutionPK13SparseElementiPKfPfii .type _Z23launchSparseConvolutionPK13SparseElementiPKfPfii, @function _Z23launchSparseConvolutionPK13SparseElementiPKfPfii: .LFB3635: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 leal 15(%r8), %eax movq %rcx, %r15 movl $1, %ecx pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 shrl $4, %eax movq %rdx, %r14 movabsq $68719476752, %rdx pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 movl %esi, %r13d movl $1, %esi pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 movq %rdi, %r12 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 movl %r9d, %ebp pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 movl %r8d, %ebx xorl %r8d, %r8d subq $40, %rsp .cfi_def_cfa_offset 96 movl %eax, 20(%rsp) leal 15(%r9), %eax xorl %r9d, %r9d shrl $4, %eax movl %eax, 24(%rsp) movq 20(%rsp), %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L9 movl %ebp, %r9d movl %ebx, %r8d movq %r15, %rcx movq %r14, %rdx movl %r13d, %esi movq %r12, %rdi call _Z66__device_stub__Z23sparseConvolutionKernelPK13SparseElementiPKfPfiiPK13SparseElementiPKfPfii .L9: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L8 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L8: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size _Z23launchSparseConvolutionPK13SparseElementiPKfPfii, .-_Z23launchSparseConvolutionPK13SparseElementiPKfPfii .section .rodata.str1.1 .LC3: .string "Sparse convolution completed successfully." .section .rodata .align 32 .LC0: .long 0 .long 0 .long 1065353216 .long 0 .long 1 .long 1073741824 .long 1 .long 0 .long 1077936128 .long 1 .long 1 .long 1082130432 .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 leaq .LC0(%rip), %rsi movl $12, %ecx pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $88, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax leaq 24(%rsp), %rdi rep movsl movl $65536, %edi call _Znam@PLT movss .LC2(%rip), %xmm0 movq %rax, %rbx xorl %eax, %eax .L13: movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $16384, %rax jne .L13 movq %rsp, %rdi movl $48, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $65536, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT movq (%rsp), %rdi movl $1, %ecx movl $48, %edx leaq 24(%rsp), %rsi call cudaMemcpy@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $65536, %edx call cudaMemcpy@PLT movq 16(%rsp), %rcx movq 8(%rsp), %rdx movl $256, %r9d movq (%rsp), %rdi movl $256, %r8d movl $4, %esi call _Z23launchSparseConvolutionPK13SparseElementiPKfPfii movl $262144, %edi call _Znam@PLT movq 16(%rsp), %rsi movl $2, %ecx movl $262144, %edx movq %rax, %rdi movq %rax, %rbp call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT leaq _ZSt4cout(%rip), %rdi leaq .LC3(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 72(%rsp), %rax subq %fs:40, %rax je .L14 call __stack_chk_fail@PLT .L14: addq $88, %rsp .cfi_def_cfa_offset 24 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC5(%rip), %rdx movq %rax, %rdi leaq _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_036453.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii .type _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii,@function _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii: # @_Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 20(%rsp), %rdi movl %esi, (%rdi) leaq 48(%rsp), %rsi movq %rdx, (%rsi) leaq 40(%rsp), %rdx movq %rcx, (%rdx) leaq 16(%rsp), %rcx movl %r8d, (%rcx) leaq 12(%rsp), %r8 movl %r9d, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 32(%rsp), %r12 leaq 24(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii .cfi_endproc # -- End function .globl _Z23launchSparseConvolutionPK13SparseElementiPKfPfii # -- Begin function _Z23launchSparseConvolutionPK13SparseElementiPKfPfii .type _Z23launchSparseConvolutionPK13SparseElementiPKfPfii,@function _Z23launchSparseConvolutionPK13SparseElementiPKfPfii: # @_Z23launchSparseConvolutionPK13SparseElementiPKfPfii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r9d, %ebx movl %r8d, %r14d movq %rcx, %r15 movq %rdx, %r12 movl %esi, %ebp movq %rdi, %r13 leal 15(%r14), %eax shrl $4, %eax leal 15(%rbx), %edi shrl $4, %edi shlq $32, %rdi orq %rax, %rdi movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq %r13, %rdi movl %ebp, %esi movq %r12, %rdx movq %r15, %rcx movl %r14d, %r8d movl %ebx, %r9d callq _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii .LBB1_2: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB1_4 # %bb.3: addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_4: .cfi_def_cfa_offset 64 movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z23launchSparseConvolutionPK13SparseElementiPKfPfii, .Lfunc_end1-_Z23launchSparseConvolutionPK13SparseElementiPKfPfii .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI2_0: .long 0 # 0x0 .long 0 # 0x0 .long 1065353216 # 0x3f800000 .long 0 # 0x0 .LCPI2_1: .long 1 # 0x1 .long 1073741824 # 0x40000000 .long 1 # 0x1 .long 0 # 0x0 .LCPI2_2: .long 1077936128 # 0x40400000 .long 1 # 0x1 .long 1 # 0x1 .long 1082130432 # 0x40800000 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [0,0,1065353216,0] movaps %xmm0, 32(%rsp) movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [1,1073741824,1,0] movaps %xmm0, 48(%rsp) movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [1077936128,1,1,1082130432] movaps %xmm0, 64(%rsp) movl $65536, %edi # imm = 0x10000 callq _Znam movq %rax, %rbx xorl %eax, %eax .LBB2_1: # =>This Inner Loop Header: Depth=1 movl $1008981770, (%rbx,%rax,4) # imm = 0x3C23D70A incq %rax cmpq $16384, %rax # imm = 0x4000 jne .LBB2_1 # %bb.2: leaq 24(%rsp), %r14 movl $48, %esi movq %r14, %rdi callq hipMalloc leaq 16(%rsp), %r15 movl $65536, %esi # imm = 0x10000 movq %r15, %rdi callq hipMalloc leaq 8(%rsp), %r12 movl $262144, %esi # imm = 0x40000 movq %r12, %rdi callq hipMalloc movq (%r14), %rdi leaq 32(%rsp), %rsi movl $48, %edx movl $1, %ecx callq hipMemcpy movq (%r15), %rdi movl $65536, %edx # imm = 0x10000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq (%r14), %rdi movq (%r15), %rdx movq (%r12), %rcx movl $4, %esi movl $256, %r8d # imm = 0x100 movl $256, %r9d # imm = 0x100 callq _Z23launchSparseConvolutionPK13SparseElementiPKfPfii movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %r13 movq (%r12), %rsi movl $262144, %edx # imm = 0x40000 movq %rax, %rdi movl $2, %ecx callq hipMemcpy movq (%r14), %rdi callq hipFree movq (%r15), %rdi callq hipFree movq (%r12), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r13, %rdi callq _ZdaPv movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $80, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii,@object # @_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .section .rodata,"a",@progbits .globl _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .p2align 3, 0x0 _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii: .quad _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii .size _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Sparse convolution completed successfully." .size .L.str.1, 43 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z23sparseConvolutionKernelPK13SparseElementiPKfPfii" .size .L__unnamed_1, 53 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z23sparseConvolutionKernelPK13SparseElementiPKfPfii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z14update_weightsPfS_fi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; ULDC UR4, c[0x0][0x174] ; UIMAD UR4, UR4, UR4, URZ ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, UR4, PT ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; LDG.E R4, [R4.64] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; FFMA R7, -R4, c[0x0][0x170], -RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13backward_passPfS_S_S_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; MOV R4, c[0x0][0x188] ; ULDC.64 UR4, c[0x0][0x118] ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; IMAD.WIDE R6, R0, R5, c[0x0][0x168] ; IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; LDG.E R6, [R6.64] ; LDG.E R3, [R2.64] ; @!P0 EXIT ; IADD3 R2, R4, -0x1, RZ ; FFMA R6, -R6, R6, 1 ; LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; FMUL R6, R6, R3 ; MOV R8, RZ ; @!P0 BRA 0xae0 ; IADD3 R9, -R7, c[0x0][0x188], RZ ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; ISETP.GT.AND P0, PT, R9, RZ, PT ; LEA R10, P1, R0.reuse, c[0x0][0x180], 0x2 ; MOV R2, c[0x0][0x160] ; LEA.HI.X R11, R0, c[0x0][0x184], R3, 0x2, P1 ; MOV R3, c[0x0][0x164] ; @!P0 BRA 0x960 ; ISETP.GT.AND P1, PT, R9, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x6b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R13, [R2.64] ; FMUL R19, R6, R13 ; STG.E [R10.64], R19 ; LDG.E R15, [R2.64+0x4] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R15 ; STG.E [R12.64], R21 ; LDG.E R17, [R2.64+0x8] ; IMAD.WIDE R14, R4, 0x4, R12 ; FMUL R23, R6, R17 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0xc] ; IMAD.WIDE R16, R4, 0x4, R14 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; LDG.E R19, [R2.64+0x10] ; IMAD.WIDE R10, R4, 0x4, R16 ; FMUL R19, R6, R19 ; STG.E [R10.64], R19 ; LDG.E R21, [R2.64+0x14] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R21 ; STG.E [R12.64], R21 ; LDG.E R23, [R2.64+0x18] ; IMAD.WIDE R14, R4, 0x4, R12 ; FMUL R23, R6, R23 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0x1c] ; IMAD.WIDE R16, R4, 0x4, R14 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; LDG.E R19, [R2.64+0x20] ; IMAD.WIDE R10, R4, 0x4, R16 ; FMUL R19, R6, R19 ; STG.E [R10.64], R19 ; LDG.E R21, [R2.64+0x24] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R21 ; STG.E [R12.64], R21 ; LDG.E R23, [R2.64+0x28] ; IMAD.WIDE R14, R4, 0x4, R12 ; FMUL R23, R6, R23 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0x2c] ; IMAD.WIDE R16, R4, 0x4, R14 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; LDG.E R19, [R2.64+0x30] ; IMAD.WIDE R10, R4, 0x4, R16 ; FMUL R19, R6, R19 ; STG.E [R10.64], R19 ; LDG.E R21, [R2.64+0x34] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R21 ; STG.E [R12.64], R21 ; LDG.E R23, [R2.64+0x38] ; IMAD.WIDE R14, R4, 0x4, R12 ; IADD3 R9, R9, -0x10, RZ ; FMUL R23, R6, R23 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0x3c] ; ISETP.GT.AND P1, PT, R9, 0xc, PT ; IMAD.WIDE R16, R4, 0x4, R14 ; IADD3 R18, P2, R2, 0x40, RZ ; IADD3 R8, R8, 0x10, RZ ; IADD3.X R19, RZ, R3, RZ, P2, !PT ; IMAD.WIDE R10, R4, 0x4, R16 ; MOV R2, R18 ; MOV R3, R19 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; @P1 BRA 0x230 ; ISETP.GT.AND P1, PT, R9, 0x4, PT ; @!P1 BRA 0x940 ; LDG.E R13, [R2.64] ; FMUL R19, R6, R13 ; STG.E [R10.64], R19 ; LDG.E R15, [R2.64+0x4] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R15 ; STG.E [R12.64], R21 ; LDG.E R17, [R2.64+0x8] ; IMAD.WIDE R14, R4, 0x4, R12 ; FMUL R23, R6, R17 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0xc] ; IMAD.WIDE R16, R4, 0x4, R14 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; LDG.E R19, [R2.64+0x10] ; IMAD.WIDE R10, R4, 0x4, R16 ; FMUL R19, R6, R19 ; STG.E [R10.64], R19 ; LDG.E R21, [R2.64+0x14] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R21 ; STG.E [R12.64], R21 ; LDG.E R23, [R2.64+0x18] ; IMAD.WIDE R14, R4, 0x4, R12 ; FMUL R23, R6, R23 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0x1c] ; IMAD.WIDE R16, R4, 0x4, R14 ; IADD3 R18, P1, R2, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R19, RZ, R3, RZ, P1, !PT ; IMAD.WIDE R10, R4, 0x4, R16 ; IADD3 R8, R8, 0x8, RZ ; IADD3 R9, R9, -0x8, RZ ; MOV R2, R18 ; MOV R3, R19 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; ISETP.NE.OR P0, PT, R9, RZ, P0 ; @!P0 BRA 0xae0 ; LDG.E R13, [R2.64] ; FMUL R19, R6, R13 ; STG.E [R10.64], R19 ; LDG.E R15, [R2.64+0x4] ; IMAD.WIDE R12, R4, 0x4, R10 ; FMUL R21, R6, R15 ; STG.E [R12.64], R21 ; LDG.E R17, [R2.64+0x8] ; IMAD.WIDE R14, R4, 0x4, R12 ; IADD3 R9, R9, -0x4, RZ ; FMUL R23, R6, R17 ; STG.E [R14.64], R23 ; LDG.E R25, [R2.64+0xc] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; IMAD.WIDE R16, R4, 0x4, R14 ; IADD3 R18, P1, R2, 0x10, RZ ; IADD3 R8, R8, 0x4, RZ ; IADD3.X R19, RZ, R3, RZ, P1, !PT ; IMAD.WIDE R10, R4, 0x4, R16 ; MOV R2, R18 ; MOV R3, R19 ; FMUL R25, R6, R25 ; STG.E [R16.64], R25 ; @P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; @!P0 EXIT ; IMAD.WIDE R2, R8, R5, c[0x0][0x160] ; IMAD R0, R8, c[0x0][0x188], R0 ; MOV R8, R2 ; MOV R9, R3 ; IMAD.WIDE R2, R0, R5, c[0x0][0x180] ; LDG.E R5, [R8.64] ; IADD3 R7, R7, -0x1, RZ ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IADD3 R8, P1, R8, 0x4, RZ ; IADD3.X R9, RZ, R9, RZ, P1, !PT ; FMUL R5, R6, R5 ; STG.E [R2.64], R5 ; IMAD.WIDE R2, R4, 0x4, R2 ; @P0 BRA 0xb50 ; EXIT ; BRA 0xbf0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z12forward_passPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; @P0 EXIT ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR4, c[0x0][0x118] ; HFMA2.MMA R20, -RZ, RZ, 0, 0 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0xb30 ; IADD3 R2, R4.reuse, -0x1, RZ ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; LOP3.LUT R6, R4, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; MOV R5, RZ ; @!P0 BRA 0xa20 ; IADD3 R8, -R6, c[0x0][0x178], RZ ; HFMA2.MMA R20, -RZ, RZ, 0, 0 ; IMAD.SHL.U32 R21, R0, 0x4, RZ ; MOV R2, c[0x0][0x160] ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; ISETP.GT.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; @!P0 BRA 0x8c0 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x630 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R26, [R2.64] ; LDG.E R24, [R2.64+0x4] ; LDG.E R23, [R2.64+0x8] ; LDG.E R22, [R2.64+0xc] ; LDG.E R19, [R2.64+0x10] ; LDG.E R7, [R2.64+0x14] ; LDG.E R16, [R2.64+0x18] ; LDG.E R12, [R2.64+0x1c] ; LDG.E R10, [R2.64+0x20] ; LDG.E R18, [R2.64+0x24] ; LDG.E R17, [R2.64+0x28] ; LDG.E R15, [R2.64+0x2c] ; LDG.E R14, [R2.64+0x30] ; LDG.E R13, [R2.64+0x34] ; LDG.E R11, [R2.64+0x38] ; LDG.E R9, [R2.64+0x3c] ; LEA R29, R4, R21, 0x2 ; IADD3 R8, R8, -0x10, RZ ; LDS R25, [R21] ; IADD3 R5, R5, 0x10, RZ ; IMAD R28, R4, 0x4, R29 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; IADD3 R2, P2, R2, 0x40, RZ ; IADD3.X R3, RZ, R3, RZ, P2, !PT ; FFMA R25, R25, R26, R20 ; LDS R26, [R29] ; LDS R20, [R28] ; LEA R29, R4, R28, 0x2 ; LDS R27, [R29] ; FFMA R25, R26, R24, R25 ; IMAD R26, R4, 0x4, R29 ; FFMA R23, R20, R23, R25 ; LDS R24, [R26] ; LEA R21, R4, R26, 0x2 ; LDS R20, [R21] ; IMAD R29, R4, 0x4, R21 ; FFMA R22, R27, R22, R23 ; LDS R25, [R29] ; LEA R28, R4, R29, 0x2 ; LDS R21, [R28] ; IMAD R23, R4, 0x4, R28 ; FFMA R22, R24, R19, R22 ; LEA R19, R4.reuse, R23, 0x2 ; LDS R23, [R23] ; IMAD R27, R4, 0x4, R19 ; LDS R19, [R19] ; FFMA R7, R20, R7, R22 ; LEA R29, R4, R27, 0x2 ; LDS R22, [R27] ; FFMA R26, R25, R16, R7 ; LDS R20, [R29] ; FFMA R21, R21, R12, R26 ; IMAD R27, R4, 0x4, R29 ; LEA R24, R4.reuse, R27, 0x2 ; LDS R25, [R27] ; IMAD R28, R4.reuse, 0x4, R24 ; LDS R24, [R24] ; LEA R7, R4, R28, 0x2 ; LDS R16, [R28] ; LDS R12, [R7] ; FFMA R10, R23, R10, R21 ; IMAD R21, R4, 0x4, R7 ; FFMA R10, R19, R18, R10 ; FFMA R10, R22, R17, R10 ; FFMA R10, R20, R15, R10 ; FFMA R10, R25, R14, R10 ; FFMA R10, R24, R13, R10 ; FFMA R10, R16, R11, R10 ; FFMA R20, R12, R9, R10 ; @P1 BRA 0x1d0 ; ISETP.GT.AND P1, PT, R8, 0x4, PT ; @!P1 BRA 0x8a0 ; LDG.E R15, [R2.64] ; LDG.E R14, [R2.64+0x4] ; LDG.E R12, [R2.64+0x8] ; LDG.E R13, [R2.64+0xc] ; LDG.E R11, [R2.64+0x10] ; LDG.E R10, [R2.64+0x14] ; LDG.E R7, [R2.64+0x18] ; LDG.E R9, [R2.64+0x1c] ; LEA R25, R4, R21, 0x2 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDS R19, [R21] ; LEA R23, R4, R25, 0x2 ; IADD3 R5, R5, 0x8, RZ ; LDS R25, [R25] ; IADD3 R8, R8, -0x8, RZ ; IMAD R27, R4, 0x4, R23 ; IADD3 R2, P1, R2, 0x20, RZ ; LDS R23, [R23] ; LEA R29, R4, R27, 0x2 ; LDS R22, [R27] ; IADD3.X R3, RZ, R3, RZ, P1, !PT ; LEA R17, R4.reuse, R29, 0x2 ; LDS R24, [R29] ; IMAD R18, R4.reuse, 0x4, R17 ; LDS R17, [R17] ; LEA R21, R4, R18, 0x2 ; LDS R18, [R18] ; LDS R16, [R21] ; IMAD R21, R4, 0x4, R21 ; FFMA R15, R19, R15, R20 ; FFMA R14, R25, R14, R15 ; FFMA R12, R23, R12, R14 ; FFMA R12, R22, R13, R12 ; FFMA R11, R24, R11, R12 ; FFMA R10, R17, R10, R11 ; FFMA R7, R18, R7, R10 ; FFMA R20, R16, R9, R7 ; ISETP.NE.OR P0, PT, R8, RZ, P0 ; @!P0 BRA 0xa20 ; LDG.E R7, [R2.64] ; LDG.E R10, [R2.64+0x4] ; LDG.E R12, [R2.64+0x8] ; LDG.E R14, [R2.64+0xc] ; LEA R9, R4, R21, 0x2 ; IADD3 R8, R8, -0x4, RZ ; LDS R21, [R21] ; LEA R11, R4, R9, 0x2 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; LDS R9, [R9] ; IADD3 R5, R5, 0x4, RZ ; IMAD R15, R4, 0x4, R11 ; IADD3 R2, P1, R2, 0x10, RZ ; LDS R13, [R11] ; IADD3.X R3, RZ, R3, RZ, P1, !PT ; LDS R16, [R15] ; FFMA R7, R7, R21, R20 ; LEA R21, R4, R15, 0x2 ; FFMA R7, R10, R9, R7 ; FFMA R7, R12, R13, R7 ; FFMA R20, R14, R16, R7 ; @P0 BRA 0x8c0 ; ISETP.NE.AND P0, PT, R6, RZ, PT ; @!P0 BRA 0xb30 ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; IMAD R7, R5.reuse, c[0x0][0x178], R0 ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; SHF.L.U32 R7, R7, 0x2, RZ ; MOV R8, R2 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; LDS R5, [R7] ; LDG.E R2, [R2.64] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R8, P1, R8, 0x4, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; LEA R7, R4, R7, 0x2 ; IADD3.X R3, RZ, R3, RZ, P1, !PT ; FFMA R20, R5, R2, R20 ; @P0 BRA 0xa90 ; FMUL R2, |R20|.reuse, 2.8853900432586669922 ; MOV R4, 0x3f800000 ; IMAD.MOV.U32 R5, RZ, RZ, 0x3c80f082 ; FSETP.GE.AND P1, PT, |R20|.reuse, 0.60000002384185791016, PT ; FMUL R6, R20.reuse, R20 ; FSETP.GE.AND P0, PT, |R20|, 9.010913848876953125, PT ; MUFU.EX2 R2, R2 ; FFMA R5, R6, R5, -0.052303962409496307373 ; FFMA R7, R6, R5, 0.1331529766321182251 ; FFMA R7, R6, R7, -0.33332768082618713379 ; FFMA R7, R6, R7, RZ ; FADD R3, R2, 1 ; MUFU.RCP R3, R3 ; FFMA R4, R3, -2, R4 ; MOV R3, 0x4 ; FSEL R5, R4, 1, !P0 ; IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; LOP3.LUT R5, R5, 0x80000000, R20.reuse, 0xf8, !PT ; @!P1 FFMA R5, R7, R20, R20 ; STG.E [R2.64], R5 ; EXIT ; BRA 0xc80; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z18initialize_weightsPfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; @P0 EXIT ; ULDC.64 UR4, c[0x0][0x118] ; CS2R R2, SR_CLOCKLO ; IADD3 R0, P0, R5, R2, RZ ; LOP3.LUT R0, R0, 0xaad26b49, RZ, 0x3c, !PT ; LEA.HI.X.SX32 R3, R5, R3, 0x1, P0 ; IMAD R0, R0, 0x4182bed5, RZ ; LOP3.LUT R3, R3, 0xf7dcefdd, RZ, 0x3c, !PT ; IADD3 R2, R0.reuse, 0x75bcd15, RZ ; IMAD R3, R3, -0x658354e5, R0 ; IADD3 R4, R0, 0x583f19, RZ ; SHF.R.U32.HI R7, RZ, 0x2, R2 ; IMAD.SHL.U32 R6, R4, 0x10, RZ ; LOP3.LUT R7, R7, R2, RZ, 0x3c, !PT ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; LOP3.LUT R6, R7.reuse, R6, R4, 0x96, !PT ; IMAD.SHL.U32 R7, R7, 0x2, RZ ; LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; IADD3 R6, R3, 0x6a788e, R6 ; IMAD.MOV.U32 R3, RZ, RZ, 0x2f800000 ; I2F.U32 R6, R6 ; FFMA R0, R6, R3, 1.1641532182693481445e-10 ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; FMUL R5, R0, 0.0099999997764825820923 ; STG.E [R2.64], R5 ; EXIT ; BRA 0x1f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18initialize_weightsPfi ; -- Begin function _Z18initialize_weightsPfi .globl _Z18initialize_weightsPfi .p2align 8 .type _Z18initialize_weightsPfi,@function _Z18initialize_weightsPfi: ; @_Z18initialize_weightsPfi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20) v_ashrrev_i32_e32 v2, 31, v1 v_add_co_u32 v0, vcc_lo, s2, v1 s_load_b64 s[0:1], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, 0, v2, vcc_lo v_xor_b32_e32 v0, 0x2c7f967f, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v8, 0xa03697cb, v3 v_mul_lo_u32 v0, 0x493c4aa1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, 0x75bcd15, v0 v_add_nc_u32_e32 v6, 0x583f19, v0 v_lshrrev_b32_e32 v5, 2, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v5, v5, v4 v_lshlrev_b32_e32 v4, 4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v7, 1, v5 v_xor_b32_e32 v7, v4, v7 v_mad_u64_u32 v[3:4], null, 0x7b99840d, v8, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor3_b32 v0, v7, v6, v5 v_add3_u32 v0, v3, v0, 0x6a788e s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v0, v0 v_fmaak_f32 v3, 0x2f800000, v0, 0x2f800000 v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v2, 0x3c23d70a, v3 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18initialize_weightsPfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18initialize_weightsPfi, .Lfunc_end0-_Z18initialize_weightsPfi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 284 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z12forward_passPfS_S_i ; -- Begin function _Z12forward_passPfS_S_i .globl _Z12forward_passPfS_S_i .p2align 8 .type _Z12forward_passPfS_S_i,@function _Z12forward_passPfS_S_i: ; @_Z12forward_passPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s4, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s4, v1 s_cbranch_execz .LBB1_10 ; %bb.1: ; %.preheader s_cmp_lt_i32 s4, 1 s_cbranch_scc1 .LBB1_4 ; %bb.2: ; %.lr.ph.preheader s_load_b64 s[2:3], s[0:1], 0x0 v_lshl_add_u32 v2, v1, 2, 0 v_mov_b32_e32 v0, 0 s_lshl_b32 s5, s4, 2 .LBB1_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) s_load_b32 s6, s[2:3], 0x0 ds_load_b32 v3, v2 s_add_i32 s4, s4, -1 v_add_nc_u32_e32 v2, s5, v2 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmp_eq_u32 s4, 0 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v0, s6, v3 s_cbranch_scc0 .LBB1_3 s_branch .LBB1_5 .LBB1_4: v_mov_b32_e32 v0, 0 .LBB1_5: ; %._crit_edge s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ngt_f32_e64 s2, 0x3f200000, |v0| ; implicit-def: $vgpr3 s_and_saveexec_b32 s3, s2 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s2, exec_lo, s3 s_cbranch_execz .LBB1_7 ; %bb.6: v_add_f32_e64 v2, |v0|, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v3, 0x3fb8aa3b, v2 v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2 v_rndne_f32_e32 v4, v3 v_fma_f32 v5, 0x3fb8aa3b, v2, -v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_f32_e32 v3, v3, v4 v_fmamk_f32 v5, v2, 0x32a5705f, v5 v_cvt_i32_f32_e32 v4, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v3, v3, v5 v_exp_f32_e32 v3, v3 s_waitcnt_depctr 0xfff v_ldexp_f32 v3, v3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2 v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v2, 1.0, v2 v_rcp_f32_e32 v2, v2 s_waitcnt_depctr 0xfff v_fma_f32 v3, v2, -2.0, 1.0 .LBB1_7: ; %Flow s_and_not1_saveexec_b32 s2, s2 ; %bb.8: v_mul_f32_e32 v2, v0, v0 s_mov_b32 s3, 0xbbbac73d s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fmaak_f32 v3, s3, v2, 0x3ca908c9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmaak_f32 v3, v2, v3, 0xbd5c1c4e v_fmaak_f32 v3, v2, v3, 0x3e088382 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmaak_f32 v3, v2, v3, 0xbeaaaa99 v_mul_f32_e64 v3, |v0|, v3 s_delay_alu instid0(VALU_DEP_1) v_fma_f32 v3, v2, v3, |v0| ; %bb.9: ; %_ZL4tanhf.exit s_or_b32 exec_lo, exec_lo, s2 s_load_b64 s[0:1], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_bfi_b32 v3, 0x7fffffff, v3, v0 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo global_store_b32 v[0:1], v3, off .LBB1_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12forward_passPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z12forward_passPfS_S_i, .Lfunc_end1-_Z12forward_passPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 480 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13backward_passPfS_S_S_S_i ; -- Begin function _Z13backward_passPfS_S_S_S_i .globl _Z13backward_passPfS_S_S_S_i .p2align 8 .type _Z13backward_passPfS_S_S_S_i,@function _Z13backward_passPfS_S_S_S_i: ; @_Z13backward_passPfS_S_S_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x3c s_load_b32 s8, s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s8, v1 s_cbranch_execz .LBB2_4 ; %bb.1: s_cmp_lt_i32 s8, 1 s_cbranch_scc1 .LBB2_4 ; %bb.2: ; %.lr.ph.preheader s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b128 s[0:3], s[0:1], 0x18 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo s_mov_b32 s0, s8 global_load_b32 v0, v[4:5], off global_load_b32 v2, v[2:3], off v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(1) v_fma_f32 v0, -v0, v0, 1.0 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f32_e32 v0, v2, v0 .LBB2_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b32 v6, v3, s[4:5] v_ashrrev_i32_e32 v2, 31, v1 s_add_i32 s0, s0, -1 s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s0, 0 v_lshlrev_b64 v[4:5], 2, v[1:2] v_add_nc_u32_e32 v1, s8, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo s_waitcnt vmcnt(0) v_mul_f32_e32 v2, v0, v6 global_store_b32 v[4:5], v2, off s_cbranch_scc1 .LBB2_3 .LBB2_4: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13backward_passPfS_S_S_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z13backward_passPfS_S_S_S_i, .Lfunc_end2-_Z13backward_passPfS_S_S_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 272 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z14update_weightsPfS_fi ; -- Begin function _Z14update_weightsPfS_fi .globl _Z14update_weightsPfS_fi .p2align 8 .type _Z14update_weightsPfS_fi,@function _Z14update_weightsPfS_fi: ; @_Z14update_weightsPfS_fi ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_mul_i32 s3, s3, s3 v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_i32_e32 vcc_lo, s3, v1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB3_3 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s0, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_load_b32 v2, v[2:3], off global_load_b32 v3, v[0:1], off s_waitcnt vmcnt(1) v_mul_f32_e64 v4, v2, -s2 .LBB3_2: ; %atomicrmw.start ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v2, v3, v4 global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v2, v3 v_mov_b32_e32 v3, v2 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB3_2 .LBB3_3: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14update_weightsPfS_fi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z14update_weightsPfS_fi, .Lfunc_end3-_Z14update_weightsPfS_fi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 200 ; NumSgprs: 18 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18initialize_weightsPfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18initialize_weightsPfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12forward_passPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12forward_passPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13backward_passPfS_S_S_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13backward_passPfS_S_S_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14update_weightsPfS_fi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14update_weightsPfS_fi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0012f972_00000000-6_cuda_code_030668.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3854: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3854: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string ": " .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3849: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC0(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3849: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z39__device_stub__Z18initialize_weightsPfiPfi .type _Z39__device_stub__Z18initialize_weightsPfiPfi, @function _Z39__device_stub__Z18initialize_weightsPfiPfi: .LFB3876: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z18initialize_weightsPfi(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3876: .size _Z39__device_stub__Z18initialize_weightsPfiPfi, .-_Z39__device_stub__Z18initialize_weightsPfiPfi .globl _Z18initialize_weightsPfi .type _Z18initialize_weightsPfi, @function _Z18initialize_weightsPfi: .LFB3877: .cfi_startproc endbr64 jmp _Z39__device_stub__Z18initialize_weightsPfiPfi .cfi_endproc .LFE3877: .size _Z18initialize_weightsPfi, .-_Z18initialize_weightsPfi .globl _Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i .type _Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i, @function _Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i: .LFB3878: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L13 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z12forward_passPfS_S_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L13: movq 136(%rsp), %rax subq %fs:40, %rax je .L15 call __stack_chk_fail@PLT .L15: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3878: .size _Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i .globl _Z12forward_passPfS_S_i .type _Z12forward_passPfS_S_i, @function _Z12forward_passPfS_S_i: .LFB3879: .cfi_startproc endbr64 jmp _Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i .cfi_endproc .LFE3879: .size _Z12forward_passPfS_S_i, .-_Z12forward_passPfS_S_i .globl _Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i .type _Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i, @function _Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i: .LFB3880: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) leaq 72(%rsp), %rdi movq %rsi, 32(%rsp) leaq 84(%rsp), %rsi movq %rdx, 24(%rsp) leaq 56(%rsp), %rdx movq %rcx, 16(%rsp) leaq 64(%rsp), %rcx movq %r8, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 80(%rsp) movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 4(%rsp), %rax movq %rax, 160(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) movq %rax, 84(%rsp) movl $1, 92(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L18 pushq 64(%rsp) .cfi_def_cfa_offset 200 leaq _Z13backward_passPfS_S_S_S_i(%rip), %rdi pushq 64(%rsp) .cfi_def_cfa_offset 208 movq 100(%rsp), %rcx movl 108(%rsp), %r8d movq 88(%rsp), %rsi movl 96(%rsp), %edx leaq 136(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 200 popq %rdx .cfi_def_cfa_offset 192 .L18: movq 168(%rsp), %rax subq %fs:40, %rax je .L20 call __stack_chk_fail@PLT .L20: addq $184, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3880: .size _Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i, .-_Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i .globl _Z13backward_passPfS_S_S_S_i .type _Z13backward_passPfS_S_S_S_i, @function _Z13backward_passPfS_S_S_S_i: .LFB3881: .cfi_startproc endbr64 jmp _Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i .cfi_endproc .LFE3881: .size _Z13backward_passPfS_S_S_S_i, .-_Z13backward_passPfS_S_S_S_i .globl _Z38__device_stub__Z14update_weightsPfS_fiPfS_fi .type _Z38__device_stub__Z14update_weightsPfS_fiPfS_fi, @function _Z38__device_stub__Z14update_weightsPfS_fiPfS_fi: .LFB3882: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 48(%rsp), %rcx leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movl %edx, 8(%rsp) leaq 40(%rsp), %rdx movss %xmm0, 12(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L23 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z14update_weightsPfS_fi(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L23: movq 136(%rsp), %rax subq %fs:40, %rax je .L25 call __stack_chk_fail@PLT .L25: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3882: .size _Z38__device_stub__Z14update_weightsPfS_fiPfS_fi, .-_Z38__device_stub__Z14update_weightsPfS_fiPfS_fi .globl _Z14update_weightsPfS_fi .type _Z14update_weightsPfS_fi, @function _Z14update_weightsPfS_fi: .LFB3883: .cfi_startproc endbr64 jmp _Z38__device_stub__Z14update_weightsPfS_fiPfS_fi .cfi_endproc .LFE3883: .size _Z14update_weightsPfS_fi, .-_Z14update_weightsPfS_fi .section .rodata.str1.1 .LC1: .string "Forward pass kernel launch failed" .LC2: .string "Memcpy failed" .LC3: .string "Synchronization failed" .LC4: .string "Backward pass kernel launch failed" .LC5: .string "Update weights kernel launch failed" .text .globl _Z20train_neural_networkPfS_S_S_S_fi .type _Z20train_neural_networkPfS_S_S_S_fi, @function _Z20train_neural_networkPfS_S_S_S_fi: .LFB3850: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 xorl %r15d, %r15d pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 movl %r9d, %r14d pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 movl $16777217, %ebx salq $8, %rbx subq $88, %rsp .cfi_def_cfa_offset 144 movq %rdi, (%rsp) movq %rsi, 24(%rsp) movq %rdx, 8(%rsp) movq %rcx, 32(%rsp) movq %r8, 16(%rsp) movss %xmm0, 44(%rsp) .L29: cmpl %r14d, %r15d jge .L41 movl $2147483649, %ebp movq 24(%rsp), %r12 xorl %r13d, %r13d addq %rbp, %rbp .L34: xorl %r9d, %r9d movl $1048576, %r8d movq %rbx, %rdx movq %rbp, %rdi movl $1, %ecx movl $1, %esi movq %rbx, 68(%rsp) movl $1, 76(%rsp) movq %rbp, 56(%rsp) movl $1, 64(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L30 movq 8(%rsp), %rdx movq (%rsp), %rdi movl $512, %ecx movq %r12, %rsi call _Z37__device_stub__Z12forward_passPfS_S_iPfS_S_i .L30: call cudaGetLastError@PLT leaq .LC1(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc cmpl $3, %r13d je .L31 movq 8(%rsp), %rsi movq (%rsp), %rdi movl $3, %ecx movl $2048, %edx call cudaMemcpy@PLT call cudaGetLastError@PLT leaq .LC2(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc .L31: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %r9d, %r9d movq %rbx, %rdx movl $1, %ecx movl $1048576, %r8d movq %rbp, %rdi movl $1, %esi movq %rbx, 68(%rsp) movl $1, 76(%rsp) movq %rbp, 56(%rsp) movl $1, 64(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L32 movq 16(%rsp), %r8 movq 32(%rsp), %rcx movl $512, %r9d movq %r12, %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z42__device_stub__Z13backward_passPfS_S_S_S_iPfS_S_S_S_i .L32: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %r9d, %r9d xorl %r8d, %r8d movq %rbx, %rdx movl $1, %ecx movq %rbp, %rdi movl $1, %esi movq %rbx, 68(%rsp) movl $1, 76(%rsp) movq %rbp, 56(%rsp) movl $1, 64(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L33 movss 44(%rsp), %xmm0 movq 16(%rsp), %rsi movl $512, %edx movq %r12, %rdi call _Z38__device_stub__Z14update_weightsPfS_fiPfS_fi .L33: call cudaGetLastError@PLT leaq .LC5(%rip), %rsi incl %r13d addq $1048576, %r12 movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc cmpl $4, %r13d jne .L34 incl %r15d jmp .L29 .L41: addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3850: .size _Z20train_neural_networkPfS_S_S_S_fi, .-_Z20train_neural_networkPfS_S_S_S_fi .section .rodata.str1.1 .LC8: .string "Memcpy input failed" .LC9: .string "Initialize weights kernel launch failed" .LC11: .string "Memcpy output failed" .LC12: .string "Output of first neuron: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3851: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $2048, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $80, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax call _Znam@PLT movl $2048, %edi movq %rax, %rbp call _Znam@PLT movl $2048, %edi movq %rax, %rbx call _Znam@PLT movss .LC6(%rip), %xmm1 movss .LC7(%rip), %xmm0 movq %rax, %r12 xorl %eax, %eax .L43: movss %xmm1, 0(%rbp,%rax) movss %xmm0, (%r12,%rax) addq $4, %rax cmpq $2048, %rax jne .L43 leaq 8(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $2048, %edx call cudaMemcpy@PLT call cudaGetLastError@PLT leaq .LC8(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1048577, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $12, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L44 movq 16(%rsp), %rdi movl $1048576, %esi call _Z39__device_stub__Z18initialize_weightsPfiPfi .L44: call cudaGetLastError@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 40(%rsp), %r8 movq 32(%rsp), %rcx movl $1000, %r9d movss .LC10(%rip), %xmm0 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z20train_neural_networkPfS_S_S_S_fi movq 24(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi movl $2048, %edx call cudaMemcpy@PLT call cudaGetLastError@PLT leaq .LC11(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq .LC12(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd (%rbx), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movq 72(%rsp), %rax subq %fs:40, %rax je .L45 call __stack_chk_fail@PLT .L45: addq $80, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3851: .size main, .-main .section .rodata.str1.1 .LC13: .string "_Z14update_weightsPfS_fi" .LC14: .string "_Z13backward_passPfS_S_S_S_i" .LC15: .string "_Z12forward_passPfS_S_i" .LC16: .string "_Z18initialize_weightsPfi" .LC17: .string "precalc_xorwow_matrix" .LC18: .string "precalc_xorwow_offset_matrix" .LC19: .string "mrg32k3aM1" .LC20: .string "mrg32k3aM2" .LC21: .string "mrg32k3aM1SubSeq" .LC22: .string "mrg32k3aM2SubSeq" .LC23: .string "mrg32k3aM1Seq" .LC24: .string "mrg32k3aM2Seq" .LC25: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3885: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z14update_weightsPfS_fi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC14(%rip), %rdx movq %rbx, %rdi leaq _Z13backward_passPfS_S_S_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC15(%rip), %rdx movq %rbx, %rdi leaq _Z12forward_passPfS_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC16(%rip), %rdx movq %rbx, %rdi leaq _Z18initialize_weightsPfi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r8d, %r8d movq %rbx, %rdi pushq $0 .cfi_def_cfa_offset 24 leaq .LC17(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC19(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC20(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC21(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC22(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC23(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC24(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC25(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3885: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC6: .long 1056964608 .align 4 .LC7: .long 1065353216 .align 4 .LC10: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_030668.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z33__device_stub__initialize_weightsPfi # -- Begin function _Z33__device_stub__initialize_weightsPfi .type _Z33__device_stub__initialize_weightsPfi,@function _Z33__device_stub__initialize_weightsPfi: # @_Z33__device_stub__initialize_weightsPfi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z18initialize_weightsPfi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z33__device_stub__initialize_weightsPfi, .Lfunc_end0-_Z33__device_stub__initialize_weightsPfi .cfi_endproc # -- End function .globl _Z27__device_stub__forward_passPfS_S_i # -- Begin function _Z27__device_stub__forward_passPfS_S_i .type _Z27__device_stub__forward_passPfS_S_i,@function _Z27__device_stub__forward_passPfS_S_i: # @_Z27__device_stub__forward_passPfS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z12forward_passPfS_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z27__device_stub__forward_passPfS_S_i, .Lfunc_end1-_Z27__device_stub__forward_passPfS_S_i .cfi_endproc # -- End function .globl _Z28__device_stub__backward_passPfS_S_S_S_i # -- Begin function _Z28__device_stub__backward_passPfS_S_S_S_i .type _Z28__device_stub__backward_passPfS_S_S_S_i,@function _Z28__device_stub__backward_passPfS_S_S_S_i: # @_Z28__device_stub__backward_passPfS_S_S_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 4(%rsp), %r8 movl %r9d, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13backward_passPfS_S_S_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z28__device_stub__backward_passPfS_S_S_S_i, .Lfunc_end2-_Z28__device_stub__backward_passPfS_S_S_S_i .cfi_endproc # -- End function .globl _Z29__device_stub__update_weightsPfS_fi # -- Begin function _Z29__device_stub__update_weightsPfS_fi .type _Z29__device_stub__update_weightsPfS_fi,@function _Z29__device_stub__update_weightsPfS_fi: # @_Z29__device_stub__update_weightsPfS_fi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movss %xmm0, (%rsi) leaq 8(%rsp), %rdi movl %edx, (%rdi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) movq %rdi, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z14update_weightsPfS_fi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z29__device_stub__update_weightsPfS_fi, .Lfunc_end3-_Z29__device_stub__update_weightsPfS_fi .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB4_2 # %bb.1: retq .LBB4_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl %edi, %ebx movl $_ZSt4cerr, %edi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end4: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end4-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl _Z20train_neural_networkPfS_S_S_S_fi # -- Begin function _Z20train_neural_networkPfS_S_S_S_fi .type _Z20train_neural_networkPfS_S_S_S_fi,@function _Z20train_neural_networkPfS_S_S_S_fi: # @_Z20train_neural_networkPfS_S_S_S_fi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movss %xmm0, 12(%rsp) # 4-byte Spill movq %r8, 16(%rsp) # 8-byte Spill movq %rcx, 32(%rsp) # 8-byte Spill movl %r9d, 8(%rsp) # 4-byte Spill testl %r9d, %r9d jle .LBB5_13 # %bb.1: # %.preheader.preheader movq %rdx, %r12 movq %rsi, %r13 movq %rdi, %rbp xorl %eax, %eax movabsq $4294967298, %rbx # imm = 0x100000002 leaq 254(%rbx), %r15 .LBB5_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB5_3 Depth 2 movq %rax, 24(%rsp) # 8-byte Spill xorl %r14d, %r14d .LBB5_3: # Parent Loop BB5_2 Depth=1 # => This Inner Loop Header: Depth=2 movl $1048576, %r8d # imm = 0x100000 movq %rbx, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_5 # %bb.4: # in Loop: Header=BB5_3 Depth=2 leaq (%r14,%r13), %rsi movq %rbp, %rdi movq %r12, %rdx movl $512, %ecx # imm = 0x200 callq _Z27__device_stub__forward_passPfS_S_i .LBB5_5: # in Loop: Header=BB5_3 Depth=2 callq hipGetLastError movl $.L.str.1, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc cmpq $3145728, %r14 # imm = 0x300000 je .LBB5_7 # %bb.6: # in Loop: Header=BB5_3 Depth=2 movl $2048, %edx # imm = 0x800 movq %rbp, %rdi movq %r12, %rsi movl $3, %ecx callq hipMemcpy callq hipGetLastError movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc .LBB5_7: # in Loop: Header=BB5_3 Depth=2 callq hipDeviceSynchronize callq hipGetLastError movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $1048576, %r8d # imm = 0x100000 movq %rbx, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_9 # %bb.8: # in Loop: Header=BB5_3 Depth=2 leaq (%r14,%r13), %rdx movq %rbp, %rdi movq %r12, %rsi movq 32(%rsp), %rcx # 8-byte Reload movq 16(%rsp), %r8 # 8-byte Reload movl $512, %r9d # imm = 0x200 callq _Z28__device_stub__backward_passPfS_S_S_S_i .LBB5_9: # in Loop: Header=BB5_3 Depth=2 callq hipGetLastError movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_11 # %bb.10: # in Loop: Header=BB5_3 Depth=2 leaq (%r14,%r13), %rdi movq 16(%rsp), %rsi # 8-byte Reload movss 12(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movl $512, %edx # imm = 0x200 callq _Z29__device_stub__update_weightsPfS_fi .LBB5_11: # in Loop: Header=BB5_3 Depth=2 callq hipGetLastError movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize callq hipGetLastError movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc addq $1048576, %r14 # imm = 0x100000 cmpq $4194304, %r14 # imm = 0x400000 jne .LBB5_3 # %bb.12: # in Loop: Header=BB5_2 Depth=1 movq 24(%rsp), %rax # 8-byte Reload incl %eax cmpl 8(%rsp), %eax # 4-byte Folded Reload jne .LBB5_2 .LBB5_13: # %._crit_edge addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size _Z20train_neural_networkPfS_S_S_S_fi, .Lfunc_end5-_Z20train_neural_networkPfS_S_S_S_fi .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI6_0: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $48, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %rbx movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %r14 xorl %eax, %eax .LBB6_1: # =>This Inner Loop Header: Depth=1 movl $1056964608, (%rbx,%rax,4) # imm = 0x3F000000 incq %rax cmpq $512, %rax # imm = 0x200 jne .LBB6_1 # %bb.2: leaq 40(%rsp), %r15 movl $2048, %esi # imm = 0x800 movq %r15, %rdi callq hipMalloc leaq 16(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc leaq 8(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc leaq 32(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc leaq 24(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc movq (%r15), %rdi movl $2048, %edx # imm = 0x800 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $4294967552, %rdx # imm = 0x100000100 leaq 3840(%rdx), %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB6_4 # %bb.3: movq 16(%rsp), %rdi movl $1048576, %esi # imm = 0x100000 callq _Z33__device_stub__initialize_weightsPfi .LBB6_4: callq hipGetLastError movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize callq hipGetLastError movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 40(%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movq 32(%rsp), %rcx movq 24(%rsp), %r8 movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movl $1000, %r9d # imm = 0x3E8 callq _Z20train_neural_networkPfS_S_S_S_fi movq 8(%rsp), %rsi movl $2048, %edx # imm = 0x800 movq %r14, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $24, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd (%r14), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movq (%rax), %rax movq -24(%rax), %rdi addq %r15, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 40(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax addq $48, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end6: .size main, .Lfunc_end6-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB7_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB7_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18initialize_weightsPfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12forward_passPfS_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13backward_passPfS_S_S_S_i, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14update_weightsPfS_fi, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end7: .size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB8_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB8_2: retq .Lfunc_end8: .size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor .cfi_endproc # -- End function .type _Z18initialize_weightsPfi,@object # @_Z18initialize_weightsPfi .section .rodata,"a",@progbits .globl _Z18initialize_weightsPfi .p2align 3, 0x0 _Z18initialize_weightsPfi: .quad _Z33__device_stub__initialize_weightsPfi .size _Z18initialize_weightsPfi, 8 .type _Z12forward_passPfS_S_i,@object # @_Z12forward_passPfS_S_i .globl _Z12forward_passPfS_S_i .p2align 3, 0x0 _Z12forward_passPfS_S_i: .quad _Z27__device_stub__forward_passPfS_S_i .size _Z12forward_passPfS_S_i, 8 .type _Z13backward_passPfS_S_S_S_i,@object # @_Z13backward_passPfS_S_S_S_i .globl _Z13backward_passPfS_S_S_S_i .p2align 3, 0x0 _Z13backward_passPfS_S_S_S_i: .quad _Z28__device_stub__backward_passPfS_S_S_S_i .size _Z13backward_passPfS_S_S_S_i, 8 .type _Z14update_weightsPfS_fi,@object # @_Z14update_weightsPfS_fi .globl _Z14update_weightsPfS_fi .p2align 3, 0x0 _Z14update_weightsPfS_fi: .quad _Z29__device_stub__update_weightsPfS_fi .size _Z14update_weightsPfS_fi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz ": " .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Forward pass kernel launch failed" .size .L.str.1, 34 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Memcpy failed" .size .L.str.2, 14 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Synchronization failed" .size .L.str.3, 23 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Backward pass kernel launch failed" .size .L.str.4, 35 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Update weights kernel launch failed" .size .L.str.5, 36 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Memcpy input failed" .size .L.str.6, 20 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Initialize weights kernel launch failed" .size .L.str.7, 40 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Memcpy output failed" .size .L.str.8, 21 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Output of first neuron: " .size .L.str.9, 25 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z18initialize_weightsPfi" .size .L__unnamed_1, 26 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z12forward_passPfS_S_i" .size .L__unnamed_2, 24 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z13backward_passPfS_S_S_S_i" .size .L__unnamed_3, 29 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z14update_weightsPfS_fi" .size .L__unnamed_4, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__initialize_weightsPfi .addrsig_sym _Z27__device_stub__forward_passPfS_S_i .addrsig_sym _Z28__device_stub__backward_passPfS_S_S_S_i .addrsig_sym _Z29__device_stub__update_weightsPfS_fi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18initialize_weightsPfi .addrsig_sym _Z12forward_passPfS_S_i .addrsig_sym _Z13backward_passPfS_S_S_S_i .addrsig_sym _Z14update_weightsPfS_fi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15poly1305_kernelPKhPhS0_m .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; LDG.E R17, [R2.64] ; LDG.E R15, [R2.64+0x4] ; LDG.E R13, [R2.64+0x8] ; LDG.E R11, [R2.64+0xc] ; BSSY B1, 0x10d0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; S2R R4, SR_CTAID.X ; S2R R9, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R9 ; IMAD.WIDE.U32 R4, R4, 0x10, RZ ; ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x17c], PT, P0 ; LOP3.LUT R0, R17, 0xffffff, RZ, 0xc0, !PT ; LOP3.LUT R6, R15, 0xffffff, RZ, 0xc0, !PT ; LOP3.LUT R7, R13, 0xffffff, RZ, 0xc0, !PT ; LOP3.LUT R8, R11, 0xffffff, RZ, 0xc0, !PT ; @P0 BRA 0x10c0 ; IADD3 R12, P1, -R4, c[0x0][0x178], RZ ; BSSY B0, 0xf10 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; CS2R R18, SRZ ; ISETP.LT.U32.AND P0, PT, R12, 0x10, PT ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; IADD3.X R10, ~R5, c[0x0][0x17c], RZ, P1, !PT ; ISETP.LT.U32.AND.EX P0, PT, R10, RZ, PT, P0 ; SEL R12, R12, 0x10, P0 ; SEL R10, R10, RZ, P0 ; ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; @!P0 BRA 0xf00 ; ISETP.GT.U32.AND P1, PT, R12, RZ, PT ; BSSY B2, 0x460 ; IADD3 R20, P2, R4, c[0x0][0x160], RZ ; CS2R R18, SRZ ; ISETP.GT.U32.AND.EX P1, PT, R10, RZ, PT, P1 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IADD3.X R22, R5, c[0x0][0x164], RZ, P2, !PT ; IMAD.MOV.U32 R21, RZ, RZ, RZ ; IMAD.MOV.U32 R23, RZ, RZ, RZ ; @P1 BRA 0x450 ; IADD3 R4, P0, R21, R20, RZ ; IMAD.X R5, R23, 0x1, R22, P0 ; LDG.E.U8 R4, [R4.64] ; LOP3.LUT R23, R21.reuse, 0xfffffffc, RZ, 0xc0, !PT ; IMAD.SHL.U32 R21, R21, 0x8, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; ISETP.EQ.AND P1, PT, R23.reuse, RZ, PT ; ISETP.EQ.AND P2, PT, R23.reuse, 0x4, PT ; ISETP.EQ.AND P3, PT, R23.reuse, 0x8, PT ; ISETP.EQ.AND P4, PT, R23, 0xc, PT ; LOP3.LUT R21, R21, 0x18, RZ, 0xc0, !PT ; @P1 IMAD.MOV.U32 R23, RZ, RZ, R19 ; @P2 IMAD.MOV.U32 R23, RZ, RZ, R18 ; @P3 IMAD.MOV.U32 R23, RZ, RZ, R16 ; @P4 IMAD.MOV.U32 R23, RZ, RZ, R14 ; SHF.L.U32 R4, R4, R21, RZ ; IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; LOP3.LUT R4, R4, R23, RZ, 0xfc, !PT ; IMAD.MOV.U32 R23, RZ, RZ, RZ ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R4.reuse ; @P2 IMAD.MOV.U32 R18, RZ, RZ, R4.reuse ; @P3 IMAD.MOV.U32 R16, RZ, RZ, R4.reuse ; @P4 IMAD.MOV.U32 R14, RZ, RZ, R4 ; BSYNC B2 ; IADD3 R4, P3, -R21, R12, RZ ; BSSY B2, 0xa40 ; ISETP.GT.U32.AND P1, PT, R12, R21, PT ; ISETP.LE.U32.AND P2, PT, R4, 0x3, PT ; IMAD.X R4, R10.reuse, 0x1, ~R23, P3 ; ISETP.GT.U32.AND.EX P1, PT, R10, R23, PT, P1 ; ISETP.LE.U32.OR.EX P1, PT, R4, RZ, !P1, P2 ; @P1 BRA 0xa30 ; IADD3 R26, P1, R12, -0x3, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R24, R10, -0x1, RZ, P1, !PT ; IADD3 R4, P1, R21, R20, RZ ; IMAD.X R5, R23, 0x1, R22, P1 ; LDG.E.U8 R29, [R4.64] ; LDG.E.U8 R28, [R4.64+0x1] ; LDG.E.U8 R25, [R4.64+0x2] ; LDG.E.U8 R27, [R4.64+0x3] ; LOP3.LUT R30, R21, 0xfffffffc, RZ, 0xc0, !PT ; IADD3 R31, R21.reuse, 0x1, RZ ; ISETP.EQ.AND P2, PT, R30.reuse, RZ, PT ; ISETP.EQ.AND P3, PT, R30.reuse, 0x4, PT ; ISETP.EQ.AND P4, PT, R30.reuse, 0x8, PT ; ISETP.EQ.AND P5, PT, R30, 0xc, PT ; IMAD.SHL.U32 R30, R21, 0x8, RZ ; LOP3.LUT R4, R31, 0xfffffffc, RZ, 0xc0, !PT ; LOP3.LUT R30, R30, 0x18, RZ, 0xc0, !PT ; @P2 IMAD.MOV.U32 R32, RZ, RZ, R19 ; ISETP.EQ.AND P1, PT, R4.reuse, RZ, PT ; @P3 IMAD.MOV.U32 R32, RZ, RZ, R18 ; ISETP.EQ.AND P6, PT, R4, 0x4, PT ; @P4 IMAD.MOV.U32 R32, RZ, RZ, R16 ; @P5 IMAD.MOV.U32 R32, RZ, RZ, R14 ; SHF.L.U32 R29, R29, R30, RZ ; LOP3.LUT R29, R29, R32, RZ, 0xfc, !PT ; @P2 IMAD.MOV.U32 R19, RZ, RZ, R29.reuse ; ISETP.EQ.AND P2, PT, R4.reuse, 0x8, PT ; @P3 IMAD.MOV.U32 R18, RZ, RZ, R29.reuse ; ISETP.EQ.AND P3, PT, R4, 0xc, PT ; IMAD.SHL.U32 R4, R31, 0x8, RZ ; IADD3 R31, R21, 0x2, RZ ; @P4 IMAD.MOV.U32 R16, RZ, RZ, R29.reuse ; @P5 IMAD.MOV.U32 R14, RZ, RZ, R29 ; LOP3.LUT R5, R4, 0x18, RZ, 0xc0, !PT ; @P1 IMAD.MOV.U32 R30, RZ, RZ, R19 ; LOP3.LUT R4, R31, 0xfffffffc, RZ, 0xc0, !PT ; @P6 IMAD.MOV.U32 R30, RZ, RZ, R18 ; SHF.L.U32 R5, R28, R5, RZ ; @P2 IMAD.MOV.U32 R30, RZ, RZ, R16 ; ISETP.EQ.AND P4, PT, R4.reuse, RZ, PT ; @P3 IMAD.MOV.U32 R30, RZ, RZ, R14 ; ISETP.EQ.AND P5, PT, R4, 0x4, PT ; IADD3 R28, R21, 0x3, RZ ; LOP3.LUT R5, R5, R30, RZ, 0xfc, !PT ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R5.reuse ; ISETP.EQ.AND P1, PT, R4.reuse, 0x8, PT ; @P6 IMAD.MOV.U32 R18, RZ, RZ, R5.reuse ; ISETP.EQ.AND P6, PT, R4, 0xc, PT ; IMAD.SHL.U32 R4, R31, 0x8, RZ ; @P2 IMAD.MOV.U32 R16, RZ, RZ, R5.reuse ; @P3 IMAD.MOV.U32 R14, RZ, RZ, R5 ; LOP3.LUT R4, R4, 0x18, RZ, 0xc0, !PT ; @P4 IMAD.MOV.U32 R29, RZ, RZ, R19 ; LOP3.LUT R5, R28, 0xfffffffc, RZ, 0xc0, !PT ; @P5 IMAD.MOV.U32 R29, RZ, RZ, R18 ; SHF.L.U32 R4, R25, R4, RZ ; @P1 IMAD.MOV.U32 R29, RZ, RZ, R16 ; ISETP.EQ.AND P2, PT, R5.reuse, RZ, PT ; @P6 IMAD.MOV.U32 R29, RZ, RZ, R14 ; ISETP.EQ.AND P3, PT, R5, 0x4, PT ; LOP3.LUT R4, R4, R29, RZ, 0xfc, !PT ; @P1 IMAD.MOV.U32 R16, RZ, RZ, R4.reuse ; IADD3 R21, P1, R21, 0x4, RZ ; @P4 IMAD.MOV.U32 R19, RZ, RZ, R4.reuse ; ISETP.EQ.AND P4, PT, R5.reuse, 0x8, PT ; @P5 IMAD.MOV.U32 R18, RZ, RZ, R4.reuse ; ISETP.EQ.AND P5, PT, R5, 0xc, PT ; IMAD.X R23, RZ, RZ, R23, P1 ; ISETP.GE.U32.AND P1, PT, R21, R26, PT ; IMAD.SHL.U32 R5, R28, 0x8, RZ ; @P6 IMAD.MOV.U32 R14, RZ, RZ, R4 ; ISETP.GE.U32.AND.EX P1, PT, R23, R24, PT, P1 ; @P2 IMAD.MOV.U32 R25, RZ, RZ, R19 ; LOP3.LUT R4, R5, 0x18, RZ, 0xc0, !PT ; @P3 IMAD.MOV.U32 R25, RZ, RZ, R18 ; @P4 IMAD.MOV.U32 R25, RZ, RZ, R16 ; SHF.L.U32 R4, R27, R4, RZ ; @P5 IMAD.MOV.U32 R25, RZ, RZ, R14 ; LOP3.LUT R4, R4, R25, RZ, 0xfc, !PT ; @P2 IMAD.MOV.U32 R19, RZ, RZ, R4.reuse ; @P3 IMAD.MOV.U32 R18, RZ, RZ, R4.reuse ; @P4 IMAD.MOV.U32 R16, RZ, RZ, R4.reuse ; @P5 IMAD.MOV.U32 R14, RZ, RZ, R4 ; @!P1 BRA 0x510 ; BSYNC B2 ; IADD3 R4, P3, -R21, R12, RZ ; BSSY B2, 0xd70 ; ISETP.GT.U32.AND P2, PT, R12, R21, PT ; ISETP.LE.U32.AND P1, PT, R4, 0x1, PT ; IMAD.X R4, R10.reuse, 0x1, ~R23, P3 ; ISETP.GT.U32.AND.EX P2, PT, R10, R23, PT, P2 ; ISETP.LE.U32.OR.EX P1, PT, R4, RZ, !P2, P1 ; @P1 BRA 0xd60 ; IADD3 R4, P0, R21, R20, RZ ; IMAD.X R5, R23, 0x1, R22, P0 ; LDG.E.U8 R24, [R4.64] ; LDG.E.U8 R26, [R4.64+0x1] ; LOP3.LUT R25, R21.reuse, 0xfffffffc, RZ, 0xc0, !PT ; IMAD.SHL.U32 R28, R21.reuse, 0x8, RZ ; IADD3 R27, R21, 0x1, RZ ; ISETP.EQ.AND P4, PT, R25.reuse, RZ, PT ; ISETP.EQ.AND P0, PT, R25, 0x4, PT ; ISETP.EQ.AND P5, PT, R25.reuse, 0x8, PT ; ISETP.EQ.AND P6, PT, R25, 0xc, PT ; LOP3.LUT R29, R28, 0x18, RZ, 0xc0, !PT ; LOP3.LUT R4, R27, 0xfffffffc, RZ, 0xc0, !PT ; @P4 IMAD.MOV.U32 R25, RZ, RZ, R19 ; ISETP.EQ.AND P1, PT, R4.reuse, RZ, PT ; @P0 IMAD.MOV.U32 R25, RZ, RZ, R18 ; ISETP.EQ.AND P2, PT, R4.reuse, 0x4, PT ; @P5 IMAD.MOV.U32 R25, RZ, RZ, R16 ; ISETP.EQ.AND P3, PT, R4, 0x8, PT ; @P6 IMAD.MOV.U32 R25, RZ, RZ, R14 ; SHF.L.U32 R24, R24, R29, RZ ; LOP3.LUT R24, R24, R25, RZ, 0xfc, !PT ; @P4 IMAD.MOV.U32 R19, RZ, RZ, R24.reuse ; ISETP.EQ.AND P4, PT, R4, 0xc, PT ; IMAD.SHL.U32 R4, R27, 0x8, RZ ; @P0 IMAD.MOV.U32 R18, RZ, RZ, R24.reuse ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; @P5 IMAD.MOV.U32 R16, RZ, RZ, R24.reuse ; LOP3.LUT R5, R4, 0x18, RZ, 0xc0, !PT ; @P6 IMAD.MOV.U32 R14, RZ, RZ, R24 ; IADD3 R21, P5, R21, 0x2, RZ ; @P1 IMAD.MOV.U32 R28, RZ, RZ, R19 ; SHF.L.U32 R5, R26, R5, RZ ; @P2 IMAD.MOV.U32 R28, RZ, RZ, R18 ; @P3 IMAD.MOV.U32 R28, RZ, RZ, R16 ; @P4 IMAD.MOV.U32 R28, RZ, RZ, R14 ; IMAD.X R23, RZ, RZ, R23, P5 ; LOP3.LUT R5, R5, R28, RZ, 0xfc, !PT ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R5.reuse ; @P2 IMAD.MOV.U32 R18, RZ, RZ, R5.reuse ; @P3 IMAD.MOV.U32 R16, RZ, RZ, R5.reuse ; @P4 IMAD.MOV.U32 R14, RZ, RZ, R5 ; BSYNC B2 ; ISETP.LT.U32.AND P1, PT, R21, R12, PT ; BSSY B2, 0xf00 ; ISETP.LT.U32.OR.EX P0, PT, R23, R10, P0, P1 ; @!P0 BRA 0xef0 ; IADD3 R4, P0, R21, R20, RZ ; IMAD.X R5, R23, 0x1, R22, P0 ; LDG.E.U8 R4, [R4.64] ; LOP3.LUT R10, R21.reuse, 0xfffffffc, RZ, 0xc0, !PT ; IMAD.SHL.U32 R21, R21, 0x8, RZ ; ISETP.EQ.AND P0, PT, R10.reuse, RZ, PT ; ISETP.EQ.AND P1, PT, R10.reuse, 0x4, PT ; ISETP.EQ.AND P2, PT, R10.reuse, 0x8, PT ; ISETP.EQ.AND P3, PT, R10, 0xc, PT ; LOP3.LUT R21, R21, 0x18, RZ, 0xc0, !PT ; @P0 IMAD.MOV.U32 R23, RZ, RZ, R19 ; @P1 IMAD.MOV.U32 R23, RZ, RZ, R18 ; @P2 IMAD.MOV.U32 R23, RZ, RZ, R16 ; @P3 IMAD.MOV.U32 R23, RZ, RZ, R14 ; SHF.L.U32 R4, R4, R21, RZ ; LOP3.LUT R4, R4, R23, RZ, 0xfc, !PT ; @P0 IMAD.MOV.U32 R19, RZ, RZ, R4.reuse ; @P1 IMAD.MOV.U32 R18, RZ, RZ, R4.reuse ; @P2 IMAD.MOV.U32 R16, RZ, RZ, R4.reuse ; @P3 IMAD.MOV.U32 R14, RZ, RZ, R4 ; BSYNC B2 ; BSYNC B0 ; LDG.E R3, [R2.64+0x10] ; IMAD R12, R11, R0.reuse, RZ ; IMAD R10, R13, R0.reuse, RZ ; IMAD R5, R15, R0, RZ ; IMAD R12, R13, R6.reuse, R12 ; IMAD R10, R15, R6.reuse, R10 ; IMAD R5, R17, R6, R5 ; IMAD R12, R15, R7, R12 ; IMAD.IADD R5, R5, 0x1, R18 ; IMAD R4, R0, R3, RZ ; IMAD R0, R17, R0, R19 ; IMAD R4, R11, R6, R4 ; IMAD R11, R17, R7, R10 ; LEA.HI R6, R0.reuse, R5, RZ, 0x6 ; IMAD R4, R13, R7, R4 ; LOP3.LUT R0, R0, 0x3ffffff, RZ, 0xc0, !PT ; IMAD R3, R17, R8, R12 ; IMAD.IADD R11, R11, 0x1, R16 ; IMAD R4, R15, R8, R4 ; IMAD.IADD R3, R3, 0x1, R14 ; LEA.HI R2, R6.reuse, R11, RZ, 0x6 ; IMAD.IADD R4, R17, 0x1, R4 ; LOP3.LUT R6, R6, 0x3ffffff, RZ, 0xc0, !PT ; LEA.HI R3, R2.reuse, R3, RZ, 0x6 ; LOP3.LUT R7, R2, 0x3ffffff, RZ, 0xc0, !PT ; LEA.HI R10, R3, R4, RZ, 0x6 ; LOP3.LUT R8, R3, 0x3ffffff, RZ, 0xc0, !PT ; BSYNC B1 ; IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; ISETP.NE.AND P1, PT, R9, RZ, PT ; ISETP.LE.U32.AND P0, PT, R2, c[0x0][0x0], PT ; @!P0 BRA 0x1210 ; IMAD.SHL.U32 R2, R9, 0x4, RZ ; IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; ISETP.GE.U32.AND P2, PT, R9, R3, PT ; @!P2 IMAD R4, R3.reuse, 0x4, R2 ; IMAD.SHL.U32 R3, R3, 0x2, RZ ; @!P2 LDS R5, [R4] ; BAR.SYNC 0x0 ; ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x0], PT ; @!P2 IMAD.IADD R10, R10, 0x1, R5 ; @!P2 IMAD.IADD R0, R0, 0x1, R5.reuse ; @!P2 IMAD.IADD R6, R6, 0x1, R5.reuse ; @!P2 STS [R9.X4], R10 ; @!P2 IMAD.IADD R7, R7, 0x1, R5.reuse ; @!P2 IMAD.IADD R8, R8, 0x1, R5 ; BAR.SYNC 0x0 ; @!P0 BRA 0x1130 ; @P1 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; STG.E [R2.64], R0 ; STG.E [R2.64+0x4], R6 ; STG.E [R2.64+0x8], R7 ; STG.E [R2.64+0xc], R8 ; EXIT ; BRA 0x1290; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15poly1305_kernelPKhPhS0_m ; -- Begin function _Z15poly1305_kernelPKhPhS0_m .globl _Z15poly1305_kernelPKhPhS0_m .p2align 8 .type _Z15poly1305_kernelPKhPhS0_m,@function _Z15poly1305_kernelPKhPhS0_m: ; @_Z15poly1305_kernelPKhPhS0_m ; %bb.0: s_clause 0x1 s_load_b256 s[4:11], s[0:1], 0x0 s_load_b32 s12, s[0:1], 0x2c s_mov_b32 s16, 1 s_mov_b32 s21, exec_lo s_waitcnt lgkmcnt(0) s_load_b128 s[0:3], s[8:9], 0x0 s_and_b32 s20, s12, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[5:6], null, s15, s20, v[0:1] s_waitcnt lgkmcnt(0) s_and_b32 s12, s0, 0xffffff s_and_b32 s13, s1, 0xffffff s_and_b32 s14, s2, 0xffffff s_and_b32 s15, s3, 0xffffff v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_lshlrev_b64 v[7:8], 4, v[5:6] v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13 v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, s15 v_mov_b32_e32 v5, s16 v_cmpx_gt_u64_e64 s[10:11], v[7:8] s_cbranch_execz .LBB0_13 ; %bb.1: ; %.lr.ph v_sub_co_u32 v1, vcc_lo, s10, v7 v_sub_co_ci_u32_e32 v2, vcc_lo, s11, v8, vcc_lo v_mov_b32_e32 v9, v6 s_mov_b32 s16, 0 s_mov_b64 s[10:11], 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 16, v[1:2] v_mov_b32_e32 v10, v6 v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 16, v1 v_cmp_lt_u64_e32 vcc_lo, 1, v[1:2] v_cndmask_b32_e32 v3, 1, v1, vcc_lo v_add_co_u32 v1, vcc_lo, s4, v7 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v8, vcc_lo v_mov_b32_e32 v8, v6 v_mov_b32_e32 v7, v6 v_lshlrev_b32_e32 v5, 3, v3 s_mov_b64 s[4:5], 0 .LBB0_2: ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v3, vcc_lo, v1, s10 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo s_and_b32 s3, s4, 24 global_load_u8 v3, v[3:4], off v_alignbit_b32 v4, s11, s10, 2 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_add_u32 s4, s4, 8 s_addc_u32 s5, s5, 0 v_cmp_eq_u32_e32 vcc_lo, 1, v4 v_cmp_eq_u32_e64 s0, 2, v4 v_cmp_eq_u32_e64 s1, 3, v4 v_cmp_eq_u64_e64 s2, s[4:5], v[5:6] v_cndmask_b32_e32 v11, v7, v8, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s16, s2, s16 v_cndmask_b32_e64 v11, v11, v9, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v11, v11, v10, s1 s_waitcnt vmcnt(0) v_lshl_or_b32 v3, v3, s3, v11 v_cmp_eq_u32_e64 s3, 0, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v8, v8, v3, vcc_lo v_cndmask_b32_e64 v10, v10, v3, s1 v_cndmask_b32_e64 v9, v9, v3, s0 v_cndmask_b32_e64 v7, v7, v3, s3 s_and_not1_b32 exec_lo, exec_lo, s16 s_cbranch_execnz .LBB0_2 ; %bb.3: ; %.preheader51.i.preheader s_or_b32 exec_lo, exec_lo, s16 s_mov_b32 s0, 0 s_mov_b64 s[10:11], 0 s_mov_b32 s1, s0 s_mov_b32 s2, s0 s_mov_b32 s3, s0 s_mov_b32 s4, s0 .LBB0_4: ; %.preheader51.i ; =>This Loop Header: Depth=1 ; Child Loop BB0_5 Depth 2 s_cmp_eq_u32 s10, 1 s_mov_b64 s[16:17], s[8:9] s_cselect_b32 s5, s13, s12 s_cmp_eq_u32 s10, 2 s_mov_b64 s[18:19], 0 s_cselect_b32 s5, s14, s5 s_cmp_eq_u32 s10, 3 s_cselect_b32 s5, s15, s5 s_cmp_eq_u32 s10, 4 s_cselect_b32 s5, 1, s5 .LBB0_5: ; Parent Loop BB0_4 Depth=1 ; => This Inner Loop Header: Depth=2 s_load_b32 s22, s[16:17], 0x0 s_add_i32 s23, s10, s18 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s23, 1 s_cselect_b32 s24, s1, s0 s_cmp_eq_u32 s23, 2 s_cselect_b32 s24, s2, s24 s_cmp_eq_u32 s23, 3 s_cselect_b32 s24, s3, s24 s_cmp_eq_u32 s23, 4 s_cselect_b32 s24, s4, s24 s_waitcnt lgkmcnt(0) s_mul_i32 s22, s22, s5 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s22, s22, s24 s_cmp_eq_u32 s23, 3 s_cselect_b32 s3, s22, s3 s_cmp_eq_u32 s23, 4 s_cselect_b32 s4, s22, s4 s_cmp_eq_u32 s23, 2 s_cselect_b32 s2, s22, s2 s_cmp_eq_u32 s23, 1 s_cselect_b32 s1, s22, s1 s_cmp_eq_u32 s23, 0 s_cselect_b32 s0, s22, s0 s_add_u32 s18, s18, 1 s_addc_u32 s19, s19, 0 s_add_u32 s16, s16, 4 s_addc_u32 s17, s17, 0 s_cmp_eq_u32 s18, 5 s_cbranch_scc0 .LBB0_5 ; %bb.6: ; in Loop: Header=BB0_4 Depth=1 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s10, 5 s_cbranch_scc1 .LBB0_4 ; %bb.7: ; %.preheader50.i.preheader v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v4, s3 v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v2, s1 v_mov_b32_e32 v1, s0 s_mov_b64 s[4:5], 0 .LBB0_8: ; %.preheader50.i ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s4, 1 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s4, 2 v_dual_cndmask_b32 v6, v1, v2 :: v_dual_cndmask_b32 v11, v7, v8 s_cselect_b32 s0, -1, 0 s_cmp_eq_u32 s4, 3 s_cselect_b32 s1, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v6, v6, v3, s0 v_cndmask_b32_e64 v11, v11, v9, s0 s_cmp_eq_u32 s4, 4 s_cselect_b32 s2, -1, 0 v_cndmask_b32_e64 v6, v6, v4, s1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v11, v11, v10, s1 s_cmp_eq_u32 s4, 0 s_cselect_b32 s3, -1, 0 v_cndmask_b32_e64 v6, v6, v5, s2 s_add_u32 s4, s4, 1 s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s4, 4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v6, v11, v6 v_cndmask_b32_e64 v5, v5, v6, s2 v_cndmask_b32_e64 v4, v4, v6, s1 v_cndmask_b32_e64 v3, v3, v6, s0 v_cndmask_b32_e32 v2, v2, v6, vcc_lo v_cndmask_b32_e64 v1, v1, v6, s3 s_cbranch_scc1 .LBB0_8 ; %bb.9: ; %.preheader49.i.preheader v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13 v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, s15 v_mov_b32_e32 v10, 1 s_mov_b64 s[4:5], 0 .LBB0_10: ; %.preheader49.i ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s4, 1 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s4, 2 v_cndmask_b32_e32 v11, v1, v2, vcc_lo s_cselect_b32 s0, -1, 0 s_cmp_eq_u32 s4, 3 s_cselect_b32 s1, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v11, v11, v3, s0 s_cmp_eq_u32 s4, 4 s_cselect_b32 s2, -1, 0 s_cmp_eq_u32 s4, 0 v_cndmask_b32_e64 v11, v11, v4, s1 s_cselect_b32 s3, -1, 0 s_add_u32 s4, s4, 1 s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s4, 5 v_cndmask_b32_e64 v11, v11, v5, s2 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v10, v10, v11, s2 v_cndmask_b32_e64 v9, v9, v11, s1 v_cndmask_b32_e64 v8, v8, v11, s0 v_cndmask_b32_e32 v7, v7, v11, vcc_lo v_cndmask_b32_e64 v6, v6, v11, s3 s_cbranch_scc1 .LBB0_10 ; %bb.11: ; %.preheader.preheader.i s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v2, v7 v_dual_mov_b32 v3, v8 :: v_dual_mov_b32 v4, v9 v_mov_b32_e32 v5, v10 s_mov_b64 s[8:9], 0 .LBB0_12: ; %.preheader.i ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s8, 4 v_lshrrev_b32_e32 v7, 26, v6 v_and_b32_e32 v6, 0x3ffffff, v6 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s8, 3 s_cselect_b32 s0, -1, 0 s_cmp_eq_u32 s8, 2 v_cndmask_b32_e32 v5, v5, v6, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s8, 1 v_cndmask_b32_e32 v3, v3, v6, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s8, 0 v_cndmask_b32_e32 v2, v2, v6, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_add_u32 s8, s8, 1 v_cndmask_b32_e32 v1, v1, v6, vcc_lo s_addc_u32 s9, s9, 0 s_cmp_eq_u32 s8, 1 v_cndmask_b32_e64 v4, v4, v6, s0 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s8, 2 v_cndmask_b32_e32 v6, v1, v2, vcc_lo s_cselect_b32 s0, -1, 0 s_cmp_eq_u32 s8, 3 s_cselect_b32 s1, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v6, v6, v3, s0 s_cmp_eq_u32 s8, 4 s_cselect_b32 s2, -1, 0 s_cmp_eq_u32 s8, 0 v_cndmask_b32_e64 v6, v6, v4, s1 s_cselect_b32 s3, -1, 0 s_and_b32 s4, exec_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v6, v6, v5, s2 v_add_nc_u32_e32 v6, v6, v7 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v5, v5, v6, s2 v_cndmask_b32_e64 v4, v4, v6, s1 v_cndmask_b32_e64 v3, v3, v6, s0 v_cndmask_b32_e32 v2, v2, v6, vcc_lo v_cndmask_b32_e64 v1, v1, v6, s3 s_mov_b32 vcc_lo, s4 s_cbranch_vccz .LBB0_12 .LBB0_13: ; %Flow156 s_or_b32 exec_lo, exec_lo, s21 s_cmp_lt_u32 s20, 2 s_cbranch_scc1 .LBB0_21 ; %bb.14: ; %.lr.ph72 v_lshl_add_u32 v6, v0, 2, 0 s_mov_b32 s5, 1 .LBB0_15: ; =>This Loop Header: Depth=1 ; Child Loop BB0_17 Depth 2 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s5, v0 s_and_saveexec_b32 s10, vcc_lo s_cbranch_execz .LBB0_18 ; %bb.16: ; %.preheader58 ; in Loop: Header=BB0_15 Depth=1 v_lshl_add_u32 v7, s5, 2, v6 s_mov_b64 s[8:9], 0 ds_load_b32 v7, v7 .LBB0_17: ; Parent Loop BB0_15 Depth=1 ; => This Inner Loop Header: Depth=2 s_cmp_eq_u32 s8, 1 s_cselect_b32 s0, -1, 0 s_cmp_eq_u32 s8, 2 v_cndmask_b32_e64 v8, v1, v2, s0 s_cselect_b32 s1, -1, 0 s_cmp_eq_u32 s8, 3 s_cselect_b32 s2, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v8, v8, v3, s1 s_cmp_eq_u32 s8, 4 s_cselect_b32 s3, -1, 0 s_cmp_eq_u32 s8, 0 v_cndmask_b32_e64 v8, v8, v4, s2 s_cselect_b32 s4, -1, 0 s_add_u32 s8, s8, 1 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s8, 5 v_cndmask_b32_e64 v8, v8, v5, s3 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v8, v7, v8 v_cndmask_b32_e64 v5, v5, v8, s3 v_cndmask_b32_e64 v4, v4, v8, s2 v_cndmask_b32_e64 v3, v3, v8, s1 v_cndmask_b32_e64 v2, v2, v8, s0 v_cndmask_b32_e64 v1, v1, v8, s4 s_cbranch_scc1 .LBB0_17 .LBB0_18: ; %Flow152 ; in Loop: Header=BB0_15 Depth=1 s_or_b32 exec_lo, exec_lo, s10 s_barrier buffer_gl0_inv s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB0_20 ; %bb.19: ; %.preheader56.preheader ; in Loop: Header=BB0_15 Depth=1 ds_store_b32 v6, v5 .LBB0_20: ; in Loop: Header=BB0_15 Depth=1 s_or_b32 exec_lo, exec_lo, s0 s_lshl_b32 s5, s5, 1 s_waitcnt lgkmcnt(0) s_cmp_ge_u32 s5, s20 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_15 .LBB0_21: ; %._crit_edge s_mov_b32 s0, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_24 ; %bb.22: ; %.preheader.preheader v_mov_b32_e32 v0, 0 s_mov_b64 s[0:1], 0 .LBB0_23: ; %.preheader ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, 1 s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s0, 2 v_cndmask_b32_e32 v6, v1, v2, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s0, 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v6, v6, v3, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_cmp_eq_u32 s0, 4 v_cndmask_b32_e32 v6, v6, v4, vcc_lo s_cselect_b32 vcc_lo, -1, 0 s_add_u32 s0, s0, 1 s_addc_u32 s1, s1, 0 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e32 v6, v6, v5, vcc_lo global_store_b32 v0, v6, s[6:7] s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_lg_u32 s0, 4 s_cbranch_scc1 .LBB0_23 .LBB0_24: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15poly1305_kernelPKhPhS0_m .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 25 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15poly1305_kernelPKhPhS0_m, .Lfunc_end0-_Z15poly1305_kernelPKhPhS0_m ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1584 ; NumSgprs: 27 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 27 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15poly1305_kernelPKhPhS0_m .private_segment_fixed_size: 0 .sgpr_count: 27 .sgpr_spill_count: 0 .symbol: _Z15poly1305_kernelPKhPhS0_m.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00031495_00000000-6_cuda_code_069983.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6838: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6838: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z14poly1305_blockPjPKjS1_ .type _Z14poly1305_blockPjPKjS1_, @function _Z14poly1305_blockPjPKjS1_: .LFB6834: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE6834: .size _Z14poly1305_blockPjPKjS1_, .-_Z14poly1305_blockPjPKjS1_ .globl _Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m .type _Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m, @function _Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m: .LFB6860: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movq %rcx, (%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L4 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z15poly1305_kernelPKhPhS0_m(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L4: movq 136(%rsp), %rax subq %fs:40, %rax je .L6 call __stack_chk_fail@PLT .L6: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6860: .size _Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m, .-_Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m .globl _Z15poly1305_kernelPKhPhS0_m .type _Z15poly1305_kernelPKhPhS0_m, @function _Z15poly1305_kernelPKhPhS0_m: .LFB6861: .cfi_startproc endbr64 jmp _Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m .cfi_endproc .LFE6861: .size _Z15poly1305_kernelPKhPhS0_m, .-_Z15poly1305_kernelPKhPhS0_m .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Hello, Poly1305!" .LC1: .string "12345678901234567890123456789012" .LC2: .string "CUDA error: " .LC3: .string "Poly1305 Tag: " .LC4: .string "%02x" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6835: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $16, %esi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $88, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movl $16, %edx leaq .LC0(%rip), %rsi call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movl $32, %edx leaq .LC1(%rip), %rsi call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d movabsq $4294967297, %rdi salq $8, %rdx movl $1024, %r8d movl $1, %ecx movl $1, %esi movq %rdx, 44(%rsp) movl $1, 52(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L11 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $16, %ecx movq 8(%rsp), %rdi call _Z42__device_stub__Z15poly1305_kernelPKhPhS0_mPKhPhS0_m .L11: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L12 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L10 .L12: movq 16(%rsp), %rsi leaq 56(%rsp), %r12 xorl %ebx, %ebx movl $2, %ecx movl $16, %edx movq %r12, %rdi leaq _ZSt4cout(%rip), %rbp call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movq %rbp, %rdi leaq .LC4(%rip), %r13 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L14: movzbl (%r12,%rbx), %edx movq %r13, %rsi movl $2, %edi xorl %eax, %eax incq %rbx call __printf_chk@PLT cmpq $16, %rbx jne .L14 movq %rbp, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L10: movq 72(%rsp), %rdx subq %fs:40, %rdx je .L15 call __stack_chk_fail@PLT .L15: addq $88, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6835: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z15poly1305_kernelPKhPhS0_m" .LC6: .string "_ZN50_INTERNAL_ba26261a_19_cuda_code_069983_cu_3dcfb91d4cuda3std3__419piecewise_constructE" .LC7: .string "_ZN50_INTERNAL_ba26261a_19_cuda_code_069983_cu_3dcfb91d4cuda3std6ranges3__45__cpo4swapE" .LC8: .string "_ZN50_INTERNAL_ba26261a_19_cuda_code_069983_cu_3dcfb91d4cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6863: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC5(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z15poly1305_kernelPKhPhS0_m(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC6(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6863: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_069983.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__poly1305_kernelPKhPhS0_m # -- Begin function _Z30__device_stub__poly1305_kernelPKhPhS0_m .type _Z30__device_stub__poly1305_kernelPKhPhS0_m,@function _Z30__device_stub__poly1305_kernelPKhPhS0_m: # @_Z30__device_stub__poly1305_kernelPKhPhS0_m .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 16(%rsp), %rdx movq %rcx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15poly1305_kernelPKhPhS0_m, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__poly1305_kernelPKhPhS0_m, .Lfunc_end0-_Z30__device_stub__poly1305_kernelPKhPhS0_m .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $56, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 24(%rsp), %rbx movl $16, %esi movq %rbx, %rdi callq hipMalloc leaq 8(%rsp), %rdi movl $16, %esi callq hipMalloc leaq 16(%rsp), %r14 movl $32, %esi movq %r14, %rdi callq hipMalloc movq (%rbx), %rdi movl $.L.str, %esi movl $16, %edx movl $1, %ecx callq hipMemcpy movq (%r14), %rdi movl $.L.str.1, %esi movl $32, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rdx movl $1024, %r8d # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 24(%rsp), %rdi movq 8(%rsp), %rsi movq 16(%rsp), %rdx movl $16, %ecx callq _Z30__device_stub__poly1305_kernelPKhPhS0_m .LBB1_2: callq hipGetLastError testl %eax, %eax je .LBB1_7 # %bb.3: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_4 # %bb.5: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_6 .LBB1_7: movq 8(%rsp), %rsi leaq 32(%rsp), %rdi movl $16, %edx movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %ebx, %ebx .LBB1_8: # =>This Inner Loop Header: Depth=1 movzbl 32(%rsp,%rbx), %esi movl $.L.str.4, %edi xorl %eax, %eax callq printf incq %rbx cmpq $16, %rbx jne .LBB1_8 # %bb.9: movq _ZSt4cout(%rip), %rax movl $_ZSt4cout, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 24(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_10 .LBB1_4: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_10: addq $56, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15poly1305_kernelPKhPhS0_m, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15poly1305_kernelPKhPhS0_m,@object # @_Z15poly1305_kernelPKhPhS0_m .section .rodata,"a",@progbits .globl _Z15poly1305_kernelPKhPhS0_m .p2align 3, 0x0 _Z15poly1305_kernelPKhPhS0_m: .quad _Z30__device_stub__poly1305_kernelPKhPhS0_m .size _Z15poly1305_kernelPKhPhS0_m, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Hello, Poly1305!" .size .L.str, 17 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "12345678901234567890123456789012" .size .L.str.1, 33 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "CUDA error: " .size .L.str.2, 13 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Poly1305 Tag: " .size .L.str.3, 15 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "%02x" .size .L.str.4, 5 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15poly1305_kernelPKhPhS0_m" .size .L__unnamed_1, 29 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__poly1305_kernelPKhPhS0_m .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15poly1305_kernelPKhPhS0_m .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z13updateWeightsPfS_S_if .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R9, SR_CTAID.X ; MOV R2, c[0x0][0x178] ; S2R R0, SR_TID.X ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; IMAD R9, R9, c[0x0][0x0], R0 ; ISETP.GE.OR P0, PT, R9, c[0x0][0x178], !P0 ; @P0 EXIT ; IADD3 R0, R2, -0x1, RZ ; HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; MOV R10, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; IMAD.WIDE R2, R9, R8, c[0x0][0x168] ; @!P0 BRA 0xe50 ; IADD3 R11, -R0, c[0x0][0x178], RZ ; IMAD R7, R9, c[0x0][0x178], RZ ; MOV R10, RZ ; ISETP.GT.AND P0, PT, R11, RZ, PT ; IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; MOV R4, c[0x0][0x170] ; MOV R5, c[0x0][0x174] ; @!P0 BRA 0xc30 ; ISETP.GT.AND P1, PT, R11, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x860 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64] ; LDG.E R14, [R6.64] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x4] ; STG.E [R6.64], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x4] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x8] ; STG.E [R6.64+0x4], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x8] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0xc] ; STG.E [R6.64+0x8], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0xc] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x10] ; STG.E [R6.64+0xc], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x10] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x14] ; STG.E [R6.64+0x10], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x14] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0x18] ; STG.E [R6.64+0x14], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0x18] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x1c] ; STG.E [R6.64+0x18], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x1c] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x20] ; STG.E [R6.64+0x1c], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x20] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0x24] ; STG.E [R6.64+0x20], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0x24] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x28] ; STG.E [R6.64+0x24], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x28] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x2c] ; STG.E [R6.64+0x28], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x2c] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0x30] ; STG.E [R6.64+0x2c], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0x30] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x34] ; STG.E [R6.64+0x30], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x34] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x38] ; STG.E [R6.64+0x34], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x38] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0x3c] ; STG.E [R6.64+0x38], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0x3c] ; IADD3 R11, R11, -0x10, RZ ; ISETP.GT.AND P1, PT, R11, 0xc, PT ; IADD3 R4, P3, R4, 0x40, RZ ; IADD3 R10, R10, 0x10, RZ ; IADD3.X R5, RZ, R5, RZ, P3, !PT ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; IADD3 R12, P2, R6, 0x40, RZ ; IADD3.X R15, RZ, R7, RZ, P2, !PT ; STG.E [R6.64+0x3c], R13 ; MOV R6, R12 ; MOV R7, R15 ; @P1 BRA 0x1c0 ; ISETP.GT.AND P1, PT, R11, 0x4, PT ; @!P1 BRA 0xc10 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64] ; LDG.E R14, [R6.64] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x4] ; STG.E [R6.64], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x4] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x8] ; STG.E [R6.64+0x4], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x8] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0xc] ; STG.E [R6.64+0x8], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0xc] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x10] ; STG.E [R6.64+0xc], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x10] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x14] ; STG.E [R6.64+0x10], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x14] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0x18] ; STG.E [R6.64+0x14], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0x18] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x1c] ; STG.E [R6.64+0x18], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x1c] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R10, R10, 0x8, RZ ; IADD3 R11, R11, -0x8, RZ ; IADD3 R4, P2, R4, 0x20, RZ ; IADD3.X R5, RZ, R5, RZ, P2, !PT ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; IADD3 R12, P1, R6, 0x20, RZ ; IADD3.X R17, RZ, R7, RZ, P1, !PT ; STG.E [R6.64+0x1c], R15 ; MOV R6, R12 ; MOV R7, R17 ; ISETP.NE.OR P0, PT, R11, RZ, P0 ; @!P0 BRA 0xe50 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64] ; LDG.E R14, [R6.64] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; LDG.E R14, [R6.64+0x4] ; STG.E [R6.64], R13 ; LDG.E R12, [R2.64] ; LDG.E R15, [R4.64+0x4] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R15, -R12, R15, R14 ; LDG.E R14, [R6.64+0x8] ; STG.E [R6.64+0x4], R15 ; LDG.E R12, [R2.64] ; LDG.E R17, [R4.64+0x8] ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R17, -R12, R17, R14 ; LDG.E R14, [R6.64+0xc] ; STG.E [R6.64+0x8], R17 ; LDG.E R12, [R2.64] ; LDG.E R13, [R4.64+0xc] ; IADD3 R11, R11, -0x4, RZ ; ISETP.NE.AND P0, PT, R11, RZ, PT ; IADD3 R4, P2, R4, 0x10, RZ ; IADD3 R10, R10, 0x4, RZ ; IADD3.X R5, RZ, R5, RZ, P2, !PT ; FMUL R12, R12, c[0x0][0x17c] ; FFMA R13, -R12, R13, R14 ; IADD3 R12, P1, R6, 0x10, RZ ; IADD3.X R15, RZ, R7, RZ, P1, !PT ; STG.E [R6.64+0xc], R13 ; MOV R6, R12 ; MOV R7, R15 ; @P0 BRA 0xc30 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; IMAD R9, R9, c[0x0][0x178], R10 ; IMAD.WIDE R10, R10, R8, c[0x0][0x170] ; IMAD.WIDE R8, R9, R8, c[0x0][0x160] ; MOV R12, R8 ; MOV R13, R9 ; MOV R7, R11 ; LDG.E R8, [R2.64] ; MOV R4, R12 ; MOV R5, R13 ; MOV R6, R10 ; LDG.E R9, [R4.64] ; LDG.E R7, [R6.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IADD3 R10, P2, R10, 0x4, RZ ; IADD3 R12, P1, R4, 0x4, RZ ; IADD3.X R11, RZ, R11, RZ, P2, !PT ; IADD3.X R13, RZ, R5, RZ, P1, !PT ; FMUL R8, R8, c[0x0][0x17c] ; FFMA R9, -R8, R7, R9 ; STG.E [R4.64], R9 ; @P0 BRA 0xec0 ; EXIT ; BRA 0xfe0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z16computeGradientsPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R6, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R3, [R2.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; FADD R0, -R4, R3 ; FADD R9, -R3.reuse, 1 ; FMUL R0, R3, R0 ; FMUL R9, R0, R9 ; STG.E [R6.64], R9 ; EXIT ; BRA 0x130; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z11forwardPassPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; BSSY B0, 0xc40 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; @P0 BRA 0xc30 ; S2R R0, SR_CTAID.Y ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; HFMA2.MMA R15, -RZ, RZ, 0, 0 ; ISETP.GE.AND P0, PT, R6, 0x1, PT ; @!P0 BRA 0xa90 ; IADD3 R2, R6.reuse, -0x1, RZ ; IMAD.MOV.U32 R15, RZ, RZ, RZ ; LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; @!P0 BRA 0x940 ; IADD3 R8, -R6, c[0x0][0x178], RZ ; IMAD R4, R0, c[0x0][0x178], RZ ; MOV R5, 0x4 ; IMAD.MOV.U32 R15, RZ, RZ, RZ ; ISETP.GT.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; MOV R2, c[0x0][0x160] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; @!P0 BRA 0x7b0 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x570 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R16, [R4.64] ; LDG.E R17, [R2.64] ; LDG.E R18, [R4.64+0x4] ; LDG.E R25, [R2.64+0x4] ; LDG.E R19, [R4.64+0x8] ; LDG.E R20, [R2.64+0x8] ; LDG.E R22, [R4.64+0xc] ; LDG.E R21, [R2.64+0xc] ; LDG.E R23, [R4.64+0x10] ; LDG.E R24, [R2.64+0x10] ; LDG.E R9, [R4.64+0x14] ; LDG.E R10, [R2.64+0x14] ; LDG.E R11, [R4.64+0x18] ; LDG.E R12, [R2.64+0x18] ; LDG.E R13, [R4.64+0x1c] ; LDG.E R14, [R2.64+0x1c] ; FFMA R17, R16, R17, R15 ; LDG.E R15, [R4.64+0x20] ; LDG.E R16, [R2.64+0x20] ; FFMA R25, R18, R25, R17 ; LDG.E R17, [R4.64+0x24] ; LDG.E R18, [R2.64+0x24] ; FFMA R25, R19, R20, R25 ; LDG.E R19, [R4.64+0x28] ; LDG.E R20, [R2.64+0x28] ; FFMA R25, R22, R21, R25 ; LDG.E R21, [R4.64+0x2c] ; LDG.E R22, [R2.64+0x2c] ; FFMA R25, R23, R24, R25 ; LDG.E R23, [R4.64+0x30] ; LDG.E R24, [R2.64+0x30] ; FFMA R25, R9, R10, R25 ; LDG.E R9, [R4.64+0x34] ; LDG.E R10, [R2.64+0x34] ; FFMA R25, R11, R12, R25 ; LDG.E R11, [R4.64+0x38] ; LDG.E R12, [R2.64+0x38] ; FFMA R25, R13, R14, R25 ; LDG.E R13, [R4.64+0x3c] ; LDG.E R14, [R2.64+0x3c] ; IADD3 R8, R8, -0x10, RZ ; IADD3 R7, R7, 0x10, RZ ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; IADD3 R4, P2, R4, 0x40, RZ ; IADD3 R2, P3, R2, 0x40, RZ ; IMAD.X R5, RZ, RZ, R5, P2 ; IADD3.X R3, RZ, R3, RZ, P3, !PT ; FFMA R15, R15, R16, R25 ; FFMA R15, R17, R18, R15 ; FFMA R15, R19, R20, R15 ; FFMA R15, R21, R22, R15 ; FFMA R15, R23, R24, R15 ; FFMA R9, R9, R10, R15 ; FFMA R9, R11, R12, R9 ; FFMA R15, R13, R14, R9 ; @P1 BRA 0x1e0 ; ISETP.GT.AND P1, PT, R8, 0x4, PT ; @!P1 BRA 0x790 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R16, [R4.64] ; LDG.E R17, [R2.64] ; LDG.E R19, [R4.64+0x4] ; LDG.E R18, [R2.64+0x4] ; LDG.E R21, [R4.64+0x8] ; LDG.E R20, [R2.64+0x8] ; LDG.E R23, [R4.64+0xc] ; LDG.E R22, [R2.64+0xc] ; LDG.E R25, [R4.64+0x10] ; LDG.E R24, [R2.64+0x10] ; LDG.E R13, [R4.64+0x14] ; LDG.E R14, [R2.64+0x14] ; LDG.E R11, [R4.64+0x18] ; LDG.E R12, [R2.64+0x18] ; LDG.E R9, [R4.64+0x1c] ; LDG.E R10, [R2.64+0x1c] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R7, R7, 0x8, RZ ; IADD3 R8, R8, -0x8, RZ ; IADD3 R4, P1, R4, 0x20, RZ ; IADD3 R2, P2, R2, 0x20, RZ ; IMAD.X R5, RZ, RZ, R5, P1 ; IMAD.X R3, RZ, RZ, R3, P2 ; FFMA R16, R16, R17, R15 ; FFMA R16, R19, R18, R16 ; FFMA R16, R21, R20, R16 ; FFMA R16, R23, R22, R16 ; FFMA R16, R25, R24, R16 ; FFMA R13, R13, R14, R16 ; FFMA R11, R11, R12, R13 ; FFMA R15, R9, R10, R11 ; ISETP.NE.OR P0, PT, R8, RZ, P0 ; @!P0 BRA 0x940 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R10, [R4.64] ; LDG.E R9, [R2.64] ; LDG.E R12, [R4.64+0x4] ; LDG.E R11, [R2.64+0x4] ; LDG.E R14, [R4.64+0x8] ; LDG.E R13, [R2.64+0x8] ; LDG.E R16, [R4.64+0xc] ; LDG.E R17, [R2.64+0xc] ; IADD3 R8, R8, -0x4, RZ ; IADD3 R7, R7, 0x4, RZ ; ISETP.NE.AND P0, PT, R8, RZ, PT ; FFMA R9, R10, R9, R15 ; IADD3 R10, P2, R2, 0x10, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; FFMA R9, R12, R11, R9 ; IADD3 R12, P1, R4, 0x10, RZ ; IMAD.X R11, RZ, RZ, R3, P2 ; IMAD.MOV.U32 R4, RZ, RZ, R12 ; MOV R3, R11 ; FFMA R9, R14, R13, R9 ; IADD3.X R13, RZ, R5, RZ, P1, !PT ; MOV R5, R13 ; FFMA R15, R16, R17, R9 ; @P0 BRA 0x7b0 ; ISETP.NE.AND P0, PT, R6, RZ, PT ; @!P0 BRA 0xa90 ; IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; IMAD R2, R0, c[0x0][0x178], R7 ; IMAD.WIDE R2, R2, R4, c[0x0][0x168] ; IMAD.WIDE R4, R7, R4, c[0x0][0x160] ; MOV R8, R2 ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; MOV R2, R8 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R2, [R2.64] ; LDG.E R4, [R4.64] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R7, P2, R7, 0x4, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; IADD3 R8, P1, R8, 0x4, RZ ; IMAD.X R5, RZ, RZ, R5, P2 ; IADD3.X R3, RZ, R3, RZ, P1, !PT ; FFMA R15, R2, R4, R15 ; @P0 BRA 0x9c0 ; MOV R2, 0x3bbb989d ; IMAD.MOV.U32 R3, RZ, RZ, 0x437c0000 ; FFMA.SAT R2, -R15, R2, 0.5 ; FFMA.RM R2, R2, R3, 12582913 ; FADD R4, R2.reuse, -12583039 ; SHF.L.U32 R2, R2, 0x17, RZ ; FFMA R4, -R15, 1.4426950216293334961, -R4 ; FFMA R4, -R15, 1.925963033500011079e-08, R4 ; MUFU.EX2 R3, R4 ; FFMA R6, R2, R3, 1 ; IADD3 R2, R6, 0x1800000, RZ ; LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; @P0 BRA 0xbb0 ; MOV R2, 0xb90 ; CALL.REL.NOINC 0xc60 ; IMAD.MOV.U32 R5, RZ, RZ, R4 ; BRA 0xbf0 ; MUFU.RCP R5, R6 ; FFMA R2, R6, R5, -1 ; FADD.FTZ R2, -R2, -RZ ; FFMA R5, R5, R2, R5 ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; STG.E [R2.64], R5 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; EXIT ; IMAD.SHL.U32 R3, R6, 0x2, RZ ; SHF.R.U32.HI R9, RZ, 0x18, R3 ; MOV R3, R6 ; ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; @P0 BRA 0xd60 ; IMAD.SHL.U32 R4, R3, 0x2, RZ ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 MUFU.RCP R4, R3 ; @!P0 BRA 0xf80 ; FFMA R3, R3, 1.84467440737095516160e+19, RZ ; MUFU.RCP R4, R3 ; FFMA R5, R3, R4, -1 ; FADD.FTZ R5, -R5, -RZ ; FFMA R4, R4, R5, R4 ; FFMA R4, R4, 1.84467440737095516160e+19, RZ ; BRA 0xf80 ; IADD3 R11, R9, -0xfd, RZ ; ISETP.GT.U32.AND P0, PT, R11, 0x1, PT ; @P0 BRA 0xf70 ; LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; HFMA2.MMA R8, -RZ, RZ, 0, 1.78813934326171875e-07 ; LOP3.LUT R4, R4, 0x3f800000, RZ, 0xfc, !PT ; MUFU.RCP R5, R4 ; SHF.L.U32 R8, R8, R11, RZ ; FFMA R6, R4, R5, -1 ; FADD.FTZ R6, -R6, -RZ ; FFMA.RM R7, R5.reuse, R6.reuse, R5.reuse ; FFMA.RP R6, R5, R6, R5 ; LOP3.LUT R5, R7.reuse, 0x7fffff, RZ, 0xc0, !PT ; FSETP.NEU.FTZ.AND P0, PT, R7, R6, PT ; LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; SEL R6, RZ, 0xffffffff, !P0 ; LOP3.LUT R8, R8, R5, RZ, 0xc0, !PT ; IMAD.MOV R6, RZ, RZ, -R6 ; SHF.R.U32.HI R8, RZ, R11, R8 ; LOP3.LUT P1, RZ, R6, R11, R5, 0xf8, !PT ; LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; SEL R4, RZ, 0x1, !P0 ; IADD3 R4, -R4, RZ, RZ ; ISETP.GE.AND P0, PT, R4, RZ, PT ; IADD3 R4, R9, -0xfc, RZ ; SHF.R.U32.HI R4, RZ, R4, R5 ; @!P0 IADD3 R4, R4, 0x1, RZ ; @!P1 IMAD.SHL.U32 R4, R4, 0x2, RZ ; LOP3.LUT R4, R4, 0x80000000, R3, 0xf8, !PT ; BRA 0xf80 ; MUFU.RCP R4, R3 ; MOV R3, 0x0 ; RET.REL.NODEC R2 0x0 ; BRA 0xfa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z17initializeWeightsPfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; @P0 EXIT ; ULDC.64 UR4, c[0x0][0x118] ; CS2R R2, SR_CLOCKLO ; IADD3 R0, P0, R5, R2, RZ ; LOP3.LUT R0, R0, 0xaad26b49, RZ, 0x3c, !PT ; LEA.HI.X.SX32 R3, R5, R3, 0x1, P0 ; IMAD R0, R0, 0x4182bed5, RZ ; LOP3.LUT R3, R3, 0xf7dcefdd, RZ, 0x3c, !PT ; IADD3 R2, R0.reuse, 0x75bcd15, RZ ; IMAD R3, R3, -0x658354e5, R0 ; IADD3 R4, R0, 0x583f19, RZ ; SHF.R.U32.HI R7, RZ, 0x2, R2 ; IMAD.SHL.U32 R6, R4, 0x10, RZ ; LOP3.LUT R7, R7, R2, RZ, 0x3c, !PT ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; LOP3.LUT R6, R7.reuse, R6, R4, 0x96, !PT ; IMAD.SHL.U32 R7, R7, 0x2, RZ ; LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; IADD3 R6, R3, 0x6a788e, R6 ; IMAD.MOV.U32 R3, RZ, RZ, 0x2f800000 ; I2F.U32 R6, R6 ; FFMA R0, R6, R3, 1.1641532182693481445e-10 ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; FMUL R5, R0, 0.0099999997764825820923 ; STG.E [R2.64], R5 ; EXIT ; BRA 0x1f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z17initializeWeightsPfi ; -- Begin function _Z17initializeWeightsPfi .globl _Z17initializeWeightsPfi .p2align 8 .type _Z17initializeWeightsPfi,@function _Z17initializeWeightsPfi: ; @_Z17initializeWeightsPfi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20) v_ashrrev_i32_e32 v2, 31, v1 v_add_co_u32 v0, vcc_lo, s2, v1 s_load_b64 s[0:1], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, 0, v2, vcc_lo v_xor_b32_e32 v0, 0x2c7f967f, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v8, 0xa03697cb, v3 v_mul_lo_u32 v0, 0x493c4aa1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, 0x75bcd15, v0 v_add_nc_u32_e32 v6, 0x583f19, v0 v_lshrrev_b32_e32 v5, 2, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v5, v5, v4 v_lshlrev_b32_e32 v4, 4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v7, 1, v5 v_xor_b32_e32 v7, v4, v7 v_mad_u64_u32 v[3:4], null, 0x7b99840d, v8, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor3_b32 v0, v7, v6, v5 v_add3_u32 v0, v3, v0, 0x6a788e s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v0, v0 v_fmaak_f32 v3, 0x2f800000, v0, 0x2f800000 v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v2, 0x3c23d70a, v3 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z17initializeWeightsPfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z17initializeWeightsPfi, .Lfunc_end0-_Z17initializeWeightsPfi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 284 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z11forwardPassPfS_S_ii ; -- Begin function _Z11forwardPassPfS_S_ii .globl _Z11forwardPassPfS_S_ii .p2align 8 .type _Z11forwardPassPfS_S_ii,@function _Z11forwardPassPfS_S_ii: ; @_Z11forwardPassPfS_S_ii ; %bb.0: s_load_b32 s3, s[0:1], 0x18 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s3, v0 s_cbranch_execz .LBB1_4 ; %bb.1: ; %.lr.ph s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_mul_i32 s10, s15, s3 v_mov_b32_e32 v0, 0 s_ashr_i32 s11, s10, 31 s_mov_b32 s2, s15 s_lshl_b64 s[10:11], s[10:11], 2 s_waitcnt lgkmcnt(0) s_add_u32 s6, s6, s10 s_addc_u32 s7, s7, s11 .LBB1_2: ; =>This Inner Loop Header: Depth=1 s_load_b32 s9, s[4:5], 0x0 s_load_b32 s10, s[6:7], 0x0 s_add_i32 s3, s3, -1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_cmp_eq_u32 s3, 0 s_waitcnt lgkmcnt(0) v_fmac_f32_e64 v0, s9, s10 s_cbranch_scc0 .LBB1_2 ; %bb.3: ; %._crit_edge s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_mul_f32_e32 v1, 0xbfb8aa3b, v0 v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v0 s_ashr_i32 s3, s2, 31 s_lshl_b64 s[2:3], s[2:3], 2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_rndne_f32_e32 v2, v1 v_fma_f32 v3, 0xbfb8aa3b, v0, -v1 s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 v_sub_f32_e32 v1, v1, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmamk_f32 v3, v0, 0xb2a5705f, v3 v_cvt_i32_f32_e32 v2, v2 v_add_f32_e32 v1, v1, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_exp_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_ldexp_f32 v1, v1, v2 v_cndmask_b32_e32 v1, 0, v1, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo v_add_f32_e32 v0, 1.0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v1, null, v0, v0, 1.0 v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0 v_rcp_f32_e32 v2, v1 s_waitcnt_depctr 0xfff v_fma_f32 v3, -v1, v2, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v2, v3, v2 v_mul_f32_e32 v3, v4, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v5, -v1, v3, v4 v_fmac_f32_e32 v3, v5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v1, -v1, v3, v4 v_div_fmas_f32 v1, v1, v2, v3 s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f32 v0, v1, v0, 1.0 v_mov_b32_e32 v1, 0 global_store_b32 v1, v0, s[0:1] .LBB1_4: ; %Flow s_or_b32 exec_lo, exec_lo, s8 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11forwardPassPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z11forwardPassPfS_S_ii, .Lfunc_end1-_Z11forwardPassPfS_S_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 396 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z16computeGradientsPfS_S_i ; -- Begin function _Z16computeGradientsPfS_S_i .globl _Z16computeGradientsPfS_S_i .p2align 8 .type _Z16computeGradientsPfS_S_i,@function _Z16computeGradientsPfS_S_i: ; @_Z16computeGradientsPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB2_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_dual_sub_f32 v4, 1.0, v2 :: v_dual_sub_f32 v3, v2, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v2, v2, v3 v_mul_f32_e32 v2, v4, v2 global_store_b32 v[0:1], v2, off .LBB2_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16computeGradientsPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z16computeGradientsPfS_S_i, .Lfunc_end2-_Z16computeGradientsPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 196 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13updateWeightsPfS_S_if ; -- Begin function _Z13updateWeightsPfS_S_if .globl _Z13updateWeightsPfS_S_if .p2align 8 .type _Z13updateWeightsPfS_S_if,@function _Z13updateWeightsPfS_S_if: ; @_Z13updateWeightsPfS_S_if ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mov_b32 s4, exec_lo v_max_i32_e32 v0, 0, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v0 s_cbranch_execz .LBB3_3 ; %bb.1: ; %.lr.ph s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v3, v1, s2 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[0:1], 2, v[1:2] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_lshlrev_b64 v[2:3], 2, v[3:4] v_mov_b32_e32 v4, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .LBB3_2: ; =>This Inner Loop Header: Depth=1 global_load_b32 v5, v[0:1], off global_load_b32 v6, v4, s[0:1] global_load_b32 v7, v[2:3], off s_add_i32 s2, s2, -1 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s2, 0 s_waitcnt vmcnt(2) v_mul_f32_e32 v5, s3, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_fma_f32 v5, -v5, v6, v7 global_store_b32 v[2:3], v5, off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_cbranch_scc1 .LBB3_2 .LBB3_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13updateWeightsPfS_S_if .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z13updateWeightsPfS_S_if, .Lfunc_end3-_Z13updateWeightsPfS_S_if ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 260 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z17initializeWeightsPfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z17initializeWeightsPfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11forwardPassPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11forwardPassPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16computeGradientsPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16computeGradientsPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13updateWeightsPfS_S_if .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13updateWeightsPfS_S_if.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0012e65c_00000000-6_cuda_code_031432.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3852: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3852: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4513: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4513: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z38__device_stub__Z17initializeWeightsPfiPfi .type _Z38__device_stub__Z17initializeWeightsPfiPfi, @function _Z38__device_stub__Z17initializeWeightsPfiPfi: .LFB3874: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z17initializeWeightsPfi(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3874: .size _Z38__device_stub__Z17initializeWeightsPfiPfi, .-_Z38__device_stub__Z17initializeWeightsPfiPfi .globl _Z17initializeWeightsPfi .type _Z17initializeWeightsPfi, @function _Z17initializeWeightsPfi: .LFB3875: .cfi_startproc endbr64 jmp _Z38__device_stub__Z17initializeWeightsPfiPfi .cfi_endproc .LFE3875: .size _Z17initializeWeightsPfi, .-_Z17initializeWeightsPfi .globl _Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii .type _Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii, @function _Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii: .LFB3876: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movq %rdx, 8(%rsp) leaq 32(%rsp), %rdx movl %ecx, 4(%rsp) leaq 40(%rsp), %rcx movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L9 pushq 40(%rsp) .cfi_def_cfa_offset 168 leaq _Z11forwardPassPfS_S_ii(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 176 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L9: movq 136(%rsp), %rax subq %fs:40, %rax je .L11 call __stack_chk_fail@PLT .L11: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3876: .size _Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii .globl _Z11forwardPassPfS_S_ii .type _Z11forwardPassPfS_S_ii, @function _Z11forwardPassPfS_S_ii: .LFB3877: .cfi_startproc endbr64 jmp _Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii .cfi_endproc .LFE3877: .size _Z11forwardPassPfS_S_ii, .-_Z11forwardPassPfS_S_ii .globl _Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i .type _Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i, @function _Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i: .LFB3878: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L14 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z16computeGradientsPfS_S_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L14: movq 136(%rsp), %rax subq %fs:40, %rax je .L16 call __stack_chk_fail@PLT .L16: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3878: .size _Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i, .-_Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i .globl _Z16computeGradientsPfS_S_i .type _Z16computeGradientsPfS_S_i, @function _Z16computeGradientsPfS_S_i: .LFB3879: .cfi_startproc endbr64 jmp _Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i .cfi_endproc .LFE3879: .size _Z16computeGradientsPfS_S_i, .-_Z16computeGradientsPfS_S_i .globl _Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if .type _Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if, @function _Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if: .LFB3880: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movq %rdx, 8(%rsp) leaq 32(%rsp), %rdx movl %ecx, 4(%rsp) leaq 40(%rsp), %rcx movss %xmm0, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L19 pushq 40(%rsp) .cfi_def_cfa_offset 168 leaq _Z13updateWeightsPfS_S_if(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 176 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L19: movq 136(%rsp), %rax subq %fs:40, %rax je .L21 call __stack_chk_fail@PLT .L21: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3880: .size _Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if, .-_Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if .globl _Z13updateWeightsPfS_S_if .type _Z13updateWeightsPfS_S_if, @function _Z13updateWeightsPfS_S_if: .LFB3881: .cfi_startproc endbr64 jmp _Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if .cfi_endproc .LFE3881: .size _Z13updateWeightsPfS_S_if, .-_Z13updateWeightsPfS_S_if .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate d_inputs: " .LC1: .string "Failed to allocate d_weights: " .LC2: .string "Failed to allocate d_outputs: " .LC3: .string "Failed to allocate d_targets: " .LC4: .string "Failed to allocate d_gradients: " .LC5: .string "Kernel launch failed: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3849: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movl $1024, %esi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $2152, %rsp .cfi_def_cfa_offset 2176 movq %fs:40, %rax movq %rax, 2136(%rsp) xorl %eax, %eax movq %rsp, %rdi call cudaMalloc@PLT leaq .LC0(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L44 leaq 8(%rsp), %rdi movl $2621440, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L27 leaq .LC1(%rip), %rsi .L44: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L24 .L27: movl $1024, %esi leaq 16(%rsp), %rdi call cudaMalloc@PLT leaq .LC2(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L44 movl $1024, %esi leaq 24(%rsp), %rdi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L44 movl $1024, %esi leaq 32(%rsp), %rdi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L44 movl $16777217, %edx movl $8388613, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx salq $9, %rdi movl $1, %ecx movl $1, %esi movq %rdx, 76(%rsp) movl $1, 84(%rsp) movq %rdi, 64(%rsp) movl $1, 72(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L32 movq 8(%rsp), %rdi movl $655360, %esi call _Z38__device_stub__Z17initializeWeightsPfiPfi .L32: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax jne .L45 leaq 88(%rsp), %rdi movl $256, %ecx movss .LC6(%rip), %xmm1 movss .LC7(%rip), %xmm0 rep stosl leaq 1112(%rsp), %rdi movl $256, %ecx leaq 88(%rsp), %rsi rep stosl leaq 1112(%rsp), %rbx xorl %eax, %eax .L34: movss %xmm1, (%rsi,%rax) movss %xmm0, (%rbx,%rax) addq $4, %rax cmpq $1024, %rax jne .L34 movq (%rsp), %rdi movl $1, %ecx movl $1024, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $1024, %edx call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d movl $1024, %r8d salq $8, %rdx movl $1, %ecx movl $1, %esi movabsq $1099511627786, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L35 movq 16(%rsp), %rdx movq 8(%rsp), %rsi movl $256, %ecx movl $10, %r8d movq (%rsp), %rdi call _Z37__device_stub__Z11forwardPassPfS_S_iiPfS_S_ii .L35: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax jne .L45 movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $8, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 84(%rsp) movq %rdx, 76(%rsp) movq %rdi, 64(%rsp) movl $1, 72(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L37 movq 32(%rsp), %rdx movq 24(%rsp), %rsi movl $256, %ecx movq 16(%rsp), %rdi call _Z41__device_stub__Z16computeGradientsPfS_S_iPfS_S_i .L37: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax jne .L45 movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $8, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 84(%rsp) movq %rdx, 76(%rsp) movq %rdi, 64(%rsp) movl $1, 72(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L39 movq (%rsp), %rdx movq 32(%rsp), %rsi movl $256, %ecx movss .LC8(%rip), %xmm0 movq 8(%rsp), %rdi call _Z39__device_stub__Z13updateWeightsPfS_S_ifPfS_S_if .L39: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L40 .L45: leaq .LC5(%rip), %rsi jmp .L44 .L40: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L24: movq 2136(%rsp), %rdx subq %fs:40, %rdx je .L41 call __stack_chk_fail@PLT .L41: addq $2152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3849: .size main, .-main .section .rodata.str1.1 .LC9: .string "_Z13updateWeightsPfS_S_if" .LC10: .string "_Z16computeGradientsPfS_S_i" .LC11: .string "_Z11forwardPassPfS_S_ii" .LC12: .string "_Z17initializeWeightsPfi" .LC13: .string "precalc_xorwow_matrix" .LC14: .string "precalc_xorwow_offset_matrix" .LC15: .string "mrg32k3aM1" .LC16: .string "mrg32k3aM2" .LC17: .string "mrg32k3aM1SubSeq" .LC18: .string "mrg32k3aM2SubSeq" .LC19: .string "mrg32k3aM1Seq" .LC20: .string "mrg32k3aM2Seq" .LC21: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3883: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC9(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z13updateWeightsPfS_S_if(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC10(%rip), %rdx movq %rbx, %rdi leaq _Z16computeGradientsPfS_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC11(%rip), %rdx movq %rbx, %rdi leaq _Z11forwardPassPfS_S_ii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC12(%rip), %rdx movq %rbx, %rdi leaq _Z17initializeWeightsPfi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 xorl %r8d, %r8d movq %rbx, %rdi pushq $0 .cfi_def_cfa_offset 24 leaq .LC13(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC15(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC19(%rip), %rdx xorl %r8d, %r8d movq %rbx, %rdi movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC20(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC21(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3883: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC6: .long 1056964608 .align 4 .LC7: .long 1060320051 .align 4 .LC8: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_031432.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z32__device_stub__initializeWeightsPfi # -- Begin function _Z32__device_stub__initializeWeightsPfi .type _Z32__device_stub__initializeWeightsPfi,@function _Z32__device_stub__initializeWeightsPfi: # @_Z32__device_stub__initializeWeightsPfi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z17initializeWeightsPfi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z32__device_stub__initializeWeightsPfi, .Lfunc_end0-_Z32__device_stub__initializeWeightsPfi .cfi_endproc # -- End function .globl _Z26__device_stub__forwardPassPfS_S_ii # -- Begin function _Z26__device_stub__forwardPassPfS_S_ii .type _Z26__device_stub__forwardPassPfS_S_ii,@function _Z26__device_stub__forwardPassPfS_S_ii: # @_Z26__device_stub__forwardPassPfS_S_ii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) movq %rsp, %rcx movl %r8d, (%rcx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z11forwardPassPfS_S_ii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $144, %rsp .cfi_adjust_cfa_offset -144 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z26__device_stub__forwardPassPfS_S_ii, .Lfunc_end1-_Z26__device_stub__forwardPassPfS_S_ii .cfi_endproc # -- End function .globl _Z31__device_stub__computeGradientsPfS_S_i # -- Begin function _Z31__device_stub__computeGradientsPfS_S_i .type _Z31__device_stub__computeGradientsPfS_S_i,@function _Z31__device_stub__computeGradientsPfS_S_i: # @_Z31__device_stub__computeGradientsPfS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z16computeGradientsPfS_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z31__device_stub__computeGradientsPfS_S_i, .Lfunc_end2-_Z31__device_stub__computeGradientsPfS_S_i .cfi_endproc # -- End function .globl _Z28__device_stub__updateWeightsPfS_S_if # -- Begin function _Z28__device_stub__updateWeightsPfS_S_if .type _Z28__device_stub__updateWeightsPfS_S_if,@function _Z28__device_stub__updateWeightsPfS_S_if: # @_Z28__device_stub__updateWeightsPfS_S_if .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) movq %rsp, %rcx movss %xmm0, (%rcx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13updateWeightsPfS_S_if, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $144, %rsp .cfi_adjust_cfa_offset -144 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z28__device_stub__updateWeightsPfS_S_if, .Lfunc_end3-_Z28__device_stub__updateWeightsPfS_S_if .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI4_0: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $2096, %rsp # imm = 0x830 .cfi_def_cfa_offset 2128 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 leaq 16(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc testl %eax, %eax je .LBB4_2 # %bb.1: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $29, %edx jmp .LBB4_9 .LBB4_2: leaq 8(%rsp), %rdi movl $2621440, %esi # imm = 0x280000 callq hipMalloc testl %eax, %eax je .LBB4_4 # %bb.3: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi jmp .LBB4_8 .LBB4_4: leaq 40(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc testl %eax, %eax je .LBB4_6 # %bb.5: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi jmp .LBB4_8 .LBB4_6: leaq 32(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc testl %eax, %eax je .LBB4_15 # %bb.7: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi .LBB4_8: movl $30, %edx .LBB4_9: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB4_11 # %bb.10: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB4_12 .LBB4_11: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB4_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB4_13: movl $-1, %eax .LBB4_14: addq $2096, %rsp # imm = 0x830 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB4_15: .cfi_def_cfa_offset 2128 leaq 24(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc testl %eax, %eax je .LBB4_18 # %bb.16: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $32, %edx .LBB4_17: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi jmp .LBB4_30 .LBB4_18: movabsq $4294967552, %rbx # imm = 0x100000100 leaq 2304(%rbx), %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_20 # %bb.19: movq 8(%rsp), %rdi movl $655360, %esi # imm = 0xA0000 callq _Z32__device_stub__initializeWeightsPfi .LBB4_20: callq hipGetLastError testl %eax, %eax jne .LBB4_29 # %bb.21: leaq 1072(%rsp), %rdi xorl %r14d, %r14d movl $1024, %edx # imm = 0x400 xorl %esi, %esi callq memset@PLT leaq 48(%rsp), %rdi movl $1024, %edx # imm = 0x400 xorl %esi, %esi callq memset@PLT .LBB4_22: # =>This Inner Loop Header: Depth=1 movl $1056964608, 1072(%rsp,%r14,4) # imm = 0x3F000000 movl $1060320051, 48(%rsp,%r14,4) # imm = 0x3F333333 incq %r14 cmpq $256, %r14 # imm = 0x100 jne .LBB4_22 # %bb.23: movq 16(%rsp), %rdi leaq 1072(%rsp), %rsi movl $1024, %edx # imm = 0x400 movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi leaq 48(%rsp), %rsi movl $1024, %edx # imm = 0x400 movl $1, %ecx callq hipMemcpy movabsq $1099511627786, %rdi # imm = 0x1000000000A movl $1024, %r8d # imm = 0x400 movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_25 # %bb.24: movq 16(%rsp), %rdi movq 8(%rsp), %rsi movq 40(%rsp), %rdx movl $256, %ecx # imm = 0x100 movl $10, %r8d callq _Z26__device_stub__forwardPassPfS_S_ii .LBB4_25: callq hipGetLastError testl %eax, %eax jne .LBB4_29 # %bb.26: leaq -255(%rbx), %r14 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_28 # %bb.27: movq 40(%rsp), %rdi movq 32(%rsp), %rsi movq 24(%rsp), %rdx movl $256, %ecx # imm = 0x100 callq _Z31__device_stub__computeGradientsPfS_S_i .LBB4_28: callq hipGetLastError testl %eax, %eax je .LBB4_31 .LBB4_29: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi .LBB4_30: callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB4_13 .LBB4_31: movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_33 # %bb.32: movq 8(%rsp), %rdi movq 24(%rsp), %rsi movq 16(%rsp), %rdx movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movl $256, %ecx # imm = 0x100 callq _Z28__device_stub__updateWeightsPfS_S_if .LBB4_33: callq hipGetLastError testl %eax, %eax je .LBB4_35 # %bb.34: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $22, %edx jmp .LBB4_17 .LBB4_35: movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB4_14 .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z17initializeWeightsPfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11forwardPassPfS_S_ii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16computeGradientsPfS_S_i, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13updateWeightsPfS_S_if, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type _Z17initializeWeightsPfi,@object # @_Z17initializeWeightsPfi .section .rodata,"a",@progbits .globl _Z17initializeWeightsPfi .p2align 3, 0x0 _Z17initializeWeightsPfi: .quad _Z32__device_stub__initializeWeightsPfi .size _Z17initializeWeightsPfi, 8 .type _Z11forwardPassPfS_S_ii,@object # @_Z11forwardPassPfS_S_ii .globl _Z11forwardPassPfS_S_ii .p2align 3, 0x0 _Z11forwardPassPfS_S_ii: .quad _Z26__device_stub__forwardPassPfS_S_ii .size _Z11forwardPassPfS_S_ii, 8 .type _Z16computeGradientsPfS_S_i,@object # @_Z16computeGradientsPfS_S_i .globl _Z16computeGradientsPfS_S_i .p2align 3, 0x0 _Z16computeGradientsPfS_S_i: .quad _Z31__device_stub__computeGradientsPfS_S_i .size _Z16computeGradientsPfS_S_i, 8 .type _Z13updateWeightsPfS_S_if,@object # @_Z13updateWeightsPfS_S_if .globl _Z13updateWeightsPfS_S_if .p2align 3, 0x0 _Z13updateWeightsPfS_S_if: .quad _Z28__device_stub__updateWeightsPfS_S_if .size _Z13updateWeightsPfS_S_if, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate d_inputs: " .size .L.str, 30 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate d_weights: " .size .L.str.1, 31 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate d_outputs: " .size .L.str.2, 31 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate d_targets: " .size .L.str.3, 31 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate d_gradients: " .size .L.str.4, 33 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Kernel launch failed: " .size .L.str.5, 23 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z17initializeWeightsPfi" .size .L__unnamed_1, 25 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z11forwardPassPfS_S_ii" .size .L__unnamed_2, 24 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z16computeGradientsPfS_S_i" .size .L__unnamed_3, 28 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z13updateWeightsPfS_S_if" .size .L__unnamed_4, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z32__device_stub__initializeWeightsPfi .addrsig_sym _Z26__device_stub__forwardPassPfS_S_ii .addrsig_sym _Z31__device_stub__computeGradientsPfS_S_i .addrsig_sym _Z28__device_stub__updateWeightsPfS_S_if .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z17initializeWeightsPfi .addrsig_sym _Z11forwardPassPfS_S_ii .addrsig_sym _Z16computeGradientsPfS_S_i .addrsig_sym _Z13updateWeightsPfS_S_if .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
9,744
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z22geneticAlgorithmKernelPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR8, c[0x0][0x160] ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R0, 0xfff, PT ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; SHF.L.U32 R4, R0, 0x7, RZ ; HFMA2.MMA R16, -RZ, RZ, 0, 0 ; MOV R25, RZ ; ULDC.64 UR4, c[0x0][0x118] ; SHF.R.S32.HI R7, RZ, 0x1f, R4 ; ULDC.64 UR6, c[0x0][0x170] ; IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; IADD3 R2, P0, R2, 0x40, RZ ; IADD3.X R3, RZ, R3, RZ, P0, !PT ; LDG.E R17, [R2.64+-0x40] ; LDG.E R26, [R2.64+-0x3c] ; LDG.E R18, [R2.64+-0x38] ; LDG.E R19, [R2.64+-0x34] ; LDG.E R23, [R2.64+-0x30] ; LDG.E R24, [R2.64+-0x2c] ; LDG.E R22, [R2.64+-0x28] ; LDG.E R21, [R2.64+-0x24] ; LDG.E R20, [R2.64+-0x20] ; LDG.E R6, [R2.64+-0x1c] ; LDG.E R8, [R2.64+-0x18] ; LDG.E R9, [R2.64+-0x14] ; LDG.E R10, [R2.64+-0x10] ; LDG.E R11, [R2.64+-0xc] ; LDG.E R12, [R2.64+-0x8] ; LDG.E R13, [R2.64+-0x4] ; LDG.E R14, [R2.64] ; LDG.E R15, [R2.64+0x4] ; FADD R17, R17, R16 ; LDG.E R16, [R2.64+0x8] ; FADD R27, R17, R26 ; LDG.E R17, [R2.64+0xc] ; FADD R26, R27, R18 ; LDG.E R18, [R2.64+0x10] ; FADD R26, R26, R19 ; LDG.E R19, [R2.64+0x14] ; FADD R27, R26, R23 ; LDG.E R23, [R2.64+0x18] ; FADD R27, R27, R24 ; LDG.E R24, [R2.64+0x1c] ; FADD R26, R27, R22 ; LDG.E R22, [R2.64+0x20] ; FADD R27, R26, R21 ; LDG.E R21, [R2.64+0x24] ; FADD R27, R27, R20 ; LDG.E R20, [R2.64+0x28] ; FADD R27, R27, R6 ; LDG.E R6, [R2.64+0x2c] ; FADD R26, R27, R8 ; LDG.E R8, [R2.64+0x30] ; FADD R27, R26, R9 ; LDG.E R9, [R2.64+0x34] ; FADD R26, R27, R10 ; LDG.E R10, [R2.64+0x38] ; FADD R27, R26, R11 ; LDG.E R11, [R2.64+0x3c] ; IADD3 R25, R25, 0x20, RZ ; FADD R12, R27, R12 ; ISETP.NE.AND P0, PT, R25, 0x80, PT ; FADD R13, R12, R13 ; FADD R14, R13, R14 ; IADD3 R2, P1, R2, 0x80, RZ ; FADD R15, R14, R15 ; IADD3.X R3, RZ, R3, RZ, P1, !PT ; FADD R16, R15, R16 ; FADD R17, R16, R17 ; FADD R18, R17, R18 ; FADD R18, R18, R19 ; FADD R23, R18, R23 ; FADD R23, R23, R24 ; FADD R22, R23, R22 ; FADD R21, R22, R21 ; FADD R21, R21, R20 ; FADD R21, R21, R6 ; FADD R8, R21, R8 ; FADD R9, R8, R9 ; FADD R10, R9, R10 ; FADD R16, R10, R11 ; @P0 BRA 0x110 ; IMAD.WIDE R2, R0.reuse, R5, c[0x0][0x168] ; ISETP.GT.AND P0, PT, R0, 0x7ff, PT ; STG.E [R2.64], R16 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; HFMA2.MMA R13, -RZ, RZ, 0, 0 ; SHF.L.U64.HI R0, R4, 0x2, R7 ; IADD3 R10, -R4.reuse, 0x7ff80, RZ ; IADD3 R11, R4.reuse, 0x1, RZ ; SHF.L.U32 R12, R4, 0x2, RZ ; MOV R6, UR8 ; MOV R7, UR9 ; IADD3 R14, P0, R12, UR8, RZ ; IMAD.WIDE R2, R10, 0x4, R6 ; IADD3.X R15, R0, UR9, RZ, P0, !PT ; LDG.E R5, [R2.64] ; LDG.E R8, [R14.64] ; IADD3 R4, P0, R12, UR6, RZ ; IMAD.WIDE R6, R11, 0x4, R6 ; FADD R8, R5, R8 ; IADD3.X R5, R0, UR7, RZ, P0, !PT ; FMUL R17, R8, 0.5 ; STG.E [R4.64], R17 ; LDG.E R16, [R2.64+0x4] ; LDG.E R19, [R6.64] ; MOV R8, UR6 ; MOV R9, UR7 ; IMAD.WIDE R8, R11, 0x4, R8 ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64], R19 ; LDG.E R16, [R2.64+0x8] ; LDG.E R21, [R6.64+0x4] ; FADD R16, R16, R21 ; FMUL R17, R16, 0.5 ; STG.E [R8.64+0x4], R17 ; LDG.E R16, [R2.64+0xc] ; LDG.E R21, [R6.64+0x8] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x8], R21 ; LDG.E R16, [R2.64+0x10] ; LDG.E R19, [R6.64+0xc] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0xc], R19 ; LDG.E R16, [R2.64+0x14] ; LDG.E R17, [R6.64+0x10] ; FADD R16, R16, R17 ; FMUL R17, R16, 0.5 ; STG.E [R8.64+0x10], R17 ; LDG.E R16, [R2.64+0x18] ; LDG.E R21, [R6.64+0x14] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x14], R21 ; LDG.E R16, [R2.64+0x1c] ; LDG.E R19, [R6.64+0x18] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0x18], R19 ; LDG.E R16, [R2.64+0x20] ; LDG.E R17, [R14.64+0x20] ; FADD R16, R16, R17 ; FMUL R17, R16, 0.5 ; STG.E [R4.64+0x20], R17 ; LDG.E R16, [R2.64+0x24] ; LDG.E R21, [R6.64+0x20] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x20], R21 ; LDG.E R16, [R2.64+0x28] ; LDG.E R19, [R6.64+0x24] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0x24], R19 ; LDG.E R16, [R2.64+0x2c] ; LDG.E R17, [R6.64+0x28] ; FADD R16, R16, R17 ; FMUL R17, R16, 0.5 ; STG.E [R8.64+0x28], R17 ; LDG.E R16, [R2.64+0x30] ; LDG.E R21, [R6.64+0x2c] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x2c], R21 ; LDG.E R16, [R2.64+0x34] ; LDG.E R19, [R6.64+0x30] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0x30], R19 ; LDG.E R16, [R2.64+0x38] ; LDG.E R17, [R6.64+0x34] ; FADD R16, R16, R17 ; FMUL R17, R16, 0.5 ; STG.E [R8.64+0x34], R17 ; LDG.E R16, [R2.64+0x3c] ; LDG.E R21, [R6.64+0x38] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x38], R21 ; LDG.E R16, [R2.64+0x40] ; LDG.E R19, [R14.64+0x40] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R4.64+0x40], R19 ; LDG.E R16, [R2.64+0x44] ; LDG.E R17, [R6.64+0x40] ; FADD R16, R16, R17 ; FMUL R17, R16, 0.5 ; STG.E [R8.64+0x40], R17 ; LDG.E R16, [R2.64+0x48] ; LDG.E R21, [R6.64+0x44] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x44], R21 ; LDG.E R16, [R2.64+0x4c] ; LDG.E R19, [R6.64+0x48] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0x48], R19 ; LDG.E R16, [R2.64+0x50] ; LDG.E R17, [R6.64+0x4c] ; FADD R16, R16, R17 ; FMUL R17, R16, 0.5 ; STG.E [R8.64+0x4c], R17 ; LDG.E R16, [R2.64+0x54] ; LDG.E R21, [R6.64+0x50] ; FADD R16, R16, R21 ; FMUL R21, R16, 0.5 ; STG.E [R8.64+0x50], R21 ; LDG.E R16, [R2.64+0x58] ; LDG.E R19, [R6.64+0x54] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0x54], R19 ; LDG.E R16, [R2.64+0x5c] ; LDG.E R17, [R6.64+0x58] ; FADD R16, R16, R17 ; FMUL R23, R16, 0.5 ; STG.E [R8.64+0x58], R23 ; LDG.E R15, [R14.64+0x60] ; LDG.E R16, [R2.64+0x60] ; FADD R16, R16, R15 ; FMUL R17, R16, 0.5 ; STG.E [R4.64+0x60], R17 ; LDG.E R16, [R2.64+0x64] ; LDG.E R19, [R6.64+0x60] ; FADD R16, R16, R19 ; FMUL R19, R16, 0.5 ; STG.E [R8.64+0x60], R19 ; LDG.E R16, [R2.64+0x68] ; LDG.E R15, [R6.64+0x64] ; FADD R15, R16, R15 ; FMUL R15, R15, 0.5 ; STG.E [R8.64+0x64], R15 ; LDG.E R4, [R2.64+0x6c] ; LDG.E R5, [R6.64+0x68] ; FADD R4, R4, R5 ; FMUL R5, R4, 0.5 ; STG.E [R8.64+0x68], R5 ; LDG.E R4, [R2.64+0x70] ; LDG.E R17, [R6.64+0x6c] ; FADD R4, R4, R17 ; FMUL R17, R4, 0.5 ; STG.E [R8.64+0x6c], R17 ; LDG.E R4, [R2.64+0x74] ; LDG.E R15, [R6.64+0x70] ; FADD R4, R4, R15 ; FMUL R15, R4, 0.5 ; STG.E [R8.64+0x70], R15 ; LDG.E R4, [R2.64+0x78] ; LDG.E R5, [R6.64+0x74] ; FADD R4, R4, R5 ; FMUL R5, R4, 0.5 ; STG.E [R8.64+0x74], R5 ; LDG.E R4, [R2.64+0x7c] ; LDG.E R17, [R6.64+0x78] ; IADD3 R13, R13, 0x20, RZ ; UIADD3 UR8, UP0, UR8, 0x80, URZ ; UIADD3 UR6, UP1, UR6, 0x80, URZ ; ISETP.NE.AND P0, PT, R13, 0x80, PT ; UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; FADD R4, R4, R17 ; FMUL R17, R4, 0.5 ; STG.E [R8.64+0x78], R17 ; @P0 BRA 0x600 ; EXIT ; BRA 0x1130; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z22geneticAlgorithmKernelPfS_S_ ; -- Begin function _Z22geneticAlgorithmKernelPfS_S_ .globl _Z22geneticAlgorithmKernelPfS_S_ .p2align 8 .type _Z22geneticAlgorithmKernelPfS_S_,@function _Z22geneticAlgorithmKernelPfS_S_: ; @_Z22geneticAlgorithmKernelPfS_S_ ; %bb.0: s_load_b32 s2, s[0:1], 0x24 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x1000, v1 s_cbranch_execz .LBB0_6 ; %bb.1: ; %.preheader29 s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v5, 7, v1 s_load_b64 s[0:1], s[0:1], 0x10 v_mov_b32_e32 v7, 0 s_mov_b64 s[2:3], 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v6, 31, v5 v_lshlrev_b64 v[3:4], 2, v[5:6] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v0, s2 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v6, vcc_lo s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmpk_eq_i32 s2, 0x200 global_load_b32 v2, v[8:9], off s_waitcnt vmcnt(0) v_add_f32_e32 v7, v7, v2 s_cbranch_scc0 .LBB0_2 ; %bb.3: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[1:2] v_add_co_u32 v8, vcc_lo, s6, v8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0x800, v1 global_store_b32 v[8:9], v7, off s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_6 ; %bb.4: ; %.preheader.preheader v_sub_nc_u32_e32 v1, 0x7ff80, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[1:2], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo v_add_co_u32 v3, vcc_lo, s0, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo s_mov_b64 s[0:1], 0 .LBB0_5: ; %.preheader ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v7, vcc_lo, v0, s0 v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo v_add_co_u32 v9, vcc_lo, v1, s0 v_add_co_ci_u32_e32 v10, vcc_lo, s1, v2, vcc_lo s_clause 0x1 global_load_b32 v5, v[7:8], off global_load_b32 v7, v[9:10], off s_waitcnt vmcnt(0) v_add_f32_e32 v5, v5, v7 v_add_co_u32 v7, vcc_lo, v3, s0 v_add_co_ci_u32_e32 v8, vcc_lo, s1, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_mul_f32_e32 v5, 0.5, v5 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmpk_lg_i32 s0, 0x200 global_store_b32 v[7:8], v5, off s_cbranch_scc1 .LBB0_5 .LBB0_6: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z22geneticAlgorithmKernelPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z22geneticAlgorithmKernelPfS_S_, .Lfunc_end0-_Z22geneticAlgorithmKernelPfS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 400 ; NumSgprs: 18 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z22geneticAlgorithmKernelPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z22geneticAlgorithmKernelPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0000649c_00000000-6_cuda_code_010807.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4292: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4292: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_ .type _Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_, @function _Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_: .LFB3660: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movq %rdx, 8(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z22geneticAlgorithmKernelPfS_S_(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L3: movq 120(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_, .-_Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_ .globl _Z22geneticAlgorithmKernelPfS_S_ .type _Z22geneticAlgorithmKernelPfS_S_, @function _Z22geneticAlgorithmKernelPfS_S_: .LFB3661: .cfi_startproc endbr64 jmp _Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_ .cfi_endproc .LFE3661: .size _Z22geneticAlgorithmKernelPfS_S_, .-_Z22geneticAlgorithmKernelPfS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Failed to allocate memory for d_population" .LC2: .string "Failed to allocate memory for d_fitness" .LC3: .string "Failed to allocate memory for d_newPopulation" .LC4: .string "Failed to copy population to device" .LC5: .string "Kernel launch failed: " .LC6: .string "Failed to copy new population back to host" .LC7: .string "Genetic algorithm kernel executed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $2097152, %edi xorl %r12d, %r12d pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $2097152, %edi movq %rax, %rbx call _Znam@PLT movq %rax, %rbp .L10: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, (%rbx,%r12,4) incq %r12 cmpq $524288, %r12 jne .L10 leaq 8(%rsp), %rdi movl $2097152, %esi call cudaMalloc@PLT testl %eax, %eax je .L11 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L12 .L11: leaq 16(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi .L23: call cudaFree@PLT .L12: orl $-1, %eax jmp .L9 .L13: leaq 24(%rsp), %rdi movl $2097152, %esi call cudaMalloc@PLT testl %eax, %eax je .L15 leaq .LC3(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi jmp .L23 .L15: movq 8(%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $2097152, %edx call cudaMemcpy@PLT leaq .LC4(%rip), %rsi testl %eax, %eax jne .L25 movl $16777217, %edx movl $268435457, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx salq $4, %rdi movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L17 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z46__device_stub__Z22geneticAlgorithmKernelPfS_S_PfS_S_ .L17: call cudaGetLastError@PLT movl %eax, %r12d testl %eax, %eax je .L18 leaq .LC5(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi jmp .L24 .L18: movq 24(%rsp), %rsi movl $2, %ecx movl $2097152, %edx movq %rbp, %rdi call cudaMemcpy@PLT testl %eax, %eax je .L19 leaq .LC6(%rip), %rsi .L25: leaq _ZSt4cerr(%rip), %rdi .L24: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi jmp .L23 .L19: movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L9: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L20 call __stack_chk_fail@PLT .L20: addq $64, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z22geneticAlgorithmKernelPfS_S_" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi leaq _Z22geneticAlgorithmKernelPfS_S_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 805306368 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_010807.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z37__device_stub__geneticAlgorithmKernelPfS_S_ # -- Begin function _Z37__device_stub__geneticAlgorithmKernelPfS_S_ .type _Z37__device_stub__geneticAlgorithmKernelPfS_S_,@function _Z37__device_stub__geneticAlgorithmKernelPfS_S_: # @_Z37__device_stub__geneticAlgorithmKernelPfS_S_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z22geneticAlgorithmKernelPfS_S_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z37__device_stub__geneticAlgorithmKernelPfS_S_, .Lfunc_end0-_Z37__device_stub__geneticAlgorithmKernelPfS_S_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x30000000 # float 4.65661287E-10 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $24, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $2097152, %edi # imm = 0x200000 callq _Znam movq %rax, %rbx movl $2097152, %edi # imm = 0x200000 callq _Znam movq %rax, %r14 xorl %r15d, %r15d .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, (%rbx,%r15,4) incq %r15 cmpq $524288, %r15 # imm = 0x80000 jne .LBB1_1 # %bb.2: movq %rsp, %rdi movl $2097152, %esi # imm = 0x200000 callq hipMalloc testl %eax, %eax je .LBB1_4 # %bb.3: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_19 .LBB1_4: leaq 16(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB1_6 # %bb.5: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $39, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi jmp .LBB1_18 .LBB1_6: leaq 8(%rsp), %rdi movl $2097152, %esi # imm = 0x200000 callq hipMalloc testl %eax, %eax je .LBB1_8 # %bb.7: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $45, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi callq hipFree movq 16(%rsp), %rdi jmp .LBB1_18 .LBB1_8: movq (%rsp), %rdi movl $2097152, %edx # imm = 0x200000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_10 # %bb.9: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_17 .LBB1_10: movabsq $4294967312, %rdi # imm = 0x100000010 leaq 240(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_12 # %bb.11: movq (%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx callq _Z37__device_stub__geneticAlgorithmKernelPfS_S_ .LBB1_12: callq hipGetLastError testl %eax, %eax je .LBB1_14 # %bb.13: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi jmp .LBB1_16 .LBB1_14: movq 8(%rsp), %rsi movl $2097152, %edx # imm = 0x200000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_21 # %bb.15: movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi .LBB1_16: callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ .LBB1_17: movq (%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi .LBB1_18: callq hipFree .LBB1_19: movl $-1, %eax .LBB1_20: addq $24, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_21: .cfi_def_cfa_offset 64 movq (%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $47, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB1_20 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z22geneticAlgorithmKernelPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z22geneticAlgorithmKernelPfS_S_,@object # @_Z22geneticAlgorithmKernelPfS_S_ .section .rodata,"a",@progbits .globl _Z22geneticAlgorithmKernelPfS_S_ .p2align 3, 0x0 _Z22geneticAlgorithmKernelPfS_S_: .quad _Z37__device_stub__geneticAlgorithmKernelPfS_S_ .size _Z22geneticAlgorithmKernelPfS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate memory for d_population" .size .L.str, 43 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate memory for d_fitness" .size .L.str.1, 40 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate memory for d_newPopulation" .size .L.str.2, 46 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy population to device" .size .L.str.3, 36 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed: " .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy new population back to host" .size .L.str.5, 43 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Genetic algorithm kernel executed successfully." .size .L.str.6, 48 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z22geneticAlgorithmKernelPfS_S_" .size .L__unnamed_1, 33 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z37__device_stub__geneticAlgorithmKernelPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z22geneticAlgorithmKernelPfS_S_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,150
5,227
113,436
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z22dictionaryAttackKernelPKcPKiiiPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ULDC UR4, c[0x0][0x174] ; BSSY B0, 0x510 ; USHF.L.U32 UR4, UR4, 0x5, URZ ; ULDC.64 UR10, c[0x0][0x118] ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @P0 BRA 0x500 ; I2F.U32.RP R5, c[0x0][0x0] ; LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; BSSY B1, 0x320 ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; IADD3 R4, R4, UR4, RZ ; MUFU.RCP R5, R5 ; IADD3 R2, R5, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R7, RZ, RZ, -R3 ; IMAD R7, R7, c[0x0][0x0], RZ ; IMAD.HI.U32 R3, R3, R7, R2 ; IMAD.HI.U32 R3, R3, R4, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R4, R5, c[0x0][0x0], R4 ; ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; @P0 IADD3 R3, R3, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; @P1 IADD3 R3, R3, 0x1, RZ ; @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; IADD3 R2, R3.reuse, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; LOP3.LUT P1, R4, R2, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; @!P1 BRA 0x310 ; IADD3 R6, P1, R0.reuse, c[0x0][0x160], RZ ; IMAD.MOV.U32 R3, RZ, RZ, R4 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; LEA.HI.X.SX32 R7, R0, c[0x0][0x164], 0x1, P1 ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R4, RZ, RZ, R6 ; LDG.E.U8 R5, [R4.64] ; IADD3 R3, R3, -0x1, RZ ; IADD3 R6, P2, R6, c[0x0][0x0], RZ ; ISETP.NE.AND P1, PT, R3, RZ, PT ; LEA.HI.X.SX32 R7, R8, R7, 0x1, P2 ; STS.U8 [R2], R5 ; IADD3 R2, R2, c[0x0][0x0], RZ ; @P1 BRA 0x270 ; BSYNC B1 ; @!P0 BRA 0x500 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; IMAD.MOV.U32 R3, RZ, RZ, R2 ; SHF.R.S32.HI R19, RZ, 0x1f, R4 ; IADD3 R4, P0, R2, c[0x0][0x160], RZ ; LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; IADD3 R6, P0, R4, c[0x0][0x0], RZ ; LDG.E.U8 R4, [R4.64] ; IMAD.X R7, R19, 0x1, R5, P0 ; IADD3 R8, P0, R6, c[0x0][0x0], RZ ; LDG.E.U8 R6, [R6.64] ; IMAD.X R9, R19, 0x1, R7, P0 ; IADD3 R10, P0, R8, c[0x0][0x0], RZ ; LDG.E.U8 R8, [R8.64] ; IMAD.X R11, R19, 0x1, R9, P0 ; LDG.E.U8 R10, [R10.64] ; IADD3 R13, R3, c[0x0][0x0], RZ ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; IADD3 R15, R13, c[0x0][0x0], RZ ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; IMAD R2, R5, 0x2, R2 ; IADD3 R17, R15, c[0x0][0x0], RZ ; IMAD R2, R7, 0x2, R2 ; ISETP.GE.AND P0, PT, R2, UR4, PT ; STS.U8 [R3], R4 ; STS.U8 [R13], R6 ; STS.U8 [R15], R8 ; STS.U8 [R17], R10 ; IADD3 R3, R17, c[0x0][0x0], RZ ; @!P0 BRA 0x360 ; BSYNC B0 ; S2R R3, SR_CTAID.X ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD R0, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; @P0 EXIT ; BSSY B0, 0x5f0 ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; IMAD R2, R0, 0x20, R3.reuse ; IMAD.MOV.U32 R6, RZ, RZ, R3 ; IADD3 R3, R3, 0x1, RZ ; LDS.U8 R2, [R2] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @P0 BRA 0x580 ; BSYNC B0 ; ISETP.NE.AND P0, PT, R6, RZ, PT ; BSSY B2, 0xe80 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; @!P0 BRA 0xe70 ; IADD3 R2, R6.reuse, -0x1, RZ ; BSSY B1, 0xde0 ; LOP3.LUT R3, R6, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; @!P0 BRA 0xdd0 ; IMAD.IADD R6, R6, 0x1, -R3 ; BSSY B0, 0xce0 ; IMAD.SHL.U32 R4, R0, 0x20, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; ISETP.GT.AND P0, PT, R6, RZ, PT ; @!P0 BRA 0xcd0 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; BSSY B3, 0xaa0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0xa90 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.IADD R9, R4, 0x1, R5 ; IADD3 R6, R6, -0x10, RZ ; IADD3 R5, R5, 0x10, RZ ; LDS R10, [R9] ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; LDS R14, [R9+0x4] ; LDS R7, [R9+0x8] ; LDS R8, [R9+0xc] ; PRMT R11, R10.reuse, 0x8880, RZ ; PRMT R12, R10, 0x9991, RZ ; PRMT R13, R10, 0xaaa2, RZ ; IMAD R11, R2, 0x1f, R11 ; PRMT R10, R10, 0xbbb3, RZ ; PRMT R9, R14.reuse, 0x8880, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R13 ; IMAD R11, R11, 0x1f, R12 ; PRMT R12, R7, 0x9991, RZ ; IMAD.MOV.U32 R13, RZ, RZ, R10 ; PRMT R10, R14.reuse, 0xaaa2, RZ ; IMAD R2, R11, 0x1f, R2 ; PRMT R11, R14, 0x9991, RZ ; PRMT R14, R14, 0xbbb3, RZ ; IMAD R2, R2, 0x1f, R13 ; IMAD R2, R2, 0x1f, R9 ; IMAD.MOV.U32 R9, RZ, RZ, R10 ; PRMT R10, R7.reuse, 0x8880, RZ ; IMAD R2, R2, 0x1f, R11 ; IMAD.MOV.U32 R11, RZ, RZ, R14 ; IMAD R2, R2, 0x1f, R9 ; IMAD.MOV.U32 R9, RZ, RZ, R10 ; PRMT R10, R7, 0xaaa2, RZ ; IMAD R2, R2, 0x1f, R11 ; IMAD.MOV.U32 R11, RZ, RZ, R12 ; IMAD R2, R2, 0x1f, R9 ; PRMT R9, R7, 0xbbb3, RZ ; IMAD.MOV.U32 R7, RZ, RZ, R10 ; PRMT R10, R8, 0x8880, RZ ; IMAD R2, R2, 0x1f, R11 ; PRMT R11, R8, 0x9991, RZ ; IMAD R2, R2, 0x1f, R7 ; IMAD.MOV.U32 R7, RZ, RZ, R10 ; PRMT R10, R8, 0xaaa2, RZ ; IMAD R2, R2, 0x1f, R9 ; PRMT R8, R8, 0xbbb3, RZ ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; IMAD R2, R2, 0x1f, R7 ; IMAD.MOV.U32 R7, RZ, RZ, R10 ; IMAD R2, R2, 0x1f, R9 ; IMAD.MOV.U32 R9, RZ, RZ, R8 ; IMAD R2, R2, 0x1f, R7 ; IMAD R2, R2, 0x1f, R9 ; @P1 BRA 0x750 ; BSYNC B3 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; BSSY B3, 0xca0 ; @!P1 BRA 0xc90 ; IMAD.IADD R7, R5.reuse, 0x1, R4 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R6, R6, -0x8, RZ ; LDS R8, [R7] ; IADD3 R5, R5, 0x8, RZ ; LDS R11, [R7+0x4] ; PRMT R9, R8.reuse, 0x8880, RZ ; PRMT R10, R8.reuse, 0x9991, RZ ; PRMT R12, R8, 0xaaa2, RZ ; IMAD R9, R2, 0x1f, R9 ; PRMT R8, R8, 0xbbb3, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R12 ; IMAD R9, R9, 0x1f, R10 ; PRMT R10, R11.reuse, 0x8880, RZ ; IMAD.MOV.U32 R7, RZ, RZ, R8 ; PRMT R8, R11, 0x9991, RZ ; IMAD R2, R9, 0x1f, R2 ; IMAD.MOV.U32 R9, RZ, RZ, R10 ; PRMT R10, R11.reuse, 0xaaa2, RZ ; IMAD R2, R2, 0x1f, R7 ; PRMT R11, R11, 0xbbb3, RZ ; IMAD.MOV.U32 R7, RZ, RZ, R8 ; IMAD R2, R2, 0x1f, R9 ; IMAD.MOV.U32 R9, RZ, RZ, R10 ; IMAD R2, R2, 0x1f, R7 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; IMAD R2, R2, 0x1f, R9 ; IMAD R2, R2, 0x1f, R7 ; BSYNC B3 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BREAK B0 ; @!P0 BRA 0xdd0 ; BSYNC B0 ; IMAD.IADD R9, R4, 0x1, R5 ; IADD3 R6, R6, -0x4, RZ ; IADD3 R5, R5, 0x4, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; LDS R9, [R9] ; PRMT R7, R9.reuse, 0x8880, RZ ; PRMT R8, R9, 0x9991, RZ ; PRMT R10, R9.reuse, 0xaaa2, RZ ; IMAD R7, R2, 0x1f, R7 ; PRMT R9, R9, 0xbbb3, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; IMAD R7, R7, 0x1f, R8 ; IMAD R2, R7, 0x1f, R2 ; IMAD R2, R2, 0x1f, R9 ; @P0 BRA 0xce0 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; @!P0 BRA 0xe70 ; IMAD R5, R0, 0x20, R5 ; LDS.S8 R7, [R5] ; IADD3 R3, R3, -0x1, RZ ; ISETP.NE.AND P0, PT, R3, RZ, PT ; IADD3 R5, R5, 0x1, RZ ; IMAD R2, R2, 0x1f, R7 ; @P0 BRA 0xe10 ; BSYNC B2 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R3, 0x1, PT ; @!P0 EXIT ; IADD3 R4, R3.reuse, -0x1, RZ ; UMOV UR4, URZ ; LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; @!P0 BRA 0x17a0 ; IADD3 R8, -R3, c[0x0][0x170], RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; ISETP.GT.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; @!P0 BRA 0x1620 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x1390 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R9, [R6.64] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64], R0 ; LDG.E R9, [R6.64+0x4] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x4], R0 ; LDG.E R9, [R6.64+0x8] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x8], R0 ; LDG.E R9, [R6.64+0xc] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0xc], R0 ; LDG.E R9, [R6.64+0x10] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x10], R0 ; LDG.E R9, [R6.64+0x14] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x14], R0 ; LDG.E R9, [R6.64+0x18] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x18], R0 ; LDG.E R9, [R6.64+0x1c] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x1c], R0 ; LDG.E R9, [R6.64+0x20] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x20], R0 ; LDG.E R9, [R6.64+0x24] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x24], R0 ; LDG.E R9, [R6.64+0x28] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x28], R0 ; LDG.E R9, [R6.64+0x2c] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x2c], R0 ; LDG.E R9, [R6.64+0x30] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x30], R0 ; LDG.E R9, [R6.64+0x34] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x34], R0 ; LDG.E R9, [R6.64+0x38] ; ISETP.NE.AND P1, PT, R2, R9, PT ; @!P1 STG.E [R4.64+0x38], R0 ; LDG.E R9, [R6.64+0x3c] ; IADD3 R8, R8, -0x10, RZ ; UIADD3 UR4, UR4, 0x10, URZ ; IADD3 R11, P2, R6, 0x40, RZ ; IMAD.X R12, RZ, RZ, R7, P2 ; IMAD.MOV.U32 R6, RZ, RZ, R11 ; IMAD.MOV.U32 R7, RZ, RZ, R12 ; ISETP.NE.AND P1, PT, R2, R9, PT ; IADD3 R9, P3, R4, 0x40, RZ ; IMAD.X R10, RZ, RZ, R5, P3 ; @!P1 STG.E [R4.64+0x3c], R0 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; IMAD.MOV.U32 R5, RZ, RZ, R10 ; @P1 BRA 0xfd0 ; ISETP.GT.AND P1, PT, R8, 0x4, PT ; @!P1 BRA 0x1600 ; LDG.E R9, [R6.64] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64], R0 ; LDG.E R9, [R6.64+0x4] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64+0x4], R0 ; LDG.E R9, [R6.64+0x8] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64+0x8], R0 ; LDG.E R9, [R6.64+0xc] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64+0xc], R0 ; LDG.E R9, [R6.64+0x10] ; IADD3 R10, P1, R6, 0x10, RZ ; IMAD.X R11, RZ, RZ, R7, P1 ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64+0x10], R0 ; LDG.E R9, [R10.64+0x4] ; IADD3 R12, P1, R4, 0x10, RZ ; IMAD.X R13, RZ, RZ, R5, P1 ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R12.64+0x4], R0 ; LDG.E R9, [R10.64+0x8] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R12.64+0x8], R0 ; LDG.E R7, [R10.64+0xc] ; IADD3 R6, P1, R10, 0x10, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R4, P2, R12, 0x10, RZ ; IADD3 R8, R8, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IMAD.X R5, RZ, RZ, R13, P2 ; IADD3 R8, R8, -0x4, RZ ; ISETP.NE.AND P0, PT, R2, R7, PT ; IMAD.X R7, RZ, RZ, R11, P1 ; @!P0 STG.E [R12.64+0xc], R0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; ISETP.NE.OR P0, PT, R8, RZ, P0 ; @!P0 BRA 0x17a0 ; LDG.E R9, [R6.64] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64], R0 ; LDG.E R9, [R6.64+0x4] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64+0x4], R0 ; LDG.E R9, [R6.64+0x8] ; ISETP.NE.AND P0, PT, R2, R9, PT ; @!P0 STG.E [R4.64+0x8], R0 ; LDG.E R9, [R6.64+0xc] ; IADD3 R8, R8, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R11, P1, R6, 0x10, RZ ; IMAD.X R12, RZ, RZ, R7, P1 ; IMAD.MOV.U32 R6, RZ, RZ, R11 ; IMAD.MOV.U32 R7, RZ, RZ, R12 ; ISETP.NE.AND P0, PT, R2, R9, PT ; IADD3 R9, P2, R4, 0x10, RZ ; IMAD.X R10, RZ, RZ, R5, P2 ; @!P0 STG.E [R4.64+0xc], R0 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; IMAD.MOV.U32 R5, RZ, RZ, R10 ; @P0 BRA 0x1620 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; @!P0 EXIT ; UMOV UR5, 0x4 ; ULDC.64 UR6, c[0x0][0x178] ; ULDC.64 UR8, c[0x0][0x168] ; UIMAD.WIDE UR6, UR4, UR5, UR6 ; UIMAD.WIDE UR4, UR4, UR5, UR8 ; IMAD.U32 R5, RZ, RZ, UR5 ; IMAD.U32 R4, RZ, RZ, UR4 ; LDG.E R5, [R4.64] ; IMAD.U32 R6, RZ, RZ, UR6 ; IADD3 R3, R3, -0x1, RZ ; IMAD.U32 R7, RZ, RZ, UR7 ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; UIADD3 UR4, UP1, UR4, 0x4, URZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; ISETP.NE.AND P0, PT, R2, R5, PT ; @!P0 STG.E [R6.64], R0 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; @P0 BRA 0x1810 ; EXIT ; BRA 0x1900; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z22dictionaryAttackKernelPKcPKiiiPi ; -- Begin function _Z22dictionaryAttackKernelPKcPKiiiPi .globl _Z22dictionaryAttackKernelPKcPKiiiPi .p2align 8 .type _Z22dictionaryAttackKernelPKcPKiiiPi,@function _Z22dictionaryAttackKernelPKcPKiiiPi: ; @_Z22dictionaryAttackKernelPKcPKiiiPi ; %bb.0: s_clause 0x2 s_load_b64 s[8:9], s[0:1], 0x10 s_load_b32 s2, s[0:1], 0x2c s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s11, exec_lo s_waitcnt lgkmcnt(0) s_lshl_b32 s10, s9, 5 s_and_b32 s3, s2, 0xffff v_cmpx_gt_i32_e64 s10, v0 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph.preheader v_add_co_u32 v1, s2, s4, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v2, null, s5, 0, s2 v_mov_b32_e32 v3, v0 s_mov_b32 s4, 0 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_u8 v4, v[1:2], off v_add_nc_u32_e32 v5, 0, v3 v_add_nc_u32_e32 v3, s3, v3 v_add_co_u32 v1, s2, v1, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v2, s2, 0, v2, s2 v_cmp_le_i32_e32 vcc_lo, s10, v3 s_or_b32 s4, vcc_lo, s4 s_waitcnt vmcnt(0) ds_store_b8 v5, v4 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow74 s_or_b32 exec_lo, exec_lo, s11 v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1] s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s9, v1 s_cbranch_execz .LBB0_15 ; %bb.4: v_lshl_add_u32 v2, v1, 5, 0 s_mov_b32 s2, 0 s_mov_b32 s3, -1 .LBB0_5: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v0, s3, v2 s_add_i32 s3, s3, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) v_mov_b32_e32 v3, s3 ds_load_u8 v0, v0 offset:1 s_waitcnt lgkmcnt(0) v_cmp_eq_u16_e32 vcc_lo, 0, v0 s_or_b32 s2, vcc_lo, s2 s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_5 ; %bb.6: ; %.preheader37 s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v0, 0 s_mov_b32 s3, 0 s_mov_b32 s2, exec_lo v_cmpx_ne_u32_e32 0, v3 s_cbranch_execz .LBB0_10 ; %bb.7: ; %.lr.ph41.preheader v_mov_b32_e32 v0, 0 s_mov_b32 s4, 0 .LBB0_8: ; %.lr.ph41 ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v4, s4, v2 s_add_i32 s4, s4, 1 v_cmp_ge_u32_e32 vcc_lo, s4, v3 ds_load_i8 v4, v4 s_or_b32 s3, vcc_lo, s3 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[5:6], null, v0, 31, v[4:5] s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v0, v5 s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_8 ; %bb.9: ; %Flow70 s_or_b32 exec_lo, exec_lo, s3 .LBB0_10: ; %Flow71 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 s_cmp_lt_i32 s8, 1 s_cbranch_scc1 .LBB0_15 ; %bb.11: ; %.lr.ph43.preheader s_load_b64 s[0:1], s[0:1], 0x18 v_mov_b32_e32 v2, 0 .LBB0_12: ; %.lr.ph43 ; =>This Inner Loop Header: Depth=1 global_load_b32 v3, v2, s[6:7] s_mov_b32 s2, exec_lo s_waitcnt vmcnt(0) v_cmpx_eq_u32_e64 v0, v3 s_cbranch_execz .LBB0_14 ; %bb.13: ; in Loop: Header=BB0_12 Depth=1 s_waitcnt lgkmcnt(0) global_store_b32 v2, v1, s[0:1] .LBB0_14: ; in Loop: Header=BB0_12 Depth=1 s_or_b32 exec_lo, exec_lo, s2 s_add_i32 s8, s8, -1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s8, 0 s_cbranch_scc1 .LBB0_12 .LBB0_15: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z22dictionaryAttackKernelPKcPKiiiPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z22dictionaryAttackKernelPKcPKiiiPi, .Lfunc_end0-_Z22dictionaryAttackKernelPKcPKiiiPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 468 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z22dictionaryAttackKernelPKcPKiiiPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z22dictionaryAttackKernelPKcPKiiiPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000756ec_00000000-6_cuda_code_032639.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi .type _Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi, @function _Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi: .LFB3660: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movl %edx, 12(%rsp) leaq 32(%rsp), %rdx movl %ecx, 8(%rsp) leaq 40(%rsp), %rcx movq %r8, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 40(%rsp) .cfi_def_cfa_offset 168 leaq _Z22dictionaryAttackKernelPKcPKiiiPi(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 176 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L2: movq 136(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi, .-_Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi .globl _Z22dictionaryAttackKernelPKcPKiiiPi .type _Z22dictionaryAttackKernelPKcPKiiiPi, @function _Z22dictionaryAttackKernelPKcPKiiiPi: .LFB3661: .cfi_startproc endbr64 jmp _Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi .cfi_endproc .LFE3661: .size _Z22dictionaryAttackKernelPKcPKiiiPi, .-_Z22dictionaryAttackKernelPKcPKiiiPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "password123" .LC1: .string "hello" .LC2: .string "world" .LC3: .string "secret" .LC4: .string "example" .LC5: .string "test" .LC6: .string "cuda" .LC7: .string "kernel" .LC8: .string "optimization" .LC9: .string "ampere" .LC10: .string "CUDA error: " .LC11: .string "Hash " .LC12: .string " matches word: " .LC13: .string " not found in dictionary." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 leaq -798720(%rsp), %r11 .cfi_def_cfa 11, 798768 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $1360, %rsp .cfi_def_cfa_offset 800128 movl $200000, %ecx movl $3200000, %esi xorl %ebx, %ebx movq %fs:40, %rax movq %rax, 800072(%rsp) xorl %eax, %eax leaq 72(%rsp), %rdi leaq 72(%rsp), %r12 rep stosl leaq .LC0(%rip), %rax leaq 8(%rsp), %rdi movq %rax, 72(%rsp) leaq .LC1(%rip), %rax movq %rax, 80(%rsp) leaq .LC2(%rip), %rax movq %rax, 88(%rsp) leaq .LC3(%rip), %rax movq %rax, 96(%rsp) leaq .LC4(%rip), %rax movq %rax, 104(%rsp) leaq .LC5(%rip), %rax movq %rax, 112(%rsp) leaq .LC6(%rip), %rax movq %rax, 120(%rsp) leaq .LC7(%rip), %rax movq %rax, 128(%rsp) leaq .LC8(%rip), %rax movq %rax, 136(%rsp) leaq .LC9(%rip), %rax movq %rax, 144(%rsp) movabsq $4241943008571542805, %rax movq %rax, 56(%rsp) call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $8, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $8, %esi call cudaMalloc@PLT movl $3200000, %edi call _Znam@PLT movq %rax, %rbp .L9: movq %rbx, %rdi movq (%r12,%rbx,8), %rsi movl $32, %edx incq %rbx salq $5, %rdi addq %rbp, %rdi call strncpy@PLT cmpq $100000, %rbx jne .L9 movq 8(%rsp), %rdi movl $1, %ecx movl $3200000, %edx movq %rbp, %rsi leaq 56(%rsp), %r12 call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $8, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi orl $-1, %esi movl $8, %edx call cudaMemset@PLT movl $16777217, %edx xorl %r9d, %r9d movabsq $4294967687, %rdi salq $8, %rdx movl $3200000, %r8d movl $1, %ecx movl $1, %esi movq %rdx, 44(%rsp) movl $1, 52(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L10 movq 24(%rsp), %r8 movq 16(%rsp), %rsi movl $100000, %ecx movl $2, %edx movq 8(%rsp), %rdi call _Z50__device_stub__Z22dictionaryAttackKernelPKcPKiiiPiPKcPKiiiPi .L10: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L11 leaq .LC10(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L11: movq 24(%rsp), %rsi leaq 64(%rsp), %r13 movl $2, %ecx xorl %ebx, %ebx movl $8, %edx movq %r13, %rdi leaq .LC11(%rip), %r14 call cudaMemcpy@PLT .L15: cmpl $-1, 0(%r13,%rbx) movq %r14, %rsi leaq _ZSt4cout(%rip), %rdi je .L13 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl (%r12,%rbx), %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC12(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movslq 0(%r13,%rbx), %rax movq 72(%rsp,%rax,8), %rsi jmp .L20 .L13: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl (%r12,%rbx), %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC13(%rip), %rsi movq %rax, %rdi .L20: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT cmpq $4, %rbx je .L21 movl $4, %ebx jmp .L15 .L21: movq %rbp, %rdi call _ZdaPv@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L8: movq 800072(%rsp), %rdx subq %fs:40, %rdx je .L16 call __stack_chk_fail@PLT .L16: addq $800080, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC14: .string "_Z22dictionaryAttackKernelPKcPKiiiPi" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rax, %rdi leaq _Z22dictionaryAttackKernelPKcPKiiiPi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_032639.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi # -- Begin function _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi .type _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi,@function _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi: # @_Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 4(%rsp), %rsi movl %edx, (%rsi) movq %rsp, %rdx movl %ecx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z22dictionaryAttackKernelPKcPKiiiPi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $144, %rsp .cfi_adjust_cfa_offset -144 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi, .Lfunc_end0-_Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset %rbp, -16 movq %rsp, %rbp .cfi_def_cfa_register %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $56, %rsp .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 movabsq $4241943008571542805, %rax # imm = 0x3ADE68B1075BCD15 movq %rax, -72(%rbp) leaq -64(%rbp), %rdi movl $3200000, %esi # imm = 0x30D400 callq hipMalloc leaq -56(%rbp), %rdi movl $8, %esi callq hipMalloc leaq -48(%rbp), %rdi movl $8, %esi callq hipMalloc movl $3200000, %edi # imm = 0x30D400 callq _Znam movq %rax, %rbx movq $-800000, %r15 # imm = 0xFFF3CB00 movq %rax, %r14 .LBB1_1: # =>This Inner Loop Header: Depth=1 movq .L__const.main.h_dictionary+800000(%r15), %rsi movl $32, %edx movq %r14, %rdi callq strncpy addq $32, %r14 addq $8, %r15 jne .LBB1_1 # %bb.2: movq -64(%rbp), %rdi movl $3200000, %edx # imm = 0x30D400 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq -56(%rbp), %rdi leaq -72(%rbp), %rsi movl $8, %edx movl $1, %ecx callq hipMemcpy movq -48(%rbp), %rdi movl $8, %edx movl $-1, %esi callq hipMemset movabsq $4294967552, %rdx # imm = 0x100000100 leaq 135(%rdx), %rdi movl $3200000, %r8d # imm = 0x30D400 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq -64(%rbp), %rdi movq -56(%rbp), %rsi movq -48(%rbp), %r8 movl $2, %edx movl $100000, %ecx # imm = 0x186A0 callq _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi .LBB1_4: callq hipGetLastError testl %eax, %eax je .LBB1_9 # %bb.5: movl %eax, %r14d movl $_ZSt4cerr, %edi movl $.L.str.10, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %r14d, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_6 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_8 .LBB1_9: movq %rbx, -88(%rbp) # 8-byte Spill movq %rsp, -80(%rbp) # 8-byte Spill movq %rsp, %r14 addq $-16, %r14 movq %r14, %rsp movq -48(%rbp), %rsi movl $8, %edx movq %r14, %rdi movl $2, %ecx callq hipMemcpy movb $1, %r13b xorl %r12d, %r12d .LBB1_10: # =>This Inner Loop Header: Depth=1 movl (%r14,%r12,4), %ebx movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $5, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl -72(%rbp,%r12,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %r15 cmpl $-1, %ebx je .LBB1_14 # %bb.11: # in Loop: Header=BB1_10 Depth=1 movl $.L.str.12, %esi movl $15, %edx movq %r15, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movslq (%r14,%r12,4), %rax movq .L__const.main.h_dictionary(,%rax,8), %r12 testq %r12, %r12 je .LBB1_12 # %bb.13: # in Loop: Header=BB1_10 Depth=1 movq %r12, %rdi callq strlen movq %r15, %rdi movq %r12, %rsi movq %rax, %rdx jmp .LBB1_15 .LBB1_14: # in Loop: Header=BB1_10 Depth=1 movl $.L.str.13, %esi movl $25, %edx movq %r15, %rdi .LBB1_15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit42 # in Loop: Header=BB1_10 Depth=1 callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_16 .LBB1_12: # in Loop: Header=BB1_10 Depth=1 movq (%r15), %rax movq -24(%rax), %rax movq %r15, %rdi addq %rax, %rdi movl 32(%r15,%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit42 # in Loop: Header=BB1_10 Depth=1 movq (%r15), %rax movq -24(%rax), %rdi addq %r15, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $1, %r12d xorl %r15d, %r15d testb $1, %r13b movl $0, %r13d jne .LBB1_10 # %bb.17: movq -88(%rbp), %rdi # 8-byte Reload callq _ZdaPv movq -64(%rbp), %rdi callq hipFree movq -56(%rbp), %rdi callq hipFree movq -48(%rbp), %rdi callq hipFree movq -80(%rbp), %rsp # 8-byte Reload jmp .LBB1_18 .LBB1_6: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %r15d .LBB1_18: movl %r15d, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_def_cfa %rsp, 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z22dictionaryAttackKernelPKcPKiiiPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z22dictionaryAttackKernelPKcPKiiiPi,@object # @_Z22dictionaryAttackKernelPKcPKiiiPi .section .rodata,"a",@progbits .globl _Z22dictionaryAttackKernelPKcPKiiiPi .p2align 3, 0x0 _Z22dictionaryAttackKernelPKcPKiiiPi: .quad _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi .size _Z22dictionaryAttackKernelPKcPKiiiPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "password123" .size .L.str, 12 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "hello" .size .L.str.1, 6 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "world" .size .L.str.2, 6 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "secret" .size .L.str.3, 7 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "example" .size .L.str.4, 8 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "test" .size .L.str.5, 5 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "cuda" .size .L.str.6, 5 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "kernel" .size .L.str.7, 7 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "optimization" .size .L.str.8, 13 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "ampere" .size .L.str.9, 7 .type .L__const.main.h_dictionary,@object # @__const.main.h_dictionary .section .rodata,"a",@progbits .p2align 4, 0x0 .L__const.main.h_dictionary: .quad .L.str .quad .L.str.1 .quad .L.str.2 .quad .L.str.3 .quad .L.str.4 .quad .L.str.5 .quad .L.str.6 .quad .L.str.7 .quad .L.str.8 .quad .L.str.9 .zero 799920 .size .L__const.main.h_dictionary, 800000 .type .L.str.10,@object # @.str.10 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.10: .asciz "CUDA error: " .size .L.str.10, 13 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Hash " .size .L.str.11, 6 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz " matches word: " .size .L.str.12, 16 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz " not found in dictionary." .size .L.str.13, 26 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z22dictionaryAttackKernelPKcPKiiiPi" .size .L__unnamed_1, 37 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z37__device_stub__dictionaryAttackKernelPKcPKiiiPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z22dictionaryAttackKernelPKcPKiiiPi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,443
5,840
113,438
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z19graphColoringKernelPjS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R6, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R6, 0x1ff, PT ; @P0 EXIT ; BSSY B0, 0x740 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; IMAD R3, R6, 0x200, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; LDG.E R4, [R2.64] ; ISETP.NE.AND P0, PT, R4, RZ, PT ; IMAD.WIDE R4, R7, R8, c[0x0][0x168] ; @!P0 BRA 0x140 ; LDG.E R9, [R4.64] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x4] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x1a0 ; LDG.E R9, [R4.64+0x4] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x8] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x200 ; LDG.E R9, [R4.64+0x8] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0xc] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x260 ; LDG.E R9, [R4.64+0xc] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x10] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x2c0 ; LDG.E R9, [R4.64+0x10] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x14] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x320 ; LDG.E R9, [R4.64+0x14] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x18] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x380 ; LDG.E R9, [R4.64+0x18] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x1c] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x3e0 ; LDG.E R9, [R4.64+0x1c] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x20] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x440 ; LDG.E R9, [R4.64+0x20] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x24] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x4a0 ; LDG.E R9, [R4.64+0x24] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x28] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x500 ; LDG.E R9, [R4.64+0x28] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x2c] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x560 ; LDG.E R9, [R4.64+0x2c] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x30] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x5c0 ; LDG.E R9, [R4.64+0x30] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x34] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x620 ; LDG.E R9, [R4.64+0x34] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R9, [R2.64+0x38] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x680 ; LDG.E R9, [R4.64+0x38] ; ISETP.NE.AND P0, PT, R9, R0, PT ; @!P0 BRA 0x6e0 ; LDG.E R2, [R2.64+0x3c] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 BRA 0x700 ; LDG.E R5, [R4.64+0x3c] ; ISETP.NE.AND P0, PT, R5, R0, PT ; @P0 BRA 0x700 ; IADD3 R0, R0, 0x1, RZ ; BRA 0x90 ; IADD3 R7, R7, 0x10, RZ ; ISETP.GE.U32.AND P0, PT, R7, 0x200, PT ; @!P0 BRA 0xa0 ; BSYNC B0 ; IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; STG.E [R6.64], R0 ; EXIT ; BRA 0x770; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z15initGraphKernelPjP17curandStateXORWOW .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R7, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R7, R7, c[0x0][0x0], R0 ; ISETP.GT.AND P0, PT, R7, 0x1ff, PT ; @P0 EXIT ; IMAD.MOV.U32 R28, RZ, RZ, 0x30 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R28, R7, R28, c[0x0][0x168] ; LDG.E R6, [R28.64+0x20] ; LDG.E.64 R20, [R28.64+0x28] ; LDG.E.64 R18, [R28.64] ; LDG.E.64 R16, [R28.64+0x8] ; LDG.E.64 R14, [R28.64+0x10] ; LDG.E.64 R12, [R28.64+0x18] ; IMAD.SHL.U32 R4, R7, 0x200, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IMAD R10, R7, 0x201, RZ ; IADD3 R2, R4.reuse, 0x1, RZ ; IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; IMAD.MOV.U32 R8, RZ, RZ, R2 ; IMAD.MOV.U32 R9, RZ, RZ, R3 ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; IMAD.MOV R2, RZ, RZ, -R7 ; IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; BSSY B0, 0x470 ; @!P0 BRA 0x3f0 ; SHF.R.U32.HI R0, RZ, 0x2, R19 ; BSSY B1, 0x3c0 ; SHF.L.U32 R22, R15, 0x4, RZ ; IMAD.MOV.U32 R23, RZ, RZ, R14 ; LOP3.LUT R0, R0, R19, RZ, 0x3c, !PT ; IADD3 R24, R18, 0x587c5, RZ ; LOP3.LUT R22, R0, R22, R15, 0x96, !PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.IADD R19, R22, 0x1, R24 ; LOP3.LUT R19, R19, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P1, PT, R19, 0x1, PT ; IMAD.SHL.U32 R19, R0, 0x2, RZ ; IMAD.MOV.U32 R0, RZ, RZ, R17 ; LOP3.LUT R19, R22, R19, RZ, 0x3c, !PT ; IMAD.MOV.U32 R25, RZ, RZ, R19 ; @P1 BRA 0x3b0 ; SHF.R.U32.HI R23, RZ, 0x2, R16 ; IADD3 R24, R18, 0xb0f8a, RZ ; LOP3.LUT R0, R23, R16, RZ, 0x3c, !PT ; MOV R23, R15 ; IMAD.MOV.U32 R15, RZ, RZ, R19 ; IMAD.SHL.U32 R16, R0, 0x2, RZ ; LOP3.LUT R25, R19, R16, R0, 0x96, !PT ; IMAD.IADD R0, R25, 0x1, R24 ; LOP3.LUT R16, R0, 0x1, RZ, 0xc0, !PT ; IMAD.SHL.U32 R0, R19, 0x10, RZ ; ISETP.EQ.U32.AND P0, PT, R16, 0x1, PT ; IMAD.MOV.U32 R16, RZ, RZ, R17 ; LOP3.LUT R25, R25, R0, RZ, 0x3c, !PT ; IMAD.MOV.U32 R0, RZ, RZ, R14 ; BSYNC B1 ; SEL R17, RZ, 0x1, !P0 ; STG.E [R4.64], R17 ; BRA 0x460 ; STG.E [R10.64], RZ ; IMAD.MOV.U32 R25, RZ, RZ, R15 ; IMAD.MOV.U32 R0, RZ, RZ, R16 ; MOV R16, R19 ; IMAD.MOV.U32 R15, RZ, RZ, R14 ; IMAD.MOV.U32 R23, RZ, RZ, R17 ; IMAD.MOV.U32 R24, RZ, RZ, R18 ; BSYNC B0 ; IADD3 R14, R3, 0x1, RZ ; BSSY B0, 0x760 ; ISETP.NE.AND P0, PT, R14, R7, PT ; @!P0 BRA 0x6e0 ; SHF.R.U32.HI R17, RZ, 0x2, R16 ; IMAD.SHL.U32 R18, R25, 0x10, RZ ; BSSY B1, 0x6b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.MOV.U32 R22, RZ, RZ, R23 ; LOP3.LUT R14, R17, R16, RZ, 0x3c, !PT ; IADD3 R16, R24, 0x587c5, RZ ; LOP3.LUT R18, R14.reuse, R18, R25, 0x96, !PT ; IMAD.SHL.U32 R19, R14, 0x2, RZ ; IMAD.IADD R17, R18.reuse, 0x1, R16 ; LOP3.LUT R19, R18, R19, RZ, 0x3c, !PT ; IMAD.MOV.U32 R18, RZ, RZ, R25 ; LOP3.LUT R17, R17, 0x1, RZ, 0xc0, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R19 ; ISETP.NE.U32.AND P1, PT, R17, 0x1, PT ; IMAD.MOV.U32 R17, RZ, RZ, R15 ; @P1 BRA 0x6a0 ; SHF.R.U32.HI R17, RZ, 0x2, R0 ; IMAD.MOV.U32 R22, RZ, RZ, R15 ; IADD3 R16, R24, 0xb0f8a, RZ ; IMAD.MOV.U32 R18, RZ, RZ, R19 ; LOP3.LUT R0, R17, R0, RZ, 0x3c, !PT ; IMAD.MOV.U32 R17, RZ, RZ, R25 ; SHF.L.U32 R14, R0, 0x1, RZ ; LOP3.LUT R27, R19.reuse, R14, R0, 0x96, !PT ; IMAD.SHL.U32 R14, R19, 0x10, RZ ; IMAD.IADD R0, R27.reuse, 0x1, R16 ; LOP3.LUT R14, R27, R14, RZ, 0x3c, !PT ; LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; ISETP.EQ.U32.AND P0, PT, R0, 0x1, PT ; IMAD.MOV.U32 R0, RZ, RZ, R23 ; BSYNC B1 ; SEL R15, RZ, 0x1, !P0 ; STG.E [R8.64], R15 ; BRA 0x750 ; STG.E [R10.64], RZ ; MOV R22, R0 ; IMAD.MOV.U32 R0, RZ, RZ, R16 ; IMAD.MOV.U32 R14, RZ, RZ, R25 ; IMAD.MOV.U32 R18, RZ, RZ, R15 ; IMAD.MOV.U32 R17, RZ, RZ, R23 ; IMAD.MOV.U32 R16, RZ, RZ, R24 ; BSYNC B0 ; IADD3 R24, R3, 0x2, RZ ; BSSY B0, 0xa50 ; ISETP.NE.AND P0, PT, R24, R7, PT ; @!P0 BRA 0x9d0 ; SHF.R.U32.HI R15, RZ, 0x2, R0 ; IMAD.SHL.U32 R19, R14, 0x10, RZ ; IADD3 R23, R16, 0x587c5, RZ ; BSSY B1, 0x9a0 ; LOP3.LUT R15, R15, R0, RZ, 0x3c, !PT ; IMAD.MOV.U32 R24, RZ, RZ, R18 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LOP3.LUT R19, R15, R19, R14, 0x96, !PT ; MOV R25, R14 ; IMAD.IADD R0, R19, 0x1, R23 ; LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ; IMAD.SHL.U32 R0, R15, 0x2, RZ ; LOP3.LUT R0, R19, R0, RZ, 0x3c, !PT ; IMAD.MOV.U32 R19, RZ, RZ, R17 ; IMAD.MOV.U32 R26, RZ, RZ, R0 ; @P1 BRA 0x990 ; SHF.R.U32.HI R15, RZ, 0x2, R22 ; IMAD.MOV.U32 R24, RZ, RZ, R14 ; IADD3 R23, R16, 0xb0f8a, RZ ; LOP3.LUT R15, R15, R22, RZ, 0x3c, !PT ; IMAD.MOV.U32 R22, RZ, RZ, R17 ; MOV R25, R0 ; IMAD.SHL.U32 R19, R15, 0x2, RZ ; LOP3.LUT R26, R0, R19, R15, 0x96, !PT ; IMAD.MOV.U32 R19, RZ, RZ, R18 ; IMAD.IADD R15, R26, 0x1, R23 ; LOP3.LUT R16, R15, 0x1, RZ, 0xc0, !PT ; IMAD.SHL.U32 R15, R0, 0x10, RZ ; ISETP.EQ.U32.AND P0, PT, R16, 0x1, PT ; LOP3.LUT R26, R26, R15, RZ, 0x3c, !PT ; BSYNC B1 ; SEL R15, RZ, 0x1, !P0 ; STG.E [R8.64+0x4], R15 ; BRA 0xa40 ; STG.E [R10.64], RZ ; IMAD.MOV.U32 R19, RZ, RZ, R22 ; MOV R22, R0 ; IMAD.MOV.U32 R26, RZ, RZ, R14 ; IMAD.MOV.U32 R25, RZ, RZ, R18 ; IMAD.MOV.U32 R24, RZ, RZ, R17 ; IMAD.MOV.U32 R23, RZ, RZ, R16 ; BSYNC B0 ; IADD3 R0, R3, 0x3, RZ ; BSSY B0, 0xd40 ; ISETP.NE.AND P0, PT, R0, R7, PT ; @!P0 BRA 0xcc0 ; SHF.R.U32.HI R15, RZ, 0x2, R22 ; IMAD.SHL.U32 R0, R26, 0x10, RZ ; IADD3 R18, R23, 0x587c5, RZ ; BSSY B1, 0xc90 ; LOP3.LUT R15, R15, R22, RZ, 0x3c, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R26 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.MOV.U32 R16, RZ, RZ, R24 ; LOP3.LUT R17, R15, R0, R26, 0x96, !PT ; IMAD.IADD R0, R17, 0x1, R18 ; LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ; IMAD.SHL.U32 R0, R15, 0x2, RZ ; LOP3.LUT R0, R17, R0, RZ, 0x3c, !PT ; IMAD.MOV.U32 R17, RZ, RZ, R25 ; IMAD.MOV.U32 R15, RZ, RZ, R0 ; @P1 BRA 0xc80 ; SHF.R.U32.HI R14, RZ, 0x2, R19 ; IMAD.MOV.U32 R17, RZ, RZ, R26 ; IADD3 R18, R23, 0xb0f8a, RZ ; LOP3.LUT R15, R14, R19, RZ, 0x3c, !PT ; IMAD.MOV.U32 R19, RZ, RZ, R24 ; SHF.L.U32 R14, R15, 0x1, RZ ; LOP3.LUT R15, R0, R14, R15, 0x96, !PT ; IMAD.IADD R14, R15, 0x1, R18 ; LOP3.LUT R16, R14, 0x1, RZ, 0xc0, !PT ; IMAD.SHL.U32 R14, R0, 0x10, RZ ; ISETP.EQ.U32.AND P0, PT, R16, 0x1, PT ; IMAD.MOV.U32 R16, RZ, RZ, R25 ; LOP3.LUT R15, R15, R14, RZ, 0x3c, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R0 ; BSYNC B1 ; SEL R23, RZ, 0x1, !P0 ; STG.E [R8.64+0x8], R23 ; BRA 0xd30 ; STG.E [R10.64], RZ ; IMAD.MOV.U32 R16, RZ, RZ, R19 ; MOV R14, R25 ; IMAD.MOV.U32 R15, RZ, RZ, R26 ; IMAD.MOV.U32 R17, RZ, RZ, R24 ; IMAD.MOV.U32 R18, RZ, RZ, R23 ; IMAD.MOV.U32 R19, RZ, RZ, R22 ; BSYNC B0 ; IADD3 R3, R3, 0x4, RZ ; IADD3 R4, P2, R4, 0x10, RZ ; ISETP.NE.AND P0, PT, R3, 0x200, PT ; IADD3 R8, P1, R8, 0x10, RZ ; IMAD.X R5, RZ, RZ, R5, P2 ; IADD3 R2, R2, 0x4, RZ ; IMAD.X R9, RZ, RZ, R9, P1 ; @P0 BRA 0x1a0 ; STG.E.64 [R28.64], R18 ; STG.E.64 [R28.64+0x8], R16 ; STG.E.64 [R28.64+0x10], R14 ; STG.E.64 [R28.64+0x18], R12 ; STG.E.64 [R28.64+0x28], R20 ; STG.E [R28.64+0x20], R6 ; EXIT ; BRA 0xe30; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15initGraphKernelPjP12hiprandState ; -- Begin function _Z15initGraphKernelPjP12hiprandState .globl _Z15initGraphKernelPjP12hiprandState .p2align 8 .type _Z15initGraphKernelPjP12hiprandState,@function _Z15initGraphKernelPjP12hiprandState: ; @_Z15initGraphKernelPjP12hiprandState ; %bb.0: s_load_b32 s4, s[2:3], 0x1c v_and_b32_e32 v5, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[10:11], null, s15, s4, v[5:6] s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e32 0x200, v10 s_cbranch_execz .LBB0_11 ; %bb.1: s_load_b128 s[4:7], s[2:3], 0x0 s_load_b64 s[0:1], s[0:1], 0x4 v_dual_mov_b32 v15, 0 :: v_dual_lshlrev_b32 v6, 9, v10 v_bfe_u32 v13, v0, 10, 10 v_lshl_add_u32 v14, v10, 9, v10 v_bfe_u32 v0, v0, 20, 10 s_delay_alu instid0(VALU_DEP_4) v_ashrrev_i32_e32 v7, 31, v6 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[8:9], null, v10, 48, s[6:7] s_lshr_b32 s0, s0, 16 v_mul_u32_u24_e32 v17, s1, v13 s_mul_i32 s0, s0, s1 v_lshlrev_b64 v[13:14], 2, v[14:15] v_mul_lo_u32 v16, s0, v5 v_lshlrev_b64 v[5:6], 2, v[6:7] s_clause 0x4 global_load_b32 v21, v[8:9], off global_load_b128 v[22:25], v[8:9], off offset:4 global_load_b32 v26, v[8:9], off offset:20 global_load_b64 v[11:12], v[8:9], off offset:40 global_load_b128 v[1:4], v[8:9], off offset:24 s_mov_b32 s0, 0 v_add3_u32 v0, v16, v17, v0 v_add_co_u32 v16, vcc_lo, s4, v13 v_add_co_ci_u32_e32 v17, vcc_lo, s5, v14, vcc_lo v_add_co_u32 v18, vcc_lo, s4, v5 s_delay_alu instid0(VALU_DEP_4) v_mul_lo_u32 v20, v0, 20 v_add_co_ci_u32_e32 v19, vcc_lo, s5, v6, vcc_lo v_add_co_u32 v13, vcc_lo, v8, 4 v_add_co_ci_u32_e32 v14, vcc_lo, 0, v9, vcc_lo s_waitcnt vmcnt(3) ds_store_2addr_b32 v20, v22, v23 offset1:1 ds_store_2addr_b32 v20, v24, v25 offset0:2 offset1:3 s_waitcnt vmcnt(2) ds_store_b32 v20, v26 offset:16 .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_mov_b32 s1, exec_lo ; implicit-def: $vgpr22 ; implicit-def: $vgpr5 ; implicit-def: $vgpr0 v_cmpx_ne_u32_e64 s0, v10 s_xor_b32 s1, exec_lo, s1 s_cbranch_execz .LBB0_6 ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 s_waitcnt vmcnt(0) v_lshrrev_b32_e32 v0, 2, v1 v_dual_mov_b32 v7, v11 :: v_dual_add_nc_u32 v22, 0x587c5, v21 s_mov_b32 s3, 0 v_mov_b32_e32 v6, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v0, v0, v1 v_lshlrev_b32_e32 v1, 4, v11 v_lshlrev_b32_e32 v5, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v1, v1, v5 v_xor3_b32 v1, v1, v11, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v1, v22 v_dual_mov_b32 v0, v1 :: v_dual_and_b32 v5, 1, v0 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v5 v_mov_b32_e32 v5, v3 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_5 ; %bb.4: ; in Loop: Header=BB0_2 Depth=1 v_lshrrev_b32_e32 v0, 2, v2 v_dual_mov_b32 v7, v1 :: v_dual_add_nc_u32 v22, 0xb0f8a, v21 v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v0, v0, v2 v_lshlrev_b32_e32 v2, 4, v1 v_lshlrev_b32_e32 v5, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v2, v5, v2 v_mov_b32_e32 v5, v4 v_xor3_b32 v0, v2, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v0, v21 v_and_b32_e32 v2, 1, v2 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v2 v_mov_b32_e32 v2, v3 s_and_b32 s3, vcc_lo, exec_lo .LBB0_5: ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s2 v_cndmask_b32_e64 v1, 0, 1, s3 ; implicit-def: $vgpr21 global_store_b32 v[18:19], v1, off .LBB0_6: ; %Flow ; in Loop: Header=BB0_2 Depth=1 s_and_not1_saveexec_b32 s1, s1 s_cbranch_execz .LBB0_8 ; %bb.7: ; in Loop: Header=BB0_2 Depth=1 s_waitcnt vmcnt(0) v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v7, v4 v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v5, v2 v_mov_b32_e32 v2, v1 v_mov_b32_e32 v22, v21 global_store_b32 v[16:17], v15, off .LBB0_8: ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v18, vcc_lo, v18, 4 v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmpk_eq_i32 s0, 0x200 s_cbranch_scc1 .LBB0_10 ; %bb.9: ; in Loop: Header=BB0_2 Depth=1 v_mov_b32_e32 v21, v22 s_waitcnt vmcnt(0) v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v4, v7 v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v3, v6 v_mov_b32_e32 v11, v0 s_branch .LBB0_2 .LBB0_10: s_waitcnt vmcnt(0) ds_load_b32 v3, v20 offset:16 ds_load_2addr_b32 v[17:18], v20 offset0:2 offset1:3 ds_load_2addr_b32 v[15:16], v20 offset1:1 v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v1, v12 s_clause 0x1 global_store_b32 v[8:9], v22, off global_store_b128 v[8:9], v[4:7], off offset:24 s_waitcnt lgkmcnt(2) global_store_b32 v[13:14], v3, off offset:16 s_waitcnt lgkmcnt(0) s_clause 0x1 global_store_b128 v[13:14], v[15:18], off global_store_b64 v[8:9], v[0:1], off offset:40 .LBB0_11: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15initGraphKernelPjP12hiprandState .amdhsa_group_segment_fixed_size 20480 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 1 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 27 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15initGraphKernelPjP12hiprandState, .Lfunc_end0-_Z15initGraphKernelPjP12hiprandState ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 732 ; NumSgprs: 18 ; NumVgprs: 27 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 20480 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 3 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 27 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .protected _Z19graphColoringKernelPjS_ ; -- Begin function _Z19graphColoringKernelPjS_ .globl _Z19graphColoringKernelPjS_ .p2align 8 .type _Z19graphColoringKernelPjS_,@function _Z19graphColoringKernelPjS_: ; @_Z19graphColoringKernelPjS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x1c s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x200, v1 s_cbranch_execz .LBB1_13 ; %bb.1: ; %.preheader s_load_b128 s[0:3], s[0:1], 0x0 v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 9, v1 v_ashrrev_i32_e32 v2, 31, v1 v_mov_b32_e32 v7, 0 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo .LBB1_2: ; =>This Loop Header: Depth=1 ; Child Loop BB1_3 Depth 2 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_mov_b32 s7, 0 s_mov_b64 s[0:1], s[2:3] s_mov_b32 s11, -1 s_mov_b32 s13, 0 ; implicit-def: $sgpr6 ; implicit-def: $sgpr5 ; implicit-def: $sgpr8 ; implicit-def: $sgpr10 ; implicit-def: $sgpr12 ; implicit-def: $sgpr9 .LBB1_3: ; Parent Loop BB1_2 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b32 v8, v[4:5], off s_mov_b32 s14, -1 s_mov_b32 s16, -1 s_mov_b32 s17, exec_lo ; implicit-def: $sgpr15 s_waitcnt vmcnt(0) v_cmpx_ne_u32_e32 0, v8 s_cbranch_execz .LBB1_5 ; %bb.4: ; in Loop: Header=BB1_3 Depth=2 global_load_b32 v8, v7, s[0:1] s_mov_b32 s15, -1 s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, v8, v6 s_or_not1_b32 s16, vcc_lo, exec_lo .LBB1_5: ; %Flow43 ; in Loop: Header=BB1_3 Depth=2 s_or_b32 exec_lo, exec_lo, s17 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 s9, s9, exec_lo s_and_b32 s15, s15, exec_lo s_and_not1_b32 s12, s12, exec_lo s_or_b32 s9, s9, s15 s_and_b32 s15, s11, exec_lo s_and_not1_b32 s10, s10, exec_lo s_and_b32 s17, s0, exec_lo s_or_b32 s12, s12, s15 s_or_b32 s10, s10, s17 s_and_saveexec_b32 s15, s16 s_cbranch_execz .LBB1_7 ; %bb.6: ; in Loop: Header=BB1_3 Depth=2 s_add_i32 s16, s13, 1 s_cmpk_lt_u32 s13, 0x1ff v_add_co_u32 v4, vcc_lo, v4, 4 s_cselect_b32 s17, -1, 0 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmpk_eq_i32 s16, 0x200 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_cselect_b32 s13, -1, 0 s_and_not1_b32 s12, s12, exec_lo s_and_b32 s11, s11, exec_lo s_and_not1_b32 s10, s10, exec_lo s_and_b32 s14, s17, exec_lo s_and_not1_b32 s9, s9, exec_lo s_or_b32 s12, s12, s11 s_or_b32 s10, s10, s14 s_or_not1_b32 s14, s13, exec_lo s_mov_b32 s13, s16 s_mov_b32 s11, s17 .LBB1_7: ; %Flow44 ; in Loop: Header=BB1_3 Depth=2 s_or_b32 exec_lo, exec_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s14, exec_lo, s14 s_or_b32 s7, s14, s7 s_and_not1_b32 s8, s8, exec_lo s_and_b32 s14, s9, exec_lo s_and_not1_b32 s5, s5, exec_lo s_or_b32 s8, s8, s14 s_and_b32 s14, s12, exec_lo s_and_not1_b32 s6, s6, exec_lo s_and_b32 s15, s10, exec_lo s_or_b32 s5, s5, s14 s_or_b32 s6, s6, s15 s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB1_3 ; %bb.8: ; %loop.exit.guard ; in Loop: Header=BB1_2 Depth=1 s_or_b32 exec_lo, exec_lo, s7 s_xor_b32 s1, s8, -1 ; implicit-def: $sgpr0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s7, s1 s_xor_b32 s1, exec_lo, s7 s_cbranch_execz .LBB1_10 ; %bb.9: ; %.critedge ; in Loop: Header=BB1_2 Depth=1 s_and_b32 s0, s6, exec_lo global_store_b32 v[0:1], v6, off .LBB1_10: ; %Flow ; in Loop: Header=BB1_2 Depth=1 s_and_not1_saveexec_b32 s1, s1 ; %bb.11: ; in Loop: Header=BB1_2 Depth=1 v_add_nc_u32_e32 v6, 1, v6 s_and_not1_b32 s0, s0, exec_lo s_and_b32 s5, s5, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s0, s0, s5 ; %bb.12: ; in Loop: Header=BB1_2 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_xor_b32 s0, s0, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, exec_lo, s0 s_or_b32 s4, s0, s4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB1_2 .LBB1_13: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19graphColoringKernelPjS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z19graphColoringKernelPjS_, .Lfunc_end1-_Z19graphColoringKernelPjS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 520 ; NumSgprs: 20 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 20 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 20480 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15initGraphKernelPjP12hiprandState .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15initGraphKernelPjP12hiprandState.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 27 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19graphColoringKernelPjS_ .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z19graphColoringKernelPjS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00026c8e_00000000-6_cuda_code_073121.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3853: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3853: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3849: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3849: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW .type _Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW, @function _Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW: .LFB3875: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z15initGraphKernelPjP17curandStateXORWOW(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3875: .size _Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW, .-_Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW .globl _Z15initGraphKernelPjP17curandStateXORWOW .type _Z15initGraphKernelPjP17curandStateXORWOW, @function _Z15initGraphKernelPjP17curandStateXORWOW: .LFB3876: .cfi_startproc endbr64 jmp _Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW .cfi_endproc .LFE3876: .size _Z15initGraphKernelPjP17curandStateXORWOW, .-_Z15initGraphKernelPjP17curandStateXORWOW .globl _Z41__device_stub__Z19graphColoringKernelPjS_PjS_ .type _Z41__device_stub__Z19graphColoringKernelPjS_PjS_, @function _Z41__device_stub__Z19graphColoringKernelPjS_PjS_: .LFB3877: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L13 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z19graphColoringKernelPjS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L13: movq 104(%rsp), %rax subq %fs:40, %rax je .L15 call __stack_chk_fail@PLT .L15: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3877: .size _Z41__device_stub__Z19graphColoringKernelPjS_PjS_, .-_Z41__device_stub__Z19graphColoringKernelPjS_PjS_ .globl _Z19graphColoringKernelPjS_ .type _Z19graphColoringKernelPjS_, @function _Z19graphColoringKernelPjS_: .LFB3878: .cfi_startproc endbr64 jmp _Z41__device_stub__Z19graphColoringKernelPjS_PjS_ .cfi_endproc .LFE3878: .size _Z19graphColoringKernelPjS_, .-_Z19graphColoringKernelPjS_ .section .rodata.str1.1 .LC3: .string "cudaMalloc d_adjMatrix" .LC4: .string "cudaMalloc d_colors" .LC5: .string "cudaMalloc d_states" .LC6: .string "initGraphKernel launch failed" .LC7: .string "cudaDeviceSynchronize failed" .LC8: .string "graphColoringKernel launch failed" .LC9: .string "cudaMemcpy d_colors to h_colors" .LC10: .string "Node colors:" .LC11: .string "Node " .LC12: .string ": Color " .LC13: .string "cudaFree d_adjMatrix" .LC14: .string "cudaFree d_colors" .LC15: .string "cudaFree d_states" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3850: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $2048, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $72, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT leaq 8(%rsp), %rdi movl $1048576, %esi movq %rax, %rbx call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 16(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 24(%rsp), %rdi movl $24576, %esi call cudaMalloc@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $2147483649, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi addq %rdi, %rdi movq %rdx, 44(%rsp) movl $1, 52(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L19 movq 24(%rsp), %rsi movq 8(%rsp), %rdi call _Z55__device_stub__Z15initGraphKernelPjP17curandStateXORWOWPjP17curandStateXORWOW .L19: call cudaGetLastError@PLT leaq .LC6(%rip), %rsi leaq .LC7(%rip), %rbp movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT movq %rbp, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $2147483649, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi addq %rdi, %rdi movq %rdx, 44(%rsp) movl $1, 52(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L20 movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z41__device_stub__Z19graphColoringKernelPjS_PjS_ .L20: call cudaGetLastError@PLT leaq .LC8(%rip), %rsi leaq _ZSt4cout(%rip), %r12 movl %eax, %edi leaq .LC11(%rip), %r13 call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT movq %rbp, %rsi xorl %ebp, %ebp movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi movl $2048, %edx call cudaMemcpy@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq .LC10(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .L21: movq %r13, %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC12(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl (%rbx,%rbp,4), %esi incq %rbp movq %rax, %rdi call _ZNSo9_M_insertImEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT cmpq $512, %rbp jne .L21 movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC13(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rdi call cudaFree@PLT leaq .LC14(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rdi call cudaFree@PLT leaq .LC15(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq %rbx, %rdi call _ZdaPv@PLT movq 56(%rsp), %rax subq %fs:40, %rax je .L22 call __stack_chk_fail@PLT .L22: addq $72, %rsp .cfi_def_cfa_offset 40 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3850: .size main, .-main .section .rodata.str1.1 .LC16: .string "_Z19graphColoringKernelPjS_" .LC17: .string "_Z15initGraphKernelPjP17curandStateXORWOW" .LC18: .string "precalc_xorwow_matrix" .LC19: .string "precalc_xorwow_offset_matrix" .LC20: .string "mrg32k3aM1" .LC21: .string "mrg32k3aM2" .LC22: .string "mrg32k3aM1SubSeq" .LC23: .string "mrg32k3aM2SubSeq" .LC24: .string "mrg32k3aM1Seq" .LC25: .string "mrg32k3aM2Seq" .LC26: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3880: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z19graphColoringKernelPjS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC17(%rip), %rdx orl $-1, %r8d leaq _Z15initGraphKernelPjP17curandStateXORWOW(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC18(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC19(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC20(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC21(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC22(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC23(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC24(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC25(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC26(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3880: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_073121.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__initGraphKernelPjP12hiprandState # -- Begin function _Z30__device_stub__initGraphKernelPjP12hiprandState .type _Z30__device_stub__initGraphKernelPjP12hiprandState,@function _Z30__device_stub__initGraphKernelPjP12hiprandState: # @_Z30__device_stub__initGraphKernelPjP12hiprandState .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15initGraphKernelPjP12hiprandState, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__initGraphKernelPjP12hiprandState, .Lfunc_end0-_Z30__device_stub__initGraphKernelPjP12hiprandState .cfi_endproc # -- End function .globl _Z34__device_stub__graphColoringKernelPjS_ # -- Begin function _Z34__device_stub__graphColoringKernelPjS_ .type _Z34__device_stub__graphColoringKernelPjS_,@function _Z34__device_stub__graphColoringKernelPjS_: # @_Z34__device_stub__graphColoringKernelPjS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z19graphColoringKernelPjS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z34__device_stub__graphColoringKernelPjS_, .Lfunc_end1-_Z34__device_stub__graphColoringKernelPjS_ .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB2_2 # %bb.1: retq .LBB2_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end2: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end2-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $32, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movabsq $4294967298, %r14 # imm = 0x100000002 movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %rbx leaq 16(%rsp), %rdi movl $1048576, %esi # imm = 0x100000 callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 8(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 24(%rsp), %rdi movl $24576, %esi # imm = 0x6000 callq hipMalloc movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 254(%r14), %r15 movq %r14, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq 16(%rsp), %rdi movq 24(%rsp), %rsi callq _Z30__device_stub__initGraphKernelPjP12hiprandState .LBB3_2: callq hipGetLastError movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %r14, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq 16(%rsp), %rdi movq 8(%rsp), %rsi callq _Z34__device_stub__graphColoringKernelPjS_ .LBB3_4: callq hipGetLastError movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rsi movl $2048, %edx # imm = 0x800 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $_ZSt4cout, %r14d movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %r14, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %r14d, %r14d .LBB3_5: # =>This Inner Loop Header: Depth=1 movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $5, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r14d, %esi callq _ZNSolsEi movq %rax, %r15 movl $.L.str.12, %esi movl $8, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl (%rbx,%r14,4), %esi movq %r15, %rdi callq _ZNSo9_M_insertImEERSoT_ movq %rax, %r15 movq (%rax), %rax movq -24(%rax), %rdi addq %r15, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r14 cmpq $512, %r14 # imm = 0x200 jne .LBB3_5 # %bb.6: movq 16(%rsp), %rdi callq hipFree movl $.L.str.13, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi callq hipFree movl $.L.str.14, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 24(%rsp), %rdi callq hipFree movl $.L.str.15, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi callq _ZdaPv xorl %eax, %eax addq $32, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15initGraphKernelPjP12hiprandState, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19graphColoringKernelPjS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z15initGraphKernelPjP12hiprandState,@object # @_Z15initGraphKernelPjP12hiprandState .section .rodata,"a",@progbits .globl _Z15initGraphKernelPjP12hiprandState .p2align 3, 0x0 _Z15initGraphKernelPjP12hiprandState: .quad _Z30__device_stub__initGraphKernelPjP12hiprandState .size _Z15initGraphKernelPjP12hiprandState, 8 .type _Z19graphColoringKernelPjS_,@object # @_Z19graphColoringKernelPjS_ .globl _Z19graphColoringKernelPjS_ .p2align 3, 0x0 _Z19graphColoringKernelPjS_: .quad _Z34__device_stub__graphColoringKernelPjS_ .size _Z19graphColoringKernelPjS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMalloc d_adjMatrix" .size .L.str.3, 22 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipMalloc d_colors" .size .L.str.4, 19 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipMalloc d_states" .size .L.str.5, 19 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "initGraphKernel launch failed" .size .L.str.6, 30 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipDeviceSynchronize failed" .size .L.str.7, 28 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "graphColoringKernel launch failed" .size .L.str.8, 34 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipMemcpy d_colors to h_colors" .size .L.str.9, 31 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Node colors:" .size .L.str.10, 13 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Node " .size .L.str.11, 6 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz ": Color " .size .L.str.12, 9 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "hipFree d_adjMatrix" .size .L.str.13, 20 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "hipFree d_colors" .size .L.str.14, 17 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "hipFree d_states" .size .L.str.15, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15initGraphKernelPjP12hiprandState" .size .L__unnamed_1, 37 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z19graphColoringKernelPjS_" .size .L__unnamed_2, 28 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__initGraphKernelPjP12hiprandState .addrsig_sym _Z34__device_stub__graphColoringKernelPjS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15initGraphKernelPjP12hiprandState .addrsig_sym _Z19graphColoringKernelPjS_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
7,820
6,666
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z10initKernelPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; CS2R R2, SR_CLOCKLO ; IADD3 R2, P0, R0, R2, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3dcccccd ; LOP3.LUT R2, R2, 0xaad26b49, RZ, 0x3c, !PT ; LEA.HI.X.SX32 R3, R0, R3, 0x1, P0 ; IMAD R2, R2, 0x4182bed5, RZ ; LOP3.LUT R3, R3, 0xf7dcefdd, RZ, 0x3c, !PT ; IADD3 R4, R2.reuse, 0x75bcd15, RZ ; IMAD R3, R3, -0x658354e5, R2 ; IADD3 R6, R2.reuse, 0x583f19, RZ ; SHF.R.U32.HI R7, RZ, 0x2, R4 ; LOP3.LUT R5, R2, 0x159a55e5, RZ, 0x3c, !PT ; LOP3.LUT R7, R7, R4, RZ, 0x3c, !PT ; IMAD.SHL.U32 R4, R6, 0x10, RZ ; SHF.R.U32.HI R5, RZ, 0x2, R5 ; IADD3 R3, R3, 0x64f0c9, RZ ; LOP3.LUT R5, R5, 0x159a55e5, R2, 0x96, !PT ; LOP3.LUT R4, R7.reuse, R4, R6, 0x96, !PT ; IMAD.SHL.U32 R7, R7, 0x2, RZ ; IMAD.SHL.U32 R2, R5, 0x2, RZ ; LOP3.LUT R4, R4, R7, RZ, 0x3c, !PT ; LOP3.LUT R5, R4.reuse, R2, R5, 0x96, !PT ; IMAD.SHL.U32 R2, R4, 0x10, RZ ; IADD3 R4, R3, 0x587c5, R4 ; LOP3.LUT R2, R5, R2, RZ, 0x3c, !PT ; I2F.U32 R4, R4 ; IADD3 R6, R3, 0xb0f8a, R2 ; IMAD.MOV.U32 R3, RZ, RZ, 0x2f800000 ; I2F.U32 R6, R6 ; FFMA R5, R4, R3, 1.1641532182693481445e-10 ; FMUL R7, R5, 10 ; IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; FFMA R8, R6, R3, 1.1641532182693481445e-10 ; IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; FFMA R9, R8, R9, -0.050000000745058059692 ; STG.E [R2.64], R7 ; STG.E [R4.64], R9 ; EXIT ; BRA 0x2c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z21gradientDescentKernelPfPKff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R9, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R9 ; IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R0, [R2.64] ; STS [R9.X4+0x400], R4 ; STS [R9.X4], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R6, [R9.X4+0x400] ; LDS R7, [R9.X4] ; FFMA R7, -R6, c[0x0][0x170], R7 ; STG.E [R2.64], R7 ; STS [R9.X4], R7 ; EXIT ; BRA 0x130; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21gradientDescentKernelPfPKff ; -- Begin function _Z21gradientDescentKernelPfPKff .globl _Z21gradientDescentKernelPfPKff .p2align 8 .type _Z21gradientDescentKernelPfPKff,@function _Z21gradientDescentKernelPfPKff: ; @_Z21gradientDescentKernelPfPKff ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s0, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v3, vcc_lo, s4, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo v_add_co_u32 v1, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo global_load_b32 v5, v[3:4], off global_load_b32 v1, v[1:2], off v_lshlrev_b32_e32 v2, 2, v0 s_waitcnt vmcnt(0) ds_store_2addr_stride64_b32 v2, v1, v5 offset1:4 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_2addr_stride64_b32 v[0:1], v2 offset1:4 s_waitcnt lgkmcnt(0) v_fma_f32 v0, -v0, s0, v1 ds_store_b32 v2, v0 offset:1024 global_store_b32 v[3:4], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21gradientDescentKernelPfPKff .amdhsa_group_segment_fixed_size 2048 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21gradientDescentKernelPfPKff, .Lfunc_end0-_Z21gradientDescentKernelPfPKff ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 192 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 2048 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z10initKernelPfS_ ; -- Begin function _Z10initKernelPfS_ .globl _Z10initKernelPfS_ .p2align 8 .type _Z10initKernelPfS_,@function _Z10initKernelPfS_: ; @_Z10initKernelPfS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x1c s_mov_b32 s4, 0x3dcccccd s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_co_u32 v0, vcc_lo, s2, v1 v_ashrrev_i32_e32 v2, 31, v1 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v0, 0x2c7f967f, v0 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v0, 0x493c4aa1, v0 v_xor_b32_e32 v3, 0xa03697cb, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v3, 0x7b99840d, v3 v_add_nc_u32_e32 v4, 0x75bcd15, v0 v_add_nc_u32_e32 v6, 0x583f19, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v5, 2, v4 v_lshlrev_b32_e32 v7, 4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_xor_b32_e32 v4, v5, v4 v_xor_b32_e32 v5, 0x159a55e5, v0 v_add3_u32 v0, v0, v3, 0x64f0c9 v_lshlrev_b32_e32 v8, 1, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v9, 2, v5 v_xor_b32_e32 v7, v7, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v5, v9, v5 v_xor3_b32 v4, v7, v6, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b32_e32 v6, 1, v5 v_lshlrev_b32_e32 v7, 4, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v6, v6, v7 v_xor3_b32 v3, v6, v5, v4 v_add3_u32 v4, v0, v4, 0x587c5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add3_u32 v0, v0, v3, 0xb0f8a v_cvt_f32_u32_e32 v3, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v4, v0 v_fmaak_f32 v5, 0x2f800000, v3, 0x2f800000 v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmaak_f32 v4, 0x2f800000, v4, 0x2f800000 v_mul_f32_e32 v5, 0x41200000, v5 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v2, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s2, v0 v_fmaak_f32 v4, s4, v4, 0xbd4ccccd v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[2:3], v5, off global_store_b32 v[0:1], v4, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10initKernelPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z10initKernelPfS_, .Lfunc_end1-_Z10initKernelPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 384 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 2048 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21gradientDescentKernelPfPKff .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21gradientDescentKernelPfPKff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10initKernelPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10initKernelPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0003e935_00000000-6_cuda_code_031556.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3853: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3853: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3849: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3849: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff .type _Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff, @function _Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff: .LFB3875: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx movq %rsi, 16(%rsp) leaq 48(%rsp), %rdi leaq 60(%rsp), %rsi movss %xmm0, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z21gradientDescentKernelPfPKff(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L8: movq 120(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3875: .size _Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff, .-_Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff .globl _Z21gradientDescentKernelPfPKff .type _Z21gradientDescentKernelPfPKff, @function _Z21gradientDescentKernelPfPKff: .LFB3876: .cfi_startproc endbr64 jmp _Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff .cfi_endproc .LFE3876: .size _Z21gradientDescentKernelPfPKff, .-_Z21gradientDescentKernelPfPKff .globl _Z32__device_stub__Z10initKernelPfS_PfS_ .type _Z32__device_stub__Z10initKernelPfS_PfS_, @function _Z32__device_stub__Z10initKernelPfS_PfS_: .LFB3877: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L13 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z10initKernelPfS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L13: movq 104(%rsp), %rax subq %fs:40, %rax je .L15 call __stack_chk_fail@PLT .L15: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3877: .size _Z32__device_stub__Z10initKernelPfS_PfS_, .-_Z32__device_stub__Z10initKernelPfS_PfS_ .globl _Z10initKernelPfS_ .type _Z10initKernelPfS_, @function _Z10initKernelPfS_: .LFB3878: .cfi_startproc endbr64 jmp _Z32__device_stub__Z10initKernelPfS_PfS_ .cfi_endproc .LFE3878: .size _Z10initKernelPfS_, .-_Z10initKernelPfS_ .section .rodata.str1.1 .LC3: .string "Failed to allocate d_params" .LC4: .string "Failed to allocate d_gradients" .LC5: .string "Kernel launch failed for initKernel" .LC6: .string "Failed to synchronize device" .LC8: .string "Kernel launch failed for gradientDescentKernel" .LC9: .string "Failed to free d_params" .LC10: .string "Failed to free d_gradients" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3850: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl $32768, %esi subq $48, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movq %rsp, %rdi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 8(%rsp), %rdi movl $32768, %esi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $134217729, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $5, %rdi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L19 movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z32__device_stub__Z10initKernelPfS_PfS_ .L19: call cudaGetLastError@PLT leaq .LC5(%rip), %rsi leaq .LC6(%rip), %rbx movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT movq %rbx, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $134217729, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $5, %rdi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L20 movss .LC7(%rip), %xmm0 movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z45__device_stub__Z21gradientDescentKernelPfPKffPfPKff .L20: call cudaGetLastError@PLT leaq .LC8(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT movq %rbx, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%rsp), %rdi call cudaFree@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC10(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 40(%rsp), %rax subq %fs:40, %rax je .L21 call __stack_chk_fail@PLT .L21: addq $48, %rsp .cfi_def_cfa_offset 16 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3850: .size main, .-main .section .rodata.str1.1 .LC11: .string "_Z10initKernelPfS_" .LC12: .string "_Z21gradientDescentKernelPfPKff" .LC13: .string "precalc_xorwow_matrix" .LC14: .string "precalc_xorwow_offset_matrix" .LC15: .string "mrg32k3aM1" .LC16: .string "mrg32k3aM2" .LC17: .string "mrg32k3aM1SubSeq" .LC18: .string "mrg32k3aM2SubSeq" .LC19: .string "mrg32k3aM1Seq" .LC20: .string "mrg32k3aM2Seq" .LC21: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3880: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z10initKernelPfS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC12(%rip), %rdx orl $-1, %r8d leaq _Z21gradientDescentKernelPfPKff(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC13(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC15(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC19(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC20(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC21(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3880: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC7: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_031556.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z36__device_stub__gradientDescentKernelPfPKff # -- Begin function _Z36__device_stub__gradientDescentKernelPfPKff .type _Z36__device_stub__gradientDescentKernelPfPKff,@function _Z36__device_stub__gradientDescentKernelPfPKff: # @_Z36__device_stub__gradientDescentKernelPfPKff .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rdx movss %xmm0, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rdx, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z21gradientDescentKernelPfPKff, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z36__device_stub__gradientDescentKernelPfPKff, .Lfunc_end0-_Z36__device_stub__gradientDescentKernelPfPKff .cfi_endproc # -- End function .globl _Z25__device_stub__initKernelPfS_ # -- Begin function _Z25__device_stub__initKernelPfS_ .type _Z25__device_stub__initKernelPfS_,@function _Z25__device_stub__initKernelPfS_: # @_Z25__device_stub__initKernelPfS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z10initKernelPfS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z25__device_stub__initKernelPfS_, .Lfunc_end1-_Z25__device_stub__initKernelPfS_ .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB2_2 # %bb.1: retq .LBB2_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end2: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end2-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $24, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movabsq $4294967328, %rbx # imm = 0x100000020 leaq 16(%rsp), %rdi movl $32768, %esi # imm = 0x8000 callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 8(%rsp), %rdi movl $32768, %esi # imm = 0x8000 callq hipMalloc movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 224(%rbx), %r14 movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq 16(%rsp), %rdi movq 8(%rsp), %rsi callq _Z25__device_stub__initKernelPfS_ .LBB3_2: callq hipGetLastError movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq 16(%rsp), %rdi movq 8(%rsp), %rsi movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero callq _Z36__device_stub__gradientDescentKernelPfPKff .LBB3_4: callq hipGetLastError movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 16(%rsp), %rdi callq hipFree movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi callq hipFree movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc xorl %eax, %eax addq $24, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21gradientDescentKernelPfPKff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10initKernelPfS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z21gradientDescentKernelPfPKff,@object # @_Z21gradientDescentKernelPfPKff .section .rodata,"a",@progbits .globl _Z21gradientDescentKernelPfPKff .p2align 3, 0x0 _Z21gradientDescentKernelPfPKff: .quad _Z36__device_stub__gradientDescentKernelPfPKff .size _Z21gradientDescentKernelPfPKff, 8 .type _Z10initKernelPfS_,@object # @_Z10initKernelPfS_ .globl _Z10initKernelPfS_ .p2align 3, 0x0 _Z10initKernelPfS_: .quad _Z25__device_stub__initKernelPfS_ .size _Z10initKernelPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate d_params" .size .L.str.3, 28 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate d_gradients" .size .L.str.4, 31 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Kernel launch failed for initKernel" .size .L.str.5, 36 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to synchronize device" .size .L.str.6, 29 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Kernel launch failed for gradientDescentKernel" .size .L.str.7, 47 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Failed to free d_params" .size .L.str.8, 24 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to free d_gradients" .size .L.str.9, 27 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z21gradientDescentKernelPfPKff" .size .L__unnamed_1, 32 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z10initKernelPfS_" .size .L__unnamed_2, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__gradientDescentKernelPfPKff .addrsig_sym _Z25__device_stub__initKernelPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21gradientDescentKernelPfPKff .addrsig_sym _Z10initKernelPfS_ .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z13decoderKernelPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GT.AND P0, PT, R3, 0x1ff, PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GT.OR P0, PT, R0, 0x1ff, P0 ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; LEA R0, R3, R0, 0x9 ; ULDC.64 UR4, c[0x0][0x118] ; LEA R0, R0, R0, 0x1 ; IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; LDG.E R6, [R2.64] ; IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; FADD R7, R6, R6 ; STG.E [R4.64], R7 ; LDG.E R0, [R2.64+0x4] ; FADD R9, R0, R0 ; STG.E [R4.64+0x4], R9 ; LDG.E R0, [R2.64+0x8] ; FADD R11, R0, R0 ; STG.E [R4.64+0x8], R11 ; EXIT ; BRA 0x1a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13encoderKernelPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GT.AND P0, PT, R3, 0x1ff, PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GT.OR P0, PT, R0, 0x1ff, P0 ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; LEA R0, R3, R0, 0x9 ; ULDC.64 UR4, c[0x0][0x118] ; LEA R0, R0, R0, 0x1 ; IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; LDG.E R6, [R2.64] ; IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; FMUL R7, R6, 0.5 ; STG.E [R4.64], R7 ; LDG.E R0, [R2.64+0x4] ; FMUL R9, R0, 0.5 ; STG.E [R4.64+0x4], R9 ; LDG.E R0, [R2.64+0x8] ; FMUL R11, R0, 0.5 ; STG.E [R4.64+0x8], R11 ; EXIT ; BRA 0x1a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13encoderKernelPfS_ ; -- Begin function _Z13encoderKernelPfS_ .globl _Z13encoderKernelPfS_ .p2align 8 .type _Z13encoderKernelPfS_,@function _Z13encoderKernelPfS_: ; @_Z13encoderKernelPfS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x1c v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_mov_b32 s2, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_max_i32_e32 v2, v0, v1 v_cmpx_gt_i32_e32 0x200, v2 s_cbranch_execz .LBB0_3 ; %bb.1: v_lshl_add_u32 v0, v1, 9, v0 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v0, 1, v0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo s_mov_b64 s[0:1], 0 .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v4, vcc_lo, v0, s0 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo global_load_b32 v6, v[4:5], off v_add_co_u32 v4, vcc_lo, v2, s0 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s0, 12 s_waitcnt vmcnt(0) v_mul_f32_e32 v6, 0.5, v6 global_store_b32 v[4:5], v6, off s_cbranch_scc1 .LBB0_2 .LBB0_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13encoderKernelPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13encoderKernelPfS_, .Lfunc_end0-_Z13encoderKernelPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 244 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z13decoderKernelPfS_ ; -- Begin function _Z13decoderKernelPfS_ .globl _Z13decoderKernelPfS_ .p2align 8 .type _Z13decoderKernelPfS_,@function _Z13decoderKernelPfS_: ; @_Z13decoderKernelPfS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x1c v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_mov_b32 s2, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_max_i32_e32 v2, v0, v1 v_cmpx_gt_i32_e32 0x200, v2 s_cbranch_execz .LBB1_3 ; %bb.1: v_lshl_add_u32 v0, v1, 9, v0 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v0, 1, v0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo s_mov_b64 s[0:1], 0 .LBB1_2: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v4, vcc_lo, v0, s0 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo global_load_b32 v6, v[4:5], off v_add_co_u32 v4, vcc_lo, v2, s0 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s0, 12 s_waitcnt vmcnt(0) v_add_f32_e32 v6, v6, v6 global_store_b32 v[4:5], v6, off s_cbranch_scc1 .LBB1_2 .LBB1_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13decoderKernelPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z13decoderKernelPfS_, .Lfunc_end1-_Z13decoderKernelPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 244 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13encoderKernelPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13encoderKernelPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13decoderKernelPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13decoderKernelPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00046be2_00000000-6_cuda_code_077183.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4294: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4294: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z35__device_stub__Z13encoderKernelPfS_PfS_ .type _Z35__device_stub__Z13encoderKernelPfS_PfS_, @function _Z35__device_stub__Z13encoderKernelPfS_PfS_: .LFB3660: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z13encoderKernelPfS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z35__device_stub__Z13encoderKernelPfS_PfS_, .-_Z35__device_stub__Z13encoderKernelPfS_PfS_ .globl _Z13encoderKernelPfS_ .type _Z13encoderKernelPfS_, @function _Z13encoderKernelPfS_: .LFB3661: .cfi_startproc endbr64 jmp _Z35__device_stub__Z13encoderKernelPfS_PfS_ .cfi_endproc .LFE3661: .size _Z13encoderKernelPfS_, .-_Z13encoderKernelPfS_ .globl _Z35__device_stub__Z13decoderKernelPfS_PfS_ .type _Z35__device_stub__Z13decoderKernelPfS_PfS_, @function _Z35__device_stub__Z13decoderKernelPfS_PfS_: .LFB3662: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L9 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z13decoderKernelPfS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L9: movq 104(%rsp), %rax subq %fs:40, %rax je .L11 call __stack_chk_fail@PLT .L11: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3662: .size _Z35__device_stub__Z13decoderKernelPfS_PfS_, .-_Z35__device_stub__Z13decoderKernelPfS_PfS_ .globl _Z13decoderKernelPfS_ .type _Z13decoderKernelPfS_, @function _Z13decoderKernelPfS_: .LFB3663: .cfi_startproc endbr64 jmp _Z35__device_stub__Z13decoderKernelPfS_PfS_ .cfi_endproc .LFE3663: .size _Z13decoderKernelPfS_, .-_Z13decoderKernelPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Failed to allocate memory for d_input: " .LC2: .string "Failed to allocate memory for d_output: " .LC3: .string "Failed to copy input image to device: " .LC4: .string "Encoder kernel launch failed: " .LC5: .string "Decoder kernel launch failed: " .LC6: .string "Failed to copy output image to host: " .LC7: .string "Image segmentation using U-Net completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $3145728, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $56, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $3145728, %edi movq %rax, %rbx call _Znam@PLT movss .LC0(%rip), %xmm1 movq %rax, %rbp xorl %eax, %eax .L15: movzbl %al, %edx cvtsi2ssl %edx, %xmm0 divss %xmm1, %xmm0 movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $786432, %rax jne .L15 movq %rsp, %rdi movl $3145728, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L16 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L17 .L16: leaq 8(%rsp), %rdi movl $3145728, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L18 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi .L30: call cudaFree@PLT .L17: orl $-1, %eax jmp .L14 .L18: movq (%rsp), %rdi movl $1, %ecx movl $3145728, %edx movq %rbx, %rsi call cudaMemcpy@PLT movl %eax, %r12d testl %eax, %eax je .L20 leaq .LC3(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi jmp .L30 .L20: xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movl $1, %esi movabsq $68719476752, %rdx movl $1, 24(%rsp) movabsq $137438953504, %rdi movq %rdx, 16(%rsp) movq %rdi, 28(%rsp) movl $1, 36(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L21 movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z35__device_stub__Z13encoderKernelPfS_PfS_ .L21: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L29 movl 24(%rsp), %ecx movq 16(%rsp), %rdx xorl %r9d, %r9d xorl %r8d, %r8d movq 28(%rsp), %rdi movl 36(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L23 movq 8(%rsp), %rdi movq %rdi, %rsi call _Z35__device_stub__Z13decoderKernelPfS_PfS_ .L23: call cudaGetLastError@PLT leaq .LC5(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L29 movq 8(%rsp), %rsi movl $2, %ecx movl $3145728, %edx movq %rbp, %rdi call cudaMemcpy@PLT movl %eax, %r12d testl %eax, %eax je .L25 leaq .LC6(%rip), %rsi .L29: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %r13 call cudaGetErrorString@PLT movq %r13, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT jmp .L17 .L25: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L14: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L26 call __stack_chk_fail@PLT .L26: addq $56, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z13decoderKernelPfS_" .LC9: .string "_Z13encoderKernelPfS_" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3665: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z13decoderKernelPfS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC9(%rip), %rdx orl $-1, %r8d leaq _Z13encoderKernelPfS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3665: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1132396544 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_077183.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z28__device_stub__encoderKernelPfS_ # -- Begin function _Z28__device_stub__encoderKernelPfS_ .type _Z28__device_stub__encoderKernelPfS_,@function _Z28__device_stub__encoderKernelPfS_: # @_Z28__device_stub__encoderKernelPfS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13encoderKernelPfS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z28__device_stub__encoderKernelPfS_, .Lfunc_end0-_Z28__device_stub__encoderKernelPfS_ .cfi_endproc # -- End function .globl _Z28__device_stub__decoderKernelPfS_ # -- Begin function _Z28__device_stub__decoderKernelPfS_ .type _Z28__device_stub__decoderKernelPfS_,@function _Z28__device_stub__decoderKernelPfS_: # @_Z28__device_stub__decoderKernelPfS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13decoderKernelPfS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z28__device_stub__decoderKernelPfS_, .Lfunc_end1-_Z28__device_stub__decoderKernelPfS_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x437f0000 # float 255 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $16, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $3145728, %edi # imm = 0x300000 callq _Znam movq %rax, %r14 movl $3145728, %edi # imm = 0x300000 callq _Znam movq %rax, %rbx xorl %eax, %eax movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero .LBB2_1: # =>This Inner Loop Header: Depth=1 movzbl %al, %ecx xorps %xmm1, %xmm1 cvtsi2ss %ecx, %xmm1 divss %xmm0, %xmm1 movss %xmm1, (%r14,%rax,4) incq %rax cmpq $786432, %rax # imm = 0xC0000 jne .LBB2_1 # %bb.2: leaq 8(%rsp), %rdi movl $3145728, %esi # imm = 0x300000 callq hipMalloc testl %eax, %eax je .LBB2_5 # %bb.3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $39, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_8 # %bb.4: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_9 .LBB2_5: movq %rsp, %rdi movl $3145728, %esi # imm = 0x300000 callq hipMalloc testl %eax, %eax je .LBB2_10 # %bb.6: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $40, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_13 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_14 .LBB2_8: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB2_23 .LBB2_10: movq 8(%rsp), %rdi movl $3145728, %edx # imm = 0x300000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_15 # %bb.11: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $38, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_20 # %bb.12: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_21 .LBB2_13: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi jmp .LBB2_22 .LBB2_15: movabsq $137438953504, %r12 # imm = 0x2000000020 movabsq $68719476752, %r15 # imm = 0x1000000010 movq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_17 # %bb.16: movq 8(%rsp), %rdi movq (%rsp), %rsi callq _Z28__device_stub__encoderKernelPfS_ .LBB2_17: callq hipGetLastError testl %eax, %eax je .LBB2_25 # %bb.18: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $30, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_29 # %bb.19: movq %rax, %r15 movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_30 .LBB2_20: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit58 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi .LBB2_22: callq hipFree .LBB2_23: movl $-1, %eax .LBB2_24: addq $16, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_25: .cfi_def_cfa_offset 64 movq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_27 # %bb.26: movq (%rsp), %rdi movq %rdi, %rsi callq _Z28__device_stub__decoderKernelPfS_ .LBB2_27: callq hipGetLastError testl %eax, %eax je .LBB2_31 # %bb.28: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $30, %edx jmp .LBB2_33 .LBB2_29: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_30: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB2_34 .LBB2_31: movq (%rsp), %rsi movl $3145728, %edx # imm = 0x300000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_35 # %bb.32: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $37, %edx .LBB2_33: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ .LBB2_34: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %r14, %rdi callq _ZdaPv movq %rbx, %rdi callq _ZdaPv jmp .LBB2_23 .LBB2_35: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %r14, %rdi callq _ZdaPv movq %rbx, %rdi callq _ZdaPv movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $54, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB2_24 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13encoderKernelPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13decoderKernelPfS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z13encoderKernelPfS_,@object # @_Z13encoderKernelPfS_ .section .rodata,"a",@progbits .globl _Z13encoderKernelPfS_ .p2align 3, 0x0 _Z13encoderKernelPfS_: .quad _Z28__device_stub__encoderKernelPfS_ .size _Z13encoderKernelPfS_, 8 .type _Z13decoderKernelPfS_,@object # @_Z13decoderKernelPfS_ .globl _Z13decoderKernelPfS_ .p2align 3, 0x0 _Z13decoderKernelPfS_: .quad _Z28__device_stub__decoderKernelPfS_ .size _Z13decoderKernelPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate memory for d_input: " .size .L.str, 40 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate memory for d_output: " .size .L.str.1, 41 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to copy input image to device: " .size .L.str.2, 39 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Encoder kernel launch failed: " .size .L.str.3, 31 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Decoder kernel launch failed: " .size .L.str.4, 31 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy output image to host: " .size .L.str.5, 38 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Image segmentation using U-Net completed successfully." .size .L.str.6, 55 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13encoderKernelPfS_" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z13decoderKernelPfS_" .size .L__unnamed_2, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__encoderKernelPfS_ .addrsig_sym _Z28__device_stub__decoderKernelPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13encoderKernelPfS_ .addrsig_sym _Z13decoderKernelPfS_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z11bTreeKernelP9BTreeNode .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R4, 0x3fff, PT ; @P0 EXIT ; IMAD.MOV.U32 R3, RZ, RZ, 0x80 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; LDG.E R3, [R2.64] ; ISETP.GE.AND P0, PT, R3, 0x1, PT ; @!P0 EXIT ; IADD3 R0, R3.reuse, -0x1, RZ ; BSSY B1, 0x960 ; SHF.R.S32.HI R5, RZ, 0x1f, R4 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; LOP3.LUT R0, R3, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x950 ; LEA R2, P0, R4.reuse, c[0x0][0x160], 0x7 ; IMAD.IADD R7, R3, 0x1, -R0 ; BSSY B0, 0x810 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; LEA.HI.X R3, R4, c[0x0][0x164], R5, 0x7, P0 ; ISETP.GT.AND P0, PT, R7, RZ, PT ; IADD3 R2, P1, R2, 0x10, RZ ; IMAD.X R3, RZ, RZ, R3, P1 ; @!P0 BRA 0x800 ; ISETP.GT.AND P1, PT, R7, 0xc, PT ; BSSY B2, 0x5a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x590 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R20, [R2.64+-0x4] ; LDG.E R17, [R2.64+-0xc] ; LDG.E R18, [R2.64+-0x8] ; LDG.E R22, [R2.64] ; LDG.E R13, [R2.64+0x1c] ; LDG.E R8, [R2.64+0x24] ; LDG.E R24, [R2.64+0x4] ; LDG.E R26, [R2.64+0x8] ; LDG.E R28, [R2.64+0xc] ; LDG.E R16, [R2.64+0x10] ; LDG.E R15, [R2.64+0x14] ; LDG.E R14, [R2.64+0x18] ; LDG.E R12, [R2.64+0x20] ; LDG.E R11, [R2.64+0x28] ; LDG.E R10, [R2.64+0x2c] ; LDG.E R9, [R2.64+0x30] ; IADD3 R7, R7, -0x10, RZ ; ISETP.GT.AND P1, PT, R7, 0xc, PT ; IADD3 R6, R6, 0x10, RZ ; IADD3 R21, R20, 0x1, RZ ; IADD3 R17, R17, 0x1, RZ ; STG.E [R2.64+-0x4], R21 ; IADD3 R19, R18, 0x1, RZ ; IADD3 R23, R22, 0x1, RZ ; STG.E [R2.64+-0xc], R17 ; IADD3 R13, R13, 0x1, RZ ; STG.E [R2.64+-0x8], R19 ; IADD3 R21, R8, 0x1, RZ ; IADD3 R8, P2, R2, 0x40, RZ ; STG.E [R2.64], R23 ; IADD3 R25, R24, 0x1, RZ ; STG.E [R2.64+0x1c], R13 ; IADD3 R27, R26, 0x1, RZ ; IADD3 R17, R28, 0x1, RZ ; IADD3 R29, R16, 0x1, RZ ; IADD3 R15, R15, 0x1, RZ ; IMAD.X R13, RZ, RZ, R3, P2 ; IADD3 R14, R14, 0x1, RZ ; IADD3 R19, R12, 0x1, RZ ; IADD3 R11, R11, 0x1, RZ ; IADD3 R23, R10, 0x1, RZ ; IADD3 R9, R9, 0x1, RZ ; STG.E [R2.64+0x4], R25 ; STG.E [R2.64+0x8], R27 ; STG.E [R2.64+0xc], R17 ; STG.E [R2.64+0x10], R29 ; STG.E [R2.64+0x14], R15 ; STG.E [R2.64+0x18], R14 ; STG.E [R2.64+0x20], R19 ; STG.E [R2.64+0x24], R21 ; STG.E [R2.64+0x28], R11 ; STG.E [R2.64+0x2c], R23 ; STG.E [R2.64+0x30], R9 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; @P1 BRA 0x210 ; BSYNC B2 ; ISETP.GT.AND P1, PT, R7, 0x4, PT ; BSSY B2, 0x7d0 ; @!P1 BRA 0x7c0 ; LDG.E R8, [R2.64+-0xc] ; LDG.E R10, [R2.64+-0x8] ; LDG.E R12, [R2.64+-0x4] ; LDG.E R14, [R2.64] ; LDG.E R16, [R2.64+0x4] ; LDG.E R18, [R2.64+0x8] ; LDG.E R20, [R2.64+0xc] ; LDG.E R22, [R2.64+0x10] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R6, R6, 0x8, RZ ; IADD3 R7, R7, -0x8, RZ ; IADD3 R9, R8, 0x1, RZ ; IADD3 R8, P1, R2, 0x20, RZ ; IADD3 R11, R10, 0x1, RZ ; STG.E [R2.64+-0xc], R9 ; IADD3 R13, R12, 0x1, RZ ; STG.E [R2.64+-0x8], R11 ; IADD3 R15, R14, 0x1, RZ ; STG.E [R2.64+-0x4], R13 ; IADD3 R17, R16, 0x1, RZ ; IMAD.X R9, RZ, RZ, R3, P1 ; STG.E [R2.64], R15 ; IADD3 R19, R18, 0x1, RZ ; STG.E [R2.64+0x4], R17 ; IADD3 R21, R20, 0x1, RZ ; STG.E [R2.64+0x8], R19 ; IADD3 R23, R22, 0x1, RZ ; STG.E [R2.64+0xc], R21 ; STG.E [R2.64+0x10], R23 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; IMAD.MOV.U32 R3, RZ, RZ, R9 ; BSYNC B2 ; ISETP.NE.OR P0, PT, R7, RZ, P0 ; @!P0 BREAK B0 ; @!P0 BRA 0x950 ; BSYNC B0 ; LDG.E R8, [R2.64+-0xc] ; LDG.E R10, [R2.64+-0x8] ; LDG.E R12, [R2.64+-0x4] ; LDG.E R14, [R2.64] ; IADD3 R7, R7, -0x4, RZ ; IADD3 R6, R6, 0x4, RZ ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IADD3 R9, R8, 0x1, RZ ; IADD3 R8, P1, R2, 0x10, RZ ; IADD3 R11, R10, 0x1, RZ ; STG.E [R2.64+-0xc], R9 ; IMAD.X R17, RZ, RZ, R3, P1 ; IADD3 R13, R12, 0x1, RZ ; STG.E [R2.64+-0x8], R11 ; IADD3 R15, R14, 0x1, RZ ; STG.E [R2.64+-0x4], R13 ; STG.E [R2.64], R15 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; IMAD.MOV.U32 R3, RZ, RZ, R17 ; @P0 BRA 0x810 ; BSYNC B1 ; WARPSYNC 0xffffffff ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; LEA R2, P0, R4, c[0x0][0x160], 0x7 ; LEA.HI.X R3, R4, c[0x0][0x164], R5, 0x7, P0 ; IMAD.WIDE R6, R6, 0x4, R2 ; IADD3 R4, P0, R6, 0x4, RZ ; IMAD.X R7, RZ, RZ, R7, P0 ; IMAD.MOV.U32 R2, RZ, RZ, R4 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; LDG.E R4, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IADD3 R5, R4, 0x1, RZ ; IADD3 R4, P1, R2, 0x4, RZ ; STG.E [R2.64], R5 ; IMAD.X R7, RZ, RZ, R3, P1 ; @P0 BRA 0x9e0 ; EXIT ; BRA 0xa90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11bTreeKernelP9BTreeNode ; -- Begin function _Z11bTreeKernelP9BTreeNode .globl _Z11bTreeKernelP9BTreeNode .p2align 8 .type _Z11bTreeKernelP9BTreeNode,@function _Z11bTreeKernelP9BTreeNode: ; @_Z11bTreeKernelP9BTreeNode ; %bb.0: s_load_b32 s2, s[0:1], 0x14 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x4000, v1 s_cbranch_execz .LBB0_4 ; %bb.1: ; %.preheader s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 7, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_mov_b32 s1, 0 global_load_b32 v2, v[0:1], off s_waitcnt vmcnt(0) v_cmp_lt_i32_e32 vcc_lo, 0, v2 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_4 ; %bb.2: ; %.lr.ph.preheader v_add_co_u32 v0, vcc_lo, v0, 4 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_mov_b32 s2, 0 .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b32 v3, v[0:1], off s_add_i32 s2, s2, 1 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_ge_i32_e32 vcc_lo, s2, v2 s_or_b32 s1, vcc_lo, s1 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v3, 1, v3 global_store_b32 v[0:1], v3, off v_add_co_u32 v0, s0, v0, 4 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, s0, 0, v1, s0 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_3 .LBB0_4: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11bTreeKernelP9BTreeNode .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11bTreeKernelP9BTreeNode, .Lfunc_end0-_Z11bTreeKernelP9BTreeNode ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 216 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11bTreeKernelP9BTreeNode .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11bTreeKernelP9BTreeNode.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00113214_00000000-6_cuda_code_049688.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " - " .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3635: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3635: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode .type _Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode, @function _Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode: .LFB3661: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 40(%rsp) movq %rax, 80(%rsp) movabsq $4294967297, %rax movq %rax, 32(%rsp) movq %rax, 44(%rsp) movl $1, 52(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 24(%rsp) .cfi_def_cfa_offset 120 leaq _Z11bTreeKernelP9BTreeNode(%rip), %rdi pushq 24(%rsp) .cfi_def_cfa_offset 128 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq 96(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 120 popq %rdx .cfi_def_cfa_offset 112 .L8: movq 88(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $104, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode, .-_Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode .globl _Z11bTreeKernelP9BTreeNode .type _Z11bTreeKernelP9BTreeNode, @function _Z11bTreeKernelP9BTreeNode: .LFB3662: .cfi_startproc endbr64 jmp _Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode .cfi_endproc .LFE3662: .size _Z11bTreeKernelP9BTreeNode, .-_Z11bTreeKernelP9BTreeNode .section .rodata.str1.1 .LC2: .string "cudaMalloc failed" .LC3: .string "cudaMemcpy failed" .LC4: .string "Kernel launch failed" .LC5: .string "cudaFree failed" .LC6: .string "The kernel executed correctly." .LC7: .string "The kernel did not execute correctly." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $2097152, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT xorl %esi, %esi movq %rax, %rbx movq %rax, %rbp movq %rax, %rdx movb $-1, %al .L15: movl $15, (%rdx) xorl %ecx, %ecx .L14: leal (%rsi,%rcx), %edi movl %edi, 4(%rdx,%rcx,4) incq %rcx cmpq $15, %rcx jne .L14 leaq 64(%rdx), %r8 movl $64, %ecx addl $15, %esi subq $-128, %rdx movq %r8, %rdi rep stosb cmpl $245760, %esi jne .L15 leaq 8(%rsp), %rdi movl $2097152, %esi leaq .LC3(%rip), %r12 call cudaMalloc@PLT leaq .LC2(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $2097152, %edx call cudaMemcpy@PLT movq %r12, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $67108865, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $6, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rdi call _Z40__device_stub__Z11bTreeKernelP9BTreeNodeP9BTreeNode .L16: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rsi movl $2097152, %edx movq %rbx, %rdi movl $2, %ecx call cudaMemcpy@PLT movq %r12, %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %edx, %edx .L17: movl 0(%rbp), %ecx xorl %eax, %eax .L21: cmpl %eax, %ecx jle .L29 movl 4(%rbp,%rax,4), %edi incq %rax leal (%rdx,%rax), %esi cmpl %esi, %edi je .L21 leaq .LC7(%rip), %rsi jmp .L28 .L29: addl $15, %edx subq $-128, %rbp cmpl $245760, %edx jne .L17 leaq .LC6(%rip), %rsi .L28: leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq %rbx, %rdi call _ZdaPv@PLT movq 40(%rsp), %rax subq %fs:40, %rax je .L23 call __stack_chk_fail@PLT .L23: addq $48, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z11bTreeKernelP9BTreeNode" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi leaq _Z11bTreeKernelP9BTreeNode(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_049688.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__bTreeKernelP9BTreeNode # -- Begin function _Z26__device_stub__bTreeKernelP9BTreeNode .type _Z26__device_stub__bTreeKernelP9BTreeNode,@function _Z26__device_stub__bTreeKernelP9BTreeNode: # @_Z26__device_stub__bTreeKernelP9BTreeNode .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $64, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) movq %rsp, %rbx movq %rax, (%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z11bTreeKernelP9BTreeNode, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $80, %rsp .cfi_adjust_cfa_offset -80 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z26__device_stub__bTreeKernelP9BTreeNode, .Lfunc_end0-_Z26__device_stub__bTreeKernelP9BTreeNode .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $2097152, %edi # imm = 0x200000 callq _Znam movq %rax, %rbx addq $4, %rax xorl %ecx, %ecx pcmpeqd %xmm0, %xmm0 xorl %edx, %edx .LBB2_1: # =>This Loop Header: Depth=1 # Child Loop BB2_2 Depth 2 movq %rdx, %rdi shlq $7, %rdi leaq (%rbx,%rdi), %rsi addq $64, %rsi movl $15, (%rbx,%rdi) xorl %edi, %edi .LBB2_2: # Parent Loop BB2_1 Depth=1 # => This Inner Loop Header: Depth=2 leal (%rcx,%rdi), %r8d movl %r8d, (%rax,%rdi,4) incq %rdi cmpq $15, %rdi jne .LBB2_2 # %bb.3: # %.preheader57.preheader # in Loop: Header=BB2_1 Depth=1 movdqu %xmm0, 48(%rsi) movdqu %xmm0, 32(%rsi) movdqu %xmm0, 16(%rsi) movdqu %xmm0, (%rsi) incq %rdx addq $15, %rcx subq $-128, %rax cmpq $16384, %rdx # imm = 0x4000 jne .LBB2_1 # %bb.4: movq %rsp, %r14 movl $2097152, %esi # imm = 0x200000 movq %r14, %rdi callq hipMalloc movl $.L.str.2, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r14), %rdi movl $2097152, %edx # imm = 0x200000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $4294967360, %rdi # imm = 0x100000040 leaq 192(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_6 # %bb.5: movq (%rsp), %rdi callq _Z26__device_stub__bTreeKernelP9BTreeNode .LBB2_6: callq hipGetLastError movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rsi movl $2097152, %edx # imm = 0x200000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rax addq $4, %rax movl $1, %ecx xorl %edx, %edx .LBB2_7: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_10 Depth 2 movq %rdx, %rsi shlq $7, %rsi movl (%rbx,%rsi), %esi testl %esi, %esi jle .LBB2_12 # %bb.8: # %.lr.ph # in Loop: Header=BB2_7 Depth=1 xorl %edi, %edi .LBB2_10: # Parent Loop BB2_7 Depth=1 # => This Inner Loop Header: Depth=2 movl (%rax,%rdi,4), %r8d leaq (%rcx,%rdi), %r9 cmpq %r8, %r9 jne .LBB2_11 # %bb.9: # in Loop: Header=BB2_10 Depth=2 incq %rdi cmpq %rdi, %rsi jne .LBB2_10 .LBB2_12: # %._crit_edge # in Loop: Header=BB2_7 Depth=1 incq %rdx subq $-128, %rax addq $15, %rcx cmpq $16384, %rdx # imm = 0x4000 jne .LBB2_7 # %bb.13: movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $30, %edx jmp .LBB2_14 .LBB2_11: # %.thread54 movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $37, %edx .LBB2_14: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movl $_ZSt4cout, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi callq hipFree movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi callq _ZdaPv xorl %eax, %eax addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11bTreeKernelP9BTreeNode, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z11bTreeKernelP9BTreeNode,@object # @_Z11bTreeKernelP9BTreeNode .section .rodata,"a",@progbits .globl _Z11bTreeKernelP9BTreeNode .p2align 3, 0x0 _Z11bTreeKernelP9BTreeNode: .quad _Z26__device_stub__bTreeKernelP9BTreeNode .size _Z11bTreeKernelP9BTreeNode, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " - " .size .L.str.1, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "hipMalloc failed" .size .L.str.2, 17 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMemcpy failed" .size .L.str.3, 17 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed" .size .L.str.4, 21 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "The kernel executed correctly." .size .L.str.5, 31 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "The kernel did not execute correctly." .size .L.str.6, 38 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipFree failed" .size .L.str.7, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11bTreeKernelP9BTreeNode" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__bTreeKernelP9BTreeNode .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11bTreeKernelP9BTreeNode .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
3,816
4,863
113,448
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15matrixMulKernelPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R9, SR_CTAID.X ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.MOV.U32 R21, RZ, RZ, RZ ; S2R R12, SR_TID.X ; ISETP.GE.AND P1, PT, R6, -0xe, PT ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; LEA R0, R9, R12, 0x4 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; LEA R3, R3, R2, 0x4 ; ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; @!P1 BRA 0x5b0 ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R6, R6, -0x1, RZ ; IMAD R4, R3, c[0x0][0x178], R12.reuse ; SHF.L.U32 R15, R2.reuse, 0x6, RZ ; IMAD R16, R2, c[0x0][0x178], R12 ; SHF.R.S32.HI R7, RZ, 0x1f, R6 ; HFMA2.MMA R21, -RZ, RZ, 0, 0 ; LEA R18, R12, 0x400, 0x2 ; IMAD R16, R9, 0x10, R16 ; LEA.HI R7, R7, R6, RZ, 0x4 ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; LEA R19, R12, R15, 0x2 ; UMOV UR4, 0xffffffff ; SHF.R.S32.HI R17, RZ, 0x4, R7 ; IMAD.MOV.U32 R13, RZ, RZ, R5 ; MOV R14, R4 ; ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; ISETP.GE.AND P2, PT, R12, c[0x0][0x178], PT ; ISETP.GE.OR P1, PT, R0, c[0x0][0x178], P1 ; ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; MOV R22, RZ ; MOV R28, RZ ; @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; @!P2 IMAD.MOV.U32 R4, RZ, RZ, R14 ; @!P2 MOV R5, R13 ; @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; @!P2 LDG.E R22, [R4.64] ; @!P1 LDG.E R28, [R24.64] ; UIADD3 UR4, UR4, 0x1, URZ ; IADD3 R14, P2, R14, 0x40, RZ ; IADD3 R2, R2, 0x10, RZ ; IADD3 R12, R12, 0x10, RZ ; ISETP.LE.AND P1, PT, R17, UR4, PT ; IADD3.X R13, RZ, R13, RZ, P2, !PT ; STS [R19], R22 ; STS [R19+0x400], R28 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R29, [R18] ; LDS.128 R8, [R15] ; LDS R24, [R18+0x40] ; LDS R27, [R18+0x80] ; LDS R26, [R18+0xc0] ; LDS R23, [R18+0x100] ; LDS.128 R4, [R15+0x10] ; LDS R20, [R18+0x140] ; LDS R25, [R18+0x180] ; LDS R22, [R18+0x1c0] ; FFMA R8, R29, R8, R21 ; LDS R21, [R18+0x200] ; FFMA R8, R24, R9, R8 ; LDS R24, [R18+0x240] ; FFMA R8, R27, R10, R8 ; FFMA R26, R26, R11, R8 ; LDS.128 R8, [R15+0x20] ; FFMA R4, R23, R4, R26 ; LDS R23, [R18+0x280] ; FFMA R4, R20, R5, R4 ; LDS R20, [R18+0x2c0] ; FFMA R4, R25, R6, R4 ; LDS R25, [R18+0x300] ; FFMA R26, R22, R7, R4 ; LDS.128 R4, [R15+0x30] ; LDS R22, [R18+0x340] ; FFMA R26, R21, R8, R26 ; LDS R21, [R18+0x380] ; FFMA R9, R24, R9, R26 ; LDS R8, [R18+0x3c0] ; FFMA R9, R23, R10, R9 ; FFMA R9, R20, R11, R9 ; FFMA R4, R25, R4, R9 ; FFMA R4, R22, R5, R4 ; MOV R5, c[0x0][0x178] ; IMAD R16, R5, 0x10, R16 ; FFMA R21, R21, R6, R4 ; FFMA R21, R8, R7, R21 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 BRA 0x1e0 ; @P0 EXIT ; HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R3, R3, c[0x0][0x178], R0 ; IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; STG.E [R2.64], R21 ; EXIT ; BRA 0x610; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15matrixMulKernelPfS_S_i ; -- Begin function _Z15matrixMulKernelPfS_S_i .globl _Z15matrixMulKernelPfS_S_i .p2align 8 .type _Z15matrixMulKernelPfS_S_i,@function _Z15matrixMulKernelPfS_S_i: ; @_Z15matrixMulKernelPfS_S_i ; %bb.0: s_clause 0x2 s_load_b32 s8, s[0:1], 0x18 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_bfe_u32 v2, v0, 10, 10 v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0x3ff, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshl_add_u32 v1, s15, 4, v2 v_lshl_add_u32 v0, s14, 4, v3 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s8, -14 s_cbranch_scc1 .LBB0_14 ; %bb.1: ; %.lr.ph v_lshlrev_b32_e32 v4, 2, v3 s_add_i32 s0, s8, -1 v_lshlrev_b32_e32 v5, 6, v2 s_ashr_i32 s1, s0, 31 v_mul_lo_u32 v8, v1, s8 v_add_nc_u32_e32 v6, 0x400, v4 s_lshr_b32 s1, s1, 28 v_cmp_gt_i32_e32 vcc_lo, s8, v1 s_add_i32 s1, s0, s1 v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, v5, v4 v_cmp_gt_i32_e64 s0, s8, v0 v_add_nc_u32_e32 v9, v6, v5 s_ashr_i32 s9, s1, 4 s_mov_b32 s10, 0 .LBB0_2: ; =>This Loop Header: Depth=1 ; Child Loop BB0_11 Depth 2 v_mov_b32_e32 v10, 0 s_and_saveexec_b32 s11, vcc_lo s_cbranch_execz .LBB0_6 ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 v_lshl_add_u32 v11, s10, 4, v3 v_mov_b32_e32 v10, 0 s_mov_b32 s12, exec_lo s_delay_alu instid0(VALU_DEP_2) v_cmpx_gt_i32_e64 s8, v11 s_cbranch_execz .LBB0_5 ; %bb.4: ; in Loop: Header=BB0_2 Depth=1 v_add_nc_u32_e32 v10, v11, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v11, 31, v10 v_lshlrev_b64 v[10:11], 2, v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v10, s1, s4, v10 v_add_co_ci_u32_e64 v11, s1, s5, v11, s1 global_load_b32 v10, v[10:11], off .LBB0_5: ; %Flow83 ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 .LBB0_6: ; in Loop: Header=BB0_2 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v11, 0 s_waitcnt vmcnt(0) ds_store_b32 v7, v10 s_and_saveexec_b32 s11, s0 s_cbranch_execz .LBB0_10 ; %bb.7: ; in Loop: Header=BB0_2 Depth=1 v_lshl_add_u32 v10, s10, 4, v2 v_mov_b32_e32 v11, 0 s_mov_b32 s12, exec_lo s_delay_alu instid0(VALU_DEP_2) v_cmpx_gt_i32_e64 s8, v10 s_cbranch_execz .LBB0_9 ; %bb.8: ; in Loop: Header=BB0_2 Depth=1 v_mad_u64_u32 v[11:12], null, v10, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v12, 31, v11 v_lshlrev_b64 v[10:11], 2, v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v10, s1, s6, v10 v_add_co_ci_u32_e64 v11, s1, s7, v11, s1 global_load_b32 v11, v[10:11], off .LBB0_9: ; %Flow ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 .LBB0_10: ; in Loop: Header=BB0_2 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v10, v6 s_mov_b32 s1, 0 s_waitcnt vmcnt(0) ds_store_b32 v9, v11 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_11: ; Parent Loop BB0_2 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v11, s1, v5 s_add_i32 s1, s1, 4 ds_load_b32 v12, v10 ds_load_b32 v11, v11 v_add_nc_u32_e32 v10, 64, v10 s_cmp_eq_u32 s1, 64 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v4, v11, v12 s_cbranch_scc0 .LBB0_11 ; %bb.12: ; in Loop: Header=BB0_2 Depth=1 s_add_i32 s1, s10, 1 s_cmp_eq_u32 s10, s9 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_14 ; %bb.13: ; in Loop: Header=BB0_2 Depth=1 s_mov_b32 s10, s1 s_branch .LBB0_2 .LBB0_14: ; %Flow85 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_max_i32_e32 v2, v1, v0 s_mov_b32 s0, exec_lo v_cmpx_gt_i32_e64 s8, v2 s_cbranch_execz .LBB0_16 ; %bb.15: v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v4, off .LBB0_16: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15matrixMulKernelPfS_S_i .amdhsa_group_segment_fixed_size 2048 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15matrixMulKernelPfS_S_i, .Lfunc_end0-_Z15matrixMulKernelPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 572 ; NumSgprs: 18 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 2048 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 2048 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15matrixMulKernelPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15matrixMulKernelPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0013b46f_00000000-6_cuda_code_074388.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3635: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3635: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i .type _Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i, @function _Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i: .LFB3661: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z15matrixMulKernelPfS_S_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L8: movq 136(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i .globl _Z15matrixMulKernelPfS_S_i .type _Z15matrixMulKernelPfS_S_i, @function _Z15matrixMulKernelPfS_S_i: .LFB3662: .cfi_startproc endbr64 jmp _Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i .cfi_endproc .LFE3662: .size _Z15matrixMulKernelPfS_S_i, .-_Z15matrixMulKernelPfS_S_i .section .rodata.str1.1 .LC5: .string "Failed to allocate device memory for A" .LC6: .string "Failed to allocate device memory for B" .LC7: .string "Failed to allocate device memory for C" .LC8: .string "Failed to copy A to device" .LC9: .string "Failed to copy B to device" .LC10: .string "Kernel launch failed" .LC11: .string "Failed to copy C from device" .LC12: .string "Matrix multiplication completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $65536, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call malloc@PLT movl $65536, %edi movq %rax, %rbp call malloc@PLT movl $65536, %edi movq %rax, %rbx call malloc@PLT movss .LC3(%rip), %xmm0 movss .LC4(%rip), %xmm1 xorl %edx, %edx movq %rax, %r12 .L14: movq %rdx, %rax movl $128, %ecx .L15: movss %xmm0, 0(%rbp,%rax) movss %xmm1, (%rbx,%rax) addq $4, %rax decl %ecx jne .L15 addq $512, %rdx cmpq $65536, %rdx jne .L14 leaq 8(%rsp), %rdi movl $65536, %esi call cudaMalloc@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 16(%rsp), %rdi movl $65536, %esi call cudaMalloc@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 24(%rsp), %rdi movl $65536, %esi call cudaMalloc@PLT leaq .LC7(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $65536, %edx call cudaMemcpy@PLT leaq .LC8(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $65536, %edx call cudaMemcpy@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movabsq $68719476752, %rdx movl $1, %esi movabsq $34359738376, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L17 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $128, %ecx movq 8(%rsp), %rdi call _Z40__device_stub__Z15matrixMulKernelPfS_S_iPfS_S_i .L17: call cudaGetLastError@PLT leaq .LC10(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rsi movl $2, %ecx movq %r12, %rdi movl $65536, %edx call cudaMemcpy@PLT leaq .LC11(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r12, %rdi call free@PLT leaq _ZSt4cout(%rip), %rdi leaq .LC12(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 56(%rsp), %rax subq %fs:40, %rax je .L18 call __stack_chk_fail@PLT .L18: addq $64, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC13: .string "_Z15matrixMulKernelPfS_S_i" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rax, %rdi leaq _Z15matrixMulKernelPfS_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC3: .long 1065353216 .align 4 .LC4: .long 1073741824 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_074388.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__matrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_i .type _Z30__device_stub__matrixMulKernelPfS_S_i,@function _Z30__device_stub__matrixMulKernelPfS_S_i: # @_Z30__device_stub__matrixMulKernelPfS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15matrixMulKernelPfS_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__matrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__matrixMulKernelPfS_S_i .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $32, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $65536, %edi # imm = 0x10000 callq malloc movq %rax, %rbx movl $65536, %edi # imm = 0x10000 callq malloc movq %rax, %r14 movl $65536, %edi # imm = 0x10000 callq malloc movq %rax, %r15 xorl %eax, %eax movl $512, %ecx # imm = 0x200 movq %rbx, %rdx movq %r14, %rsi .LBB2_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_2 Depth 2 xorl %edi, %edi .LBB2_2: # Parent Loop BB2_1 Depth=1 # => This Inner Loop Header: Depth=2 movl $1065353216, (%rdx,%rdi,4) # imm = 0x3F800000 movl $1073741824, (%rsi,%rdi,4) # imm = 0x40000000 incq %rdi cmpq $128, %rdi jne .LBB2_2 # %bb.3: # in Loop: Header=BB2_1 Depth=1 incq %rax addq %rcx, %rsi addq %rcx, %rdx cmpq $128, %rax jne .LBB2_1 # %bb.4: leaq 24(%rsp), %r13 movl $65536, %esi # imm = 0x10000 movq %r13, %rdi callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 16(%rsp), %r12 movl $65536, %esi # imm = 0x10000 movq %r12, %rdi callq hipMalloc movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 8(%rsp), %rdi movl $65536, %esi # imm = 0x10000 callq hipMalloc movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r13), %rdi movl $65536, %edx # imm = 0x10000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r12), %rdi movl $65536, %edx # imm = 0x10000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $34359738376, %rdi # imm = 0x800000008 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_6 # %bb.5: movq 24(%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movl $128, %ecx callq _Z30__device_stub__matrixMulKernelPfS_S_i .LBB2_6: callq hipGetLastError movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rsi movl $65536, %edx # imm = 0x10000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $45, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $32, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15matrixMulKernelPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z15matrixMulKernelPfS_S_i,@object # @_Z15matrixMulKernelPfS_S_i .section .rodata,"a",@progbits .globl _Z15matrixMulKernelPfS_S_i .p2align 3, 0x0 _Z15matrixMulKernelPfS_S_i: .quad _Z30__device_stub__matrixMulKernelPfS_S_i .size _Z15matrixMulKernelPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate device memory for A" .size .L.str.3, 39 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate device memory for B" .size .L.str.4, 39 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to allocate device memory for C" .size .L.str.5, 39 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy A to device" .size .L.str.6, 27 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to copy B to device" .size .L.str.7, 27 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Kernel launch failed" .size .L.str.8, 21 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to copy C from device" .size .L.str.9, 29 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Matrix multiplication completed successfully." .size .L.str.10, 46 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15matrixMulKernelPfS_S_i" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__matrixMulKernelPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15matrixMulKernelPfS_S_i .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,224
5,248
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z27homomorphicEncryptionKernelPiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R3, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B0, 0x310 ; IMAD R0, R0, c[0x0][0xc], RZ ; I2F.U32.RP R6, R0 ; IADD3 R9, RZ, -R0, RZ ; IMAD.IADD R2, R0.reuse, 0x1, R3 ; ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; IADD3 R7, R7, c[0x0][0x170], R0 ; MUFU.RCP R6, R6 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IMAD R9, R9, R5, RZ ; IMAD.HI.U32 R2, R5, R9, R4 ; IMAD.HI.U32 R2, R2, R7, RZ ; IADD3 R4, -R2, RZ, RZ ; IMAD R7, R0, R4, R7 ; ISETP.GE.U32.AND P0, PT, R7, R0, PT ; @P0 IMAD.IADD R7, R7, 0x1, -R0 ; @P0 IADD3 R2, R2, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R7, R0, PT ; @P1 IADD3 R2, R2, 0x1, RZ ; @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; IADD3 R4, R2.reuse, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x300 ; IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; MOV R2, R4 ; IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; LDG.E R8, [R6.64] ; IADD3 R2, R2, -0x1, RZ ; IMAD.IADD R3, R0, 0x1, R3 ; ISETP.NE.AND P0, PT, R2, RZ, PT ; IMAD.WIDE R6, R0, 0x4, R6 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R4.64], R9 ; IMAD.WIDE R4, R0, 0x4, R4 ; @P0 BRA 0x270 ; BSYNC B0 ; @!P1 EXIT ; HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; LDG.E R2, [R4.64] ; IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; IMAD.WIDE R8, R0, 0x4, R4 ; IADD3 R17, R2, 0x1, RZ ; STG.E [R6.64], R17 ; LDG.E R2, [R8.64] ; IMAD.WIDE R10, R0, 0x4, R6 ; IMAD.WIDE R12, R0, 0x4, R8 ; IADD3 R19, R2, 0x1, RZ ; STG.E [R10.64], R19 ; LDG.E R2, [R12.64] ; IMAD.WIDE R4, R0, 0x4, R10 ; IMAD.WIDE R14, R0, 0x4, R12 ; IADD3 R21, R2, 0x1, RZ ; STG.E [R4.64], R21 ; LDG.E R14, [R14.64] ; IMAD.WIDE R6, R0.reuse, 0x4, R4 ; IADD3 R3, R0, R3, R0 ; IADD3 R3, R0, R3, R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; IADD3 R9, R14, 0x1, RZ ; STG.E [R6.64], R9 ; @!P0 BRA 0x320 ; EXIT ; BRA 0x4c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z27homomorphicEncryptionKernelPiS_i ; -- Begin function _Z27homomorphicEncryptionKernelPiS_i .globl _Z27homomorphicEncryptionKernelPiS_i .p2align 8 .type _Z27homomorphicEncryptionKernelPiS_i,@function _Z27homomorphicEncryptionKernelPiS_i: ; @_Z27homomorphicEncryptionKernelPiS_i ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b32 s10, s[0:1], 0x10 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s10, v1 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph.preheader s_load_b32 s2, s[2:3], 0x0 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s2, s2, s8 s_ashr_i32 s3, s2, 31 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[8:9], s[2:3], 2 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) v_add_co_u32 v4, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo v_add_nc_u32_e32 v1, s2, v1 global_load_b32 v0, v[4:5], off v_add_co_u32 v4, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v2, vcc_lo, v2, s8 v_cmp_le_i32_e64 s0, s10, v1 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) s_or_b32 s1, s0, s1 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v0, 1, v0 global_store_b32 v[4:5], v0, off s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow19 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z27homomorphicEncryptionKernelPiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z27homomorphicEncryptionKernelPiS_i, .Lfunc_end0-_Z27homomorphicEncryptionKernelPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 228 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z27homomorphicEncryptionKernelPiS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z27homomorphicEncryptionKernelPiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_001512b9_00000000-6_cuda_code_073045.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4292: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4292: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i .type _Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i, @function _Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i: .LFB3660: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movl %edx, 12(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z27homomorphicEncryptionKernelPiS_i(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L3: movq 120(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i, .-_Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i .globl _Z27homomorphicEncryptionKernelPiS_i .type _Z27homomorphicEncryptionKernelPiS_i, @function _Z27homomorphicEncryptionKernelPiS_i: .LFB3661: .cfi_startproc endbr64 jmp _Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i .cfi_endproc .LFE3661: .size _Z27homomorphicEncryptionKernelPiS_i, .-_Z27homomorphicEncryptionKernelPiS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate device memory for data (error code " .LC1: .string ")" .LC2: .string "Failed to allocate device memory for result (error code " .LC3: .string "Failed to copy data from host to device (error code " .LC4: .string "Kernel launch failed (error code " .LC5: .string "Failed to copy result from device to host (error code " .LC6: .string "Homomorphic encryption operation failed!" .LC7: .string "Homomorphic encryption operation successful!" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $4096, %rsp .cfi_def_cfa_offset 4128 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 8224 orq $0, (%rsp) subq $48, %rsp .cfi_def_cfa_offset 8272 movq %fs:40, %rax movq %rax, 8232(%rsp) xorl %eax, %eax leaq 40(%rsp), %rbp .L10: movl %eax, 0(%rbp,%rax,4) incq %rax cmpq $1024, %rax jne .L10 movq %rsp, %rdi movl $4096, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L11 leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L12 .L11: leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi .L30: call cudaFree@PLT .L12: orl $-1, %eax jmp .L9 .L13: movq (%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $4096, %edx call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L32 movl $16777217, %edx movl $1073741825, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx salq $2, %rdi movl $1, %ecx movl $1, %esi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rsi movq (%rsp), %rdi movl $1024, %edx call _Z50__device_stub__Z27homomorphicEncryptionKernelPiS_iPiS_i .L16: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L32 movq 8(%rsp), %rsi movl $4096, %edx movl $2, %ecx leaq 4136(%rsp), %r12 movq %r12, %rdi call cudaMemcpy@PLT xorl %edx, %edx movl %eax, %ebx testl %eax, %eax je .L18 leaq .LC5(%rip), %rsi .L32: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi jmp .L30 .L18: movl 0(%rbp,%rdx), %eax incl %eax cmpl %eax, (%r12,%rdx) jne .L19 addq $4, %rdx cmpq $4096, %rdx jne .L18 leaq .LC7(%rip), %rsi jmp .L31 .L19: leaq .LC6(%rip), %rsi .L31: leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L9: movq 8232(%rsp), %rdx subq %fs:40, %rdx je .L22 call __stack_chk_fail@PLT .L22: addq $8240, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z27homomorphicEncryptionKernelPiS_i" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi leaq _Z27homomorphicEncryptionKernelPiS_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_073045.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z42__device_stub__homomorphicEncryptionKernelPiS_i # -- Begin function _Z42__device_stub__homomorphicEncryptionKernelPiS_i .type _Z42__device_stub__homomorphicEncryptionKernelPiS_i,@function _Z42__device_stub__homomorphicEncryptionKernelPiS_i: # @_Z42__device_stub__homomorphicEncryptionKernelPiS_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z27homomorphicEncryptionKernelPiS_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z42__device_stub__homomorphicEncryptionKernelPiS_i, .Lfunc_end0-_Z42__device_stub__homomorphicEncryptionKernelPiS_i .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $8208, %rsp # imm = 0x2010 .cfi_def_cfa_offset 8224 .cfi_offset %rbx, -16 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %eax, 16(%rsp,%rax,4) incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB1_1 # %bb.2: movq %rsp, %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax je .LBB1_4 # %bb.3: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $54, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebx, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_15 .LBB1_4: leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax je .LBB1_6 # %bb.5: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $56, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebx, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi jmp .LBB1_14 .LBB1_6: movq (%rsp), %rdi leaq 16(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_8 # %bb.7: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $52, %edx jmp .LBB1_12 .LBB1_8: movabsq $4294967300, %rdi # imm = 0x100000004 leaq 252(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_10 # %bb.9: movq (%rsp), %rdi movq 8(%rsp), %rsi movl $1024, %edx # imm = 0x400 callq _Z42__device_stub__homomorphicEncryptionKernelPiS_i .LBB1_10: callq hipGetLastError testl %eax, %eax je .LBB1_17 # %bb.11: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $33, %edx .LBB1_12: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebx, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_13: movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi .LBB1_14: callq hipFree .LBB1_15: movl $-1, %eax .LBB1_16: addq $8208, %rsp # imm = 0x2010 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_17: .cfi_def_cfa_offset 8224 movq 8(%rsp), %rsi leaq 4112(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_19 # %bb.18: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $54, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebx, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %rbx, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_13 .LBB1_19: # %.preheader.preheader xorl %eax, %eax .LBB1_20: # %.preheader # =>This Inner Loop Header: Depth=1 movl 16(%rsp,%rax,4), %ecx incl %ecx cmpl %ecx, 4112(%rsp,%rax,4) jne .LBB1_23 # %bb.21: # in Loop: Header=BB1_20 Depth=1 incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB1_20 # %bb.22: # %.critedge movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $44, %edx jmp .LBB1_24 .LBB1_23: movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $40, %edx .LBB1_24: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_16 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z27homomorphicEncryptionKernelPiS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z27homomorphicEncryptionKernelPiS_i,@object # @_Z27homomorphicEncryptionKernelPiS_i .section .rodata,"a",@progbits .globl _Z27homomorphicEncryptionKernelPiS_i .p2align 3, 0x0 _Z27homomorphicEncryptionKernelPiS_i: .quad _Z42__device_stub__homomorphicEncryptionKernelPiS_i .size _Z27homomorphicEncryptionKernelPiS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory for data (error code " .size .L.str, 55 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz ")" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate device memory for result (error code " .size .L.str.2, 57 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy data from host to device (error code " .size .L.str.3, 53 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed (error code " .size .L.str.4, 34 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy result from device to host (error code " .size .L.str.5, 55 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Homomorphic encryption operation successful!" .size .L.str.6, 45 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Homomorphic encryption operation failed!" .size .L.str.7, 41 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z27homomorphicEncryptionKernelPiS_i" .size .L__unnamed_1, 37 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z42__device_stub__homomorphicEncryptionKernelPiS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z27homomorphicEncryptionKernelPiS_i .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,104
5,040
113,452
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z23featureExtractionKernelPKfPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R7, SR_TID.Y ; ULDC.64 UR4, c[0x0][0x118] ; S2R R0, SR_CTAID.Y ; S2R R8, SR_TID.X ; S2R R3, SR_CTAID.X ; IMAD R0, R0, c[0x0][0x4], R7 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; IMAD R3, R3, c[0x0][0x0], R8 ; ISETP.LT.AND P0, PT, R3, c[0x0][0x170], !P0 ; @P0 MOV R5, 0x4 ; @P0 IMAD R4, R0, c[0x0][0x170], R3 ; @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; @P0 LDG.E R4, [R4.64] ; IADD3 R2, R8, -0x1, RZ ; BSSY B0, 0x2b0 ; IADD3 R6, R7.reuse, -0x1, RZ ; ISETP.GT.U32.AND P1, PT, R2, 0x1d, PT ; LEA R21, R7, R8, 0x5 ; HFMA2.MMA R7, -RZ, RZ, 0, 0 ; ISETP.GT.U32.OR P1, PT, R6, 0x1d, P1 ; @!P0 STS [R21.X4], RZ ; @P0 STS [R21.X4], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P1 BRA 0x2a0 ; LDS R2, [R21.X4+-0x80] ; LDS R5, [R21.X4+-0x84] ; LDS R7, [R21.X4+-0x7c] ; LDS R9, [R21.X4+-0x4] ; LDS R11, [R21.X4] ; LDS R13, [R21.X4+0x4] ; LDS R15, [R21.X4+0x7c] ; LDS R17, [R21.X4+0x80] ; LDS R19, [R21.X4+0x84] ; FADD R2, R2, R5 ; FADD R2, R2, R7 ; FADD R2, R2, R9 ; FADD R2, R2, R11 ; FADD R2, R2, R13 ; FADD R2, R2, R15 ; FADD R2, R2, R17 ; FADD R7, R2, R19 ; BSYNC B0 ; @!P0 EXIT ; MOV R2, 0x4 ; IMAD R3, R0, c[0x0][0x170], R3 ; IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; STG.E [R2.64], R7 ; EXIT ; BRA 0x310; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z23featureExtractionKernelPKfPfii ; -- Begin function _Z23featureExtractionKernelPKfPfii .globl _Z23featureExtractionKernelPKfPfii .p2align 8 .type _Z23featureExtractionKernelPKfPfii,@function _Z23featureExtractionKernelPKfPfii: ; @_Z23featureExtractionKernelPKfPfii ; %bb.0: s_clause 0x2 s_load_b32 s8, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b128 s[4:7], s[0:1], 0x0 v_and_b32_e32 v3, 0x3ff, v0 v_bfe_u32 v4, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s1, s8, 0xffff s_lshr_b32 s0, s8, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_mad_u64_u32 v[0:1], null, s14, s1, v[3:4] v_mad_u64_u32 v[1:2], null, s15, s0, v[4:5] v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0 v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s0, s3, v1 s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_2 ; %bb.1: v_mad_u64_u32 v[5:6], null, v1, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v6, 31, v5 v_lshlrev_b64 v[5:6], 2, v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b32 v5, v[5:6], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s1 v_add_nc_u32_e32 v6, -1, v3 v_add_nc_u32_e32 v7, -1, v4 v_lshlrev_b32_e32 v3, 2, v3 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_max_u32_e32 v8, v6, v7 v_lshl_add_u32 v3, v4, 7, v3 s_waitcnt vmcnt(0) ds_store_b32 v3, v5 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 30, v8 s_cbranch_execz .LBB0_4 ; %bb.3: v_lshlrev_b32_e32 v2, 2, v6 v_add_nc_u32_e32 v6, -4, v3 s_delay_alu instid0(VALU_DEP_2) v_lshl_add_u32 v2, v7, 7, v2 ds_load_2addr_b32 v[4:5], v2 offset1:1 v_add_nc_u32_e32 v2, 0xffffff84, v3 ds_load_b32 v10, v2 ds_load_2addr_b32 v[6:7], v6 offset1:1 ds_load_2addr_b32 v[8:9], v3 offset0:31 offset1:32 ds_load_2addr_b32 v[2:3], v3 offset0:1 offset1:33 s_waitcnt lgkmcnt(4) v_add_f32_e32 v4, v4, v5 s_waitcnt lgkmcnt(3) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f32_e32 v4, v4, v10 s_waitcnt lgkmcnt(2) v_add_f32_e32 v4, v4, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f32_e32 v4, v4, v7 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v4, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v2, v2, v8 v_add_f32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v2, v2, v3 .LBB0_4: s_or_b32 exec_lo, exec_lo, s1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_6 ; %bb.5: v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23featureExtractionKernelPKfPfii .amdhsa_group_segment_fixed_size 4096 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z23featureExtractionKernelPKfPfii, .Lfunc_end0-_Z23featureExtractionKernelPKfPfii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 444 ; NumSgprs: 18 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 4096 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 4096 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23featureExtractionKernelPKfPfii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z23featureExtractionKernelPKfPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00009bcd_00000000-6_cuda_code_016488.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4292: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4292: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii .type _Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii, @function _Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii: .LFB3660: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movl %edx, 12(%rsp) leaq 40(%rsp), %rdx movl %ecx, 8(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z23featureExtractionKernelPKfPfii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L3: movq 136(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii, .-_Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii .globl _Z23featureExtractionKernelPKfPfii .type _Z23featureExtractionKernelPKfPfii, @function _Z23featureExtractionKernelPKfPfii: .LFB3661: .cfi_startproc endbr64 jmp _Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii .cfi_endproc .LFE3661: .size _Z23featureExtractionKernelPKfPfii, .-_Z23featureExtractionKernelPKfPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Error allocating device memory for input: " .LC2: .string "Error allocating device memory for output: " .LC3: .string "Error copying input data to device: " .LC4: .string "Error launching kernel: " .LC5: .string "Error copying output data to host: " .LC6: .string "Feature extraction completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $16777216, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call malloc@PLT movl $16777216, %edi movq %rax, %rbx call malloc@PLT movss .LC0(%rip), %xmm0 movq %rax, %rbp xorl %eax, %eax .L10: movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $4194304, %rax jne .L10 movq %rsp, %rdi movl $16777216, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L11 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L12 .L11: leaq 8(%rsp), %rdi movl $16777216, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi .L22: call cudaFree@PLT .L12: orl $-1, %eax jmp .L9 .L13: movq (%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $16777216, %edx call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L23 xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movl $1, %esi movabsq $137438953504, %rdx movabsq $274877907008, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rsi movq (%rsp), %rdi movl $2048, %ecx movl $2048, %edx call _Z48__device_stub__Z23featureExtractionKernelPKfPfiiPKfPfii .L16: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L23 movq 8(%rsp), %rsi movl $2, %ecx movl $16777216, %edx movq %rbp, %rdi call cudaMemcpy@PLT movl %eax, %r12d testl %eax, %eax je .L18 leaq .LC5(%rip), %rsi .L23: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi jmp .L22 .L18: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call free@PLT movq %rbp, %rdi call free@PLT leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L9: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L19 call __stack_chk_fail@PLT .L19: addq $48, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z23featureExtractionKernelPKfPfii" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rax, %rdi leaq _Z23featureExtractionKernelPKfPfii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_016488.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z38__device_stub__featureExtractionKernelPKfPfii # -- Begin function _Z38__device_stub__featureExtractionKernelPKfPfii .type _Z38__device_stub__featureExtractionKernelPKfPfii,@function _Z38__device_stub__featureExtractionKernelPKfPfii: # @_Z38__device_stub__featureExtractionKernelPKfPfii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 8(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z23featureExtractionKernelPKfPfii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z38__device_stub__featureExtractionKernelPKfPfii, .Lfunc_end0-_Z38__device_stub__featureExtractionKernelPKfPfii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $16, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl $16777216, %edi # imm = 0x1000000 callq malloc movq %rax, %rbx movl $16777216, %edi # imm = 0x1000000 callq malloc movq %rax, %r14 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 incq %rax cmpq $4194304, %rax # imm = 0x400000 jne .LBB1_1 # %bb.2: movq %rsp, %rdi movl $16777216, %esi # imm = 0x1000000 callq hipMalloc testl %eax, %eax je .LBB1_5 # %bb.3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_8 # %bb.4: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_9 .LBB1_5: leaq 8(%rsp), %rdi movl $16777216, %esi # imm = 0x1000000 callq hipMalloc testl %eax, %eax je .LBB1_10 # %bb.6: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $43, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_12 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_13 .LBB1_8: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_24 .LBB1_10: movq (%rsp), %rdi movl $16777216, %edx # imm = 0x1000000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_14 # %bb.11: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $36, %edx jmp .LBB1_18 .LBB1_12: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit36 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi jmp .LBB1_23 .LBB1_14: movabsq $274877907008, %rdi # imm = 0x4000000040 movabsq $137438953504, %rdx # imm = 0x2000000020 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_16 # %bb.15: movq (%rsp), %rdi movq 8(%rsp), %rsi movl $2048, %edx # imm = 0x800 movl $2048, %ecx # imm = 0x800 callq _Z38__device_stub__featureExtractionKernelPKfPfii .LBB1_16: callq hipGetLastError testl %eax, %eax je .LBB1_26 # %bb.17: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $24, %edx .LBB1_18: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_20 # %bb.19: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_21 .LBB1_20: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit38 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_22: movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi .LBB1_23: callq hipFree .LBB1_24: movl $-1, %eax .LBB1_25: addq $16, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_26: .cfi_def_cfa_offset 48 movq 8(%rsp), %rsi movl $16777216, %edx # imm = 0x1000000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_28 # %bb.27: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_22 .LBB1_28: movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB1_25 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23featureExtractionKernelPKfPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z23featureExtractionKernelPKfPfii,@object # @_Z23featureExtractionKernelPKfPfii .section .rodata,"a",@progbits .globl _Z23featureExtractionKernelPKfPfii .p2align 3, 0x0 _Z23featureExtractionKernelPKfPfii: .quad _Z38__device_stub__featureExtractionKernelPKfPfii .size _Z23featureExtractionKernelPKfPfii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error allocating device memory for input: " .size .L.str, 43 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error allocating device memory for output: " .size .L.str.1, 44 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Error copying input data to device: " .size .L.str.2, 37 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Error launching kernel: " .size .L.str.3, 25 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error copying output data to host: " .size .L.str.4, 36 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Feature extraction completed successfully." .size .L.str.5, 43 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z23featureExtractionKernelPKfPfii" .size .L__unnamed_1, 35 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z38__device_stub__featureExtractionKernelPKfPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z23featureExtractionKernelPKfPfii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,067
5,624
113,454
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z23sparseConvolutionKernelPKfS0_PfPii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; HFMA2.MMA R25, -RZ, RZ, 0, 0 ; SHF.R.S32.HI R7, RZ, 0x1f, R0 ; ULDC.64 UR6, c[0x0][0x160] ; IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; LDG.E.CONSTANT R6, [R2.64] ; MOV R4, c[0x0][0x168] ; MOV R5, c[0x0][0x16c] ; MOV R8, RZ ; MOV R2, UR6 ; LDG.E.CONSTANT R16, [R4.64] ; MOV R3, UR7 ; LDG.E.CONSTANT R18, [R4.64+0x4] ; IMAD.WIDE R2, R6, 0x4, R2 ; LDG.E.CONSTANT R19, [R4.64+0x8] ; LDG.E.CONSTANT R15, [R2.64] ; LDG.E.CONSTANT R17, [R2.64+0x4] ; LDG.E.CONSTANT R20, [R2.64+0x8] ; LDG.E.CONSTANT R22, [R4.64+0xc] ; LDG.E.CONSTANT R21, [R2.64+0xc] ; LDG.E.CONSTANT R23, [R4.64+0x10] ; LDG.E.CONSTANT R24, [R2.64+0x10] ; LDG.E.CONSTANT R9, [R4.64+0x14] ; LDG.E.CONSTANT R10, [R2.64+0x14] ; LDG.E.CONSTANT R11, [R4.64+0x18] ; LDG.E.CONSTANT R12, [R2.64+0x18] ; LDG.E.CONSTANT R13, [R4.64+0x1c] ; LDG.E.CONSTANT R14, [R2.64+0x1c] ; LDG.E.CONSTANT R26, [R2.64+0x3c] ; FFMA R25, R16, R15, R25 ; LDG.E.CONSTANT R15, [R4.64+0x20] ; LDG.E.CONSTANT R16, [R2.64+0x20] ; FFMA R25, R18, R17, R25 ; LDG.E.CONSTANT R17, [R4.64+0x24] ; FFMA R25, R19, R20, R25 ; LDG.E.CONSTANT R18, [R2.64+0x24] ; LDG.E.CONSTANT R19, [R4.64+0x28] ; FFMA R25, R22, R21, R25 ; LDG.E.CONSTANT R20, [R2.64+0x28] ; LDG.E.CONSTANT R21, [R4.64+0x2c] ; FFMA R25, R23, R24, R25 ; LDG.E.CONSTANT R22, [R2.64+0x2c] ; LDG.E.CONSTANT R23, [R4.64+0x30] ; FFMA R25, R9, R10, R25 ; LDG.E.CONSTANT R24, [R2.64+0x30] ; LDG.E.CONSTANT R9, [R4.64+0x34] ; FFMA R27, R11, R12, R25 ; LDG.E.CONSTANT R10, [R2.64+0x34] ; LDG.E.CONSTANT R12, [R4.64+0x38] ; LDG.E.CONSTANT R11, [R2.64+0x38] ; LDG.E.CONSTANT R25, [R4.64+0x3c] ; FFMA R13, R13, R14, R27 ; IADD3 R8, R8, 0x10, RZ ; ISETP.NE.AND P0, PT, R8, 0x200, PT ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; IADD3 R4, P1, R4, 0x40, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IADD3.X R5, RZ, R5, RZ, P1, !PT ; FFMA R13, R15, R16, R13 ; FFMA R13, R17, R18, R13 ; FFMA R13, R19, R20, R13 ; FFMA R13, R21, R22, R13 ; FFMA R13, R23, R24, R13 ; FFMA R9, R9, R10, R13 ; FFMA R9, R12, R11, R9 ; FFMA R25, R25, R26, R9 ; @P0 BRA 0x100 ; LEA R2, P0, R0, c[0x0][0x170], 0x2 ; LEA.HI.X R3, R0, c[0x0][0x174], R7, 0x2, P0 ; STG.E [R2.64], R25 ; EXIT ; BRA 0x4e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z23sparseConvolutionKernelPKfS0_PfPii ; -- Begin function _Z23sparseConvolutionKernelPKfS0_PfPii .globl _Z23sparseConvolutionKernelPKfS0_PfPii .p2align 8 .type _Z23sparseConvolutionKernelPKfS0_PfPii,@function _Z23sparseConvolutionKernelPKfS0_PfPii: ; @_Z23sparseConvolutionKernelPKfS0_PfPii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b32 s3, s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_4 ; %bb.1: s_load_b256 s[0:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[3:4], 2, v[2:3] v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v3, vcc_lo, s0, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo s_mov_b64 s[0:1], 0 .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) v_add_co_u32 v5, vcc_lo, v3, s0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo s_add_u32 s6, s2, s0 s_addc_u32 s7, s3, s1 s_add_u32 s0, s0, 4 global_load_b32 v5, v[5:6], off s_load_b32 s6, s[6:7], 0x0 s_addc_u32 s1, s1, 0 s_cmpk_eq_i32 s0, 0x800 s_waitcnt vmcnt(0) lgkmcnt(0) v_fmac_f32_e32 v2, s6, v5 s_cbranch_scc0 .LBB0_2 ; %bb.3: v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23sparseConvolutionKernelPKfS0_PfPii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z23sparseConvolutionKernelPKfS0_PfPii, .Lfunc_end0-_Z23sparseConvolutionKernelPKfS0_PfPii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 252 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23sparseConvolutionKernelPKfS0_PfPii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z23sparseConvolutionKernelPKfS0_PfPii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000c7421_00000000-6_cuda_code_035490.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4292: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4292: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii .type _Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii, @function _Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii: .LFB3660: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movl %r8d, 12(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 16(%rsp), %rax movq %rdi, 16(%rsp) leaq 64(%rsp), %rdi movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 40(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rsi, 24(%rsp) leaq 76(%rsp), %rsi movq %rdx, 32(%rsp) leaq 48(%rsp), %rdx movq %rcx, 40(%rsp) leaq 56(%rsp), %rcx movq %rax, 144(%rsp) movabsq $4294967297, %rax movq %rax, 64(%rsp) movl $1, 72(%rsp) movq %rax, 76(%rsp) movl $1, 84(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 56(%rsp) .cfi_def_cfa_offset 184 leaq _Z23sparseConvolutionKernelPKfS0_PfPii(%rip), %rdi pushq 56(%rsp) .cfi_def_cfa_offset 192 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq 128(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 184 popq %rdx .cfi_def_cfa_offset 176 .L3: movq 152(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $168, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii, .-_Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii .globl _Z23sparseConvolutionKernelPKfS0_PfPii .type _Z23sparseConvolutionKernelPKfS0_PfPii, @function _Z23sparseConvolutionKernelPKfS0_PfPii: .LFB3661: .cfi_startproc endbr64 jmp _Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii .cfi_endproc .LFE3661: .size _Z23sparseConvolutionKernelPKfS0_PfPii, .-_Z23sparseConvolutionKernelPKfS0_PfPii .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "Error allocating memory for d_input: " .LC3: .string "Error allocating memory for d_filter: " .LC4: .string "Error allocating memory for d_output: " .LC5: .string "Error allocating memory for d_inputIndices: " .LC6: .string "Error copying h_input to d_input: " .LC7: .string "Error copying h_filter to d_filter: " .LC8: .string "Error copying h_inputIndices to d_inputIndices: " .LC9: .string "Error launching kernel: " .LC10: .string "Error copying d_output to h_output: " .LC11: .string "Sparse convolution completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 movl $2048, %edi pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $2048, %edi movq %rax, %r12 call _Znam@PLT movl $2048, %edi movq %rax, %rbp call _Znam@PLT movl $2048, %edi movq %rax, %r13 call _Znam@PLT movss .LC0(%rip), %xmm0 movq %rax, %rbx xorl %eax, %eax .L10: movl %eax, (%rbx,%rax,4) movss %xmm0, (%r12,%rax,4) incq %rax cmpq $512, %rax jne .L10 movss .LC1(%rip), %xmm0 xorl %eax, %eax .L11: movss %xmm0, 0(%rbp,%rax,4) incq %rax cmpq $512, %rax jne .L11 movl $2048, %esi movq %rsp, %rdi call cudaMalloc@PLT leaq .LC2(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 leaq 8(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT movl %eax, %r14d testl %eax, %eax je .L14 leaq .LC3(%rip), %rsi .L28: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r14d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L9 .L14: movl $2048, %esi leaq 16(%rsp), %rdi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movl $2048, %esi leaq 24(%rsp), %rdi call cudaMalloc@PLT leaq .LC5(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq (%rsp), %rdi movq %r12, %rsi movl $1, %ecx movl $2048, %edx call cudaMemcpy@PLT leaq .LC6(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq 8(%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $2048, %edx call cudaMemcpy@PLT leaq .LC7(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq 24(%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $2048, %edx call cudaMemcpy@PLT leaq .LC8(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movl $16777217, %edx movl $2147483649, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx addq %rdi, %rdi movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L21 movq 24(%rsp), %rcx movq 16(%rsp), %rdx movl $512, %r8d movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z52__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiiPKfS0_PfPii .L21: call cudaGetLastError@PLT leaq .LC9(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq 16(%rsp), %rsi movl $2, %ecx movl $2048, %edx movq %r13, %rdi call cudaMemcpy@PLT leaq .LC10(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %r13, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT leaq .LC11(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L9: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L24 call __stack_chk_fail@PLT .L24: addq $64, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z23sparseConvolutionKernelPKfS0_PfPii" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rax, %rdi leaq _Z23sparseConvolutionKernelPKfS0_PfPii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .align 4 .LC1: .long 1056964608 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_035490.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii .type _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii,@function _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii: # @_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 12(%rsp), %rcx movl %r8d, (%rcx) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z23sparseConvolutionKernelPKfS0_PfPii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $32, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %rbx movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %r14 movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %r15 movl $2048, %edi # imm = 0x800 callq _Znam movq %rax, %r12 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 movl %eax, (%r12,%rax,4) incq %rax cmpq $512, %rax # imm = 0x200 jne .LBB1_1 # %bb.2: # %.preheader.preheader xorl %eax, %eax .LBB1_3: # %.preheader # =>This Inner Loop Header: Depth=1 movl $1056964608, (%r14,%rax,4) # imm = 0x3F000000 incq %rax cmpq $512, %rax # imm = 0x200 jne .LBB1_3 # %bb.4: leaq 24(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax je .LBB1_6 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $37, %edx jmp .LBB1_11 .LBB1_6: leaq 16(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax je .LBB1_8 # %bb.7: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi jmp .LBB1_10 .LBB1_8: leaq 8(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax je .LBB1_17 # %bb.9: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi .LBB1_10: movl $38, %edx .LBB1_11: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_13 # %bb.12: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_14 .LBB1_13: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_15: movl $-1, %eax .LBB1_16: addq $32, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_17: .cfi_def_cfa_offset 80 movq %rsp, %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax je .LBB1_19 # %bb.18: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $44, %edx jmp .LBB1_11 .LBB1_19: movq 24(%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_21 # %bb.20: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $34, %edx jmp .LBB1_30 .LBB1_21: movq 16(%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_24 # %bb.22: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi .LBB1_23: movl $36, %edx jmp .LBB1_30 .LBB1_24: movq (%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %r12, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_26 # %bb.25: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.6, %esi movl $48, %edx jmp .LBB1_30 .LBB1_26: movabsq $4294967298, %rdi # imm = 0x100000002 leaq 254(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_28 # %bb.27: movq 24(%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movq (%rsp), %rcx movl $512, %r8d # imm = 0x200 callq _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii .LBB1_28: callq hipGetLastError testl %eax, %eax je .LBB1_31 # %bb.29: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.7, %esi movl $24, %edx .LBB1_30: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_15 .LBB1_31: movq 8(%rsp), %rsi movl $2048, %edx # imm = 0x800 movq %r15, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_33 # %bb.32: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.8, %esi jmp .LBB1_23 .LBB1_33: movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %r12, %rdi callq _ZdaPv movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB1_16 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23sparseConvolutionKernelPKfS0_PfPii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z23sparseConvolutionKernelPKfS0_PfPii,@object # @_Z23sparseConvolutionKernelPKfS0_PfPii .section .rodata,"a",@progbits .globl _Z23sparseConvolutionKernelPKfS0_PfPii .p2align 3, 0x0 _Z23sparseConvolutionKernelPKfS0_PfPii: .quad _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii .size _Z23sparseConvolutionKernelPKfS0_PfPii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error allocating memory for d_input: " .size .L.str, 38 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error allocating memory for d_filter: " .size .L.str.1, 39 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Error allocating memory for d_output: " .size .L.str.2, 39 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Error allocating memory for d_inputIndices: " .size .L.str.3, 45 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error copying h_input to d_input: " .size .L.str.4, 35 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Error copying h_filter to d_filter: " .size .L.str.5, 37 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Error copying h_inputIndices to d_inputIndices: " .size .L.str.6, 49 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Error launching kernel: " .size .L.str.7, 25 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Error copying d_output to h_output: " .size .L.str.8, 37 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Sparse convolution completed successfully." .size .L.str.9, 43 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z23sparseConvolutionKernelPKfS0_PfPii" .size .L__unnamed_1, 39 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z23sparseConvolutionKernelPKfS0_PfPii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,481
5,821
113,456
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z18convBackwardKernelPfS_S_S_iiiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.Y ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; S2R R3, SR_TID.Y ; S2R R7, SR_CTAID.X ; S2R R2, SR_TID.X ; IMAD R0, R0, c[0x0][0x4], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x190], PT ; IMAD R7, R7, c[0x0][0x0], R2 ; ISETP.GE.OR P0, PT, R7, c[0x0][0x18c], P0 ; ISETP.LT.OR P0, PT, R4, 0x1, P0 ; @P0 EXIT ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R2, R0, 0x20, R7 ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @P0 BRA 0x4c0 ; IADD3 R0, R4, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x450 ; IADD3 R4, -R0, c[0x0][0x180], RZ ; ISETP.GT.AND P0, PT, R4, RZ, PT ; @!P0 BRA 0x3e0 ; ISETP.GT.AND P1, PT, R4, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x300 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R4, R4, -0x10, RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; ISETP.GT.AND P1, PT, R4, 0xc, PT ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; @P1 BRA 0x1d0 ; ISETP.GT.AND P1, PT, R4, 0x4, PT ; @!P1 BRA 0x3c0 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R4, R4, -0x8, RZ ; ISETP.NE.OR P0, PT, R4, RZ, P0 ; @!P0 BRA 0x450 ; IADD3 R4, R4, -0x4, RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; ISETP.NE.AND P0, PT, R4, RZ, PT ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; @P0 BRA 0x3e0 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; IADD3 R0, R0, -0x1, RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; BRA 0x470 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x184] ; MOV R9, RZ ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IADD3 R4, R6.reuse, -0x1, RZ ; LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; IADD3 R8, -R6, c[0x0][0x184], RZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x184] ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0xcb0 ; IMAD R4, R9, c[0x0][0x190], R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD R4, R4, c[0x0][0x18c], R7 ; IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; LDG.E R11, [R4.64] ; HFMA2.MMA R10, -RZ, RZ, 0, 0 ; IMAD R13, R9, c[0x0][0x188], R10 ; IADD3 R10, R10, 0x1, RZ ; UMOV UR4, URZ ; IMAD R13, R13, c[0x0][0x184], RZ ; ISETP.GE.AND P2, PT, R10, c[0x0][0x188], PT ; @!P1 BRA 0xbc0 ; ISETP.GT.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; UMOV UR4, URZ ; IMAD.MOV.U32 R14, RZ, RZ, R8 ; IMAD.WIDE R4, R13, R4, c[0x0][0x170] ; @!P0 BRA 0xac0 ; ISETP.GT.AND P3, PT, R14, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P3 BRA 0x920 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R21, [R4.64] ; LDG.E R23, [R4.64+0x4] ; LDG.E R19, [R4.64+0x8] ; LDG.E R17, [R4.64+0xc] ; LDG.E R16, [R4.64+0x10] ; LDG.E R15, [R4.64+0x14] ; LDG.E R28, [R4.64+0x18] ; LDG.E R26, [R4.64+0x1c] ; LDG.E R24, [R4.64+0x20] ; LDG.E R22, [R4.64+0x24] ; LDG.E R20, [R4.64+0x28] ; LDG.E R18, [R4.64+0x2c] ; FFMA R21, R11, R21, R12 ; LDG.E R12, [R4.64+0x30] ; FFMA R23, R11, R23, R21 ; LDG.E R21, [R4.64+0x34] ; FFMA R23, R11, R19, R23 ; LDG.E R19, [R4.64+0x38] ; FFMA R23, R11, R17, R23 ; LDG.E R17, [R4.64+0x3c] ; IADD3 R14, R14, -0x10, RZ ; FFMA R16, R11.reuse, R16, R23 ; UIADD3 UR4, UR4, 0x10, URZ ; ISETP.GT.AND P3, PT, R14, 0xc, PT ; FFMA R15, R11, R15, R16 ; FFMA R15, R11, R28, R15 ; IADD3 R4, P4, R4, 0x40, RZ ; FFMA R15, R11, R26, R15 ; IADD3.X R5, RZ, R5, RZ, P4, !PT ; FFMA R15, R11, R24, R15 ; FFMA R15, R11, R22, R15 ; FFMA R15, R11, R20, R15 ; FFMA R15, R11, R18, R15 ; FFMA R12, R11, R12, R15 ; FFMA R12, R11, R21, R12 ; FFMA R12, R11, R19, R12 ; FFMA R12, R11, R17, R12 ; @P3 BRA 0x6c0 ; ISETP.GT.AND P3, PT, R14, 0x4, PT ; @!P3 BRA 0xaa0 ; LDG.E R15, [R4.64] ; LDG.E R17, [R4.64+0x4] ; LDG.E R18, [R4.64+0x8] ; LDG.E R19, [R4.64+0xc] ; LDG.E R20, [R4.64+0x10] ; LDG.E R21, [R4.64+0x14] ; LDG.E R22, [R4.64+0x18] ; LDG.E R16, [R4.64+0x1c] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; UIADD3 UR4, UR4, 0x8, URZ ; IADD3 R14, R14, -0x8, RZ ; FFMA R12, R11, R15, R12 ; IADD3 R15, P3, R4, 0x20, RZ ; FFMA R12, R11.reuse, R17, R12 ; IMAD.X R5, RZ, RZ, R5, P3 ; FFMA R12, R11.reuse, R18, R12 ; IMAD.MOV.U32 R4, RZ, RZ, R15 ; FFMA R12, R11, R19, R12 ; FFMA R12, R11, R20, R12 ; FFMA R12, R11, R21, R12 ; FFMA R12, R11, R22, R12 ; FFMA R12, R11, R16, R12 ; ISETP.NE.OR P0, PT, R14, RZ, P0 ; @!P0 BRA 0xbc0 ; LDG.E R15, [R4.64] ; LDG.E R16, [R4.64+0x4] ; LDG.E R17, [R4.64+0x8] ; LDG.E R18, [R4.64+0xc] ; IADD3 R14, R14, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; ISETP.NE.AND P0, PT, R14, RZ, PT ; FFMA R12, R11, R15, R12 ; IADD3 R15, P3, R4, 0x10, RZ ; FFMA R12, R11.reuse, R16, R12 ; IADD3.X R16, RZ, R5, RZ, P3, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R15 ; FFMA R12, R11.reuse, R17, R12 ; IMAD.MOV.U32 R5, RZ, RZ, R16 ; FFMA R12, R11, R18, R12 ; @P0 BRA 0xac0 ; ISETP.NE.AND P0, PT, R6, RZ, PT ; @!P0 BRA 0xca0 ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R4, R13, UR4, RZ ; IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; LDG.E R13, [R4.64] ; ISETP.NE.AND P0, PT, R6, 0x1, PT ; FFMA R12, R11, R13, R12 ; @!P0 BRA 0xca0 ; ISETP.NE.AND P0, PT, R6, 0x2, PT ; LDG.E R13, [R4.64+0x4] ; @P0 LDG.E R14, [R4.64+0x8] ; FFMA R12, R11, R13, R12 ; @P0 FFMA R12, R11, R14, R12 ; @!P2 BRA 0x5c0 ; IADD3 R9, R9, 0x1, RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R12 ; ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; @!P0 BRA 0x530 ; EXIT ; BRA 0xd00; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18convBackwardKernelPfS_S_S_iiiii ; -- Begin function _Z18convBackwardKernelPfS_S_S_iiiii .globl _Z18convBackwardKernelPfS_S_S_iiiii .p2align 8 .type _Z18convBackwardKernelPfS_S_S_iiiii,@function _Z18convBackwardKernelPfS_S_S_iiiii: ; @_Z18convBackwardKernelPfS_S_S_iiiii ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x44 s_load_b128 s[4:7], s[0:1], 0x20 s_load_b32 s10, s[0:1], 0x30 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_mov_b32 s11, 0 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] v_cmp_gt_i32_e32 vcc_lo, s7, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s2, s10, v1 s_and_b32 s2, vcc_lo, s2 s_cmp_gt_i32 s4, 0 s_cselect_b32 s3, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_11 ; %bb.1: ; %.lr.ph68 s_load_b64 s[8:9], s[0:1], 0x0 v_lshl_add_u32 v2, v1, 5, v0 s_load_b128 s[0:3], s[0:1], 0x10 s_cmp_gt_i32 s6, 0 v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0 s_delay_alu instid0(VALU_DEP_2) v_ashrrev_i32_e32 v3, 31, v2 s_cselect_b32 s12, -1, 0 s_cmp_gt_i32 s5, 0 s_mul_i32 s14, s6, s5 s_cselect_b32 s13, -1, 0 v_lshlrev_b64 v[2:3], 2, v[2:3] s_mov_b32 s15, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s8, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo .LBB0_2: ; =>This Loop Header: Depth=1 ; Child Loop BB0_4 Depth 2 ; Child Loop BB0_6 Depth 3 ; Child Loop BB0_9 Depth 2 s_and_not1_b32 vcc_lo, exec_lo, s12 s_cbranch_vccnz .LBB0_8 ; %bb.3: ; %.preheader.lr.ph ; in Loop: Header=BB0_2 Depth=1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, s15, s10, v[1:2] s_mov_b32 s16, 0 s_mov_b32 s17, s11 v_mad_u64_u32 v[8:9], null, v4, s7, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v9, 31, v8 v_lshlrev_b64 v[4:5], 2, v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo .LBB0_4: ; %.preheader ; Parent Loop BB0_2 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_6 Depth 3 s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB0_7 ; %bb.5: ; %.lr.ph ; in Loop: Header=BB0_4 Depth=2 global_load_b32 v8, v[4:5], off s_mov_b32 s8, s17 s_mov_b32 s18, s5 .LBB0_6: ; Parent Loop BB0_2 Depth=1 ; Parent Loop BB0_4 Depth=2 ; => This Inner Loop Header: Depth=3 s_ashr_i32 s9, s8, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[20:21], s[8:9], 2 s_add_u32 s20, s0, s20 s_addc_u32 s21, s1, s21 s_add_i32 s18, s18, -1 global_load_b32 v9, v6, s[20:21] s_add_i32 s8, s8, 1 s_cmp_eq_u32 s18, 0 s_waitcnt vmcnt(0) v_fmac_f32_e32 v7, v9, v8 s_cbranch_scc0 .LBB0_6 .LBB0_7: ; %._crit_edge ; in Loop: Header=BB0_4 Depth=2 s_add_i32 s16, s16, 1 s_add_i32 s17, s17, s5 s_cmp_eq_u32 s16, s6 s_cbranch_scc0 .LBB0_4 .LBB0_8: ; %._crit_edge64 ; in Loop: Header=BB0_2 Depth=1 global_load_b32 v5, v[2:3], off s_mov_b32 s8, 0 .LBB0_9: ; %atomicrmw.start ; Parent Loop BB0_2 Depth=1 ; => This Inner Loop Header: Depth=2 s_waitcnt vmcnt(0) v_add_f32_e32 v4, v5, v7 global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v4, v5 v_mov_b32_e32 v5, v4 s_or_b32 s8, vcc_lo, s8 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s8 s_cbranch_execnz .LBB0_9 ; %bb.10: ; %atomicrmw.end ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s8 s_add_i32 s15, s15, 1 s_add_i32 s11, s11, s14 s_cmp_eq_u32 s15, s4 s_cbranch_scc0 .LBB0_2 .LBB0_11: ; %.loopexit s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18convBackwardKernelPfS_S_S_iiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 22 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18convBackwardKernelPfS_S_S_iiiii, .Lfunc_end0-_Z18convBackwardKernelPfS_S_S_iiiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 460 ; NumSgprs: 24 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 24 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18convBackwardKernelPfS_S_S_iiiii .private_segment_fixed_size: 0 .sgpr_count: 24 .sgpr_spill_count: 0 .symbol: _Z18convBackwardKernelPfS_S_S_iiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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4,251
113,457
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000b6acf_00000000-6_cuda_code_028383.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4292: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4292: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii .type _Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii, @function _Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii: .LFB3660: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 40(%rsp) leaq 64(%rsp), %rdi movq %rsi, 32(%rsp) leaq 76(%rsp), %rsi movq %rdx, 24(%rsp) leaq 48(%rsp), %rdx movq %rcx, 16(%rsp) leaq 56(%rsp), %rcx movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 72(%rsp) movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) movabsq $4294967297, %rax movq %rax, 64(%rsp) movq %rax, 76(%rsp) movl $1, 84(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 56(%rsp) .cfi_def_cfa_offset 216 leaq _Z18convBackwardKernelPfS_S_S_iiiii(%rip), %rdi pushq 56(%rsp) .cfi_def_cfa_offset 224 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq 128(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 216 popq %rdx .cfi_def_cfa_offset 208 .L3: movq 184(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $200, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii, .-_Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii .globl _Z18convBackwardKernelPfS_S_S_iiiii .type _Z18convBackwardKernelPfS_S_S_iiiii, @function _Z18convBackwardKernelPfS_S_S_iiiii: .LFB3661: .cfi_startproc endbr64 jmp _Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii .cfi_endproc .LFE3661: .size _Z18convBackwardKernelPfS_S_S_iiiii, .-_Z18convBackwardKernelPfS_S_S_iiiii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Failed to allocate d_input (error code " .LC2: .string ")" .LC3: .string "Failed to allocate d_output (error code " .LC4: .string "Failed to allocate d_filters (error code " .LC5: .string "Failed to allocate d_deltas (error code " .LC6: .string "Failed to launch convBackwardKernel (error code " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 movl $65536, %edi xorl %r14d, %r14d pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $401408, %edi movq %rax, %rbx call _Znam@PLT movl $800, %edi movq %rax, %r13 call _Znam@PLT movl $401408, %edi movq %rax, %r12 call _Znam@PLT movq %rax, %rbp .L10: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, (%rbx,%r14,4) incq %r14 cmpq $16384, %r14 jne .L10 xorl %r14d, %r14d .L11: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, 0(%r13,%r14,4) incq %r14 cmpq $100352, %r14 jne .L11 xorl %r14d, %r14d .L12: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, (%r12,%r14,4) incq %r14 cmpq $200, %r14 jne .L12 xorl %r14d, %r14d .L13: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, 0(%rbp,%r14,4) incq %r14 cmpq $100352, %r14 jne .L13 movl $65536, %esi movq %rsp, %rdi call cudaMalloc@PLT leaq .LC1(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 leaq 8(%rsp), %rdi movl $401408, %esi call cudaMalloc@PLT movl %eax, %r14d testl %eax, %eax je .L16 leaq .LC3(%rip), %rsi .L28: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r14d, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L9 .L16: movl $800, %esi leaq 16(%rsp), %rdi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movl $401408, %esi leaq 24(%rsp), %rdi call cudaMalloc@PLT leaq .LC5(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq (%rsp), %rdi movl $1, %ecx movl $65536, %edx movq %rbx, %rsi call cudaMemcpy@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $401408, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $800, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $401408, %edx call cudaMemcpy@PLT xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movabsq $68719476752, %rdx movl $1, %esi movabsq $8589934594, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L20 pushq %rax .cfi_def_cfa_offset 120 movl $5, %r9d movl $8, %r8d pushq $28 .cfi_def_cfa_offset 128 pushq $28 .cfi_def_cfa_offset 136 pushq $5 .cfi_def_cfa_offset 144 movq 56(%rsp), %rcx movq 48(%rsp), %rdx movq 40(%rsp), %rsi movq 32(%rsp), %rdi call _Z49__device_stub__Z18convBackwardKernelPfS_S_S_iiiiiPfS_S_S_iiiii addq $32, %rsp .cfi_def_cfa_offset 112 .L20: call cudaGetLastError@PLT leaq .LC6(%rip), %rsi movl %eax, %r14d testl %eax, %eax jne .L28 movq (%rsp), %rsi movl $2, %ecx movl $65536, %edx movq %rbx, %rdi call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %r13, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT xorl %eax, %eax .L9: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L22 call __stack_chk_fail@PLT .L22: addq $64, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z18convBackwardKernelPfS_S_S_iiiii" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rax, %rdi leaq _Z18convBackwardKernelPfS_S_S_iiiii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 805306368 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_028383.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii # -- Begin function _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii .type _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii,@function _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii: # @_Z33__device_stub__convBackwardKernelPfS_S_S_iiiii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $176, %rsp .cfi_def_cfa_offset 224 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 12(%rsp), %rcx movl %r8d, (%rcx) leaq 8(%rsp), %r8 movl %r9d, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 224(%rsp), %rax movq %rax, 48(%rbx) leaq 232(%rsp), %rax movq %rax, 56(%rbx) leaq 240(%rsp), %rax movq %rax, 64(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z18convBackwardKernelPfS_S_S_iiiii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $192, %rsp .cfi_adjust_cfa_offset -192 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii, .Lfunc_end0-_Z33__device_stub__convBackwardKernelPfS_S_S_iiiii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x30000000 # float 4.65661287E-10 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $65536, %edi # imm = 0x10000 callq _Znam movq %rax, %rbx movl $401408, %edi # imm = 0x62000 callq _Znam movq %rax, %r14 movl $800, %edi # imm = 0x320 callq _Znam movq %rax, %r15 movl $401408, %edi # imm = 0x62000 callq _Znam movq %rax, %r12 xorl %r13d, %r13d .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss %xmm1, %xmm0 movss %xmm0, (%rbx,%r13,4) incq %r13 cmpq $16384, %r13 # imm = 0x4000 jne .LBB1_1 # %bb.2: # %.preheader58.preheader xorl %r13d, %r13d .LBB1_3: # %.preheader58 # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, (%r14,%r13,4) incq %r13 cmpq $100352, %r13 # imm = 0x18800 jne .LBB1_3 # %bb.4: # %.preheader57.preheader xorl %r13d, %r13d .LBB1_5: # %.preheader57 # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, (%r15,%r13,4) incq %r13 cmpq $200, %r13 jne .LBB1_5 # %bb.6: # %.preheader.preheader xorl %r13d, %r13d .LBB1_7: # %.preheader # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, (%r12,%r13,4) incq %r13 cmpq $100352, %r13 # imm = 0x18800 jne .LBB1_7 # %bb.8: leaq 8(%rsp), %rdi movl $65536, %esi # imm = 0x10000 callq hipMalloc testl %eax, %eax je .LBB1_10 # %bb.9: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $39, %edx jmp .LBB1_15 .LBB1_10: leaq 32(%rsp), %rdi movl $401408, %esi # imm = 0x62000 callq hipMalloc testl %eax, %eax je .LBB1_13 # %bb.11: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi .LBB1_12: movl $40, %edx jmp .LBB1_15 .LBB1_13: leaq 24(%rsp), %rdi movl $800, %esi # imm = 0x320 callq hipMalloc testl %eax, %eax je .LBB1_18 # %bb.14: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $41, %edx .LBB1_15: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebp, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_16: movl $-1, %eax .LBB1_17: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_18: .cfi_def_cfa_offset 96 leaq 16(%rsp), %rdi movl $401408, %esi # imm = 0x62000 callq hipMalloc testl %eax, %eax je .LBB1_20 # %bb.19: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi jmp .LBB1_12 .LBB1_20: movq 8(%rsp), %rdi movl $65536, %edx # imm = 0x10000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi movl $401408, %edx # imm = 0x62000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movl $800, %edx # imm = 0x320 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movl $401408, %edx # imm = 0x62000 movq %r12, %rsi movl $1, %ecx callq hipMemcpy movabsq $8589934594, %rdi # imm = 0x200000002 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_22 # %bb.21: movq 8(%rsp), %rdi movq 32(%rsp), %rsi movq 24(%rsp), %rdx movq 16(%rsp), %rcx subq $8, %rsp .cfi_adjust_cfa_offset 8 movl $28, %eax movl $8, %r8d movl $5, %r9d pushq %rax .cfi_adjust_cfa_offset 8 pushq %rax .cfi_adjust_cfa_offset 8 pushq $5 .cfi_adjust_cfa_offset 8 callq _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii addq $32, %rsp .cfi_adjust_cfa_offset -32 .LBB1_22: callq hipGetLastError testl %eax, %eax je .LBB1_24 # %bb.23: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $48, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi movl %ebp, %esi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %rbx, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_16 .LBB1_24: movq 8(%rsp), %rsi movl $65536, %edx # imm = 0x10000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %r12, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB1_17 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18convBackwardKernelPfS_S_S_iiiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z18convBackwardKernelPfS_S_S_iiiii,@object # @_Z18convBackwardKernelPfS_S_S_iiiii .section .rodata,"a",@progbits .globl _Z18convBackwardKernelPfS_S_S_iiiii .p2align 3, 0x0 _Z18convBackwardKernelPfS_S_S_iiiii: .quad _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii .size _Z18convBackwardKernelPfS_S_S_iiiii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate d_input (error code " .size .L.str, 40 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz ")" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate d_output (error code " .size .L.str.2, 41 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate d_filters (error code " .size .L.str.3, 42 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate d_deltas (error code " .size .L.str.4, 41 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to launch convBackwardKernel (error code " .size .L.str.5, 49 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z18convBackwardKernelPfS_S_S_iiiii" .size .L__unnamed_1, 36 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__convBackwardKernelPfS_S_S_iiiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18convBackwardKernelPfS_S_S_iiiii .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z10searchKeysPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; @P0 EXIT ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; LDG.E R3, [R2.64] ; BSSY B0, 0x280 ; SHF.R.S32.HI R11, RZ, 0x1f, R0 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.HI R4, R3, -0x7efdfbf7, R2 ; SHF.R.S32.HI R5, RZ, 0x1f, R3 ; SHF.R.U32.HI R7, RZ, 0x1f, R4 ; LEA.HI R5, R5, R3, RZ, 0x7 ; LEA.HI.SX32 R7, R4, R7, 0x1a ; LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; IMAD R7, R7, -0x7f, R3 ; IMAD.IADD R6, R3, 0x1, -R5 ; IADD3 R7, R7, 0x1, RZ ; IMAD R4, R7, R8, R6 ; IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; SHF.R.S32.HI R5, RZ, 0x1f, R4 ; LEA.HI R5, R5, R4, RZ, 0x7 ; LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; IMAD.IADD R5, R4, 0x1, -R5 ; IMAD.WIDE R4, R5, R10, c[0x0][0x168] ; LDG.E R5, [R4.64] ; IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; ISETP.NE.AND P0, PT, R5, R3, PT ; @!P0 BRA 0x270 ; IADD3 R8, R8, 0x1, RZ ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; ISETP.NE.AND P1, PT, R5, RZ, PT ; ISETP.GE.U32.AND P0, PT, R8, 0x80, PT ; @!P0 BRA P1, 0x170 ; BSYNC B0 ; LEA R2, P0, R0, c[0x0][0x170], 0x2 ; LEA.HI.X R3, R0, c[0x0][0x174], R11, 0x2, P0 ; STG.E [R2.64], R9 ; EXIT ; BRA 0x2c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z10insertKeysPiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; @P0 EXIT ; IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R2, R8, c[0x0][0x160] ; LDG.E R3, [R2.64] ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.HI R4, R3, -0x7efdfbf7, R2 ; SHF.R.S32.HI R0, RZ, 0x1f, R3 ; SHF.R.U32.HI R5, RZ, 0x1f, R4 ; LEA.HI R0, R0, R3, RZ, 0x7 ; LEA.HI.SX32 R4, R4, R5, 0x1a ; LOP3.LUT R0, R0, 0xffffff80, RZ, 0xc0, !PT ; IMAD R4, R4, -0x7f, R3 ; IMAD.IADD R0, R3, 0x1, -R0 ; IADD3 R7, R4, 0x1, RZ ; IMAD R2, R7, R6, R0 ; YIELD ; SHF.R.S32.HI R5, RZ, 0x1f, R2 ; LEA.HI R5, R5, R2, RZ, 0x7 ; LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; IMAD.IADD R5, R2, 0x1, -R5 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.WIDE R4, R5, R8, c[0x0][0x168] ; ATOMG.E.CAS.STRONG.GPU PT, R2, [R4], R2, R3 ; IADD3 R6, R6, 0x1, RZ ; ISETP.NE.AND P0, PT, R2.reuse, R3, PT ; ISETP.NE.AND P1, PT, R2, RZ, PT ; @P0 BRA P1, 0x150 ; EXIT ; BRA 0x230; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10insertKeysPiS_i ; -- Begin function _Z10insertKeysPiS_i .globl _Z10insertKeysPiS_i .p2align 8 .type _Z10insertKeysPiS_i,@function _Z10insertKeysPiS_i: ; @_Z10insertKeysPiS_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_3 ; %bb.1: s_load_b128 s[0:3], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_mov_b32 s1, 0 global_load_b32 v0, v[0:1], off s_waitcnt vmcnt(0) v_mul_hi_i32 v1, 0x81020409, v0 v_ashrrev_i32_e32 v3, 31, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v1, v1, v0 v_lshrrev_b32_e32 v2, 31, v1 v_ashrrev_i32_e32 v1, 6, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v1, v1, v2 v_lshrrev_b32_e32 v2, 25, v3 v_mul_lo_u32 v1, 0x7f, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v0, v2 v_sub_nc_u32_e32 v3, v0, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xffffff80, v2 v_dual_mov_b32 v4, v1 :: v_dual_add_nc_u32 v3, 1, v3 s_delay_alu instid0(VALU_DEP_2) v_sub_nc_u32_e32 v2, v0, v2 .LBB0_2: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v4, v3, v[2:3] v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshrrev_b32_e32 v6, 25, v6 v_add_nc_u32_e32 v6, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v6, 0xffffff80, v6 v_sub_nc_u32_e32 v5, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v6, 31, v5 v_lshlrev_b64 v[5:6], 2, v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo global_atomic_cmpswap_b32 v5, v[5:6], v[0:1], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, 0, v5 v_cmp_eq_u32_e64 s0, v5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s0, vcc_lo, s0 s_xor_b32 s4, s0, -1 s_and_b32 s0, exec_lo, s0 v_cndmask_b32_e64 v5, 0, 1, s4 s_or_b32 s1, s0, s1 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v4, v4, v5 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %.loopexit s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10insertKeysPiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10insertKeysPiS_i, .Lfunc_end0-_Z10insertKeysPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 368 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z10searchKeysPiS_S_i ; -- Begin function _Z10searchKeysPiS_S_i .globl _Z10searchKeysPiS_S_i .p2align 8 .type _Z10searchKeysPiS_S_i,@function _Z10searchKeysPiS_S_i: ; @_Z10searchKeysPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB1_6 ; %bb.1: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s11, 0 ; implicit-def: $sgpr8 ; implicit-def: $sgpr10 ; implicit-def: $sgpr9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo s_mov_b32 s4, 0 ; implicit-def: $sgpr5 global_load_b32 v3, v[2:3], off s_waitcnt vmcnt(0) v_mul_hi_i32 v2, 0x81020409, v3 v_ashrrev_i32_e32 v5, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v3 v_lshrrev_b32_e32 v4, 31, v2 v_ashrrev_i32_e32 v2, 6, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v2, v4 v_lshrrev_b32_e32 v4, 25, v5 v_mul_lo_u32 v2, 0x7f, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v4, v3, v4 v_and_b32_e32 v4, 0xffffff80, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v5, v3, v2 v_sub_nc_u32_e32 v2, v3, v4 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, 1, v5 .LBB1_2: ; =>This Inner Loop Header: Depth=1 s_and_not1_b32 s0, s10, exec_lo s_and_b32 s1, s11, exec_lo s_and_not1_b32 s9, s9, exec_lo s_or_b32 s10, s0, s1 s_or_b32 s8, s8, exec_lo s_mov_b32 s12, exec_lo v_cmpx_gt_u32_e32 0x80, v5 s_cbranch_execz .LBB1_4 ; %bb.3: ; in Loop: Header=BB1_2 Depth=1 v_mad_u64_u32 v[6:7], null, v5, v4, v[2:3] s_and_not1_b32 s9, s9, exec_lo s_and_not1_b32 s10, s10, exec_lo s_and_not1_b32 s8, s8, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshrrev_b32_e32 v7, 25, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v7, v6, v7 v_and_b32_e32 v7, 0xffffff80, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v6, v6, v7 v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[6:7] v_add_co_u32 v6, vcc_lo, s6, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo global_load_b32 v6, v[6:7], off s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, v6, v3 v_cmp_ne_u32_e64 s1, 0, v6 v_cmp_eq_u32_e64 s0, v6, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_b32 vcc_lo, s1, vcc_lo s_or_b32 s11, s0, s11 s_xor_b32 s1, vcc_lo, -1 v_add_co_ci_u32_e64 v5, s0, 0, v5, vcc_lo s_and_b32 s0, s11, exec_lo s_and_b32 s1, s1, exec_lo s_or_b32 s9, s9, s0 s_or_b32 s10, s10, s0 s_or_b32 s8, s8, s1 ; implicit-def: $sgpr11 .LBB1_4: ; %Flow ; in Loop: Header=BB1_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, exec_lo, s8 s_or_b32 s4, s0, s4 s_and_not1_b32 s0, s11, exec_lo s_and_b32 s1, s9, exec_lo s_and_not1_b32 s5, s5, exec_lo s_and_b32 s12, s10, exec_lo s_or_b32 s11, s0, s1 s_or_b32 s5, s5, s12 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB1_2 ; %bb.5: s_or_b32 exec_lo, exec_lo, s4 v_add_co_u32 v0, vcc_lo, s2, v0 v_cndmask_b32_e64 v2, 0, 1, s5 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB1_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10searchKeysPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z10searchKeysPiS_S_i, .Lfunc_end1-_Z10searchKeysPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 524 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10insertKeysPiS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10insertKeysPiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10searchKeysPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10searchKeysPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00019bb9_00000000-6_cuda_code_067825.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z10insertKeysPiS_iPiS_i .type _Z33__device_stub__Z10insertKeysPiS_iPiS_i, @function _Z33__device_stub__Z10insertKeysPiS_iPiS_i: .LFB3660: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movl %edx, 12(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z10insertKeysPiS_i(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L2: movq 120(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z33__device_stub__Z10insertKeysPiS_iPiS_i, .-_Z33__device_stub__Z10insertKeysPiS_iPiS_i .globl _Z10insertKeysPiS_i .type _Z10insertKeysPiS_i, @function _Z10insertKeysPiS_i: .LFB3661: .cfi_startproc endbr64 jmp _Z33__device_stub__Z10insertKeysPiS_iPiS_i .cfi_endproc .LFE3661: .size _Z10insertKeysPiS_i, .-_Z10insertKeysPiS_i .globl _Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i .type _Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i, @function _Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i: .LFB3662: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z10searchKeysPiS_S_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L8: movq 136(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3662: .size _Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i .globl _Z10searchKeysPiS_S_i .type _Z10searchKeysPiS_S_i, @function _Z10searchKeysPiS_S_i: .LFB3663: .cfi_startproc endbr64 jmp _Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i .cfi_endproc .LFE3663: .size _Z10searchKeysPiS_S_i, .-_Z10searchKeysPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Yes" .LC1: .string "No" .LC2: .string "CUDA error after insertKeys: " .LC3: .string "CUDA error after searchKeys: " .LC4: .string "Key " .LC5: .string " found: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $1, %edx movl $1024, %esi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi call cudaMallocManaged@PLT leaq 16(%rsp), %rdi movl $1, %edx movl $512, %esi call cudaMallocManaged@PLT movl $1, %edx leaq 24(%rsp), %rdi movl $1024, %esi call cudaMallocManaged@PLT movq 8(%rsp), %rdx xorl %eax, %eax .L14: movl %eax, (%rdx,%rax,4) incq %rax cmpq $256, %rax jne .L14 movq 16(%rsp), %rdi xorl %eax, %eax movl $128, %ecx xorl %r9d, %r9d movl $16777217, %edx xorl %r8d, %r8d movl $1, %esi movl $1, 52(%rsp) rep stosl salq $8, %rdx movl $1, %ecx movabsq $4294967297, %rdi movq %rdx, 44(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L15 movq 16(%rsp), %rsi movq 8(%rsp), %rdi movl $256, %edx call _Z33__device_stub__Z10insertKeysPiS_iPiS_i .L15: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L16 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi jmp .L29 .L16: movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $8, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 52(%rsp) movq %rdx, 44(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $256, %ecx movq 8(%rsp), %rdi call _Z35__device_stub__Z10searchKeysPiS_S_iPiS_S_i .L18: call cudaDeviceSynchronize@PLT xorl %ebx, %ebx leaq .LC4(%rip), %r12 call cudaGetLastError@PLT movl %eax, %ebp testl %eax, %eax je .L19 leaq .LC3(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi .L29: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L13 .L19: movq %r12, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq 8(%rsp), %rax movl (%rax,%rbx), %esi call _ZNSolsEi@PLT leaq .LC5(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi movq 24(%rsp), %rax cmpl $0, (%rax,%rbx) leaq .LC0(%rip), %rax cmovne %rax, %rsi addq $4, %rbx call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT cmpq $1024, %rbx jne .L19 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L13: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L22 call __stack_chk_fail@PLT .L22: addq $64, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z10searchKeysPiS_S_i" .LC7: .string "_Z10insertKeysPiS_i" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3665: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z10searchKeysPiS_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC7(%rip), %rdx orl $-1, %r8d leaq _Z10insertKeysPiS_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3665: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_067825.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z25__device_stub__insertKeysPiS_i # -- Begin function _Z25__device_stub__insertKeysPiS_i .type _Z25__device_stub__insertKeysPiS_i,@function _Z25__device_stub__insertKeysPiS_i: # @_Z25__device_stub__insertKeysPiS_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z10insertKeysPiS_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z25__device_stub__insertKeysPiS_i, .Lfunc_end0-_Z25__device_stub__insertKeysPiS_i .cfi_endproc # -- End function .globl _Z25__device_stub__searchKeysPiS_S_i # -- Begin function _Z25__device_stub__searchKeysPiS_S_i .type _Z25__device_stub__searchKeysPiS_S_i,@function _Z25__device_stub__searchKeysPiS_S_i: # @_Z25__device_stub__searchKeysPiS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z10searchKeysPiS_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z25__device_stub__searchKeysPiS_S_i, .Lfunc_end1-_Z25__device_stub__searchKeysPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $24, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 8(%rsp), %rbx movl $1024, %esi # imm = 0x400 movq %rbx, %rdi movl $1, %edx callq hipMallocManaged movq %rsp, %rdi movl $512, %esi # imm = 0x200 movl $1, %edx callq hipMallocManaged leaq 16(%rsp), %rdi movl $1024, %esi # imm = 0x400 movl $1, %edx callq hipMallocManaged xorl %eax, %eax movq (%rbx), %rcx .LBB2_1: # =>This Inner Loop Header: Depth=1 movl %eax, (%rcx,%rax,4) incq %rax cmpq $256, %rax # imm = 0x100 jne .LBB2_1 # %bb.2: # %.preheader56 movabsq $4294967297, %rbx # imm = 0x100000001 movq (%rsp), %rdi movl $512, %edx # imm = 0x200 xorl %esi, %esi callq memset@PLT leaq 255(%rbx), %r14 movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: movq 8(%rsp), %rdi movq (%rsp), %rsi movl $256, %edx # imm = 0x100 callq _Z25__device_stub__insertKeysPiS_i .LBB2_4: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB2_11 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $29, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi jmp .LBB2_6 .LBB2_11: movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_13 # %bb.12: movq 8(%rsp), %rdi movq (%rsp), %rsi movq 16(%rsp), %rdx movl $256, %ecx # imm = 0x100 callq _Z25__device_stub__searchKeysPiS_S_i .LBB2_13: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB2_14 # %bb.17: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $29, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi .LBB2_6: callq hipGetErrorString testq %rax, %rax je .LBB2_7 # %bb.8: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_9 .LBB2_7: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB2_10: addq $24, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_14: # %.preheader.preheader .cfi_def_cfa_offset 64 xorl %r14d, %r14d movl $.L.str.5, %r15d .LBB2_15: # %.preheader # =>This Inner Loop Header: Depth=1 movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $4, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 8(%rsp), %rax movl (%rax,%r14,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.3, %esi movl $8, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 16(%rsp), %rax xorl %edx, %edx cmpl $0, (%rax,%r14,4) sete %dl movl $.L.str.4, %esi cmoveq %r15, %rsi xorq $3, %rdx movq %rbx, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r14 cmpq $256, %r14 # imm = 0x100 jne .LBB2_15 # %bb.16: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB2_10 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10insertKeysPiS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10searchKeysPiS_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z10insertKeysPiS_i,@object # @_Z10insertKeysPiS_i .section .rodata,"a",@progbits .globl _Z10insertKeysPiS_i .p2align 3, 0x0 _Z10insertKeysPiS_i: .quad _Z25__device_stub__insertKeysPiS_i .size _Z10insertKeysPiS_i, 8 .type _Z10searchKeysPiS_S_i,@object # @_Z10searchKeysPiS_S_i .globl _Z10searchKeysPiS_S_i .p2align 3, 0x0 _Z10searchKeysPiS_S_i: .quad _Z25__device_stub__searchKeysPiS_S_i .size _Z10searchKeysPiS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error after insertKeys: " .size .L.str, 30 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "CUDA error after searchKeys: " .size .L.str.1, 30 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Key " .size .L.str.2, 5 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz " found: " .size .L.str.3, 9 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Yes" .size .L.str.4, 4 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "No" .size .L.str.5, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10insertKeysPiS_i" .size .L__unnamed_1, 20 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z10searchKeysPiS_S_i" .size .L__unnamed_2, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__insertKeysPiS_i .addrsig_sym _Z25__device_stub__searchKeysPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10insertKeysPiS_i .addrsig_sym _Z10searchKeysPiS_S_i .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,795
5,888
113,460
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R3, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x188], PT ; @P0 EXIT ; HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x18c], PT ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R3, R0, c[0x0][0x178] ; LDG.E.CONSTANT R3, [R2.64] ; @!P0 MOV R7, RZ ; @!P0 BRA 0xb80 ; MOV R6, c[0x0][0x18c] ; SHF.R.S32.HI R2, RZ, 0x1f, R3 ; LEA R8, P0, R3.reuse, c[0x0][0x160], 0x2 ; IADD3 R4, R6, -0x1, RZ ; LEA.HI.X R9, R3, c[0x0][0x164], R2, 0x2, P0 ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; LDG.E.CONSTANT R2, [R8.64] ; MOV R7, RZ ; MOV R5, RZ ; LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0xa80 ; IADD3 R6, -R4, c[0x0][0x18c], RZ ; HFMA2.MMA R7, -RZ, RZ, 0, 0 ; MOV R5, RZ ; ISETP.GT.AND P0, PT, R6, RZ, PT ; MOV R16, c[0x0][0x180] ; MOV R17, c[0x0][0x184] ; @!P0 BRA 0x920 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x690 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.CONSTANT R9, [R16.64] ; LDG.E.CONSTANT R21, [R16.64+0x4] ; LDG.E.CONSTANT R19, [R16.64+0x8] ; LDG.E.CONSTANT R13, [R16.64+0xc] ; LDG.E.CONSTANT R15, [R16.64+0x10] ; LDG.E.CONSTANT R27, [R16.64+0x14] ; LDG.E.CONSTANT R29, [R16.64+0x18] ; LDG.E.CONSTANT R10, [R16.64+0x1c] ; LDG.E.CONSTANT R12, [R16.64+0x20] ; LDG.E.CONSTANT R14, [R16.64+0x24] ; LDG.E.CONSTANT R26, [R16.64+0x28] ; LDG.E.CONSTANT R28, [R16.64+0x2c] ; LDG.E.CONSTANT R24, [R16.64+0x30] ; LDG.E.CONSTANT R22, [R16.64+0x34] ; LDG.E.CONSTANT R23, [R16.64+0x38] ; LDG.E.CONSTANT R25, [R16.64+0x3c] ; IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; IMAD.WIDE R20, R21, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R8, [R8.64] ; IMAD.WIDE R18, R19, R0, c[0x0][0x168] ; LDG.E.CONSTANT R11, [R18.64] ; LDG.E.CONSTANT R9, [R20.64] ; IMAD.WIDE R18, R15, R0, c[0x0][0x168] ; IMAD.WIDE R20, R13, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R15, [R18.64] ; LDG.E.CONSTANT R13, [R20.64] ; IMAD.WIDE R18, R29, R0, c[0x0][0x168] ; IMAD.WIDE R20, R27, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R29, [R18.64] ; LDG.E.CONSTANT R27, [R20.64] ; IMAD.WIDE R18, R12, R0, c[0x0][0x168] ; IMAD.WIDE R20, R10, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R12, [R18.64] ; LDG.E.CONSTANT R10, [R20.64] ; IMAD.WIDE R18, R26, R0, c[0x0][0x168] ; IMAD.WIDE R20, R14, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R26, [R18.64] ; LDG.E.CONSTANT R14, [R20.64] ; IMAD.WIDE R18, R24, R0, c[0x0][0x168] ; IMAD.WIDE R20, R28, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R19, [R18.64] ; LDG.E.CONSTANT R28, [R20.64] ; IMAD.WIDE R24, R25, R0, c[0x0][0x168] ; LDG.E.CONSTANT R25, [R24.64] ; IMAD.WIDE R20, R22, R0, c[0x0][0x168] ; IMAD.WIDE R22, R23, R0, c[0x0][0x168] ; LDG.E.CONSTANT R21, [R20.64] ; LDG.E.CONSTANT R23, [R22.64] ; IADD3 R6, R6, -0x10, RZ ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; IADD3 R16, P2, R16, 0x40, RZ ; IADD3 R5, R5, 0x10, RZ ; IADD3.X R17, RZ, R17, RZ, P2, !PT ; FFMA R8, R2, R8, R7 ; FFMA R8, R2, R9, R8 ; FFMA R8, R2, R11, R8 ; FFMA R8, R2, R13, R8 ; FFMA R8, R2, R15, R8 ; FFMA R8, R2, R27, R8 ; FFMA R29, R2, R29, R8 ; FFMA R29, R2, R10, R29 ; FFMA R29, R2, R12, R29 ; FFMA R29, R2, R14, R29 ; FFMA R29, R2, R26, R29 ; FFMA R28, R2, R28, R29 ; FFMA R19, R2, R19, R28 ; FFMA R19, R2, R21, R19 ; FFMA R19, R2, R23, R19 ; FFMA R7, R2, R25, R19 ; @P1 BRA 0x230 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0x900 ; LDG.E.CONSTANT R25, [R16.64] ; LDG.E.CONSTANT R9, [R16.64+0x4] ; LDG.E.CONSTANT R11, [R16.64+0x8] ; LDG.E.CONSTANT R13, [R16.64+0xc] ; LDG.E.CONSTANT R15, [R16.64+0x10] ; LDG.E.CONSTANT R19, [R16.64+0x14] ; LDG.E.CONSTANT R23, [R16.64+0x18] ; LDG.E.CONSTANT R21, [R16.64+0x1c] ; IMAD.WIDE R24, R25, R0, c[0x0][0x168] ; IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R20, [R24.64] ; IMAD.WIDE R10, R11, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R9, [R8.64] ; IMAD.WIDE R12, R13, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R11, [R10.64] ; IMAD.WIDE R14, R15, R0, c[0x0][0x168] ; LDG.E.CONSTANT R13, [R12.64] ; IMAD.WIDE R18, R19, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R14, [R14.64] ; IMAD.WIDE R22, R23, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R18, [R18.64] ; IMAD.WIDE R24, R21, R0, c[0x0][0x168] ; LDG.E.CONSTANT R22, [R22.64] ; LDG.E.CONSTANT R24, [R24.64] ; IADD3 R16, P1, R16, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R17, RZ, R17, RZ, P1, !PT ; IADD3 R5, R5, 0x8, RZ ; IADD3 R6, R6, -0x8, RZ ; FFMA R20, R2, R20, R7 ; FFMA R9, R2, R9, R20 ; FFMA R9, R2, R11, R9 ; FFMA R9, R2, R13, R9 ; FFMA R9, R2, R14, R9 ; FFMA R9, R2, R18, R9 ; FFMA R9, R2, R22, R9 ; FFMA R7, R2, R24, R9 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0xa80 ; LDG.E.CONSTANT R9, [R16.64] ; LDG.E.CONSTANT R11, [R16.64+0x4] ; LDG.E.CONSTANT R13, [R16.64+0x8] ; LDG.E.CONSTANT R15, [R16.64+0xc] ; IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; IMAD.WIDE R10, R11, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R8, [R8.64] ; IMAD.WIDE R12, R13, R0.reuse, c[0x0][0x168] ; LDG.E.CONSTANT R10, [R10.64] ; IMAD.WIDE R14, R15, R0, c[0x0][0x168] ; LDG.E.CONSTANT R12, [R12.64] ; LDG.E.CONSTANT R14, [R14.64] ; IADD3 R6, R6, -0x4, RZ ; IADD3 R16, P1, R16, 0x10, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; IADD3.X R17, RZ, R17, RZ, P1, !PT ; IADD3 R5, R5, 0x4, RZ ; FFMA R7, R2, R8, R7 ; FFMA R7, R2, R10, R7 ; FFMA R7, R2, R12, R7 ; FFMA R7, R2, R14, R7 ; @P0 BRA 0x920 ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 BRA 0xb80 ; IMAD.WIDE R8, R5, R0, c[0x0][0x180] ; MOV R5, R8 ; MOV R6, R9 ; MOV R10, R5 ; MOV R11, R6 ; LDG.E.CONSTANT R9, [R10.64] ; IADD3 R4, R4, -0x1, RZ ; ISETP.NE.AND P0, PT, R4, RZ, PT ; IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; LDG.E.CONSTANT R8, [R8.64] ; IADD3 R5, P1, R5, 0x4, RZ ; IADD3.X R6, RZ, R6, RZ, P1, !PT ; FFMA R7, R2, R8, R7 ; @P0 BRA 0xad0 ; IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; STG.E [R2.64], R7 ; EXIT ; BRA 0xbb0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii ; -- Begin function _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .globl _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .p2align 8 .type _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii,@function _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii: ; @_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x3c s_load_b64 s[2:3], s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_6 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_cmp_lt_i32 s3, 1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b32 v0, v[0:1], off s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_cbranch_scc1 .LBB0_4 ; %bb.2: ; %.lr.ph s_clause 0x1 s_load_b128 s[8:11], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x20 s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo global_load_b32 v3, v[2:3], off v_mov_b32_e32 v2, 0 .LBB0_3: ; =>This Inner Loop Header: Depth=1 s_load_b32 s6, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_ashr_i32 s7, s6, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[6:7], s[6:7], 2 s_add_u32 s6, s10, s6 s_addc_u32 s7, s11, s7 s_add_i32 s3, s3, -1 s_load_b32 s2, s[6:7], 0x0 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_eq_u32 s3, 0 s_waitcnt vmcnt(0) lgkmcnt(0) v_fmac_f32_e32 v2, s2, v3 s_cbranch_scc0 .LBB0_3 s_branch .LBB0_5 .LBB0_4: v_mov_b32_e32 v2, 0 .LBB0_5: ; %Flow30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii, .Lfunc_end0-_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 292 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
3,872
3,311
113,461
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000a5e30_00000000-6_cuda_code_079141.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6836: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6836: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z14initializeDataPfS_PiS0_ii .type _Z14initializeDataPfS_PiS0_ii, @function _Z14initializeDataPfS_PiS0_ii: .LFB6832: .cfi_startproc endbr64 movss .LC0(%rip), %xmm0 xorl %eax, %eax .L3: cmpl %eax, %r8d jle .L8 movl %eax, (%rdx,%rax,4) movss %xmm0, (%rdi,%rax,4) incq %rax jmp .L3 .L8: movss .LC1(%rip), %xmm0 xorl %eax, %eax .L5: cmpl %eax, %r9d jle .L9 movl %eax, (%rcx,%rax,4) movss %xmm0, (%rsi,%rax,4) incq %rax jmp .L5 .L9: ret .cfi_endproc .LFE6832: .size _Z14initializeDataPfS_PiS0_ii, .-_Z14initializeDataPfS_PiS0_ii .globl _Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii .type _Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii, @function _Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii: .LFB6858: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movl %r9d, 12(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rdi, 24(%rsp) leaq 80(%rsp), %rdi movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 208(%rsp), %rax movq %rsi, 32(%rsp) leaq 92(%rsp), %rsi movq %rdx, 40(%rsp) leaq 64(%rsp), %rdx movq %rcx, 48(%rsp) leaq 72(%rsp), %rcx movq %rax, 176(%rsp) movabsq $4294967297, %rax movq %r8, 56(%rsp) movq %rax, 80(%rsp) movl $1, 88(%rsp) movq %rax, 92(%rsp) movl $1, 100(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L10 pushq 72(%rsp) .cfi_def_cfa_offset 216 leaq _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii(%rip), %rdi pushq 72(%rsp) .cfi_def_cfa_offset 224 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq 144(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 216 popq %rdx .cfi_def_cfa_offset 208 .L10: movq 184(%rsp), %rax subq %fs:40, %rax je .L12 call __stack_chk_fail@PLT .L12: addq $200, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6858: .size _Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii, .-_Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii .globl _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .type _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii, @function _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii: .LFB6859: .cfi_startproc endbr64 jmp _Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii .cfi_endproc .LFE6859: .size _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii, .-_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "CUDA error: " .LC3: .string "Sparse convolution completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6833: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $4096, %edi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax call _Znam@PLT movl $4096, %edi movq %rax, %r13 call _Znam@PLT movl $65536, %edi movq %rax, %r12 call _Znam@PLT movl $4096, %edi movq %rax, %r14 call _Znam@PLT movl $4096, %edi movq %rax, %rbp call _Znam@PLT movq %rbp, %rdx movq %r12, %rsi movq %r13, %rdi movl $1024, %r9d movl $1024, %r8d movq %rax, %rcx movq %rax, %rbx call _Z14initializeDataPfS_PiS0_ii leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $65536, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 32(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 40(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $4096, %edx call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1073741825, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $2, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 pushq %rax .cfi_def_cfa_offset 152 movl $1024, %r9d pushq $1024 .cfi_def_cfa_offset 160 movq 56(%rsp), %r8 movq 48(%rsp), %rcx movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z56__device_stub__Z23sparseConvolutionKernelPKfS0_PfPiS2_iiPKfS0_PfPiS2_ii popq %rdx .cfi_def_cfa_offset 152 popq %rcx .cfi_def_cfa_offset 144 .L16: call cudaGetLastError@PLT movl %eax, %r15d testl %eax, %eax je .L17 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r15d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L15 .L17: movq 24(%rsp), %rsi movl $2, %ecx movl $65536, %edx movq %r14, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movq %r14, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT leaq .LC3(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT xorl %eax, %eax .L15: movq 72(%rsp), %rdx subq %fs:40, %rdx je .L19 call __stack_chk_fail@PLT .L19: addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6833: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii" .LC5: .string "_ZN50_INTERNAL_f5268163_19_cuda_code_079141_cu_85115dac4cuda3std3__419piecewise_constructE" .LC6: .string "_ZN50_INTERNAL_f5268163_19_cuda_code_079141_cu_85115dac4cuda3std6ranges3__45__cpo4swapE" .LC7: .string "_ZN50_INTERNAL_f5268163_19_cuda_code_079141_cu_85115dac4cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6861: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC4(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC5(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6861: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .align 4 .LC1: .long 1056964608 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_079141.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii .type _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii,@function _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii: # @_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $160, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 4(%rsp), %r8 movl %r9d, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 208(%rsp), %rax movq %rax, 48(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $176, %rsp .cfi_adjust_cfa_offset -176 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii .cfi_endproc # -- End function .globl _Z14initializeDataPfS_PiS0_ii # -- Begin function _Z14initializeDataPfS_PiS0_ii .type _Z14initializeDataPfS_PiS0_ii,@function _Z14initializeDataPfS_PiS0_ii: # @_Z14initializeDataPfS_PiS0_ii .cfi_startproc # %bb.0: testl %r8d, %r8d jle .LBB1_3 # %bb.1: # %.lr.ph.preheader movl %r8d, %eax xorl %r8d, %r8d .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl %r8d, (%rdx,%r8,4) movl $1065353216, (%rdi,%r8,4) # imm = 0x3F800000 incq %r8 cmpq %r8, %rax jne .LBB1_2 .LBB1_3: # %.preheader testl %r9d, %r9d jle .LBB1_6 # %bb.4: # %.lr.ph18.preheader movl %r9d, %eax xorl %edx, %edx .LBB1_5: # %.lr.ph18 # =>This Inner Loop Header: Depth=1 movl %edx, (%rcx,%rdx,4) movl $1056964608, (%rsi,%rdx,4) # imm = 0x3F000000 incq %rdx cmpq %rdx, %rax jne .LBB1_5 .LBB1_6: # %._crit_edge retq .Lfunc_end1: .size _Z14initializeDataPfS_PiS0_ii, .Lfunc_end1-_Z14initializeDataPfS_PiS0_ii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %r14 movl $65536, %edi # imm = 0x10000 callq _Znam movq %rax, 48(%rsp) # 8-byte Spill movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %r12 movl $4096, %edi # imm = 0x1000 callq _Znam movq %rax, %r13 xorl %eax, %eax .LBB2_1: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movl %eax, (%r12,%rax,4) movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB2_1 # %bb.2: # %.lr.ph18.i.preheader xorl %eax, %eax .LBB2_3: # %.lr.ph18.i # =>This Inner Loop Header: Depth=1 movl %eax, (%r13,%rax,4) movl $1056964608, (%r14,%rax,4) # imm = 0x3F000000 incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB2_3 # %bb.4: # %_Z14initializeDataPfS_PiS0_ii.exit leaq 40(%rsp), %rbp movl $4096, %esi # imm = 0x1000 movq %rbp, %rdi callq hipMalloc leaq 24(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc leaq 16(%rsp), %rdi movl $65536, %esi # imm = 0x10000 callq hipMalloc leaq 32(%rsp), %r15 movl $4096, %esi # imm = 0x1000 movq %r15, %rdi callq hipMalloc leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc movq (%rbp), %rdi movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy leaq 24(%rsp), %rax movq (%rax), %rdi movl $4096, %edx # imm = 0x1000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq (%r15), %rdi movl $4096, %edx # imm = 0x1000 movq %r12, %rsi movl $1, %ecx callq hipMemcpy leaq 8(%rsp), %rax movq (%rax), %rdi movl $4096, %edx # imm = 0x1000 movq %r13, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967300, %rdi # imm = 0x100000004 leaq 252(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_6 # %bb.5: movq 40(%rsp), %rdi movq 24(%rsp), %rsi movq 16(%rsp), %rdx movq 32(%rsp), %rcx movq 8(%rsp), %r8 movl $1024, (%rsp) # imm = 0x400 movl $1024, %r9d # imm = 0x400 callq _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii .LBB2_6: callq hipGetLastError testl %eax, %eax je .LBB2_9 # %bb.7: movl %eax, %ebp movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_10 # %bb.8: movq %rax, %r14 movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_11 .LBB2_9: movq 16(%rsp), %rsi movl $65536, %edx # imm = 0x10000 movq 48(%rsp), %r15 # 8-byte Reload movq %r15, %rdi movl $2, %ecx callq hipMemcpy movq 40(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movq %r12, %rdi callq _ZdaPv movq %r13, %rdi callq _ZdaPv movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %ebp, %ebp jmp .LBB2_12 .LBB2_10: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movl $-1, %ebp .LBB2_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl %ebp, %eax addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii,@object # @_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .section .rodata,"a",@progbits .globl _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .p2align 3, 0x0 _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii: .quad _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii .size _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Sparse convolution completed successfully." .size .L.str.1, 43 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z23sparseConvolutionKernelPKfS0_PfPiS2_ii" .size .L__unnamed_1, 43 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPiS2_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z23sparseConvolutionKernelPKfS0_PfPiS2_ii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15sparseMatVecMulPKiS0_PKfS2_Pf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R14, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R14, R14, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R14, 0x3ff, PT ; @P0 EXIT ; HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; LDG.E R19, [R2.64] ; LDG.E R16, [R2.64+0x4] ; BSSY B0, 0xe40 ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; SHF.R.S32.HI R17, RZ, 0x1f, R14 ; ISETP.GE.AND P0, PT, R19, R16, PT ; @P0 BRA 0xe30 ; IADD3 R3, R19.reuse, 0x1, RZ ; BSSY B1, 0x330 ; MOV R8, RZ ; IMNMX R0, R16, R3, !PT ; LOP3.LUT R3, RZ, R19, RZ, 0x33, !PT ; IADD3 R2, -R19, R0, RZ ; IADD3 R3, R0, R3, RZ ; LOP3.LUT P1, R0, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; @!P1 BRA 0x320 ; IMAD.WIDE R2, R19, R15, c[0x0][0x168] ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; IMAD.WIDE R4, R19, R15, c[0x0][0x170] ; MOV R9, R2 ; MOV R12, R3 ; MOV R7, R4 ; MOV R10, R5 ; MOV R4, R9 ; MOV R5, R12 ; LDG.E R2, [R4.64] ; MOV R4, R7 ; MOV R5, R10 ; LDG.E R6, [R4.64] ; IMAD.WIDE R2, R2, R15, c[0x0][0x178] ; LDG.E R3, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P1, PT, R0, RZ, PT ; IADD3 R9, P2, R9, 0x4, RZ ; IADD3 R7, P3, R7, 0x4, RZ ; IADD3 R19, R19, 0x1, RZ ; IADD3.X R12, RZ, R12, RZ, P2, !PT ; IADD3.X R10, RZ, R10, RZ, P3, !PT ; FFMA R8, R3, R6, R8 ; @P1 BRA 0x210 ; BSYNC B1 ; @!P0 BRA 0xe30 ; IADD3 R0, R16, -R19, RZ ; IMAD.WIDE R2, R19, R15, c[0x2][0x0] ; BSSY B1, 0x990 ; ISETP.GT.AND P1, PT, R0, 0xc, PT ; IADD3 R4, P0, R2.reuse, c[0x0][0x170], RZ ; IADD3 R6, P2, R2, c[0x0][0x168], RZ ; IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; IADD3.X R7, R3, c[0x0][0x16c], RZ, P2, !PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x980 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R18, R16, -0xc, RZ ; LDG.E R24, [R6.64+-0x8] ; LDG.E R10, [R6.64+-0x4] ; LDG.E R20, [R6.64] ; LDG.E R22, [R6.64+0x4] ; LDG.E R26, [R6.64+0x8] ; LDG.E R3, [R4.64+-0x8] ; LDG.E R12, [R4.64+-0x4] ; LDG.E R13, [R6.64+0xc] ; LDG.E R28, [R6.64+0x10] ; LDG.E R29, [R4.64] ; LDG.E R2, [R4.64+0x4] ; IMAD.WIDE R24, R24, R15, c[0x0][0x178] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R0, [R24.64] ; IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x178] ; LDG.E R9, [R10.64] ; LDG.E R21, [R20.64] ; IMAD.WIDE R22, R22, R15, c[0x0][0x178] ; LDG.E R24, [R6.64+0x18] ; IMAD.WIDE R26, R26, R15, c[0x0][0x178] ; LDG.E R25, [R22.64] ; LDG.E R20, [R6.64+0x14] ; LDG.E R10, [R26.64] ; LDG.E R11, [R4.64+0x8] ; LDG.E R23, [R4.64+0xc] ; LDG.E R22, [R6.64+0x20] ; LDG.E R26, [R6.64+0x30] ; FFMA R0, R0, R3, R8 ; LDG.E R3, [R4.64+0x14] ; FFMA R0, R9, R12, R0 ; IMAD.WIDE R12, R13, R15, c[0x0][0x178] ; IMAD.WIDE R8, R28, R15, c[0x0][0x178] ; LDG.E R28, [R4.64+0x18] ; FFMA R0, R21, R29, R0 ; LDG.E R21, [R12.64] ; LDG.E R29, [R6.64+0x1c] ; LDG.E R9, [R8.64] ; IMAD.WIDE R12, R20, R15, c[0x0][0x178] ; LDG.E R20, [R4.64+0x10] ; FFMA R0, R25, R2, R0 ; LDG.E R27, [R12.64] ; IMAD.WIDE R24, R24, R15, c[0x0][0x178] ; LDG.E R2, [R6.64+0x24] ; LDG.E R8, [R6.64+0x28] ; FFMA R12, R10, R11, R0 ; LDG.E R11, [R24.64] ; LDG.E R10, [R6.64+0x2c] ; LDG.E R0, [R6.64+0x34] ; LDG.E R24, [R4.64+0x20] ; LDG.E R25, [R4.64+0x24] ; FFMA R21, R21, R23, R12 ; LDG.E R23, [R4.64+0x1c] ; IMAD.WIDE R12, R29, R15, c[0x0][0x178] ; LDG.E R29, [R4.64+0x28] ; FFMA R9, R9, R20, R21 ; IMAD.WIDE R20, R22, R15, c[0x0][0x178] ; LDG.E R22, [R12.64] ; FFMA R27, R27, R3, R9 ; IMAD.WIDE R2, R2, R15.reuse, c[0x0][0x178] ; LDG.E R21, [R20.64] ; IMAD.WIDE R8, R8, R15, c[0x0][0x178] ; LDG.E R2, [R2.64] ; FFMA R28, R11, R28, R27 ; LDG.E R8, [R8.64] ; IMAD.WIDE R10, R10, R15, c[0x0][0x178] ; LDG.E R20, [R4.64+0x2c] ; IMAD.WIDE R12, R26, R15, c[0x0][0x178] ; LDG.E R11, [R10.64] ; IMAD.WIDE R26, R0, R15, c[0x0][0x178] ; LDG.E R13, [R12.64] ; LDG.E R0, [R4.64+0x30] ; LDG.E R26, [R26.64] ; LDG.E R3, [R4.64+0x34] ; IADD3 R19, R19, 0x10, RZ ; ISETP.GE.AND P1, PT, R19, R18, PT ; IADD3 R6, P3, R6, 0x40, RZ ; IADD3 R9, P2, R4, 0x40, RZ ; IADD3.X R7, RZ, R7, RZ, P3, !PT ; IADD3.X R5, RZ, R5, RZ, P2, !PT ; MOV R4, R9 ; FFMA R22, R22, R23, R28 ; FFMA R21, R21, R24, R22 ; FFMA R2, R2, R25, R21 ; FFMA R2, R8, R29, R2 ; FFMA R2, R11, R20, R2 ; FFMA R0, R13, R0, R2 ; FFMA R8, R26, R3, R0 ; @!P1 BRA 0x400 ; BSYNC B1 ; IADD3 R0, R16, -R19, RZ ; BSSY B1, 0xcd0 ; ISETP.GT.AND P1, PT, R0, 0x4, PT ; @!P1 BRA 0xcc0 ; LDG.E R22, [R6.64+-0x8] ; LDG.E R28, [R6.64+-0x4] ; LDG.E R2, [R6.64] ; LDG.E R3, [R6.64+0x4] ; LDG.E R10, [R6.64+0x8] ; LDG.E R12, [R6.64+0xc] ; LDG.E R20, [R6.64+0x10] ; LDG.E R24, [R6.64+0x14] ; LDG.E R0, [R4.64+-0x8] ; LDG.E R18, [R4.64+-0x4] ; LDG.E R27, [R4.64] ; IMAD.WIDE R22, R22, R15, c[0x0][0x178] ; IMAD.WIDE R28, R28, R15.reuse, c[0x0][0x178] ; LDG.E R9, [R22.64] ; LDG.E R25, [R28.64] ; IMAD.WIDE R22, R2, R15, c[0x0][0x178] ; IMAD.WIDE R2, R3, R15.reuse, c[0x0][0x178] ; LDG.E R26, [R22.64] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R29, [R4.64+0xc] ; LDG.E R2, [R2.64] ; IMAD.WIDE R12, R12, R15, c[0x0][0x178] ; LDG.E R10, [R10.64] ; IMAD.WIDE R20, R20, R15, c[0x0][0x178] ; LDG.E R12, [R12.64] ; LDG.E R3, [R4.64+0x4] ; LDG.E R11, [R4.64+0x8] ; IMAD.WIDE R22, R24, R15, c[0x0][0x178] ; LDG.E R20, [R20.64] ; LDG.E R24, [R4.64+0x10] ; LDG.E R22, [R22.64] ; LDG.E R28, [R4.64+0x14] ; IADD3 R6, P2, R6, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R7, RZ, R7, RZ, P2, !PT ; IADD3 R19, R19, 0x8, RZ ; FFMA R0, R9, R0, R8 ; FFMA R0, R25, R18, R0 ; FFMA R0, R26, R27, R0 ; FFMA R0, R2, R3, R0 ; FFMA R0, R10, R11, R0 ; FFMA R29, R12, R29, R0 ; IADD3 R0, P1, R4, 0x20, RZ ; FFMA R29, R20, R24, R29 ; IADD3.X R5, RZ, R5, RZ, P1, !PT ; MOV R4, R0 ; FFMA R8, R22, R28, R29 ; BSYNC B1 ; ISETP.LT.OR P0, PT, R19, R16, P0 ; @!P0 BRA 0xe30 ; LDG.E R2, [R6.64+-0x8] ; LDG.E R10, [R6.64+-0x4] ; LDG.E R12, [R6.64] ; LDG.E R18, [R6.64+0x4] ; LDG.E R0, [R4.64+-0x8] ; LDG.E R9, [R4.64+-0x4] ; LDG.E R6, [R4.64+0x4] ; IMAD.WIDE R2, R2, R15, c[0x0][0x178] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R3, [R2.64] ; IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x178] ; LDG.E R11, [R10.64] ; IMAD.WIDE R18, R18, R15, c[0x0][0x178] ; LDG.E R13, [R12.64] ; LDG.E R15, [R4.64] ; LDG.E R19, [R18.64] ; FFMA R0, R3, R0, R8 ; FFMA R0, R11, R9, R0 ; FFMA R0, R13, R15, R0 ; FFMA R8, R19, R6, R0 ; BSYNC B0 ; LEA R2, P0, R14, c[0x0][0x180], 0x2 ; LEA.HI.X R3, R14, c[0x0][0x184], R17, 0x2, P0 ; STG.E [R2.64], R8 ; EXIT ; BRA 0xe80; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15sparseMatVecMulPKiS0_PKfS2_Pf ; -- Begin function _Z15sparseMatVecMulPKiS0_PKfS2_Pf .globl _Z15sparseMatVecMulPKiS0_PKfS2_Pf .p2align 8 .type _Z15sparseMatVecMulPKiS0_PKfS2_Pf,@function _Z15sparseMatVecMulPKiS0_PKfS2_Pf: ; @_Z15sparseMatVecMulPKiS0_PKfS2_Pf ; %bb.0: s_load_b32 s2, s[0:1], 0x34 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x400, v1 s_cbranch_execz .LBB0_6 ; %bb.1: s_load_b256 s[4:11], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[2:3], s[0:1], 0x20 v_mov_b32_e32 v8, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_cmpx_lt_i32_e64 v2, v3 s_cbranch_execz .LBB0_5 ; %bb.2: ; %.lr.ph.preheader v_ashrrev_i32_e32 v5, 31, v2 v_mov_b32_e32 v4, v2 v_mov_b32_e32 v8, 0 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[4:5] v_add_co_u32 v4, vcc_lo, s8, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo v_add_co_u32 v6, vcc_lo, s6, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b32 v9, v[6:7], off v_add_nc_u32_e32 v2, 1, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s0, v2, v3 s_or_b32 s4, s0, s4 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v10, 31, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[9:10], 2, v[9:10] v_add_co_u32 v9, vcc_lo, s10, v9 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo global_load_b32 v11, v[4:5], off global_load_b32 v9, v[9:10], off v_add_co_u32 v4, vcc_lo, v4, 4 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo v_add_co_u32 v6, vcc_lo, v6, 4 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo s_waitcnt vmcnt(0) v_fmac_f32_e32 v8, v11, v9 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_3 ; %bb.4: ; %Flow s_or_b32 exec_lo, exec_lo, s4 .LBB0_5: ; %Flow42 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v8, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15sparseMatVecMulPKiS0_PKfS2_Pf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15sparseMatVecMulPKiS0_PKfS2_Pf, .Lfunc_end0-_Z15sparseMatVecMulPKiS0_PKfS2_Pf ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 352 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15sparseMatVecMulPKiS0_PKfS2_Pf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15sparseMatVecMulPKiS0_PKfS2_Pf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000dbce2_00000000-6_cuda_code_038659.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .type _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf, @function _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf: .LFB3660: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) leaq 64(%rsp), %rdi movq %rsi, 32(%rsp) leaq 76(%rsp), %rsi movq %rdx, 24(%rsp) leaq 48(%rsp), %rdx movq %rcx, 16(%rsp) leaq 56(%rsp), %rcx movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 72(%rsp) movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movabsq $4294967297, %rax movq %rax, 64(%rsp) movq %rax, 76(%rsp) movl $1, 84(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 56(%rsp) .cfi_def_cfa_offset 184 leaq _Z15sparseMatVecMulPKiS0_PKfS2_Pf(%rip), %rdi pushq 56(%rsp) .cfi_def_cfa_offset 192 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq 128(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 184 popq %rdx .cfi_def_cfa_offset 176 .L2: movq 152(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $168, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf, .-_Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .globl _Z15sparseMatVecMulPKiS0_PKfS2_Pf .type _Z15sparseMatVecMulPKiS0_PKfS2_Pf, @function _Z15sparseMatVecMulPKiS0_PKfS2_Pf: .LFB3661: .cfi_startproc endbr64 jmp _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .cfi_endproc .LFE3661: .size _Z15sparseMatVecMulPKiS0_PKfS2_Pf, .-_Z15sparseMatVecMulPKiS0_PKfS2_Pf .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "CUDA error: " .LC2: .string "First 10 elements of the result vector y:" .LC3: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $4096, %rsp .cfi_def_cfa_offset 4144 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 8240 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 12336 orq $0, (%rsp) subq $592, %rsp .cfi_def_cfa_offset 12928 xorl %ebp, %ebp xorl %ebx, %ebx movq %fs:40, %rax movq %rax, 12872(%rsp) xorl %eax, %eax .L11: leaq 8772(%rsp), %r12 movl $10, %r13d movl %ebx, (%r12,%rbp,4) .L10: cmpl $63, %ebx jg .L9 call rand@PLT movl $1024, %ecx movslq %ebx, %r14 incl %ebx cltd idivl %ecx movl %edx, 68(%rsp,%r14,4) call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, 324(%rsp,%r14,4) .L9: decl %r13d jne .L10 incq %rbp cmpq $1024, %rbp jne .L11 movl %ebx, 12868(%rsp) xorl %ebx, %ebx .L12: call rand@PLT leaq 580(%rsp), %rbp cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, 0(%rbp,%rbx,4) incq %rbx cmpq $1024, %rbx jne .L12 movq %rsp, %rdi movl $4100, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movq (%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $4100, %edx call cudaMemcpy@PLT movq 8(%rsp), %rdi leaq 68(%rsp), %rsi movl $1, %ecx movl $256, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx leaq 324(%rsp), %rsi movl $256, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $4096, %edx call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1073741825, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $2, %rdi movq %rdx, 56(%rsp) movl $1, 64(%rsp) movq %rdi, 44(%rsp) movl $1, 52(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L13 movq 32(%rsp), %r8 movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .L13: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L14 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L14: movq 32(%rsp), %rsi leaq 4676(%rsp), %r12 xorl %ebx, %ebx movl $2, %ecx movl $4096, %edx movq %r12, %rdi leaq _ZSt4cout(%rip), %rbp call cudaMemcpy@PLT movq (%rsp), %rdi leaq .LC3(%rip), %r13 call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT leaq .LC2(%rip), %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .L16: movq %rbp, %rdi cvtss2sd (%r12,%rbx,4), %xmm0 incq %rbx call _ZNSo9_M_insertIdEERSoT_@PLT movq %r13, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $10, %rbx jne .L16 movq %rbp, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT xorl %eax, %eax .L8: movq 12872(%rsp), %rdx subq %fs:40, %rdx je .L17 call __stack_chk_fail@PLT .L17: addq $12880, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z15sparseMatVecMulPKiS0_PKfS2_Pf" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC4(%rip), %rdx movq %rax, %rdi leaq _Z15sparseMatVecMulPKiS0_PKfS2_Pf(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 805306368 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_038659.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf # -- Begin function _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .type _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf,@function _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf: # @_Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15sparseMatVecMulPKiS0_PKfS2_Pf, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf, .Lfunc_end0-_Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x30000000 # float 4.65661287E-10 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $12864, %rsp # imm = 0x3240 .cfi_def_cfa_offset 12912 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 xorl %ebx, %ebx xorl %ebp, %ebp .LBB1_1: # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 movl %ebp, 560(%rsp,%rbx,4) movl $10, %r14d .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 cmpl $63, %ebp jg .LBB1_4 # %bb.3: # in Loop: Header=BB1_2 Depth=2 callq rand # kill: def $eax killed $eax def $rax leal 1023(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx andl $-1024, %ecx # imm = 0xFC00 subl %ecx, %eax movslq %ebp, %r15 movl %eax, 304(%rsp,%r15,4) callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, 48(%rsp,%r15,4) incl %ebp .LBB1_4: # in Loop: Header=BB1_2 Depth=2 decl %r14d jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 incq %rbx cmpq $1024, %rbx # imm = 0x400 jne .LBB1_1 # %bb.6: movl %ebp, 4656(%rsp) xorl %ebx, %ebx .LBB1_7: # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, 8768(%rsp,%rbx,4) incq %rbx cmpq $1024, %rbx # imm = 0x400 jne .LBB1_7 # %bb.8: leaq 40(%rsp), %r12 movl $4100, %esi # imm = 0x1004 movq %r12, %rdi callq hipMalloc leaq 32(%rsp), %r15 movl $256, %esi # imm = 0x100 movq %r15, %rdi callq hipMalloc leaq 24(%rsp), %r14 movl $256, %esi # imm = 0x100 movq %r14, %rdi callq hipMalloc leaq 16(%rsp), %rbx movl $4096, %esi # imm = 0x1000 movq %rbx, %rdi callq hipMalloc leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc movq (%r12), %rdi leaq 560(%rsp), %rsi movl $4100, %edx # imm = 0x1004 movl $1, %ecx callq hipMemcpy movq (%r15), %rdi leaq 304(%rsp), %rsi movl $256, %edx # imm = 0x100 movl $1, %ecx callq hipMemcpy movq (%r14), %rdi leaq 48(%rsp), %rsi movl $256, %edx # imm = 0x100 movl $1, %ecx callq hipMemcpy movq (%rbx), %rdi leaq 8768(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movl $1, %ecx callq hipMemcpy movabsq $4294967300, %rdi # imm = 0x100000004 leaq 252(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_10 # %bb.9: movq 40(%rsp), %rdi movq 32(%rsp), %rsi movq 24(%rsp), %rdx movq 16(%rsp), %rcx movq 8(%rsp), %r8 callq _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .LBB1_10: callq hipGetLastError testl %eax, %eax je .LBB1_13 # %bb.11: movl %eax, %ebp movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_15 # %bb.12: movq %rax, %r14 movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_16 .LBB1_13: movq 8(%rsp), %rsi leaq 4672(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movl $2, %ecx callq hipMemcpy movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $41, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %r14d, %r14d xorl %r15d, %r15d .LBB1_14: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtss2sd 4672(%rsp,%r15,4), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r15 cmpq $10, %r15 jne .LBB1_14 jmp .LBB1_17 .LBB1_15: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movl $-1, %r14d .LBB1_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq (%rbx), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl %r14d, %eax addq $12864, %rsp # imm = 0x3240 .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15sparseMatVecMulPKiS0_PKfS2_Pf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15sparseMatVecMulPKiS0_PKfS2_Pf,@object # @_Z15sparseMatVecMulPKiS0_PKfS2_Pf .section .rodata,"a",@progbits .globl _Z15sparseMatVecMulPKiS0_PKfS2_Pf .p2align 3, 0x0 _Z15sparseMatVecMulPKiS0_PKfS2_Pf: .quad _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .size _Z15sparseMatVecMulPKiS0_PKfS2_Pf, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "First 10 elements of the result vector y:" .size .L.str.1, 42 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz " " .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15sparseMatVecMulPKiS0_PKfS2_Pf" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15sparseMatVecMulPKiS0_PKfS2_Pf .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z14traverseAndSumP8TreeNodePi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x118] ; S2R R7, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R7 ; ISETP.GE.AND P1, PT, R2, 0x1000, PT ; @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0xc ; @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @!P1 LDG.E R2, [R2.64] ; MOV R0, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R7, RZ, PT ; @P1 STS [R7.X4], RZ ; ISETP.GE.AND P2, PT, R0, 0x2, PT ; @!P1 STS [R7.X4], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P2 BRA 0x1c0 ; SHF.R.U32.HI R3, RZ, 0x1, R0 ; IMAD.SHL.U32 R0, R7, 0x4, RZ ; ISETP.GE.AND P1, PT, R7, R3, PT ; @!P1 IMAD R2, R3, 0x4, R0 ; @!P1 LDS R4, [R7.X4] ; SHF.R.U32.HI R3, RZ, 0x1, R3 ; @!P1 LDS R5, [R2] ; @!P1 IADD3 R4, R4, R5, RZ ; @!P1 STS [R7.X4], R4 ; BAR.SYNC 0x0 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @P1 BRA 0x120 ; @P0 EXIT ; LDS R5, [RZ] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; MOV R3, c[0x0][0x16c] ; RED.E.ADD.STRONG.GPU [R2.64], R5 ; EXIT ; BRA 0x220; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14traverseAndSumP8TreeNodePi ; -- Begin function _Z14traverseAndSumP8TreeNodePi .globl _Z14traverseAndSumP8TreeNodePi .p2align 8 .type _Z14traverseAndSumP8TreeNodePi,@function _Z14traverseAndSumP8TreeNodePi: ; @_Z14traverseAndSumP8TreeNodePi ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b128 s[0:3], s[0:1], 0x0 s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_mov_b32_e32 v2, 0 v_cmpx_gt_i32_e32 0x1000, v1 s_cbranch_execz .LBB0_2 ; %bb.1: v_mad_i64_i32 v[2:3], null, v1, 12, s[0:1] global_load_b32 v2, v[2:3], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s5 v_lshl_add_u32 v1, v0, 2, 0 s_cmp_lt_u32 s4, 2 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier .LBB0_3: ; =>This Inner Loop Header: Depth=1 buffer_gl0_inv s_cbranch_scc1 .LBB0_7 ; %bb.4: ; %.lr.ph ; in Loop: Header=BB0_3 Depth=1 s_lshr_b32 s0, s4, 1 s_mov_b32 s1, exec_lo v_cmpx_gt_u32_e64 s0, v0 s_cbranch_execz .LBB0_6 ; %bb.5: ; in Loop: Header=BB0_3 Depth=1 v_lshl_add_u32 v2, s0, 2, v1 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v2, v3, v2 ds_store_b32 v1, v2 .LBB0_6: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s4, 4 s_mov_b32 s4, s0 s_branch .LBB0_3 .LBB0_7: ; %._crit_edge s_mov_b32 s0, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_10 ; %bb.8: s_mov_b32 s0, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v0, s0, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_and_b32 s1, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s1 s_cbranch_execz .LBB0_10 ; %bb.9: v_mov_b32_e32 v0, 0 s_bcnt1_i32_b32 s0, s0 ds_load_b32 v1, v0 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v1, v1, s0 global_atomic_add_u32 v0, v1, s[2:3] .LBB0_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14traverseAndSumP8TreeNodePi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14traverseAndSumP8TreeNodePi, .Lfunc_end0-_Z14traverseAndSumP8TreeNodePi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 308 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14traverseAndSumP8TreeNodePi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14traverseAndSumP8TreeNodePi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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2,948
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0014fcbc_00000000-6_cuda_code_065408.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6835: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6835: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB7717: .cfi_startproc jmp *%rsi .cfi_endproc .LFE7717: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi .type _Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi, @function _Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi: .LFB6857: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z14traverseAndSumP8TreeNodePi(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6857: .size _Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi, .-_Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi .globl _Z14traverseAndSumP8TreeNodePi .type _Z14traverseAndSumP8TreeNodePi, @function _Z14traverseAndSumP8TreeNodePi: .LFB6858: .cfi_startproc endbr64 jmp _Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi .cfi_endproc .LFE6858: .size _Z14traverseAndSumP8TreeNodePi, .-_Z14traverseAndSumP8TreeNodePi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate device memory for tree: " .LC1: .string "Failed to allocate device memory for sum: " .LC2: .string "Failed to copy tree data to device: " .LC3: .string "Failed to copy sum data to device: " .LC4: .string "Kernel launch failed: " .LC5: .string "Failed to copy sum data back to host: " .LC6: .string "Sum of all nodes in the binary tree: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6832: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 leaq -49152(%rsp), %r11 .cfi_def_cfa 11, 49176 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $72, %rsp .cfi_def_cfa_offset 49248 movl $2, %edx movq %fs:40, %rax movq %rax, 49208(%rsp) xorl %eax, %eax xorl %eax, %eax movl %eax, 12(%rsp) leaq 56(%rsp), %rax movq %rax, %rbp .L10: movl %edx, 8(%rax) leal -1(%rdx), %ecx addl $2, %edx addq $12, %rax movl $1, -12(%rax) movl %ecx, -8(%rax) cmpl $8194, %edx jne .L10 leaq 16(%rsp), %rdi movl $49152, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L11 leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L12 .L11: leaq 24(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L13 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 16(%rsp), %rdi .L23: call cudaFree@PLT .L12: orl $-1, %eax jmp .L9 .L13: movq 16(%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $49152, %edx call cudaMemcpy@PLT leaq .LC2(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L24 movq 24(%rsp), %rdi leaq 12(%rsp), %rbp movl $1, %ecx movl $4, %edx movq %rbp, %rsi call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L24 movl $16777217, %edx movl $268435457, %edi xorl %r9d, %r9d movl $1024, %r8d salq $8, %rdx salq $4, %rdi movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L17 movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z44__device_stub__Z14traverseAndSumP8TreeNodePiP8TreeNodePi .L17: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L24 movq 24(%rsp), %rsi movl $2, %ecx movl $4, %edx movq %rbp, %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax je .L19 leaq .LC5(%rip), %rsi .L24: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi jmp .L23 .L19: movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl 12(%rsp), %esi movq %rax, %rdi call _ZNSolsEi@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L9: movq 49208(%rsp), %rdx subq %fs:40, %rdx je .L20 call __stack_chk_fail@PLT .L20: addq $49224, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6832: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z14traverseAndSumP8TreeNodePi" .LC8: .string "_ZN50_INTERNAL_26699370_19_cuda_code_065408_cu_71b83b304cuda3std3__419piecewise_constructE" .LC9: .string "_ZN50_INTERNAL_26699370_19_cuda_code_065408_cu_71b83b304cuda3std6ranges3__45__cpo4swapE" .LC10: .string "_ZN50_INTERNAL_26699370_19_cuda_code_065408_cu_71b83b304cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6860: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z14traverseAndSumP8TreeNodePi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC8(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC9(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6860: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_065408.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z29__device_stub__traverseAndSumP8TreeNodePi # -- Begin function _Z29__device_stub__traverseAndSumP8TreeNodePi .type _Z29__device_stub__traverseAndSumP8TreeNodePi,@function _Z29__device_stub__traverseAndSumP8TreeNodePi: # @_Z29__device_stub__traverseAndSumP8TreeNodePi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z14traverseAndSumP8TreeNodePi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z29__device_stub__traverseAndSumP8TreeNodePi, .Lfunc_end0-_Z29__device_stub__traverseAndSumP8TreeNodePi .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $49184, %rsp # imm = 0xC020 .cfi_def_cfa_offset 49200 .cfi_offset %rbx, -16 movl $0, 28(%rsp) movl $4, %eax movl $2, %ecx .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1, 24(%rsp,%rax,2) leal -1(%rcx), %edx movl %edx, 28(%rsp,%rax,2) movl %ecx, 32(%rsp,%rax,2) addq $6, %rax addl $2, %ecx cmpq $24580, %rax # imm = 0x6004 jne .LBB1_1 # %bb.2: leaq 16(%rsp), %rdi movl $49152, %esi # imm = 0xC000 callq hipMalloc testl %eax, %eax je .LBB1_5 # %bb.3: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $43, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_8 # %bb.4: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_9 .LBB1_5: leaq 8(%rsp), %rdi movl $4, %esi callq hipMalloc testl %eax, %eax je .LBB1_10 # %bb.6: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_12 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_13 .LBB1_8: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_22 .LBB1_10: movq 16(%rsp), %rdi leaq 32(%rsp), %rsi movl $49152, %edx # imm = 0xC000 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_14 # %bb.11: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $36, %edx jmp .LBB1_16 .LBB1_12: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit41 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rdi jmp .LBB1_21 .LBB1_14: movq 8(%rsp), %rdi leaq 28(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_24 # %bb.15: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $35, %edx .LBB1_16: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_18 # %bb.17: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_19 .LBB1_18: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit43 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_20: movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi .LBB1_21: callq hipFree .LBB1_22: movl $-1, %eax .LBB1_23: addq $49184, %rsp # imm = 0xC020 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_24: .cfi_def_cfa_offset 49200 movabsq $4294967312, %rdi # imm = 0x100000010 leaq 240(%rdi), %rdx movl $1024, %r8d # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_26 # %bb.25: movq 16(%rsp), %rdi movq 8(%rsp), %rsi callq _Z29__device_stub__traverseAndSumP8TreeNodePi .LBB1_26: callq hipGetLastError testl %eax, %eax je .LBB1_28 # %bb.27: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $22, %edx jmp .LBB1_30 .LBB1_28: movq 8(%rsp), %rsi leaq 28(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_31 # %bb.29: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $38, %edx .LBB1_30: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_20 .LBB1_31: movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $37, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 28(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB1_23 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14traverseAndSumP8TreeNodePi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z14traverseAndSumP8TreeNodePi,@object # @_Z14traverseAndSumP8TreeNodePi .section .rodata,"a",@progbits .globl _Z14traverseAndSumP8TreeNodePi .p2align 3, 0x0 _Z14traverseAndSumP8TreeNodePi: .quad _Z29__device_stub__traverseAndSumP8TreeNodePi .size _Z14traverseAndSumP8TreeNodePi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory for tree: " .size .L.str, 44 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate device memory for sum: " .size .L.str.1, 43 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to copy tree data to device: " .size .L.str.2, 37 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy sum data to device: " .size .L.str.3, 36 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed: " .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy sum data back to host: " .size .L.str.5, 39 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Sum of all nodes in the binary tree: " .size .L.str.6, 38 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14traverseAndSumP8TreeNodePi" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__traverseAndSumP8TreeNodePi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14traverseAndSumP8TreeNodePi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z13simulateClothP5Pointii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; @P0 EXIT ; HFMA2.MMA R2, -RZ, RZ, 0, 7.152557373046875e-07 ; IMAD R3, R3, c[0x0][0x168], R0 ; MOV R5, 0x3c23d70a ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64+0x4], R5 ; BAR.SYNC 0x0 ; EXIT ; BRA 0x120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13simulateClothP5Pointii ; -- Begin function _Z13simulateClothP5Pointii .globl _Z13simulateClothP5Pointii .p2align 8 .type _Z13simulateClothP5Pointii,@function _Z13simulateClothP5Pointii: ; @_Z13simulateClothP5Pointii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b64 s[4:5], s[0:1], 0x8 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s4, v0 v_cmp_gt_i32_e64 s2, s5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_4 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mad_i64_i32 v[0:1], null, v2, 12, s[0:1] s_mov_b32 s0, 0 global_load_b32 v3, v[0:1], off offset:4 v_add_co_u32 v0, vcc_lo, v0, 4 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo .LBB0_2: ; %atomicrmw.start ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_add_f32_e32 v2, 0x3c23d70a, v3 global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v2, v3 v_mov_b32_e32 v3, v2 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_2 ; %bb.3: ; %atomicrmw.end s_barrier buffer_gl0_inv .LBB0_4: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13simulateClothP5Pointii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13simulateClothP5Pointii, .Lfunc_end0-_Z13simulateClothP5Pointii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 224 ; NumSgprs: 18 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13simulateClothP5Pointii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13simulateClothP5Pointii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000ca74f_00000000-6_cuda_code_022287.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6835: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6835: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB7719: .cfi_startproc jmp *%rsi .cfi_endproc .LFE7719: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z40__device_stub__Z13simulateClothP5PointiiP5Pointii .type _Z40__device_stub__Z13simulateClothP5PointiiP5Pointii, @function _Z40__device_stub__Z13simulateClothP5PointiiP5Pointii: .LFB6857: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 24(%rsp), %rcx leaq 32(%rsp), %rdi movl %esi, 4(%rsp) leaq 44(%rsp), %rsi movl %edx, (%rsp) leaq 16(%rsp), %rdx movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 40(%rsp) movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 32(%rsp) movq %rax, 44(%rsp) movl $1, 52(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 24(%rsp) .cfi_def_cfa_offset 136 leaq _Z13simulateClothP5Pointii(%rip), %rdi pushq 24(%rsp) .cfi_def_cfa_offset 144 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq 96(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6857: .size _Z40__device_stub__Z13simulateClothP5PointiiP5Pointii, .-_Z40__device_stub__Z13simulateClothP5PointiiP5Pointii .globl _Z13simulateClothP5Pointii .type _Z13simulateClothP5Pointii, @function _Z13simulateClothP5Pointii: .LFB6858: .cfi_startproc endbr64 jmp _Z40__device_stub__Z13simulateClothP5PointiiP5Pointii .cfi_endproc .LFE6858: .size _Z13simulateClothP5Pointii, .-_Z13simulateClothP5Pointii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Failed to allocate device memory: " .LC2: .string "Failed to copy data to device: " .LC3: .string "Kernel launch failed: " .LC4: .string "Failed to copy data from device: " .LC5: .string "First few points after simulation:" .LC6: .string "Point " .LC7: .string ": (" .LC8: .string ", " .LC9: .string ")" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6832: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $786432, %edi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $1, 24(%rsp) movabsq $68719476752, %rax movq %rax, 28(%rsp) movl $1, 36(%rsp) call _Znam@PLT movq %rax, %rbx movq %rax, %rbp leaq 786432(%rax), %rdx .L10: movl $0x00000000, (%rax) addq $12, %rax movl $0x00000000, -8(%rax) movl $0x00000000, -4(%rax) cmpq %rdx, %rax jne .L10 leaq 8(%rsp), %rdi movl $786432, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L11 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L12 .L11: movq 8(%rsp), %rdi movl $1, %ecx movl $786432, %edx movq %rbx, %rsi call cudaMemcpy@PLT movl %eax, %r12d testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi .L23: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT .L12: orl $-1, %eax jmp .L9 .L13: movl 24(%rsp), %ecx movq 28(%rsp), %rdi xorl %r9d, %r9d xorl %r8d, %r8d movabsq $68719476752, %rdx movl 36(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L15 movq 8(%rsp), %rdi movl $256, %edx movl $256, %esi call _Z40__device_stub__Z13simulateClothP5PointiiP5Pointii .L15: call cudaGetLastError@PLT leaq .LC3(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L23 movq 8(%rsp), %rsi movl $2, %ecx movl $786432, %edx movq %rbx, %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L23 movq 8(%rsp), %rdi leaq _ZSt4cout(%rip), %r13 xorl %r12d, %r12d leaq .LC6(%rip), %r14 call cudaFree@PLT leaq .LC5(%rip), %rsi movq %r13, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 .L18: movq %r14, %rsi movq %r13, %rdi leaq .LC8(%rip), %r15 addq $12, %rbp call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %esi incl %r12d movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC7(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -12(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %r15, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -8(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %r15, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -4(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT leaq .LC9(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 cmpl $10, %r12d jne .L18 movq %rbx, %rdi call _ZdaPv@PLT xorl %eax, %eax .L9: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L19 call __stack_chk_fail@PLT .L19: addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6832: .size main, .-main .section .rodata.str1.1 .LC10: .string "_Z13simulateClothP5Pointii" .LC11: .string "_ZN50_INTERNAL_d9ce1b8e_19_cuda_code_022287_cu_4104fed84cuda3std3__419piecewise_constructE" .LC12: .string "_ZN50_INTERNAL_d9ce1b8e_19_cuda_code_022287_cu_4104fed84cuda3std6ranges3__45__cpo4swapE" .LC13: .string "_ZN50_INTERNAL_d9ce1b8e_19_cuda_code_022287_cu_4104fed84cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6860: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z13simulateClothP5Pointii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC11(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6860: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_022287.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z28__device_stub__simulateClothP5Pointii # -- Begin function _Z28__device_stub__simulateClothP5Pointii .type _Z28__device_stub__simulateClothP5Pointii,@function _Z28__device_stub__simulateClothP5Pointii: # @_Z28__device_stub__simulateClothP5Pointii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) movq %rsp, %rsi movl %edx, (%rsi) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13simulateClothP5Pointii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $112, %rsp .cfi_adjust_cfa_offset -112 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z28__device_stub__simulateClothP5Pointii, .Lfunc_end0-_Z28__device_stub__simulateClothP5Pointii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $16, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $786432, %edi # imm = 0xC0000 callq _Znam movq %rax, %rbx movl $786432, %edx # imm = 0xC0000 movq %rax, %rdi xorl %esi, %esi callq memset@PLT leaq 8(%rsp), %rdi movl $786432, %esi # imm = 0xC0000 callq hipMalloc testl %eax, %eax je .LBB1_3 # %bb.1: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $34, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_5 # %bb.2: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_6 .LBB1_3: movq 8(%rsp), %rdi movl $786432, %edx # imm = 0xC0000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_7 # %bb.4: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $31, %edx jmp .LBB1_13 .LBB1_5: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_17 .LBB1_7: movabsq $68719476752, %rdi # imm = 0x1000000010 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_9 # %bb.8: movq 8(%rsp), %rdi movl $256, %esi # imm = 0x100 movl $256, %edx # imm = 0x100 callq _Z28__device_stub__simulateClothP5Pointii .LBB1_9: callq hipGetLastError testl %eax, %eax je .LBB1_11 # %bb.10: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $22, %edx jmp .LBB1_13 .LBB1_11: movq 8(%rsp), %rsi movl $786432, %edx # imm = 0xC0000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_19 # %bb.12: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $33, %edx .LBB1_13: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_15 # %bb.14: movq %rax, %r14 movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_16 .LBB1_15: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv .LBB1_17: movl $-1, %eax .LBB1_18: addq $16, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_19: .cfi_def_cfa_offset 64 movq 8(%rsp), %rdi callq hipFree movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $34, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq %rbx, %r12 addq $8, %r12 xorl %r14d, %r14d .LBB1_20: # =>This Inner Loop Header: Depth=1 movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $6, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r14d, %esi callq _ZNSolsEi movq %rax, %r15 movl $.L.str.6, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd -8(%r12), %xmm0 movq %r15, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.7, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd -4(%r12), %xmm0 movq %r15, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.7, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd (%r12), %xmm0 movq %r15, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.8, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r15), %rax movq -24(%rax), %rdi addq %r15, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r14 addq $12, %r12 cmpq $10, %r14 jne .LBB1_20 # %bb.21: movq %rbx, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB1_18 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13simulateClothP5Pointii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z13simulateClothP5Pointii,@object # @_Z13simulateClothP5Pointii .section .rodata,"a",@progbits .globl _Z13simulateClothP5Pointii .p2align 3, 0x0 _Z13simulateClothP5Pointii: .quad _Z28__device_stub__simulateClothP5Pointii .size _Z13simulateClothP5Pointii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory: " .size .L.str, 35 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to copy data to device: " .size .L.str.1, 32 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Kernel launch failed: " .size .L.str.2, 23 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy data from device: " .size .L.str.3, 34 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "First few points after simulation:" .size .L.str.4, 35 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Point " .size .L.str.5, 7 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz ": (" .size .L.str.6, 4 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz ", " .size .L.str.7, 3 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz ")" .size .L.str.8, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13simulateClothP5Pointii" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__simulateClothP5Pointii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13simulateClothP5Pointii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z10stencil64DPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R11, SR_CTAID.Y ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B0, 0x150 ; S2R R10, SR_TID.Y ; S2R R8, SR_CTAID.X ; S2R R9, SR_TID.X ; LEA R6, R11, R10, 0x4 ; ISETP.GE.AND P0, PT, R6.reuse, 0x40, PT ; ISETP.GT.AND P1, PT, R6, 0x3f, PT ; LEA R3, R8, R9, 0x4 ; IMAD R2, R10, 0x16, R9 ; ISETP.GT.OR P2, PT, R9, 0x2, P1 ; ISETP.LT.AND P0, PT, R3, 0x40, !P0 ; LEA R0, R6, R3, 0x6 ; IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; @!P0 BRA 0x140 ; LDG.E R7, [R4.64] ; STS [R2.X4+0x114], R7 ; BSYNC B0 ; BSSY B0, 0x1f0 ; @P2 BRA 0x1e0 ; ISETP.GE.AND P2, PT, R3, 0x3, PT ; BSSY B1, 0x1d0 ; HFMA2.MMA R7, -RZ, RZ, 0, 0 ; @!P2 BRA 0x1c0 ; LDG.E R7, [R4.64+-0xc] ; BSYNC B1 ; STS [R2.X4+0x108], R7 ; BSYNC B0 ; ISETP.LT.OR P1, PT, R9, 0xd, P1 ; BSSY B0, 0x2a0 ; @P1 BRA 0x290 ; ISETP.GT.AND P1, PT, R3, 0x3c, PT ; BSSY B1, 0x280 ; MOV R7, RZ ; @P1 BRA 0x270 ; LDG.E R7, [R4.64+0xc] ; BSYNC B1 ; STS [R2.X4+0x120], R7 ; BSYNC B0 ; ISETP.GT.AND P1, PT, R3, 0x3f, PT ; BSSY B0, 0x360 ; ISETP.GT.OR P2, PT, R10, 0x2, P1 ; @P2 BRA 0x350 ; ISETP.GE.AND P2, PT, R6, 0x3, PT ; BSSY B1, 0x340 ; HFMA2.MMA R3, -RZ, RZ, 0, 0 ; @!P2 BRA 0x330 ; LDG.E R3, [R4.64+-0x300] ; BSYNC B1 ; STS [R2.X4+0xc], R3 ; BSYNC B0 ; ISETP.LT.OR P1, PT, R10, 0xd, P1 ; BSSY B0, 0x410 ; @P1 BRA 0x400 ; ISETP.GT.AND P1, PT, R6, 0x3c, PT ; BSSY B1, 0x3f0 ; MOV R3, RZ ; @P1 BRA 0x3e0 ; LDG.E R3, [R4.64+0x300] ; BSYNC B1 ; STS [R2.X4+0x21c], R3 ; BSYNC B0 ; ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x90], PT ; ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x8c], PT, P1 ; @P1 BRA 0x450 ; BPT.TRAP 0x1 ; S2R R4, SR_TID.Z ; IADD3 R3, R9, R10, RZ ; BSSY B0, 0x6d0 ; BAR.SYNC 0x0 ; IADD3 R4, -R4, RZ, RZ ; ISETP.NE.AND P1, PT, R3, R4, PT ; @P1 BRA 0x6c0 ; S2R R4, SR_CTAID.Z ; MOV R3, c[0x0][0xc] ; S2R R5, SR_LANEID ; MEMBAR.ALL.GPU ; VOTEU.ANY UR6, UPT, PT ; IADD3 R7, RZ, -R3, RZ ; FLO.U32 R6, UR6 ; MOV R10, c[0x0][0x14] ; UPOPC UR7, UR6 ; IADD3 R3, R8, R11, RZ ; IMAD R7, R7, c[0x0][0x10], RZ ; IADD3 R8, -R4, RZ, RZ ; ERRBAR; IMAD R4, R7, R10, -0x7fffffff ; ISETP.NE.AND P1, PT, R3, R8, PT ; SEL R3, R4, 0x1, !P1 ; MOV R4, c[0x0][0x90] ; ISETP.EQ.U32.AND P2, PT, R6, R5, PT ; IMAD R7, R3, UR7, RZ ; MOV R5, c[0x0][0x8c] ; @P2 ATOM.E.ADD.STRONG.GPU PT, R7, [R4.64+0x4], R7 ; S2R R8, SR_LTMASK ; LOP3.LUT R8, R8, UR6, RZ, 0xc0, !PT ; POPC R8, R8 ; SHFL.IDX PT, R6, R7, R6, 0x1f ; IMAD R3, R3, R8, R6 ; LD.E.STRONG.GPU R6, [R4.64+0x4] ; YIELD ; LOP3.LUT R7, R6, R3, RZ, 0x3c, !PT ; CCTL.IVALL ; ISETP.GT.AND P1, PT, R7, -0x1, PT ; @P1 BRA 0x660 ; BSYNC B0 ; BRA.CONV ~URZ, 0x710 ; MOV R4, 0x700 ; CALL.REL.NOINC 0xd90 ; BRA 0x720 ; BAR.SYNC 0x0 ; @!P0 EXIT ; LDS R3, [R2.X4] ; LDS R6, [R2.X4+0x4] ; LDS R7, [R2.X4+0x8] ; LDS R8, [R2.X4+0xc] ; LDS R9, [R2.X4+0x10] ; LDS R10, [R2.X4+0x14] ; LDS R11, [R2.X4+0x18] ; LDS R12, [R2.X4+0x58] ; LDS R13, [R2.X4+0x5c] ; LDS R4, [R2.X4+0x60] ; FADD R5, RZ, R3 ; LDS R16, [R2.X4+0x210] ; FADD R6, R5, R6 ; LDS R3, [R2.X4+0x64] ; FADD R7, R6, R7 ; LDS R5, [R2.X4+0x68] ; FADD R8, R7, R8 ; LDS R6, [R2.X4+0x6c] ; FADD R9, R8, R9 ; LDS R7, [R2.X4+0x70] ; FADD R10, R9, R10 ; LDS R8, [R2.X4+0xb0] ; FADD R11, R10, R11 ; LDS R9, [R2.X4+0xb4] ; FADD R12, R11, R12 ; LDS R10, [R2.X4+0xb8] ; FADD R13, R12, R13 ; LDS R11, [R2.X4+0xbc] ; FADD R14, R13, R4 ; LDS R12, [R2.X4+0xc0] ; LDS R4, [R2.X4+0xc4] ; FADD R14, R14, R3 ; LDS R18, [R2.X4+0x218] ; FADD R13, R14, R5 ; LDS R3, [R2.X4+0xc8] ; FADD R14, R13, R6 ; LDS R5, [R2.X4+0x108] ; FADD R13, R14, R7 ; LDS R6, [R2.X4+0x10c] ; FADD R14, R13, R8 ; LDS R7, [R2.X4+0x110] ; FADD R13, R14, R9 ; LDS R8, [R2.X4+0x114] ; FADD R14, R13, R10 ; LDS R9, [R2.X4+0x118] ; FADD R13, R14, R11 ; LDS R10, [R2.X4+0x11c] ; FADD R13, R13, R12 ; LDS R11, [R2.X4+0x120] ; FADD R14, R13, R4 ; LDS R12, [R2.X4+0x160] ; LDS R4, [R2.X4+0x164] ; FADD R14, R14, R3 ; LDS R20, [R2.X4+0x220] ; FADD R13, R14, R5 ; LDS R3, [R2.X4+0x168] ; FADD R14, R13, R6 ; LDS R5, [R2.X4+0x16c] ; FADD R13, R14, R7 ; LDS R6, [R2.X4+0x170] ; FADD R14, R13, R8 ; LDS R7, [R2.X4+0x174] ; FADD R13, R14, R9 ; LDS R8, [R2.X4+0x178] ; FADD R14, R13, R10 ; LDS R9, [R2.X4+0x1b8] ; FADD R13, R14, R11 ; LDS R10, [R2.X4+0x1bc] ; FADD R13, R13, R12 ; LDS R11, [R2.X4+0x1c0] ; FADD R14, R13, R4 ; LDS R12, [R2.X4+0x1c4] ; LDS R4, [R2.X4+0x1c8] ; FADD R14, R14, R3 ; LDS R3, [R2.X4+0x1cc] ; FADD R5, R14, R5 ; LDS R14, [R2.X4+0x1d0] ; FADD R6, R5, R6 ; LDS R5, [R2.X4+0x228] ; FADD R7, R6, R7 ; LDS R6, [R2.X4+0x214] ; FADD R8, R7, R8 ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; FADD R9, R8, R9 ; LDS R8, [R2.X4+0x21c] ; FADD R10, R9, R10 ; FADD R11, R10, R11 ; LDS R10, [R2.X4+0x224] ; FADD R11, R11, R12 ; FADD R4, R11, R4 ; FADD R3, R4, R3 ; FADD R3, R3, R14 ; FADD R3, R3, R16 ; FADD R3, R3, R6 ; FADD R3, R3, R18 ; FADD R3, R3, R8 ; FADD R3, R3, R20 ; FADD R10, R3, R10 ; IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; FADD R5, R10, R5 ; STG.E [R2.64], R5 ; EXIT ; MOV R5, 0x0 ; WARPSYNC 0xffffffff ; BAR.SYNC 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0xdd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10stencil64DPfS_ ; -- Begin function _Z10stencil64DPfS_ .globl _Z10stencil64DPfS_ .p2align 8 .type _Z10stencil64DPfS_,@function _Z10stencil64DPfS_: ; @_Z10stencil64DPfS_ ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x0 v_and_b32_e32 v5, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshl_add_u32 v6, s14, 4, v5 v_lshl_add_u32 v7, s15, 4, v3 v_lshlrev_b32_e32 v4, 2, v5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_i32_e32 vcc_lo, 64, v6 v_cmp_gt_i32_e64 s2, 64, v7 v_lshl_add_u32 v1, v7, 6, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s8, vcc_lo, s2 s_and_saveexec_b32 s9, s8 s_cbranch_execz .LBB0_2 ; %bb.1: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[8:9], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v8, s3, s4, v8 v_add_co_ci_u32_e64 v9, s3, s5, v9, s3 global_load_b32 v2, v[8:9], off v_mad_u32_u24 v8, 0x58, v3, v4 s_waitcnt vmcnt(0) ds_store_b32 v8, v2 offset:276 .LBB0_2: s_or_b32 exec_lo, exec_lo, s9 v_cmp_gt_u32_e64 s3, 3, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s3, s3, s2 s_and_saveexec_b32 s9, s3 s_cbranch_execz .LBB0_6 ; %bb.3: v_mov_b32_e32 v2, 0 s_mov_b32 s10, exec_lo v_cmpx_lt_i32_e32 2, v6 s_cbranch_execz .LBB0_5 ; %bb.4: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v8, s3, s4, v8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v9, s3, s5, v9, s3 global_load_b32 v2, v[8:9], off offset:-12 .LBB0_5: s_or_b32 exec_lo, exec_lo, s10 v_mad_u32_u24 v8, 0x58, v3, v4 s_waitcnt vmcnt(0) ds_store_b32 v8, v2 offset:264 .LBB0_6: ; %Flow113 s_or_b32 exec_lo, exec_lo, s9 v_cmp_lt_u32_e64 s3, 12, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, s3, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_10 ; %bb.7: v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo v_cmpx_gt_i32_e32 61, v6 s_cbranch_execz .LBB0_9 ; %bb.8: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v8, s2, s4, v8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v9, s2, s5, v9, s2 global_load_b32 v2, v[8:9], off offset:12 .LBB0_9: s_or_b32 exec_lo, exec_lo, s9 v_mad_u32_u24 v8, 0x58, v3, v4 s_waitcnt vmcnt(0) ds_store_b32 v8, v2 offset:288 .LBB0_10: ; %Flow112 s_or_b32 exec_lo, exec_lo, s3 v_cmp_gt_u32_e64 s2, 3, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, vcc_lo s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_14 ; %bb.11: v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo v_cmpx_lt_i32_e32 2, v7 s_cbranch_execz .LBB0_13 ; %bb.12: v_lshlrev_b32_e32 v2, 6, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v8, v6, v2, 0xffffff40 v_ashrrev_i32_e32 v9, 31, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[8:9] s_waitcnt lgkmcnt(0) v_add_co_u32 v8, s2, s4, v8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v9, s2, s5, v9, s2 global_load_b32 v2, v[8:9], off .LBB0_13: s_or_b32 exec_lo, exec_lo, s9 v_mad_u32_u24 v8, 0x58, v3, v4 s_waitcnt vmcnt(0) ds_store_b32 v8, v2 offset:12 .LBB0_14: ; %Flow111 s_or_b32 exec_lo, exec_lo, s3 v_cmp_lt_u32_e64 s2, 12, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s3, s2, vcc_lo s_and_saveexec_b32 s2, s3 s_cbranch_execz .LBB0_18 ; %bb.15: v_mov_b32_e32 v2, 0 s_mov_b32 s3, exec_lo v_cmpx_gt_i32_e32 61, v7 s_cbranch_execz .LBB0_17 ; %bb.16: v_lshlrev_b32_e32 v2, 6, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v6, v6, v2, 0xc0 v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[6:7] s_waitcnt lgkmcnt(0) v_add_co_u32 v6, vcc_lo, s4, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_load_b32 v2, v[6:7], off .LBB0_17: s_or_b32 exec_lo, exec_lo, s3 v_mad_u32_u24 v6, 0x58, v3, v4 s_waitcnt vmcnt(0) ds_store_b32 v6, v2 offset:540 .LBB0_18: ; %Flow110 s_or_b32 exec_lo, exec_lo, s2 v_bfe_u32 v0, v0, 20, 10 s_mov_b32 s2, exec_lo s_waitcnt lgkmcnt(0) buffer_gl1_inv buffer_gl0_inv s_barrier v_or3_b32 v0, v3, v0, v5 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_28 ; %bb.19: s_load_b64 s[0:1], s[0:1], 0x68 s_mov_b32 s5, exec_lo s_mov_b32 s4, exec_lo v_mbcnt_lo_u32_b32 v0, s5, 0 ; implicit-def: $vgpr2 s_waitcnt lgkmcnt(0) s_load_b32 s3, s[0:1], 0x28 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_21 ; %bb.20: s_bcnt1_i32_b32 s5, s5 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s5 global_atomic_add_u32 v2, v2, v5, s[0:1] offset:32 glc .LBB0_21: s_or_b32 exec_lo, exec_lo, s4 s_waitcnt vmcnt(0) v_readfirstlane_b32 s4, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, s4, v0 s_waitcnt lgkmcnt(0) s_add_i32 s4, s3, -1 v_and_b32_e32 v2, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ne_u32_e32 vcc_lo, s4, v2 s_and_saveexec_b32 s4, vcc_lo s_xor_b32 s4, exec_lo, s4 s_cbranch_execz .LBB0_25 ; %bb.22: ; %.preheader.i.i.i.i.preheader v_mov_b32_e32 v2, 0 s_mov_b32 s5, 0 .LBB0_23: ; %.preheader.i.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_load_b32 v5, v2, s[0:1] offset:32 glc s_waitcnt vmcnt(0) v_xor_b32_e32 v5, v5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_lt_u32_e32 vcc_lo, 0xffff, v5 s_or_b32 s5, vcc_lo, s5 s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_23 ; %bb.24: ; %Flow105 s_or_b32 exec_lo, exec_lo, s5 .LBB0_25: ; %Flow107 s_and_not1_saveexec_b32 s4, s4 s_cbranch_execz .LBB0_28 ; %bb.26: s_mov_b32 s4, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v0, s4, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_and_b32 s5, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s5 s_cbranch_execz .LBB0_28 ; %bb.27: s_sub_i32 s3, 0x10000, s3 s_bcnt1_i32_b32 s4, s4 v_mov_b32_e32 v0, 0 s_mul_i32 s3, s3, s4 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v2, s3 global_atomic_add_u32 v0, v2, s[0:1] offset:32 .LBB0_28: ; %Flow109 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt_vscnt null, 0x0 s_barrier s_and_saveexec_b32 s0, s8 s_cbranch_execz .LBB0_34 ; %bb.29: ; %.preheader85 v_mad_u32_u24 v2, 0x58, v3, v4 v_mov_b32_e32 v0, 0 s_mov_b32 s0, -3 .LBB0_30: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_31 Depth 2 s_movk_i32 s1, 0xffe4 .LBB0_31: ; Parent Loop BB0_30 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s1, v2 s_add_i32 s1, s1, 4 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s1, 0 ds_load_b32 v3, v3 offset:28 s_waitcnt lgkmcnt(0) v_add_f32_e32 v0, v0, v3 s_cbranch_scc0 .LBB0_31 ; %bb.32: ; in Loop: Header=BB0_30 Depth=1 v_add_nc_u32_e32 v2, 0x58, v2 s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, 4 s_cbranch_scc0 .LBB0_30 ; %bb.33: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s6, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB0_34: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10stencil64DPfS_ .amdhsa_group_segment_fixed_size 1936 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10stencil64DPfS_, .Lfunc_end0-_Z10stencil64DPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1160 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 1936 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 104 .size: 8 .value_kind: hidden_multigrid_sync_arg .group_segment_fixed_size: 1936 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10stencil64DPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10stencil64DPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0009e2f0_00000000-6_cuda_code_040587.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6835: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6835: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB7717: .cfi_startproc jmp *%rsi .cfi_endproc .LFE7717: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z32__device_stub__Z10stencil64DPfS_PfS_ .type _Z32__device_stub__Z10stencil64DPfS_PfS_, @function _Z32__device_stub__Z10stencil64DPfS_PfS_: .LFB6857: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movq %rsi, (%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z10stencil64DPfS_(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6857: .size _Z32__device_stub__Z10stencil64DPfS_PfS_, .-_Z32__device_stub__Z10stencil64DPfS_PfS_ .globl _Z10stencil64DPfS_ .type _Z10stencil64DPfS_, @function _Z10stencil64DPfS_: .LFB6858: .cfi_startproc endbr64 jmp _Z32__device_stub__Z10stencil64DPfS_PfS_ .cfi_endproc .LFE6858: .size _Z10stencil64DPfS_, .-_Z10stencil64DPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Failed to allocate device input memory: " .LC2: .string "Failed to allocate device output memory: " .LC3: .string "Failed to copy input data to device: " .LC4: .string "Kernel launch failed: " .LC5: .string "Failed to copy output data to host: " .LC6: .string "Stencil computation completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6832: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $16384, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $16384, %edi movq %rax, %rbx call _Znam@PLT movss .LC0(%rip), %xmm0 movq %rax, %rbp xorl %eax, %eax .L10: movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $4096, %rax jne .L10 movl $16384, %esi movq %rsp, %rdi call cudaMalloc@PLT leaq .LC1(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L22 leaq 8(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi .L22: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L9 .L13: movq (%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $16384, %edx call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L22 xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movl $1, %esi movabsq $68719476752, %rdx movabsq $17179869188, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z32__device_stub__Z10stencil64DPfS_PfS_ .L16: call cudaGetLastError@PLT leaq .LC4(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L22 movq 8(%rsp), %rsi movl $2, %ecx movl $16384, %edx movq %rbp, %rdi call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L22 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 xorl %eax, %eax .L9: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L19 call __stack_chk_fail@PLT .L19: addq $48, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6832: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z10stencil64DPfS_" .LC8: .string "_ZN50_INTERNAL_953b3398_19_cuda_code_040587_cu_e9dcdb644cuda3std3__419piecewise_constructE" .LC9: .string "_ZN50_INTERNAL_953b3398_19_cuda_code_040587_cu_e9dcdb644cuda3std6ranges3__45__cpo4swapE" .LC10: .string "_ZN50_INTERNAL_953b3398_19_cuda_code_040587_cu_e9dcdb644cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6860: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z10stencil64DPfS_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC8(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC9(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6860: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_040587.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z25__device_stub__stencil64DPfS_ # -- Begin function _Z25__device_stub__stencil64DPfS_ .type _Z25__device_stub__stencil64DPfS_,@function _Z25__device_stub__stencil64DPfS_: # @_Z25__device_stub__stencil64DPfS_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 16(%rsp), %rcx movq %rsi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 8(%rsp), %r12 movq %rsp, %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z10stencil64DPfS_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z25__device_stub__stencil64DPfS_, .Lfunc_end0-_Z25__device_stub__stencil64DPfS_ .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $16, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl $16384, %edi # imm = 0x4000 callq _Znam movq %rax, %rbx movl $16384, %edi # imm = 0x4000 callq _Znam movq %rax, %r14 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB1_4 # %bb.3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $40, %edx jmp .LBB1_12 .LBB1_4: movq %rsp, %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB1_6 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $41, %edx jmp .LBB1_12 .LBB1_6: movq 8(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_8 # %bb.7: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $37, %edx jmp .LBB1_12 .LBB1_8: movabsq $17179869188, %rdi # imm = 0x400000004 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_10 # %bb.9: movq 8(%rsp), %rdi movq (%rsp), %rsi callq _Z25__device_stub__stencil64DPfS_ .LBB1_10: callq hipGetLastError testl %eax, %eax je .LBB1_18 # %bb.11: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $22, %edx .LBB1_12: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_14 # %bb.13: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_15 .LBB1_14: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_16: movl $-1, %eax .LBB1_17: addq $16, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_18: .cfi_def_cfa_offset 48 movq (%rsp), %rsi movl $16384, %edx # imm = 0x4000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_20 # %bb.19: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $36, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_16 .LBB1_20: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $43, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %eax, %eax jmp .LBB1_17 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10stencil64DPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10stencil64DPfS_,@object # @_Z10stencil64DPfS_ .section .rodata,"a",@progbits .globl _Z10stencil64DPfS_ .p2align 3, 0x0 _Z10stencil64DPfS_: .quad _Z25__device_stub__stencil64DPfS_ .size _Z10stencil64DPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device input memory: " .size .L.str, 41 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate device output memory: " .size .L.str.1, 42 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to copy input data to device: " .size .L.str.2, 38 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Kernel launch failed: " .size .L.str.3, 23 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to copy output data to host: " .size .L.str.4, 37 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Stencil computation completed successfully." .size .L.str.5, 44 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10stencil64DPfS_" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__stencil64DPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10stencil64DPfS_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,586
4,460
113,470
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z21clothSimulationKernelPfS_S_f .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B0, 0x170 ; S2R R8, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R8 ; ISETP.GE.AND P0, PT, R3, 0x100, PT ; IMAD R0, R0, c[0x0][0x0], R5 ; LEA R8, R8, R5, 0x4 ; ISETP.LT.AND P0, PT, R0, 0x100, !P0 ; LEA R0, R3, R0, 0x8 ; SHF.R.S32.HI R11, RZ, 0x1f, R0 ; IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; @!P0 BRA 0x160 ; LDG.E R7, [R2.64] ; LDG.E R9, [R4.64] ; STS [R8.X4], R7 ; STS [R8.X4+0x400], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 EXIT ; LEA R6, P0, R0.reuse, c[0x0][0x170], 0x2 ; LDS R9, [R8.X4+0x400] ; LEA.HI.X R7, R0, c[0x0][0x174], R11, 0x2, P0 ; LDS R0, [R8.X4] ; LDG.E R6, [R6.64] ; FFMA R9, R6, c[0x0][0x178], R9 ; FFMA R11, R9, c[0x0][0x178], R0 ; STG.E [R4.64], R9 ; STG.E [R2.64], R11 ; EXIT ; BRA 0x230; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21clothSimulationKernelPfS_S_f ; -- Begin function _Z21clothSimulationKernelPfS_S_f .globl _Z21clothSimulationKernelPfS_S_f .p2align 8 .type _Z21clothSimulationKernelPfS_S_f,@function _Z21clothSimulationKernelPfS_S_f: ; @_Z21clothSimulationKernelPfS_S_f ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b128 s[4:7], s[0:1], 0x0 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2] v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1] v_lshlrev_b32_e32 v0, 4, v0 v_max_i32_e32 v4, v2, v3 v_lshl_add_u32 v2, v3, 8, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, 0x100, v4 v_ashrrev_i32_e32 v3, 31, v2 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[2:3] v_add_co_u32 v6, s2, s4, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v7, s2, s5, v5, s2 v_add_co_u32 v4, s2, s6, v4 v_add_co_ci_u32_e64 v5, s2, s7, v5, s2 global_load_b32 v6, v[6:7], off global_load_b32 v4, v[4:5], off v_add_lshl_u32 v5, v0, v1, 2 s_waitcnt vmcnt(0) ds_store_2addr_stride64_b32 v5, v6, v4 offset1:4 .LBB0_2: s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_4 ; %bb.3: s_load_b64 s[2:3], s[0:1], 0x10 v_lshlrev_b64 v[2:3], 2, v[2:3] v_add_lshl_u32 v0, v0, v1, 2 s_load_b32 s0, s[0:1], 0x18 ds_load_2addr_stride64_b32 v[0:1], v0 offset1:4 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo global_load_b32 v4, v[4:5], off s_waitcnt vmcnt(0) v_fma_f32 v6, s0, v4, v1 v_add_co_u32 v4, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v1, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_4) v_fmac_f32_e32 v0, s0, v6 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v3, vcc_lo global_store_b32 v[4:5], v6, off global_store_b32 v[1:2], v0, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21clothSimulationKernelPfS_S_f .amdhsa_group_segment_fixed_size 2048 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21clothSimulationKernelPfS_S_f, .Lfunc_end0-_Z21clothSimulationKernelPfS_S_f ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 360 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 2048 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 2048 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21clothSimulationKernelPfS_S_f .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21clothSimulationKernelPfS_S_f.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000108b7_00000000-6_cuda_code_081467.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3635: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3635: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f .type _Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f, @function _Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f: .LFB3661: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 48(%rsp), %rcx leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movss %xmm0, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z21clothSimulationKernelPfS_S_f(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L8: movq 136(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f, .-_Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f .globl _Z21clothSimulationKernelPfS_S_f .type _Z21clothSimulationKernelPfS_S_f, @function _Z21clothSimulationKernelPfS_S_f: .LFB3662: .cfi_startproc endbr64 jmp _Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f .cfi_endproc .LFE3662: .size _Z21clothSimulationKernelPfS_S_f, .-_Z21clothSimulationKernelPfS_S_f .section .rodata.str1.1 .LC3: .string "Failed to allocate d_positions" .LC4: .string "Failed to allocate d_velocities" .LC5: .string "Failed to allocate d_forces" .LC6: .string "Failed to copy h_positions to d_positions" .LC7: .string "Failed to copy h_velocities to d_velocities" .LC8: .string "Failed to copy h_forces to d_forces" .LC10: .string "Kernel launch failed" .LC11: .string "Failed to copy d_positions to h_positions" .LC12: .string "Failed to copy d_velocities to h_velocities" .LC13: .string "Cloth simulation completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 movl $262144, %edi pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $262144, %edi movq %rax, %rbp call _Znam@PLT movl $262144, %edi movq %rax, %rbx call _Znam@PLT movl $65536, %ecx movq %rbp, %rdi movl $262144, %esi movq %rax, %r12 xorl %eax, %eax rep stosl movl $65536, %ecx movq %rbx, %rdi rep stosl movl $65536, %ecx movq %r12, %rdi rep stosl leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 16(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 24(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $262144, %edx call cudaMemcpy@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $262144, %edx call cudaMemcpy@PLT leaq .LC7(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $262144, %edx call cudaMemcpy@PLT leaq .LC8(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movabsq $68719476752, %rdi movl $1, %esi movq %rdi, %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L14 movss .LC9(%rip), %xmm0 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z46__device_stub__Z21clothSimulationKernelPfS_S_fPfS_S_f .L14: call cudaGetLastError@PLT leaq .LC10(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rsi movl $2, %ecx movq %rbp, %rdi movl $262144, %edx call cudaMemcpy@PLT leaq .LC11(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rsi movl $2, %ecx movq %rbx, %rdi movl $262144, %edx call cudaMemcpy@PLT leaq .LC12(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT leaq _ZSt4cout(%rip), %rdi leaq .LC13(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 56(%rsp), %rax subq %fs:40, %rax je .L15 call __stack_chk_fail@PLT .L15: addq $64, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC14: .string "_Z21clothSimulationKernelPfS_S_f" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rax, %rdi leaq _Z21clothSimulationKernelPfS_S_f(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC9: .long 1008981770 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_081467.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z36__device_stub__clothSimulationKernelPfS_S_f # -- Begin function _Z36__device_stub__clothSimulationKernelPfS_S_f .type _Z36__device_stub__clothSimulationKernelPfS_S_f,@function _Z36__device_stub__clothSimulationKernelPfS_S_f: # @_Z36__device_stub__clothSimulationKernelPfS_S_f .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movss %xmm0, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z21clothSimulationKernelPfS_S_f, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z36__device_stub__clothSimulationKernelPfS_S_f, .Lfunc_end0-_Z36__device_stub__clothSimulationKernelPfS_S_f .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x3c23d70a # float 0.00999999977 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %rbx movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %r14 movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %r15 movl $262144, %edx # imm = 0x40000 movq %rbx, %rdi xorl %esi, %esi callq memset@PLT movl $262144, %edx # imm = 0x40000 movq %r14, %rdi xorl %esi, %esi callq memset@PLT movl $262144, %edx # imm = 0x40000 movq %r15, %rdi xorl %esi, %esi callq memset@PLT leaq 8(%rsp), %rbp movl $262144, %esi # imm = 0x40000 movq %rbp, %rdi callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rsp, %r13 movl $262144, %esi # imm = 0x40000 movq %r13, %rdi callq hipMalloc movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 16(%rsp), %r12 movl $262144, %esi # imm = 0x40000 movq %r12, %rdi callq hipMalloc movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rbp), %rdi movl $262144, %edx # imm = 0x40000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r13), %rdi movl $262144, %edx # imm = 0x40000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r12), %rdi movl $262144, %edx # imm = 0x40000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $68719476752, %rdi # imm = 0x1000000010 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movq 8(%rsp), %rdi movq (%rsp), %rsi movq 16(%rsp), %rdx movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero callq _Z36__device_stub__clothSimulationKernelPfS_S_f .LBB2_2: callq hipGetLastError movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rsi movl $262144, %edx # imm = 0x40000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.10, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rsi movl $262144, %edx # imm = 0x40000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.11, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $40, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21clothSimulationKernelPfS_S_f, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z21clothSimulationKernelPfS_S_f,@object # @_Z21clothSimulationKernelPfS_S_f .section .rodata,"a",@progbits .globl _Z21clothSimulationKernelPfS_S_f .p2align 3, 0x0 _Z21clothSimulationKernelPfS_S_f: .quad _Z36__device_stub__clothSimulationKernelPfS_S_f .size _Z21clothSimulationKernelPfS_S_f, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate d_positions" .size .L.str.3, 31 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate d_velocities" .size .L.str.4, 32 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to allocate d_forces" .size .L.str.5, 28 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy h_positions to d_positions" .size .L.str.6, 42 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to copy h_velocities to d_velocities" .size .L.str.7, 44 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Failed to copy h_forces to d_forces" .size .L.str.8, 36 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Kernel launch failed" .size .L.str.9, 21 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Failed to copy d_positions to h_positions" .size .L.str.10, 42 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Failed to copy d_velocities to h_velocities" .size .L.str.11, 44 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "Cloth simulation completed successfully." .size .L.str.12, 41 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z21clothSimulationKernelPfS_S_f" .size .L__unnamed_1, 33 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__clothSimulationKernelPfS_S_f .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21clothSimulationKernelPfS_S_f .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z14insertSkipListP4NodeiPii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR8, c[0x0][0x118] ; BSSY B0, 0x150 ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; @P0 BRA 0x140 ; IMAD.MOV.U32 R3, RZ, RZ, 0x18 ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; LDG.E R5, [R2.64+0x4] ; LDG.E R4, [R2.64] ; LDG.E R9, [R2.64+0xc] ; LDG.E R8, [R2.64+0x8] ; LDG.E R11, [R2.64+0x14] ; LDG.E R10, [R2.64+0x10] ; IMAD R6, R0, 0x18, RZ ; STS.64 [R6], R4 ; STS.64 [R6+0x8], R8 ; STS.64 [R6+0x10], R10 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; BSSY B0, 0x550 ; @P0 BRA 0x540 ; LDS R0, [0x8] ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @!P1 BRA 0x270 ; HFMA2.MMA R5, -RZ, RZ, 0, 0 ; IMAD R3, R0, 0x18, RZ ; LDS R2, [R3] ; ISETP.GE.AND P1, PT, R2, c[0x0][0x168], PT ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; @P1 BRA 0x270 ; LDS R0, [R3+0x8] ; IMAD.MOV.U32 R5, RZ, RZ, R2 ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @P1 BRA 0x1e0 ; IMAD R0, R5, 0x18, RZ ; MOV R2, c[0x0][0x170] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; LDS R0, [R0+0xc] ; STG.E [R2.64], R5 ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @!P1 BRA 0x370 ; IMAD R6, R0, 0x18, RZ ; LDS R4, [R6] ; ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; @P1 BRA 0x370 ; LDS R0, [R6+0xc] ; MOV R5, R4 ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @P1 BRA 0x2e0 ; IMAD R0, R5, 0x18, RZ ; STG.E [R2.64+0x4], R5 ; LDS R0, [R0+0x10] ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @!P1 BRA 0x450 ; IMAD R6, R0, 0x18, RZ ; LDS R4, [R6] ; ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; @P1 BRA 0x450 ; LDS R0, [R6+0x10] ; IMAD.MOV.U32 R5, RZ, RZ, R4 ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @P1 BRA 0x3c0 ; IMAD R0, R5, 0x18, RZ ; STG.E [R2.64+0x8], R5 ; LDS R0, [R0+0x14] ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @!P1 BRA 0x530 ; IMAD R6, R0, 0x18, RZ ; LDS R4, [R6] ; ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; MOV R4, R0 ; @P1 BRA 0x530 ; LDS R0, [R6+0x14] ; IMAD.MOV.U32 R5, RZ, RZ, R4 ; ISETP.NE.AND P1, PT, R0, -0x1, PT ; @P1 BRA 0x4a0 ; STG.E [R2.64+0xc], R5 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; MOV R3, c[0x0][0x174] ; LDG.E R0, [R2.64] ; LDG.E R4, [R2.64+0x4] ; LDG.E R5, [R2.64+0x8] ; LDG.E R6, [R2.64+0xc] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x178] ; ISETP.GE.AND P0, PT, R7, 0x1, PT ; IMAD R0, R0, 0x18, RZ ; IMAD R4, R4, 0x18, RZ ; STS [R0+0x8], RZ ; IMAD R5, R5, 0x18, RZ ; STS [R4+0xc], RZ ; IMAD R6, R6, 0x18, RZ ; STS [R5+0x10], RZ ; STS [R6+0x14], RZ ; @!P0 EXIT ; IADD3 R2, R7.reuse, -0x1, RZ ; UMOV UR4, URZ ; LOP3.LUT R0, R7, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P1 BRA 0x9a0 ; IADD3 R28, -R0, c[0x0][0x178], RZ ; IMAD.MOV.U32 R29, RZ, RZ, c[0x0][0x160] ; MOV R24, c[0x0][0x164] ; UMOV UR4, URZ ; UMOV UR5, URZ ; IMAD.MOV.U32 R3, RZ, RZ, R24 ; LDS.128 R20, [UR5] ; IMAD.MOV.U32 R2, RZ, RZ, R29 ; IADD3 R28, R28, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; LDS.128 R16, [UR5+0x10] ; ISETP.NE.AND P1, PT, R28, RZ, PT ; LDS.128 R12, [UR5+0x20] ; IADD3 R29, P2, R2, 0x60, RZ ; LDS.128 R8, [UR5+0x30] ; LDS.128 R4, [UR5+0x40] ; LDS.128 R24, [UR5+0x50] ; UIADD3 UR5, UR5, 0x60, URZ ; STG.E [R2.64], R20 ; STG.E [R2.64+0x4], R21 ; STG.E [R2.64+0x8], R22 ; STG.E [R2.64+0xc], R23 ; STG.E [R2.64+0x10], R16 ; STG.E [R2.64+0x14], R17 ; STG.E [R2.64+0x18], R18 ; STG.E [R2.64+0x1c], R19 ; STG.E [R2.64+0x20], R12 ; STG.E [R2.64+0x24], R13 ; STG.E [R2.64+0x28], R14 ; STG.E [R2.64+0x2c], R15 ; STG.E [R2.64+0x30], R8 ; STG.E [R2.64+0x34], R9 ; STG.E [R2.64+0x38], R10 ; STG.E [R2.64+0x3c], R11 ; STG.E [R2.64+0x40], R4 ; STG.E [R2.64+0x44], R5 ; STG.E [R2.64+0x48], R6 ; STG.E [R2.64+0x4c], R7 ; STG.E [R2.64+0x54], R25 ; STG.E [R2.64+0x58], R26 ; STG.E [R2.64+0x5c], R27 ; STG.E [R2.64+0x50], R24 ; IADD3.X R24, RZ, R3, RZ, P2, !PT ; @P1 BRA 0x730 ; @!P0 EXIT ; UMOV UR5, 0x18 ; ULDC.64 UR6, c[0x0][0x160] ; UIMAD.WIDE UR6, UR4, UR5, UR6 ; UIMAD UR4, UR4, UR5, 0x10 ; UIADD3 UR10, UP0, UR6, 0xc, URZ ; UIADD3.X UR6, URZ, UR7, URZ, UP0, !UPT ; IMAD.U32 R10, RZ, RZ, UR10 ; IMAD.U32 R11, RZ, RZ, UR6 ; LDS.64 R4, [UR4+-0x8] ; MOV R2, R10 ; IMAD.MOV.U32 R3, RZ, RZ, R11 ; IADD3 R0, R0, -0x1, RZ ; LDS.64 R6, [UR4] ; IADD3 R10, P1, R2, 0x18, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; LDS.64 R8, [UR4+-0x10] ; UIADD3 UR4, UR4, 0x18, URZ ; IADD3.X R11, RZ, R3, RZ, P1, !PT ; STG.E [R2.64+-0x4], R4 ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R6 ; STG.E [R2.64+0x8], R7 ; STG.E [R2.64+-0xc], R8 ; STG.E [R2.64+-0x8], R9 ; @P0 BRA 0xa30 ; EXIT ; BRA 0xb50; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z12initSkipListP4Nodei .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; @P0 EXIT ; HFMA2.MMA R2, -RZ, RZ, 0, 1.430511474609375e-06 ; MOV R7, 0x1 ; ULDC.64 UR4, c[0x0][0x118] ; MOV R9, 0xffffffff ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R7 ; STG.E [R2.64+0x8], R9 ; STG.E [R2.64+0xc], R9 ; STG.E [R2.64+0x10], R9 ; STG.E [R2.64+0x14], R9 ; EXIT ; BRA 0x120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12initSkipListP4Nodei ; -- Begin function _Z12initSkipListP4Nodei .globl _Z12initSkipListP4Nodei .p2align 8 .type _Z12initSkipListP4Nodei,@function _Z12initSkipListP4Nodei: ; @_Z12initSkipListP4Nodei ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: ; %.loopexit.loopexit s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v3, -1 :: v_dual_mov_b32 v2, 1 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v4, v3 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[5:6], null, v1, 24, s[0:1] s_clause 0x1 global_store_b128 v[5:6], v[1:4], off global_store_b64 v[5:6], v[3:4], off offset:16 .LBB0_2: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12initSkipListP4Nodei .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12initSkipListP4Nodei, .Lfunc_end0-_Z12initSkipListP4Nodei ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 128 ; NumSgprs: 16 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 16 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z14insertSkipListP4NodeiPii ; -- Begin function _Z14insertSkipListP4NodeiPii .globl _Z14insertSkipListP4NodeiPii .p2align 8 .type _Z14insertSkipListP4NodeiPii,@function _Z14insertSkipListP4NodeiPii: ; @_Z14insertSkipListP4NodeiPii ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_load_b64 s[4:5], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB1_2 ; %bb.1: v_mad_i64_i32 v[6:7], null, v1, 24, s[4:5] s_mov_b32 s6, 0 s_clause 0x1 global_load_b128 v[2:5], v[6:7], off offset:8 global_load_b128 v[6:9], v[6:7], off v_mad_u64_u32 v[10:11], null, v1, 24, s[6:7] s_waitcnt vmcnt(1) ds_store_2addr_b32 v10, v4, v5 offset0:4 offset1:5 ds_store_2addr_b32 v10, v2, v3 offset0:2 offset1:3 s_waitcnt vmcnt(0) ds_store_2addr_b32 v10, v8, v9 offset0:2 offset1:3 ds_store_2addr_b32 v10, v6, v7 offset1:1 .LBB1_2: s_or_b32 exec_lo, exec_lo, s2 s_load_b64 s[6:7], s[0:1], 0x10 v_cmp_eq_u32_e64 s2, 0, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_saveexec_b32 s8, s2 s_cbranch_execz .LBB1_10 ; %bb.3: ; %.outer.preheader s_load_b32 s9, s[0:1], 0x8 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 s_add_u32 s10, s6, -4 s_addc_u32 s11, s7, -1 s_mov_b32 s0, 1 .LBB1_4: ; %.outer ; =>This Loop Header: Depth=1 ; Child Loop BB1_5 Depth 2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_mov_b32_e32 v2, v1 s_add_i32 s1, s0, -1 s_lshl_b32 s1, s1, 2 .LBB1_5: ; Parent Loop BB1_4 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v1, v2 v_mul_lo_u32 v2, v1, 24 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, 0, v2 v_add_nc_u32_e32 v2, s1, v2 ds_load_b32 v2, v2 offset:8 s_waitcnt lgkmcnt(0) v_cmp_eq_u32_e32 vcc_lo, -1, v2 s_cbranch_vccnz .LBB1_7 ; %bb.6: ; in Loop: Header=BB1_5 Depth=2 v_mul_lo_u32 v3, v2, 24 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v3, 0, v3 ds_load_b32 v3, v3 s_waitcnt lgkmcnt(0) v_cmp_le_i32_e64 s12, s9, v3 s_branch .LBB1_8 .LBB1_7: ; in Loop: Header=BB1_5 Depth=2 s_mov_b32 s12, -1 ; implicit-def: $vgpr2 .LBB1_8: ; %Flow71 ; in Loop: Header=BB1_5 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s12 s_cbranch_vccnz .LBB1_5 ; %bb.9: ; %.critedge ; in Loop: Header=BB1_4 Depth=1 s_ashr_i32 s1, s0, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[12:13], s[0:1], 2 s_add_u32 s12, s10, s12 s_addc_u32 s13, s11, s13 s_add_i32 s0, s0, 1 global_store_b32 v0, v1, s[12:13] s_cmp_lg_u32 s0, 5 s_cbranch_scc1 .LBB1_4 .LBB1_10: ; %Flow73 s_or_b32 exec_lo, exec_lo, s8 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_and_saveexec_b32 s0, s2 s_cbranch_execz .LBB1_16 ; %bb.11: ; %.preheader45.preheader v_mov_b32_e32 v0, 0 s_add_i32 s2, 0, 8 s_mov_b64 s[0:1], 0 .LBB1_12: ; %.preheader45 ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s8, s6, s0 s_addc_u32 s9, s7, s1 s_add_u32 s0, s0, 4 global_load_b32 v1, v0, s[8:9] s_addc_u32 s1, s1, 0 s_waitcnt vmcnt(0) v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v1, s2, v1 s_add_i32 s2, s2, 4 s_cmp_eq_u32 s0, 16 ds_store_b32 v1, v0 s_cbranch_scc0 .LBB1_12 ; %bb.13: ; %.preheader s_cmp_lt_i32 s3, 1 s_cbranch_scc1 .LBB1_16 ; %bb.14: ; %.lr.ph.preheader v_mov_b32_e32 v0, 0 s_mov_b32 s0, 0 .LBB1_15: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v5, s0 s_add_i32 s3, s3, -1 ds_load_2addr_b32 v[1:2], v5 offset0:2 offset1:3 ds_load_2addr_b32 v[3:4], v5 offset0:4 offset1:5 ds_load_2addr_b32 v[5:6], v5 offset1:1 s_waitcnt lgkmcnt(2) v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v7, v1 s_waitcnt lgkmcnt(1) global_store_b128 v0, v[1:4], s[4:5] offset:8 s_waitcnt lgkmcnt(0) global_store_b128 v0, v[5:8], s[4:5] s_add_u32 s4, s4, 24 s_addc_u32 s5, s5, 0 s_add_i32 s0, s0, 24 s_cmp_lg_u32 s3, 0 s_cbranch_scc1 .LBB1_15 .LBB1_16: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14insertSkipListP4NodeiPii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z14insertSkipListP4NodeiPii, .Lfunc_end1-_Z14insertSkipListP4NodeiPii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 608 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12initSkipListP4Nodei .private_segment_fixed_size: 0 .sgpr_count: 16 .sgpr_spill_count: 0 .symbol: _Z12initSkipListP4Nodei.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14insertSkipListP4NodeiPii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14insertSkipListP4NodeiPii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000d17e9_00000000-6_cuda_code_004103.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3852: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3852: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .type _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei, @function _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei: .LFB3874: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z12initSkipListP4Nodei(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L2: movq 104(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3874: .size _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei, .-_Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .globl _Z12initSkipListP4Nodei .type _Z12initSkipListP4Nodei, @function _Z12initSkipListP4Nodei: .LFB3875: .cfi_startproc endbr64 jmp _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .cfi_endproc .LFE3875: .size _Z12initSkipListP4Nodei, .-_Z12initSkipListP4Nodei .globl _Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii .type _Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii, @function _Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii: .LFB3876: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movl %esi, 20(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 16(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z14insertSkipListP4NodeiPii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L8: movq 136(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3876: .size _Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii, .-_Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii .globl _Z14insertSkipListP4NodeiPii .type _Z14insertSkipListP4NodeiPii, @function _Z14insertSkipListP4NodeiPii: .LFB3877: .cfi_startproc endbr64 jmp _Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii .cfi_endproc .LFE3877: .size _Z14insertSkipListP4NodeiPii, .-_Z14insertSkipListP4NodeiPii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3849: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movl $3072, %esi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $56, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movq %rsp, %rdi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT movl $33554433, %edx xorl %r9d, %r9d xorl %r8d, %r8d salq $7, %rdx movl $1, %ecx movabsq $4294967297, %rdi movl $1, %esi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L14 movq (%rsp), %rdi movl $128, %esi call _Z37__device_stub__Z12initSkipListP4NodeiP4Nodei .L14: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax jne .L22 movl $33554433, %edx xorl %r9d, %r9d movl $1, %ecx movabsq $4294967297, %rdi salq $7, %rdx movl $3072, %r8d movl $1, %esi movl $1, 36(%rsp) movq %rdx, 28(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L17 movq 8(%rsp), %rdx movq (%rsp), %rdi movl $128, %ecx movl $64, %esi call _Z42__device_stub__Z14insertSkipListP4NodeiPiiP4NodeiPii .L17: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L18 .L22: leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L13 .L18: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L13: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L20 call __stack_chk_fail@PLT .L20: addq $56, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3849: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z14insertSkipListP4NodeiPii" .LC2: .string "_Z12initSkipListP4Nodei" .LC3: .string "precalc_xorwow_matrix" .LC4: .string "precalc_xorwow_offset_matrix" .LC5: .string "mrg32k3aM1" .LC6: .string "mrg32k3aM2" .LC7: .string "mrg32k3aM1SubSeq" .LC8: .string "mrg32k3aM2SubSeq" .LC9: .string "mrg32k3aM1Seq" .LC10: .string "mrg32k3aM2Seq" .LC11: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3879: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC1(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z14insertSkipListP4NodeiPii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC2(%rip), %rdx orl $-1, %r8d leaq _Z12initSkipListP4Nodei(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC3(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC4(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC5(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC7(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC9(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3879: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_004103.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z27__device_stub__initSkipListP4Nodei # -- Begin function _Z27__device_stub__initSkipListP4Nodei .type _Z27__device_stub__initSkipListP4Nodei,@function _Z27__device_stub__initSkipListP4Nodei: # @_Z27__device_stub__initSkipListP4Nodei .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z12initSkipListP4Nodei, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z27__device_stub__initSkipListP4Nodei, .Lfunc_end0-_Z27__device_stub__initSkipListP4Nodei .cfi_endproc # -- End function .globl _Z29__device_stub__insertSkipListP4NodeiPii # -- Begin function _Z29__device_stub__insertSkipListP4NodeiPii .type _Z29__device_stub__insertSkipListP4NodeiPii,@function _Z29__device_stub__insertSkipListP4NodeiPii: # @_Z29__device_stub__insertSkipListP4NodeiPii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 12(%rsp), %rdi movl %esi, (%rdi) leaq 32(%rsp), %rsi movq %rdx, (%rsi) leaq 8(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z14insertSkipListP4NodeiPii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z29__device_stub__insertSkipListP4NodeiPii, .Lfunc_end1-_Z29__device_stub__insertSkipListP4NodeiPii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $16, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movabsq $4294967297, %rbx # imm = 0x100000001 movq %rsp, %rdi movl $3072, %esi # imm = 0xC00 callq hipMalloc leaq 8(%rsp), %rdi movl $16, %esi callq hipMalloc leaq 127(%rbx), %r14 movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movq (%rsp), %rdi movl $128, %esi callq _Z27__device_stub__initSkipListP4Nodei .LBB2_2: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB2_8 # %bb.3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi jmp .LBB2_4 .LBB2_8: movl $3072, %r8d # imm = 0xC00 movq %rbx, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_10 # %bb.9: movq (%rsp), %rdi movq 8(%rsp), %rdx movl $64, %esi movl $128, %ecx callq _Z29__device_stub__insertSkipListP4NodeiPii .LBB2_10: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB2_12 # %bb.11: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi .LBB2_4: callq hipGetErrorString testq %rax, %rax je .LBB2_5 # %bb.6: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_7 .LBB2_5: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB2_13: addq $16, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_12: .cfi_def_cfa_offset 48 movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB2_13 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12initSkipListP4Nodei, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14insertSkipListP4NodeiPii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z12initSkipListP4Nodei,@object # @_Z12initSkipListP4Nodei .section .rodata,"a",@progbits .globl _Z12initSkipListP4Nodei .p2align 3, 0x0 _Z12initSkipListP4Nodei: .quad _Z27__device_stub__initSkipListP4Nodei .size _Z12initSkipListP4Nodei, 8 .type _Z14insertSkipListP4NodeiPii,@object # @_Z14insertSkipListP4NodeiPii .globl _Z14insertSkipListP4NodeiPii .p2align 3, 0x0 _Z14insertSkipListP4NodeiPii: .quad _Z29__device_stub__insertSkipListP4NodeiPii .size _Z14insertSkipListP4NodeiPii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12initSkipListP4Nodei" .size .L__unnamed_1, 24 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z14insertSkipListP4NodeiPii" .size .L__unnamed_2, 29 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__initSkipListP4Nodei .addrsig_sym _Z29__device_stub__insertSkipListP4NodeiPii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12initSkipListP4Nodei .addrsig_sym _Z14insertSkipListP4NodeiPii .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
6,096
4,819
113,476
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z18crossProductKernelP6float3S0_S0_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; HFMA2.MMA R15, -RZ, RZ, 0, 7.152557373046875e-07 ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B0, 0x1a0 ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; IMAD R6, R3, 0xc, RZ ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; IMAD R7, R15, c[0x0][0x0], R6 ; @P0 BRA 0x190 ; IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; IMAD.WIDE R4, R0, R15, c[0x0][0x168] ; LDG.E R9, [R2.64] ; LDG.E R11, [R2.64+0x4] ; LDG.E R13, [R2.64+0x8] ; LDG.E R8, [R4.64] ; LDG.E R10, [R4.64+0x4] ; LDG.E R12, [R4.64+0x8] ; STS [R6], R9 ; STS [R6+0x4], R11 ; STS [R6+0x8], R13 ; STS [R7], R8 ; STS [R7+0x4], R10 ; STS [R7+0x8], R12 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; LDS R4, [R7] ; LDS R8, [R6+0x4] ; LDS R5, [R7+0x8] ; LDS R3, [R7+0x4] ; LDS R9, [R6+0x8] ; LDS R2, [R6] ; FMUL R12, R4, R8 ; FMUL R10, R3, R9 ; FMUL R11, R2.reuse, R5 ; FFMA R13, R2, R3, -R12 ; IMAD.WIDE R2, R0, R15, c[0x0][0x170] ; FFMA R5, R5, R8, -R10 ; STG.E [R2.64+0x8], R13 ; FFMA R11, R4, R9, -R11 ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R11 ; EXIT ; BRA 0x2d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i ; -- Begin function _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .globl _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .p2align 8 .type _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i,@function _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i: ; @_Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i ; %bb.0: s_clause 0x3 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_mad_u32_u24 v2, v0, 12, 0 v_cmp_gt_i32_e32 vcc_lo, s3, v1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: v_mad_i64_i32 v[3:4], null, v1, 12, s[4:5] v_mad_i64_i32 v[6:7], null, v1, 12, s[6:7] v_add_nc_u32_e32 v0, s2, v0 global_load_b96 v[3:5], v[3:4], off global_load_b96 v[6:8], v[6:7], off v_mad_u32_u24 v0, v0, 12, 0 s_waitcnt vmcnt(1) ds_store_2addr_b32 v2, v3, v4 offset1:1 ds_store_b32 v2, v5 offset:8 s_waitcnt vmcnt(0) ds_store_2addr_b32 v0, v6, v7 offset1:1 ds_store_b32 v0, v8 offset:8 .LBB0_2: s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_4 ; %bb.3: v_mad_u64_u32 v[3:4], null, s2, 12, v[2:3] v_mad_i64_i32 v[8:9], null, v1, 12, s[0:1] ds_load_b32 v10, v2 offset:8 ds_load_2addr_b32 v[4:5], v3 offset1:1 ds_load_2addr_b32 v[6:7], v2 offset1:1 ds_load_b32 v0, v3 offset:8 s_waitcnt lgkmcnt(1) v_dual_mul_f32 v2, v10, v5 :: v_dual_mul_f32 v11, v7, v4 s_waitcnt lgkmcnt(0) v_mul_f32_e32 v3, v6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v0, v7, v0, -v2 v_fma_f32 v2, v6, v5, -v11 s_delay_alu instid0(VALU_DEP_3) v_fma_f32 v1, v10, v4, -v3 global_store_b96 v[8:9], v[0:2], off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i, .Lfunc_end0-_Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 312 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 152 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
808
3,089
113,477
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0003a4c6_00000000-6_cuda_code_005359.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4292: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4292: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i .type _Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i, @function _Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i: .LFB3660: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z18crossProductKernelP6float3S0_S0_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L3: movq 136(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i, .-_Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i .globl _Z18crossProductKernelP6float3S0_S0_i .type _Z18crossProductKernelP6float3S0_S0_i, @function _Z18crossProductKernelP6float3S0_S0_i: .LFB3661: .cfi_startproc endbr64 jmp _Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i .cfi_endproc .LFE3661: .size _Z18crossProductKernelP6float3S0_S0_i, .-_Z18crossProductKernelP6float3S0_S0_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate device memory for d_a" .LC1: .string "Failed to allocate device memory for d_b" .LC2: .string "Failed to allocate device memory for d_result" .LC3: .string "Failed to copy data from host to device for d_a" .LC4: .string "Failed to copy data from host to device for d_b" .LC5: .string "Kernel launch failed: " .LC6: .string "Failed to copy data from device to host" .LC7: .string "Cross product computation failed!" .LC8: .string "Cross product computation successful!" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $24576, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $72, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $24576, %edi movq %rax, %rbp call _Znam@PLT movl $24576, %edi movq %rax, %rbx call _Znam@PLT xorl %ecx, %ecx movq %rax, %r12 xorl %eax, %eax .L10: movl %ecx, %edx incl %ecx cvtsi2ssl %edx, %xmm0 leal 2(%rdx), %esi movss %xmm0, 0(%rbp,%rax) cvtsi2ssl %ecx, %xmm0 movss %xmm0, 4(%rbp,%rax) cvtsi2ssl %esi, %xmm0 leal 3(%rdx), %esi movss %xmm0, 8(%rbp,%rax) cvtsi2ssl %esi, %xmm0 leal 4(%rdx), %esi addl $5, %edx movss %xmm0, (%rbx,%rax) cvtsi2ssl %esi, %xmm0 movss %xmm0, 4(%rbx,%rax) cvtsi2ssl %edx, %xmm0 movss %xmm0, 8(%rbx,%rax) addq $12, %rax cmpl $2048, %ecx jne .L10 movl $24576, %esi leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq .LC0(%rip), %rsi testl %eax, %eax jne .L36 leaq 16(%rsp), %rdi movl $24576, %esi call cudaMalloc@PLT testl %eax, %eax je .L13 leaq .LC1(%rip), %rsi .L36: leaq _ZSt4cerr(%rip), %rdi .L37: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L9 .L13: movl $24576, %esi leaq 24(%rsp), %rdi call cudaMalloc@PLT leaq .LC2(%rip), %rsi testl %eax, %eax jne .L36 movq 8(%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $24576, %edx call cudaMemcpy@PLT leaq .LC3(%rip), %rsi testl %eax, %eax jne .L36 movq 16(%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $24576, %edx call cudaMemcpy@PLT leaq .LC4(%rip), %rsi testl %eax, %eax jne .L36 movl $16777217, %edx movl $536870913, %edi xorl %r9d, %r9d movl $6144, %r8d salq $8, %rdx salq $3, %rdi movl $1, %ecx movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $2048, %ecx movq 8(%rsp), %rdi call _Z51__device_stub__Z18crossProductKernelP6float3S0_S0_iP6float3S0_S0_i .L18: call cudaGetLastError@PLT movl %eax, %r13d testl %eax, %eax je .L19 leaq .LC5(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r13d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi jmp .L37 .L19: movq 24(%rsp), %rsi movl $24576, %edx movl $2, %ecx movq %r12, %rdi call cudaMemcpy@PLT leaq .LC6(%rip), %rsi movl %eax, %edx xorl %eax, %eax testl %edx, %edx jne .L36 .L20: movss 8(%rbp,%rax), %xmm2 movss 4(%rbp,%rax), %xmm1 movss 8(%rbx,%rax), %xmm6 movss 4(%rbx,%rax), %xmm5 movss (%rbx,%rax), %xmm3 movaps %xmm2, %xmm4 movss 0(%rbp,%rax), %xmm0 mulss %xmm5, %xmm2 movaps %xmm6, %xmm7 mulss %xmm3, %xmm4 mulss %xmm1, %xmm3 mulss %xmm6, %xmm1 mulss %xmm0, %xmm7 mulss %xmm5, %xmm0 subss %xmm2, %xmm1 ucomiss (%r12,%rax), %xmm1 subss %xmm7, %xmm4 subss %xmm3, %xmm0 jp .L21 jne .L21 ucomiss 4(%r12,%rax), %xmm4 jp .L21 jne .L21 ucomiss 8(%r12,%rax), %xmm0 jp .L21 je .L24 .L21: leaq .LC7(%rip), %rsi jmp .L38 .L24: addq $12, %rax cmpq $24576, %rax jne .L20 leaq .LC8(%rip), %rsi .L38: leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT xorl %eax, %eax .L9: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L27 call __stack_chk_fail@PLT .L27: addq $72, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC9: .string "_Z18crossProductKernelP6float3S0_S0_i" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC9(%rip), %rdx movq %rax, %rdi leaq _Z18crossProductKernelP6float3S0_S0_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_005359.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i # -- Begin function _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .type _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i,@function _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i: # @_Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i, .Lfunc_end0-_Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $24, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $24576, %edi # imm = 0x6000 callq _Znam movq %rax, %rbx movl $24576, %edi # imm = 0x6000 callq _Znam movq %rax, %r14 movl $24576, %edi # imm = 0x6000 callq _Znam movq %rax, %r15 movq $-2048, %rax # imm = 0xF800 movl $8, %ecx .LBB1_1: # =>This Inner Loop Header: Depth=1 leal 2048(%rax), %edx xorps %xmm0, %xmm0 cvtsi2ss %edx, %xmm0 leal 2049(%rax), %edx xorps %xmm1, %xmm1 cvtsi2ss %edx, %xmm1 leal 2050(%rax), %edx xorps %xmm2, %xmm2 cvtsi2ss %edx, %xmm2 unpcklps %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] movlps %xmm0, -8(%rbx,%rcx) movss %xmm2, (%rbx,%rcx) leal 2051(%rax), %edx xorps %xmm0, %xmm0 cvtsi2ss %edx, %xmm0 leal 2052(%rax), %edx xorps %xmm1, %xmm1 cvtsi2ss %edx, %xmm1 unpcklps %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] leal 2053(%rax), %edx xorps %xmm1, %xmm1 cvtsi2ss %edx, %xmm1 movlps %xmm0, -8(%r14,%rcx) movss %xmm1, (%r14,%rcx) addq $12, %rcx incq %rax jne .LBB1_1 # %bb.2: leaq 16(%rsp), %rdi movl $24576, %esi # imm = 0x6000 callq hipMalloc testl %eax, %eax je .LBB1_4 # %bb.3: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi jmp .LBB1_6 .LBB1_4: leaq 8(%rsp), %rdi movl $24576, %esi # imm = 0x6000 callq hipMalloc testl %eax, %eax je .LBB1_10 # %bb.5: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi .LBB1_6: movl $40, %edx .LBB1_7: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_8: movl $-1, %eax .LBB1_9: addq $24, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_10: .cfi_def_cfa_offset 64 movq %rsp, %rdi movl $24576, %esi # imm = 0x6000 callq hipMalloc testl %eax, %eax je .LBB1_12 # %bb.11: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $45, %edx jmp .LBB1_7 .LBB1_12: movq 16(%rsp), %rdi movl $24576, %edx # imm = 0x6000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_14 # %bb.13: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $47, %edx jmp .LBB1_7 .LBB1_14: movq 8(%rsp), %rdi movl $24576, %edx # imm = 0x6000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_17 # %bb.15: movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $47, %edx .LBB1_16: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi jmp .LBB1_21 .LBB1_17: movabsq $4294967304, %rdi # imm = 0x100000008 leaq 248(%rdi), %rdx movl $6144, %r8d # imm = 0x1800 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_19 # %bb.18: movq 16(%rsp), %rdi movq 8(%rsp), %rsi movq (%rsp), %rdx movl $2048, %ecx # imm = 0x800 callq _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .LBB1_19: callq hipGetLastError testl %eax, %eax je .LBB1_22 # %bb.20: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi .LBB1_21: callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_8 .LBB1_22: movq (%rsp), %rsi movl $24576, %edx # imm = 0x6000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_24 # %bb.23: movl $_ZSt4cerr, %edi movl $.L.str.6, %esi movl $39, %edx jmp .LBB1_16 .LBB1_24: # %.preheader.preheader movl $8, %eax .LBB1_25: # %.preheader # =>This Inner Loop Header: Depth=1 movss -4(%rbx,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero movss (%r14,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero movaps %xmm0, %xmm4 mulss %xmm2, %xmm4 movss (%rbx,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero movss -4(%r14,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero movaps %xmm3, %xmm5 mulss %xmm1, %xmm5 subss %xmm5, %xmm4 movss -8(%r15,%rax), %xmm5 # xmm5 = mem[0],zero,zero,zero ucomiss %xmm4, %xmm5 jne .LBB1_30 jp .LBB1_30 # %bb.26: # in Loop: Header=BB1_25 Depth=1 movss -8(%rbx,%rax), %xmm5 # xmm5 = mem[0],zero,zero,zero movss -8(%r14,%rax), %xmm4 # xmm4 = mem[0],zero,zero,zero mulss %xmm4, %xmm3 mulss %xmm5, %xmm2 subss %xmm2, %xmm3 movss -4(%r15,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero ucomiss %xmm3, %xmm2 jne .LBB1_30 jp .LBB1_30 # %bb.27: # in Loop: Header=BB1_25 Depth=1 mulss %xmm5, %xmm1 mulss %xmm4, %xmm0 subss %xmm0, %xmm1 movss (%r15,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero ucomiss %xmm1, %xmm0 jne .LBB1_30 jp .LBB1_30 # %bb.28: # in Loop: Header=BB1_25 Depth=1 addq $12, %rax cmpq $24584, %rax # imm = 0x6008 jne .LBB1_25 # %bb.29: movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $37, %edx jmp .LBB1_31 .LBB1_30: # %.thread95 movl $_ZSt4cout, %edi movl $.L.str.8, %esi movl $33, %edx .LBB1_31: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB1_9 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i,@object # @_Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .section .rodata,"a",@progbits .globl _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .p2align 3, 0x0 _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i: .quad _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .size _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory for d_a" .size .L.str, 41 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate device memory for d_b" .size .L.str.1, 41 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate device memory for d_result" .size .L.str.2, 46 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy data from host to device for d_a" .size .L.str.3, 48 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to copy data from host to device for d_b" .size .L.str.4, 48 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Kernel launch failed: " .size .L.str.5, 23 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy data from device to host" .size .L.str.6, 40 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Cross product computation successful!" .size .L.str.7, 38 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Cross product computation failed!" .size .L.str.8, 34 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i" .size .L__unnamed_1, 55 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18crossProductKernelP15HIP_vector_typeIfLj3EES1_S1_i .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,542
6,150
113,478
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z21topologicalSortKernelP8ParticlePiS1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.WIDE R14, R0, R15, c[0x0][0x170] ; LDG.E R5, [R14.64] ; SHF.R.S32.HI R2, RZ, 0x1f, R0 ; IMAD.MOV.U32 R13, RZ, RZ, 0x410 ; BSSY B0, 0x880 ; IMAD.WIDE.U32 R6, R0, R13, c[0x0][0x160] ; IMAD R3, R2, 0x410, RZ ; IMAD.WIDE R12, R0, R13, c[0x0][0x160] ; IMAD.IADD R3, R7, 0x1, R3 ; STS [R0.X4], R5 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R8, [R12.64+0x40c] ; BSSY B1, 0x370 ; ISETP.GE.AND P0, PT, R8, 0x1, PT ; @!P0 BRA 0x1d0 ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; IMAD.WIDE R4, R9, 0x4, R2 ; LDG.E R4, [R4.64+0xc] ; LDS R2, [R4.X4] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 BRA 0x360 ; IADD3 R9, R9, 0x1, RZ ; ISETP.GE.AND P0, PT, R9, R8, PT ; @!P0 BRA 0x140 ; LDS R2, [R0.X4] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @P0 BRA 0x360 ; S2R R5, SR_LANEID ; YIELD ; VOTEU.ANY UR8, UPT, PT ; FLO.U32 R2, UR8 ; ULDC.64 UR4, c[0x0][0x168] ; UIADD3 UR4, UP0, UR4, 0x400, URZ ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; POPC R11, UR8 ; IMAD.U32 R8, RZ, RZ, UR4 ; IMAD.U32 R9, RZ, RZ, UR5 ; ISETP.EQ.U32.AND P0, PT, R2, R5, PT ; @P0 ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R11 ; IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; S2R R5, SR_LTMASK ; STS [R0.X4], R17 ; LOP3.LUT R10, R5, UR8, RZ, 0xc0, !PT ; POPC R5, R10 ; SHFL.IDX PT, R4, R9, R2, 0x1f ; IMAD.IADD R4, R4, 0x1, R5 ; IMAD.WIDE R4, R4, R19, c[0x0][0x168] ; STG.E [R4.64], R0 ; BSYNC B1 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.SHL.U32 R4, R2, 0x4, RZ ; LDS.128 R8, [R4] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x10] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x20] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x30] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x40] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x50] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x60] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0x820 ; LDS.128 R8, [R4+0x70] ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; IADD3 R2, R2, 0x20, RZ ; @P0 BRA 0x850 ; WARPSYNC 0xffffffff ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BRA 0xf0 ; ISETP.GE.U32.AND P0, PT, R2, 0x100, PT ; @!P0 BRA 0x380 ; BSYNC B0 ; LDS R3, [R0.X4] ; STG.E [R14.64], R3 ; EXIT ; BRA 0x8b0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21topologicalSortKernelP8ParticlePiS1_ ; -- Begin function _Z21topologicalSortKernelP8ParticlePiS1_ .globl _Z21topologicalSortKernelP8ParticlePiS1_ .p2align 8 .type _Z21topologicalSortKernelP8ParticlePiS1_,@function _Z21topologicalSortKernelP8ParticlePiS1_: ; @_Z21topologicalSortKernelP8ParticlePiS1_ ; %bb.0: s_load_b64 s[4:5], s[0:1], 0x10 v_lshlrev_b32_e32 v1, 2, v0 s_load_b128 s[0:3], s[0:1], 0x0 v_mov_b32_e32 v9, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_dual_mov_b32 v11, 1 :: v_dual_add_nc_u32 v10, 0, v1 s_waitcnt lgkmcnt(0) global_load_b32 v7, v1, s[4:5] v_mad_u64_u32 v[5:6], null, 0x410, v0, s[0:1] v_add_co_u32 v1, s0, s4, v1 v_add_co_ci_u32_e64 v2, null, s5, 0, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v3, vcc_lo, 0x40c, v5 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo v_add_co_u32 v5, vcc_lo, v5, 12 v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v10, v7 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_1: ; =>This Loop Header: Depth=1 ; Child Loop BB0_3 Depth 2 ; Child Loop BB0_13 Depth 2 global_load_b32 v12, v[3:4], off s_mov_b32 s4, -1 s_mov_b32 s1, exec_lo s_waitcnt vmcnt(0) v_cmpx_lt_i32_e32 0, v12 s_cbranch_execz .LBB0_7 ; %bb.2: ; %.lr.ph.preheader ; in Loop: Header=BB0_1 Depth=1 v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5 s_mov_b32 s4, 0 ; implicit-def: $sgpr5 ; implicit-def: $sgpr7 ; implicit-def: $sgpr6 .LBB0_3: ; %.lr.ph ; Parent Loop BB0_1 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b32 v13, v[7:8], off s_or_b32 s6, s6, exec_lo s_or_b32 s7, s7, exec_lo s_mov_b32 s8, exec_lo s_waitcnt vmcnt(0) v_lshl_add_u32 v13, v13, 2, 0 ds_load_b32 v13, v13 s_waitcnt lgkmcnt(0) v_cmpx_ne_u32_e32 0, v13 ; %bb.4: ; in Loop: Header=BB0_3 Depth=2 v_add_nc_u32_e32 v12, -1, v12 v_add_co_u32 v7, s0, v7, 4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v8, s0, 0, v8, s0 v_cmp_eq_u32_e32 vcc_lo, 0, v12 s_and_not1_b32 s0, s7, exec_lo s_and_not1_b32 s6, s6, exec_lo s_and_b32 s7, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s7, s0, s7 ; %bb.5: ; %Flow55 ; in Loop: Header=BB0_3 Depth=2 s_or_b32 exec_lo, exec_lo, s8 s_xor_b32 s0, s6, -1 s_and_b32 s8, exec_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_or_b32 s4, s8, s4 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s0, s0, exec_lo s_or_b32 s5, s5, s0 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_3 ; %bb.6: ; %loop.exit.guard ; in Loop: Header=BB0_1 Depth=1 s_or_b32 exec_lo, exec_lo, s4 s_delay_alu instid0(SALU_CYCLE_1) s_or_not1_b32 s4, s5, exec_lo .LBB0_7: ; %Flow56 ; in Loop: Header=BB0_1 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_and_saveexec_b32 s0, s4 s_cbranch_execz .LBB0_12 ; %bb.8: ; %.critedge ; in Loop: Header=BB0_1 Depth=1 ds_load_b32 v7, v10 s_waitcnt lgkmcnt(0) v_cmp_eq_u32_e32 vcc_lo, 0, v7 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_12 ; %bb.9: ; in Loop: Header=BB0_1 Depth=1 s_mov_b32 s1, exec_lo s_mov_b32 s4, exec_lo v_mbcnt_lo_u32_b32 v7, s1, 0 ds_store_b32 v10, v11 ; implicit-def: $vgpr8 v_cmpx_eq_u32_e32 0, v7 s_cbranch_execz .LBB0_11 ; %bb.10: ; in Loop: Header=BB0_1 Depth=1 s_bcnt1_i32_b32 s1, s1 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v8, s1 global_atomic_add_u32 v8, v9, v8, s[2:3] offset:1024 glc .LBB0_11: ; in Loop: Header=BB0_1 Depth=1 s_or_b32 exec_lo, exec_lo, s4 s_waitcnt vmcnt(0) v_readfirstlane_b32 s1, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v7, s1, v7 v_ashrrev_i32_e32 v8, 31, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[7:8] v_add_co_u32 v7, vcc_lo, s2, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo global_store_b32 v[7:8], v0, off .LBB0_12: ; %.loopexit.preheader ; in Loop: Header=BB0_1 Depth=1 s_or_b32 exec_lo, exec_lo, s0 s_mov_b32 s0, 0 .LBB0_13: ; %.loopexit ; Parent Loop BB0_1 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s1, s0, 0 v_mov_b32_e32 v7, s1 ds_load_b32 v7, v7 s_waitcnt lgkmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v7 s_cbranch_vccz .LBB0_15 ; %bb.14: ; in Loop: Header=BB0_13 Depth=2 s_add_i32 s0, s0, 4 s_mov_b32 s1, 0 s_cmpk_eq_i32 s0, 0x400 s_cselect_b32 s4, -1, 0 s_branch .LBB0_16 .LBB0_15: ; in Loop: Header=BB0_13 Depth=2 s_mov_b32 s1, -1 s_mov_b32 s4, -1 ; implicit-def: $sgpr0 .LBB0_16: ; %Flow ; in Loop: Header=BB0_13 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s4 s_cbranch_vccnz .LBB0_13 ; %bb.17: ; %loop.exit.guard53 ; in Loop: Header=BB0_1 Depth=1 s_and_b32 vcc_lo, exec_lo, s1 s_mov_b32 s0, -1 s_cbranch_vccz .LBB0_19 ; %bb.18: ; %.critedge34 ; in Loop: Header=BB0_1 Depth=1 s_mov_b32 s0, 0 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv .LBB0_19: ; %Flow57 ; in Loop: Header=BB0_1 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_1 ; %bb.20: ; %.critedge35 ds_load_b32 v0, v10 s_waitcnt lgkmcnt(0) global_store_b32 v[1:2], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21topologicalSortKernelP8ParticlePiS1_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 9 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21topologicalSortKernelP8ParticlePiS1_, .Lfunc_end0-_Z21topologicalSortKernelP8ParticlePiS1_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 624 ; NumSgprs: 11 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 11 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21topologicalSortKernelP8ParticlePiS1_ .private_segment_fixed_size: 0 .sgpr_count: 11 .sgpr_spill_count: 0 .symbol: _Z21topologicalSortKernelP8ParticlePiS1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000b7a09_00000000-6_cuda_code_026341.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_ .type _Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_, @function _Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_: .LFB3660: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movq %rdx, 8(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z21topologicalSortKernelP8ParticlePiS1_(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L2: movq 120(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_, .-_Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_ .globl _Z21topologicalSortKernelP8ParticlePiS1_ .type _Z21topologicalSortKernelP8ParticlePiS1_, @function _Z21topologicalSortKernelP8ParticlePiS1_: .LFB3661: .cfi_startproc endbr64 jmp _Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_ .cfi_endproc .LFE3661: .size _Z21topologicalSortKernelP8ParticlePiS1_, .-_Z21topologicalSortKernelP8ParticlePiS1_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string "Topologically sorted indices: " .LC2: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 leaq -266240(%rsp), %r11 .cfi_def_cfa 11, 266280 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $2120, %rsp .cfi_def_cfa_offset 268400 movl $256, %ecx xorl %edx, %edx movq %fs:40, %rax movq %rax, 268344(%rsp) xorl %eax, %eax leaq 1080(%rsp), %rdi rep stosl leaq 2104(%rsp), %rax movq %rax, %rbx .L11: cvtsi2ssl %edx, %xmm0 movss %xmm0, (%rax) movss %xmm0, 4(%rax) movss %xmm0, 8(%rax) testl %edx, %edx jne .L9 xorl %ecx, %ecx movl %ecx, 1036(%rax) jmp .L10 .L9: movl $1, 1036(%rax) leal -1(%rdx), %ecx movl %ecx, 12(%rax) .L10: incl %edx addq $1040, %rax cmpl $256, %edx jne .L11 leaq 8(%rsp), %rdi movl $266240, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $1024, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $1024, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $266240, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movl $1024, %edx leaq 1080(%rsp), %rsi call cudaMemcpy@PLT movq 16(%rsp), %rdi xorl %esi, %esi movl $1024, %edx call cudaMemset@PLT movl $16777217, %edx xorl %r9d, %r9d movabsq $4294967297, %rdi salq $8, %rdx movl $1024, %r8d movl $1, %ecx movl $1, %esi movq %rdx, 44(%rsp) movl $1, 52(%rsp) movq %rdi, 32(%rsp) movl $1, 40(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L12 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z54__device_stub__Z21topologicalSortKernelP8ParticlePiS1_P8ParticlePiS1_ .L12: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L13 leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L13: movq 16(%rsp), %rsi leaq 56(%rsp), %r12 xorl %ebx, %ebx movl $2, %ecx movl $1024, %edx movq %r12, %rdi leaq _ZSt4cout(%rip), %rbp call cudaMemcpy@PLT leaq .LC1(%rip), %rsi movq %rbp, %rdi leaq .LC2(%rip), %r13 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L15: movl (%r12,%rbx,4), %esi movq %rbp, %rdi incq %rbx call _ZNSolsEi@PLT movq %r13, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $256, %rbx jne .L15 movq %rbp, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L8: movq 268344(%rsp), %rdx subq %fs:40, %rdx je .L16 call __stack_chk_fail@PLT .L16: addq $268360, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z21topologicalSortKernelP8ParticlePiS1_" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC3(%rip), %rdx movq %rax, %rdi leaq _Z21topologicalSortKernelP8ParticlePiS1_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_026341.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ # -- Begin function _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ .type _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_,@function _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_: # @_Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z21topologicalSortKernelP8ParticlePiS1_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_, .Lfunc_end0-_Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $268320, %rsp # imm = 0x41820 .cfi_def_cfa_offset 268352 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 32(%rsp), %rdi xorl %ebx, %ebx movl $1024, %edx # imm = 0x400 xorl %esi, %esi callq memset@PLT movl $-1, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 leal 1(%rax), %ecx xorps %xmm0, %xmm0 cvtsi2ss %ecx, %xmm0 movss %xmm0, 2080(%rsp,%rbx) movss %xmm0, 2084(%rsp,%rbx) movss %xmm0, 2088(%rsp,%rbx) movl $0, 3116(%rsp,%rbx) testq %rbx, %rbx je .LBB1_3 # %bb.2: # in Loop: Header=BB1_1 Depth=1 movl $1, 3116(%rsp,%rbx) movl %eax, 2092(%rsp,%rbx) .LBB1_3: # in Loop: Header=BB1_1 Depth=1 addq $1040, %rbx # imm = 0x410 movl %ecx, %eax cmpq $266240, %rbx # imm = 0x41000 jne .LBB1_1 # %bb.4: leaq 24(%rsp), %r14 movl $266240, %esi # imm = 0x41000 movq %r14, %rdi callq hipMalloc leaq 8(%rsp), %rbx movl $1024, %esi # imm = 0x400 movq %rbx, %rdi callq hipMalloc leaq 16(%rsp), %r15 movl $1024, %esi # imm = 0x400 movq %r15, %rdi callq hipMalloc movq (%r14), %rdi leaq 2080(%rsp), %rsi movl $266240, %edx # imm = 0x41000 movl $1, %ecx callq hipMemcpy movq (%r15), %rdi leaq 32(%rsp), %rsi movl $1024, %edx # imm = 0x400 movl $1, %ecx callq hipMemcpy movq (%rbx), %rdi movl $1024, %edx # imm = 0x400 xorl %esi, %esi callq hipMemset movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rdx movl $1024, %r8d # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 24(%rsp), %rdi movq 8(%rsp), %rsi movq 16(%rsp), %rdx callq _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ .LBB1_6: callq hipGetLastError testl %eax, %eax je .LBB1_11 # %bb.7: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_8 # %bb.9: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_10 .LBB1_11: movq 8(%rsp), %rsi leaq 1056(%rsp), %rdi movl $1024, %edx # imm = 0x400 movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $30, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %ebx, %ebx .LBB1_12: # =>This Inner Loop Header: Depth=1 movl 1056(%rsp,%rbx,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %rbx cmpq $256, %rbx # imm = 0x100 jne .LBB1_12 # %bb.13: movq _ZSt4cout(%rip), %rax movl $_ZSt4cout, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 24(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_14 .LBB1_8: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_14: addq $268320, %rsp # imm = 0x41820 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21topologicalSortKernelP8ParticlePiS1_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z21topologicalSortKernelP8ParticlePiS1_,@object # @_Z21topologicalSortKernelP8ParticlePiS1_ .section .rodata,"a",@progbits .globl _Z21topologicalSortKernelP8ParticlePiS1_ .p2align 3, 0x0 _Z21topologicalSortKernelP8ParticlePiS1_: .quad _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ .size _Z21topologicalSortKernelP8ParticlePiS1_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Topologically sorted indices: " .size .L.str.1, 31 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz " " .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z21topologicalSortKernelP8ParticlePiS1_" .size .L__unnamed_1, 41 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__topologicalSortKernelP8ParticlePiS1_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21topologicalSortKernelP8ParticlePiS1_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
3,757
4,571
113,482
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z17insertKeyIntoNodeP9BTreeNodeii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R3, RZ, RZ, 0x20 ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; LDG.E R0, [R2.64] ; S2R R7, SR_TID.X ; IMAD.WIDE R4, R7.reuse, 0x4, R2 ; ISETP.GE.AND P0, PT, R7, R0, PT ; @!P0 LDG.E R0, [R4.64+0x4] ; @!P0 STS [R7.X4], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R9, [R2.64] ; BSSY B0, 0x810 ; ISETP.GE.AND P0, PT, R7, R9, PT ; ISETP.GE.U32.OR P0, PT, R7, c[0x0][0x0], P0 ; @P0 BRA 0x800 ; BSSY B1, 0x1a0 ; IMAD.MOV.U32 R0, RZ, RZ, R7 ; LDS R6, [R0.X4] ; ISETP.GE.AND P0, PT, R6, c[0x0][0x16c], PT ; @P0 BRA 0x190 ; IADD3 R0, R0, 0x1, RZ ; ISETP.GE.AND P0, PT, R0, R9, PT ; @!P0 BRA 0x130 ; BSYNC B1 ; ISETP.GT.AND P0, PT, R9, R0, PT ; BSSY B1, 0x7e0 ; @!P0 BRA 0x7d0 ; IMAD.IADD R6, R9.reuse, 0x1, -R0 ; LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; BSSY B2, 0x2e0 ; LOP3.LUT P1, R6, R6, 0x3, RZ, 0xc0, !PT ; IMAD.IADD R8, R9, 0x1, R8 ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; @!P1 BRA 0x2d0 ; IMAD.SHL.U32 R8, R9, 0x4, RZ ; LDS R11, [R8+-0x4] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R10, R8, -0x4, RZ ; ISETP.NE.AND P1, PT, R6, RZ, PT ; IADD3 R9, R9, -0x1, RZ ; STS [R8], R11 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; @P1 BRA 0x250 ; BSYNC B2 ; @!P0 BRA 0x7d0 ; IMAD.IADD R6, R9, 0x1, -R0 ; BSSY B2, 0x5c0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; LEA R6, R9, 0xfffffff8, 0x2 ; @!P1 BRA 0x5b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R20, R0, 0xc, RZ ; LDS R11, [R6+0x4] ; IADD3 R9, R9, -0x10, RZ ; LDS R13, [R6] ; ISETP.GT.AND P1, PT, R9, R20, PT ; LDS R15, [R6+-0x4] ; LDS R17, [R6+-0x8] ; LDS R19, [R6+-0xc] ; LDS R21, [R6+-0x10] ; LDS R23, [R6+-0x14] ; LDS R25, [R6+-0x18] ; LDS R27, [R6+-0x1c] ; LDS R29, [R6+-0x20] ; LDS R8, [R6+-0x24] ; LDS R10, [R6+-0x28] ; LDS R12, [R6+-0x2c] ; LDS R14, [R6+-0x30] ; LDS R16, [R6+-0x34] ; LDS R18, [R6+-0x38] ; STS [R6+0x8], R11 ; STS [R6+0x4], R13 ; STS [R6], R15 ; STS [R6+-0x4], R17 ; STS [R6+-0x8], R19 ; STS [R6+-0xc], R21 ; STS [R6+-0x10], R23 ; STS [R6+-0x14], R25 ; STS [R6+-0x18], R27 ; STS [R6+-0x1c], R29 ; STS [R6+-0x20], R8 ; STS [R6+-0x24], R10 ; STS [R6+-0x28], R12 ; STS [R6+-0x2c], R14 ; STS [R6+-0x30], R16 ; STS [R6+-0x34], R18 ; IADD3 R6, R6, -0x40, RZ ; @P1 BRA 0x370 ; BSYNC B2 ; IMAD.IADD R8, R9, 0x1, -R0 ; BSSY B2, 0x740 ; ISETP.GT.AND P1, PT, R8, 0x4, PT ; @!P1 BRA 0x730 ; LDS R11, [R6+0x4] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R9, R9, -0x8, RZ ; LDS R13, [R6] ; LDS R15, [R6+-0x4] ; LDS R17, [R6+-0x8] ; LDS R19, [R6+-0xc] ; LDS R21, [R6+-0x10] ; LDS R23, [R6+-0x14] ; LDS R25, [R6+-0x18] ; STS [R6+0x8], R11 ; STS [R6+0x4], R13 ; STS [R6], R15 ; STS [R6+-0x4], R17 ; STS [R6+-0x8], R19 ; STS [R6+-0xc], R21 ; STS [R6+-0x10], R23 ; STS [R6+-0x14], R25 ; IADD3 R6, R6, -0x20, RZ ; BSYNC B2 ; ISETP.GT.OR P0, PT, R9, R0, P0 ; @P0 LDS R9, [R6+0x4] ; @P0 LDS R11, [R6] ; @P0 LDS R13, [R6+-0x4] ; @P0 LDS R15, [R6+-0x8] ; @P0 STS [R6+0x8], R9 ; @P0 STS [R6+0x4], R11 ; @P0 STS [R6], R13 ; @P0 STS [R6+-0x4], R15 ; BSYNC B1 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; STS [R0.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R0, [R2.64] ; ISETP.NE.AND P1, PT, R7.reuse, RZ, PT ; ISETP.GE.AND P0, PT, R7, R0, PT ; @!P0 LDS R9, [R7.X4] ; @!P0 STG.E [R4.64+0x4], R9 ; @P1 EXIT ; LDG.E R0, [R2.64] ; IADD3 R5, R0, 0x1, RZ ; STG.E [R2.64], R5 ; EXIT ; BRA 0x8c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z20initializeBTreeNodesP9BTreeNode .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R2, 0x7ff, PT ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 1.9073486328125e-06 ; MOV R5, 0xffffffff ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; STG.E [R2.64+0x10], R5 ; STG.E [R2.64+0x14], R5 ; STG.E [R2.64+0x18], R5 ; STG.E [R2.64+0x1c], R5 ; STG.E [R2.64], RZ ; STG.E [R2.64+0x4], RZ ; STG.E [R2.64+0x8], RZ ; STG.E [R2.64+0xc], RZ ; EXIT ; BRA 0x130; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z20initializeBTreeNodesP9BTreeNode ; -- Begin function _Z20initializeBTreeNodesP9BTreeNode .globl _Z20initializeBTreeNodesP9BTreeNode .p2align 8 .type _Z20initializeBTreeNodesP9BTreeNode,@function _Z20initializeBTreeNodesP9BTreeNode: ; @_Z20initializeBTreeNodesP9BTreeNode ; %bb.0: s_load_b32 s2, s[0:1], 0x14 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x800, v1 s_cbranch_execz .LBB0_2 ; %bb.1: ; %.preheader.preheader s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 v_mov_b32_e32 v4, -1 v_mov_b32_e32 v0, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[7:8], 5, v[1:2] v_mov_b32_e32 v5, v4 s_delay_alu instid0(VALU_DEP_3) v_mov_b32_e32 v1, v0 v_mov_b32_e32 v2, v0 v_mov_b32_e32 v3, v0 v_mov_b32_e32 v6, v4 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s0, v7 v_add_co_ci_u32_e32 v10, vcc_lo, s1, v8, vcc_lo v_mov_b32_e32 v7, v4 s_clause 0x1 global_store_b128 v[9:10], v[0:3], off global_store_b128 v[9:10], v[4:7], off offset:16 .LBB0_2: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z20initializeBTreeNodesP9BTreeNode .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z20initializeBTreeNodesP9BTreeNode, .Lfunc_end0-_Z20initializeBTreeNodesP9BTreeNode ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 156 ; NumSgprs: 18 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z17insertKeyIntoNodeP9BTreeNodeii ; -- Begin function _Z17insertKeyIntoNodeP9BTreeNodeii .globl _Z17insertKeyIntoNodeP9BTreeNodeii .p2align 8 .type _Z17insertKeyIntoNodeP9BTreeNodeii,@function _Z17insertKeyIntoNodeP9BTreeNodeii: ; @_Z17insertKeyIntoNodeP9BTreeNodeii ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt lgkmcnt(0) s_ashr_i32 s3, s6, 31 s_mov_b32 s2, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[8:9], s[2:3], 5 s_add_u32 s2, s4, s8 s_addc_u32 s3, s5, s9 s_load_b32 s6, s[2:3], 0x0 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s6, v0 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB1_2 ; %bb.1: s_add_u32 s10, s4, s8 s_addc_u32 s11, s5, s9 v_add_nc_u32_e32 v3, 0, v1 global_load_b32 v2, v1, s[10:11] offset:4 s_waitcnt vmcnt(0) ds_store_b32 v3, v2 .LBB1_2: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_load_b32 s10, s[2:3], 0x0 s_mov_b32 s6, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s10, v0 s_cbranch_execz .LBB1_12 ; %bb.3: s_load_b32 s0, s[0:1], 0x1c s_waitcnt lgkmcnt(0) s_and_b32 s0, s0, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s0, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_12 ; %bb.4: ; %.lr.ph.preheader v_lshl_add_u32 v3, v0, 2, 0 v_mov_b32_e32 v4, v0 s_mov_b32 s0, 0 ; implicit-def: $sgpr1 .LBB1_5: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 ds_load_b32 v2, v3 s_or_b32 s1, s1, exec_lo s_mov_b32 s11, exec_lo ; implicit-def: $vgpr5 s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s7, v2 ; %bb.6: ; in Loop: Header=BB1_5 Depth=1 v_dual_mov_b32 v4, s10 :: v_dual_add_nc_u32 v5, 1, v4 v_add_nc_u32_e32 v3, 4, v3 s_and_not1_b32 s1, s1, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_le_i32_e32 vcc_lo, s10, v5 s_and_b32 s12, vcc_lo, exec_lo s_or_b32 s1, s1, s12 ; %bb.7: ; %Flow58 ; in Loop: Header=BB1_5 Depth=1 s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v2, v4 v_mov_b32_e32 v4, v5 s_and_b32 s11, exec_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s0, s11, s0 s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB1_5 ; %bb.8: ; %.critedge s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s0, exec_lo v_cmpx_gt_i32_e64 s10, v2 s_cbranch_execz .LBB1_11 ; %bb.9: ; %.lr.ph43.preheader s_lshl_b32 s1, s10, 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s11, s1, 0 s_mov_b32 s1, 0 s_add_i32 s11, s11, -4 .LBB1_10: ; %.lr.ph43 ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v3, s11 s_add_i32 s10, s10, -1 s_add_i32 s11, s11, -4 v_cmp_le_i32_e32 vcc_lo, s10, v2 ds_load_b32 v4, v3 s_or_b32 s1, vcc_lo, s1 s_waitcnt lgkmcnt(0) ds_store_b32 v3, v4 offset:4 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB1_10 .LBB1_11: ; %Flow57 s_or_b32 exec_lo, exec_lo, s0 v_lshl_add_u32 v2, v2, 2, 0 v_mov_b32_e32 v3, s7 ds_store_b32 v2, v3 .LBB1_12: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_load_b32 s0, s[2:3], 0x0 s_mov_b32 s1, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s0, v0 s_cbranch_execz .LBB1_14 ; %bb.13: v_add_nc_u32_e32 v2, 0, v1 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 ds_load_b32 v2, v2 s_waitcnt lgkmcnt(0) global_store_b32 v1, v2, s[4:5] offset:4 .LBB1_14: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s1, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB1_16 ; %bb.15: s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 global_store_b32 v0, v1, s[2:3] .LBB1_16: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z17insertKeyIntoNodeP9BTreeNodeii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 13 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z17insertKeyIntoNodeP9BTreeNodeii, .Lfunc_end1-_Z17insertKeyIntoNodeP9BTreeNodeii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 544 ; NumSgprs: 15 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 15 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z20initializeBTreeNodesP9BTreeNode .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z20initializeBTreeNodesP9BTreeNode.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z17insertKeyIntoNodeP9BTreeNodeii .private_segment_fixed_size: 0 .sgpr_count: 15 .sgpr_spill_count: 0 .symbol: _Z17insertKeyIntoNodeP9BTreeNodeii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_001485c8_00000000-6_cuda_code_064736.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode .type _Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode, @function _Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode: .LFB3660: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 40(%rsp) movq %rax, 80(%rsp) movabsq $4294967297, %rax movq %rax, 32(%rsp) movq %rax, 44(%rsp) movl $1, 52(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 24(%rsp) .cfi_def_cfa_offset 120 leaq _Z20initializeBTreeNodesP9BTreeNode(%rip), %rdi pushq 24(%rsp) .cfi_def_cfa_offset 128 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq 96(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 120 popq %rdx .cfi_def_cfa_offset 112 .L2: movq 88(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $104, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode, .-_Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode .globl _Z20initializeBTreeNodesP9BTreeNode .type _Z20initializeBTreeNodesP9BTreeNode, @function _Z20initializeBTreeNodesP9BTreeNode: .LFB3661: .cfi_startproc endbr64 jmp _Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode .cfi_endproc .LFE3661: .size _Z20initializeBTreeNodesP9BTreeNode, .-_Z20initializeBTreeNodesP9BTreeNode .globl _Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii .type _Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii, @function _Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii: .LFB3662: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 24(%rsp), %rcx leaq 32(%rsp), %rdi movl %esi, 4(%rsp) leaq 44(%rsp), %rsi movl %edx, (%rsp) leaq 16(%rsp), %rdx movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 40(%rsp) movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 32(%rsp) movq %rax, 44(%rsp) movl $1, 52(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 24(%rsp) .cfi_def_cfa_offset 136 leaq _Z17insertKeyIntoNodeP9BTreeNodeii(%rip), %rdi pushq 24(%rsp) .cfi_def_cfa_offset 144 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq 96(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3662: .size _Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii, .-_Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii .globl _Z17insertKeyIntoNodeP9BTreeNodeii .type _Z17insertKeyIntoNodeP9BTreeNodeii, @function _Z17insertKeyIntoNodeP9BTreeNodeii: .LFB3663: .cfi_startproc endbr64 jmp _Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii .cfi_endproc .LFE3663: .size _Z17insertKeyIntoNodeP9BTreeNodeii, .-_Z17insertKeyIntoNodeP9BTreeNodeii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate device memory: " .LC1: .string "Failed to launch kernel: " .LC2: .string "Failed to launch insert key kernel: " .LC3: .string "Keys in node " .LC4: .string ": " .LC5: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $65536, %esi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $56, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi call cudaMalloc@PLT testl %eax, %eax je .L14 movl %eax, %ebx leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L15 .L14: movl $16777217, %edx movl $536870913, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx salq $3, %rdi movl $1, %ecx movl $1, %esi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rdi call _Z49__device_stub__Z20initializeBTreeNodesP9BTreeNodeP9BTreeNode .L16: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L17 leaq .LC1(%rip), %rsi .L25: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT .L15: orl $-1, %eax jmp .L13 .L17: call cudaDeviceSynchronize@PLT xorl %r9d, %r9d movl $12, %r8d movabsq $4294967299, %rdx movl $1, %ecx movl $1, %esi movabsq $4294967297, %rdi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L19 movq 8(%rsp), %rdi movl $10, %edx xorl %esi, %esi call _Z48__device_stub__Z17insertKeyIntoNodeP9BTreeNodeiiP9BTreeNodeii .L19: call cudaGetLastError@PLT leaq .LC2(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L25 call cudaDeviceSynchronize@PLT movl $65536, %edi xorl %ebp, %ebp leaq _ZSt4cout(%rip), %r12 call malloc@PLT movq 8(%rsp), %rsi movl $2, %ecx movl $65536, %edx movq %rax, %rdi movq %rax, %rbx leaq .LC5(%rip), %r13 call cudaMemcpy@PLT leaq .LC3(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT xorl %esi, %esi movq %rax, %rdi call _ZNSolsEi@PLT leaq .LC4(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L21: cmpl %ebp, (%rbx) jle .L26 movl 4(%rbx,%rbp,4), %esi movq %r12, %rdi incq %rbp call _ZNSolsEi@PLT movq %r13, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT jmp .L21 .L26: movq %r12, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call free@PLT xorl %eax, %eax .L13: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L23 call __stack_chk_fail@PLT .L23: addq $56, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z17insertKeyIntoNodeP9BTreeNodeii" .LC7: .string "_Z20initializeBTreeNodesP9BTreeNode" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3665: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z17insertKeyIntoNodeP9BTreeNodeii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC7(%rip), %rdx orl $-1, %r8d leaq _Z20initializeBTreeNodesP9BTreeNode(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3665: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_064736.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z35__device_stub__initializeBTreeNodesP9BTreeNode # -- Begin function _Z35__device_stub__initializeBTreeNodesP9BTreeNode .type _Z35__device_stub__initializeBTreeNodesP9BTreeNode,@function _Z35__device_stub__initializeBTreeNodesP9BTreeNode: # @_Z35__device_stub__initializeBTreeNodesP9BTreeNode .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $64, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) movq %rsp, %rbx movq %rax, (%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z20initializeBTreeNodesP9BTreeNode, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $80, %rsp .cfi_adjust_cfa_offset -80 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z35__device_stub__initializeBTreeNodesP9BTreeNode, .Lfunc_end0-_Z35__device_stub__initializeBTreeNodesP9BTreeNode .cfi_endproc # -- End function .globl _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii # -- Begin function _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii .type _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii,@function _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii: # @_Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) movq %rsp, %rsi movl %edx, (%rsi) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z17insertKeyIntoNodeP9BTreeNodeii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $112, %rsp .cfi_adjust_cfa_offset -112 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii, .Lfunc_end1-_Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsp, %rdi movl $65536, %esi # imm = 0x10000 callq hipMalloc testl %eax, %eax je .LBB2_3 # %bb.1: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $34, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_7 # %bb.2: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_8 .LBB2_3: movabsq $4294967297, %rbx # imm = 0x100000001 leaq 7(%rbx), %rdi leaq 255(%rbx), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_5 # %bb.4: movq (%rsp), %rdi callq _Z35__device_stub__initializeBTreeNodesP9BTreeNode .LBB2_5: callq hipGetLastError testl %eax, %eax je .LBB2_9 # %bb.6: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi jmp .LBB2_13 .LBB2_7: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB2_17 .LBB2_9: callq hipDeviceSynchronize leaq 2(%rbx), %rdx movl $12, %r8d movq %rbx, %rdi movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_11 # %bb.10: movq (%rsp), %rdi xorl %esi, %esi movl $10, %edx callq _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii .LBB2_11: callq hipGetLastError testl %eax, %eax je .LBB2_19 # %bb.12: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $36, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi .LBB2_13: callq hipGetErrorString testq %rax, %rax je .LBB2_15 # %bb.14: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_16 .LBB2_15: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit40 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi callq hipFree .LBB2_17: movl $-1, %ebp .LBB2_18: movl %ebp, %eax addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_19: .cfi_def_cfa_offset 48 callq hipDeviceSynchronize movl $65536, %edi # imm = 0x10000 callq malloc movq %rax, %rbx movq (%rsp), %rsi movl $65536, %edx # imm = 0x10000 movq %rax, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %r14d movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $13, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %ebp, %ebp movl $_ZSt4cout, %edi xorl %esi, %esi callq _ZNSolsEi movl $.L.str.4, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cmpl $0, (%rbx) jle .LBB2_22 # %bb.20: # %.lr.ph.preheader xorl %r15d, %r15d .LBB2_21: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl 4(%rbx,%r15,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str.5, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r15 movslq (%rbx), %rax cmpq %rax, %r15 jl .LBB2_21 .LBB2_22: # %._crit_edge movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %r14, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq free jmp .LBB2_18 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z20initializeBTreeNodesP9BTreeNode, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z17insertKeyIntoNodeP9BTreeNodeii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z20initializeBTreeNodesP9BTreeNode,@object # @_Z20initializeBTreeNodesP9BTreeNode .section .rodata,"a",@progbits .globl _Z20initializeBTreeNodesP9BTreeNode .p2align 3, 0x0 _Z20initializeBTreeNodesP9BTreeNode: .quad _Z35__device_stub__initializeBTreeNodesP9BTreeNode .size _Z20initializeBTreeNodesP9BTreeNode, 8 .type _Z17insertKeyIntoNodeP9BTreeNodeii,@object # @_Z17insertKeyIntoNodeP9BTreeNodeii .globl _Z17insertKeyIntoNodeP9BTreeNodeii .p2align 3, 0x0 _Z17insertKeyIntoNodeP9BTreeNodeii: .quad _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii .size _Z17insertKeyIntoNodeP9BTreeNodeii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory: " .size .L.str, 35 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to launch kernel: " .size .L.str.1, 26 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to launch insert key kernel: " .size .L.str.2, 37 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Keys in node " .size .L.str.3, 14 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz ": " .size .L.str.4, 3 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz " " .size .L.str.5, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z20initializeBTreeNodesP9BTreeNode" .size .L__unnamed_1, 36 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z17insertKeyIntoNodeP9BTreeNodeii" .size .L__unnamed_2, 35 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z35__device_stub__initializeBTreeNodesP9BTreeNode .addrsig_sym _Z32__device_stub__insertKeyIntoNodeP9BTreeNodeii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z20initializeBTreeNodesP9BTreeNode .addrsig_sym _Z17insertKeyIntoNodeP9BTreeNodeii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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113,484
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z13initParticlesP6float4i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; S2R R3, SR_CTAID.X ; IMAD R0, R3, c[0x0][0x0], R0 ; CS2R R2, SR_CLOCKLO ; ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; @P0 EXIT ; IADD3 R2, P0, R0, R2, RZ ; ULDC.64 UR4, c[0x0][0x118] ; LOP3.LUT R2, R2, 0xaad26b49, RZ, 0x3c, !PT ; LEA.HI.X.SX32 R3, R0, R3, 0x1, P0 ; IMAD R2, R2, 0x4182bed5, RZ ; LOP3.LUT R3, R3, 0xf7dcefdd, RZ, 0x3c, !PT ; IADD3 R4, R2.reuse, 0x75bcd15, RZ ; IMAD R3, R3, -0x658354e5, RZ ; IADD3 R6, R2.reuse, 0x583f19, RZ ; SHF.R.U32.HI R7, RZ, 0x2, R4 ; LOP3.LUT R5, R2, 0x159a55e5, RZ, 0x3c, !PT ; LOP3.LUT R7, R7, R4, RZ, 0x3c, !PT ; IMAD.SHL.U32 R4, R6, 0x10, RZ ; SHF.R.U32.HI R5, RZ, 0x2, R5 ; LOP3.LUT R8, R5, 0x159a55e5, R2, 0x96, !PT ; LOP3.LUT R6, R7.reuse, R4, R6, 0x96, !PT ; IMAD.SHL.U32 R7, R7, 0x2, RZ ; IADD3 R4, R3, 0x1f123bb5, RZ ; IMAD.SHL.U32 R5, R8, 0x2, RZ ; IADD3 R2, R2, 0x64f0c9, R3 ; LOP3.LUT R7, R6, R7, RZ, 0x3c, !PT ; SHF.R.U32.HI R9, RZ, 0x2, R4 ; LOP3.LUT R8, R7.reuse, R5, R8, 0x96, !PT ; IMAD.SHL.U32 R5, R7, 0x10, RZ ; LOP3.LUT R6, R9, R4, RZ, 0x3c, !PT ; LOP3.LUT R4, R3, 0x5491333, RZ, 0x3c, !PT ; LOP3.LUT R5, R8, R5, RZ, 0x3c, !PT ; IMAD.SHL.U32 R8, R6, 0x2, RZ ; SHF.R.U32.HI R10, RZ, 0x2, R4 ; IADD3 R7, R2, 0x587c5, R7 ; LOP3.LUT R9, R5.reuse, R8, R6, 0x96, !PT ; IMAD.SHL.U32 R6, R5, 0x10, RZ ; LOP3.LUT R10, R10, 0x5491333, R3, 0x96, !PT ; I2F.U32 R4, R7 ; IADD3 R5, R2, 0xb0f8a, R5 ; LOP3.LUT R9, R9, R6, RZ, 0x3c, !PT ; IMAD.SHL.U32 R3, R10, 0x2, RZ ; I2F.U32 R5, R5 ; LOP3.LUT R10, R9.reuse, R3, R10, 0x96, !PT ; IMAD.SHL.U32 R3, R9, 0x10, RZ ; IADD3 R9, R2, 0x10974f, R9 ; LOP3.LUT R3, R10, R3, RZ, 0x3c, !PT ; I2F.U32 R6, R9 ; IADD3 R8, R2, 0x161f14, R3 ; IMAD.MOV.U32 R2, RZ, RZ, 0x2f800000 ; IMAD.MOV.U32 R3, RZ, RZ, 0x10 ; I2F.U32 R7, R8 ; FFMA R4, R4, R2, 1.1641532182693481445e-10 ; FFMA R5, R5, R2.reuse, 1.1641532182693481445e-10 ; FFMA R6, R6, R2.reuse, 1.1641532182693481445e-10 ; FFMA R7, R7, R2, 1.1641532182693481445e-10 ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; STG.E.128 [R2.64], R4 ; EXIT ; BRA 0x3d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z12bubbleSort4DP6float4i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; IMAD.MOV.U32 R3, RZ, RZ, 0x10 ; ULDC.64 UR8, c[0x0][0x118] ; BSSY B0, 0xd0 ; S2R R13, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R13 ; ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @P0 BRA 0xc0 ; LDG.E.128 R4, [R2.64] ; STS.128 [R13.X16], R4 ; BSYNC B0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P1, PT, R0, 0x2, PT ; @!P1 BRA 0x280 ; IADD3 R0, R0, -0x1, RZ ; UMOV UR4, URZ ; ULOP3.LUT UR5, URZ, UR4, URZ, 0x33, !UPT ; BSSY B0, 0x240 ; ULDC UR6, c[0x0][0x168] ; UIADD3 UR5, UR5, UR6, URZ ; ISETP.GE.AND P1, PT, R13, UR5, PT ; @P1 BRA 0x230 ; IMAD.MOV.U32 R12, RZ, RZ, R13 ; IMAD.SHL.U32 R14, R12.reuse, 0x10, RZ ; IADD3 R12, R12, c[0x0][0x0], RZ ; LDS.128 R4, [R14+0x10] ; LDS.128 R8, [R14] ; FSETP.GT.AND P1, PT, R8, R4, PT ; @P1 STS.128 [R14], R4 ; @P1 STS.128 [R14+0x10], R8 ; ISETP.GE.AND P1, PT, R12, UR5, PT ; @!P1 BRA 0x1a0 ; BSYNC B0 ; UIADD3 UR4, UR4, 0x1, URZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.LE.AND P1, PT, R0, UR4, PT ; @!P1 BRA 0x130 ; @P0 EXIT ; LDS.128 R4, [R13.X16] ; STG.E.128 [R2.64], R4 ; EXIT ; BRA 0x2c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi ; -- Begin function _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .globl _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .p2align 8 .type _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi,@function _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi: ; @_Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi ; %bb.0: s_clause 0x2 s_load_b32 s5, s[0:1], 0x1c s_load_b32 s4, s[0:1], 0x8 s_load_b64 s[2:3], s[0:1], 0x0 v_lshl_add_u32 v3, v0, 4, 0 s_waitcnt lgkmcnt(0) s_and_b32 s1, s5, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1] v_cmp_gt_i32_e32 vcc_lo, s4, v1 v_ashrrev_i32_e32 v2, 31, v1 s_and_saveexec_b32 s5, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[4:5], 4, v[1:2] v_lshl_add_u32 v8, v0, 4, 0 v_add_co_u32 v4, s0, s2, v4 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, s3, v5, s0 global_load_b128 v[4:7], v[4:5], off s_waitcnt vmcnt(0) ds_store_b128 v8, v[4:7] .LBB0_2: s_or_b32 exec_lo, exec_lo, s5 s_cmp_lt_i32 s4, 2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_10 ; %bb.3: ; %.preheader.preheader s_add_i32 s5, s4, -2 s_mov_b32 s7, 0 s_lshl_b32 s6, s1, 4 .LBB0_4: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 s_not_b32 s8, s7 s_mov_b32 s9, exec_lo s_add_i32 s8, s8, s4 s_delay_alu instid0(SALU_CYCLE_1) v_cmpx_gt_i32_e64 s8, v0 s_cbranch_execz .LBB0_9 ; %bb.5: ; %.lr.ph.preheader ; in Loop: Header=BB0_4 Depth=1 v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v5, v0 s_mov_b32 s10, 0 .LBB0_6: ; %.lr.ph ; Parent Loop BB0_4 Depth=1 ; => This Inner Loop Header: Depth=2 ds_load_2addr_b32 v[6:7], v4 offset1:4 s_mov_b32 s11, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_f32_e32 v6, v7 s_cbranch_execz .LBB0_8 ; %bb.7: ; in Loop: Header=BB0_6 Depth=2 v_add_nc_u32_e32 v6, 16, v4 ds_load_b128 v[6:9], v6 ds_load_b128 v[10:13], v4 s_waitcnt lgkmcnt(1) ds_store_b128 v4, v[6:9] s_waitcnt lgkmcnt(1) ds_store_b128 v4, v[10:13] offset:16 .LBB0_8: ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s11 v_add_nc_u32_e32 v5, s1, v5 v_add_nc_u32_e32 v4, s6, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_i32_e64 s0, s8, v5 s_or_b32 s10, s0, s10 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s10 s_cbranch_execnz .LBB0_6 .LBB0_9: ; %Flow32 ; in Loop: Header=BB0_4 Depth=1 s_or_b32 exec_lo, exec_lo, s9 s_add_i32 s0, s7, 1 s_cmp_eq_u32 s7, s5 s_mov_b32 s7, s0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_4 .LBB0_10: ; %._crit_edge26 s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB0_12 ; %bb.11: ds_load_b128 v[3:6], v3 v_lshlrev_b64 v[0:1], 4, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt lgkmcnt(0) global_store_b128 v[0:1], v[3:6], off .LBB0_12: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi, .Lfunc_end0-_Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 424 ; NumSgprs: 18 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13initParticlesP15HIP_vector_typeIfLj4EEi ; -- Begin function _Z13initParticlesP15HIP_vector_typeIfLj4EEi .globl _Z13initParticlesP15HIP_vector_typeIfLj4EEi .p2align 8 .type _Z13initParticlesP15HIP_vector_typeIfLj4EEi,@function _Z13initParticlesP15HIP_vector_typeIfLj4EEi: ; @_Z13initParticlesP15HIP_vector_typeIfLj4EEi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20) v_cmp_gt_i32_e32 vcc_lo, s3, v1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB1_2 ; %bb.1: v_add_co_u32 v0, vcc_lo, s2, v1 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v0, 0x2c7f967f, v0 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v0, 0x493c4aa1, v0 v_xor_b32_e32 v3, 0xa03697cb, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v3, 0x7b99840d, v3 v_add_nc_u32_e32 v4, 0x75bcd15, v0 v_add_nc_u32_e32 v6, 0x583f19, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v5, 2, v4 v_lshlrev_b32_e32 v7, 4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_xor_b32_e32 v4, v5, v4 v_xor_b32_e32 v5, 0x159a55e5, v0 v_add3_u32 v0, v0, v3, 0x64f0c9 v_lshlrev_b32_e32 v8, 1, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v9, 2, v5 v_xor_b32_e32 v7, v7, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v5, v9, v5 v_xor3_b32 v4, v7, v6, v4 v_add_nc_u32_e32 v6, 0x1f123bb5, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v7, 1, v5 v_lshlrev_b32_e32 v8, 4, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v9, 2, v6 v_xor_b32_e32 v7, v7, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v6, v9, v6 v_xor3_b32 v5, v7, v5, v4 v_xor_b32_e32 v7, 0x5491333, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b32_e32 v8, 1, v6 v_add3_u32 v4, v0, v4, 0x587c5 v_lshlrev_b32_e32 v9, 4, v5 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v10, 2, v7 v_xor_b32_e32 v8, v8, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v7, v10, v7 v_xor3_b32 v6, v8, v6, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v8, 1, v7 v_add3_u32 v5, v0, v5, 0xb0f8a v_lshlrev_b32_e32 v9, 4, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v8, v8, v9 v_xor3_b32 v3, v8, v7, v6 v_add3_u32 v6, v0, v6, 0x10974f v_cvt_f32_u32_e32 v7, v5 s_delay_alu instid0(VALU_DEP_3) v_add3_u32 v0, v0, v3, 0x161f14 v_cvt_f32_u32_e32 v3, v4 v_lshlrev_b64 v[4:5], 4, v[1:2] v_cvt_f32_u32_e32 v6, v6 v_fmaak_f32 v1, 0x2f800000, v7, 0x2f800000 v_cvt_f32_u32_e32 v8, v0 v_fmaak_f32 v0, 0x2f800000, v3, 0x2f800000 s_delay_alu instid0(VALU_DEP_4) v_fmaak_f32 v2, 0x2f800000, v6, 0x2f800000 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s0, v4 v_fmaak_f32 v3, 0x2f800000, v8, 0x2f800000 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo global_store_b128 v[4:5], v[0:3], off .LBB1_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13initParticlesP15HIP_vector_typeIfLj4EEi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z13initParticlesP15HIP_vector_typeIfLj4EEi, .Lfunc_end1-_Z13initParticlesP15HIP_vector_typeIfLj4EEi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 496 ; NumSgprs: 18 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13initParticlesP15HIP_vector_typeIfLj4EEi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13initParticlesP15HIP_vector_typeIfLj4EEi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0012cc73_00000000-6_cuda_code_080759.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3852: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3852: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4509: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4509: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i .type _Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i, @function _Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i: .LFB3874: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z12bubbleSort4DP6float4i(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L3: movq 104(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3874: .size _Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i, .-_Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i .globl _Z12bubbleSort4DP6float4i .type _Z12bubbleSort4DP6float4i, @function _Z12bubbleSort4DP6float4i: .LFB3875: .cfi_startproc endbr64 jmp _Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i .cfi_endproc .LFE3875: .size _Z12bubbleSort4DP6float4i, .-_Z12bubbleSort4DP6float4i .globl _Z40__device_stub__Z13initParticlesP6float4iP6float4i .type _Z40__device_stub__Z13initParticlesP6float4iP6float4i, @function _Z40__device_stub__Z13initParticlesP6float4iP6float4i: .LFB3876: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L9 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z13initParticlesP6float4i(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L9: movq 104(%rsp), %rax subq %fs:40, %rax je .L11 call __stack_chk_fail@PLT .L11: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3876: .size _Z40__device_stub__Z13initParticlesP6float4iP6float4i, .-_Z40__device_stub__Z13initParticlesP6float4iP6float4i .globl _Z13initParticlesP6float4i .type _Z13initParticlesP6float4i, @function _Z13initParticlesP6float4i: .LFB3877: .cfi_startproc endbr64 jmp _Z40__device_stub__Z13initParticlesP6float4iP6float4i .cfi_endproc .LFE3877: .size _Z13initParticlesP6float4i, .-_Z13initParticlesP6float4i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate memory on device: " .LC1: .string "Failed to initialize particles: " .LC2: .string "Failed to sort particles: " .LC3: .string "Failed to copy data from device to host: " .LC4: .string "Sorted particles:" .LC5: .string "(" .LC6: .string ", " .LC7: .string ")" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3849: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movl $16384, %esi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi call cudaMalloc@PLT testl %eax, %eax je .L15 movl %eax, %ebx leaq .LC0(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L16 .L15: movl $16777217, %edx movl $1073741825, %edi xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx salq $2, %rdi movl $1, %ecx movl $1, %esi movq %rdx, 28(%rsp) movl $1, 36(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L17 movq 8(%rsp), %rdi movl $1024, %esi call _Z40__device_stub__Z13initParticlesP6float4iP6float4i .L17: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L18 leaq .LC1(%rip), %rsi .L27: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi call cudaFree@PLT .L16: orl $-1, %eax jmp .L14 .L18: movl $16777217, %edx xorl %r9d, %r9d movl $1, %ecx movabsq $4294967297, %rdi salq $8, %rdx movl $4096, %r8d movl $1, %esi movl $1, 36(%rsp) movq %rdx, 28(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L20 movq 8(%rsp), %rdi movl $1024, %esi call _Z39__device_stub__Z12bubbleSort4DP6float4iP6float4i .L20: call cudaGetLastError@PLT leaq .LC2(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L27 movl $16384, %edi call malloc@PLT movq 8(%rsp), %rsi movl $2, %ecx movl $16384, %edx movq %rax, %rdi movq %rax, %rbx call cudaMemcpy@PLT movl %eax, %ebp testl %eax, %eax je .L22 leaq .LC3(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %edi movq %rax, %r12 call cudaGetErrorString@PLT movq %r12, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call free@PLT jmp .L16 .L22: leaq _ZSt4cout(%rip), %r12 leaq .LC4(%rip), %rsi movq %rbx, %rbp movq %r12, %rdi leaq 16384(%rbx), %r15 leaq .LC5(%rip), %r13 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 .L23: movq %r13, %rsi movq %r12, %rdi leaq .LC6(%rip), %r14 addq $16, %rbp call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -16(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %r14, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -12(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %r14, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -8(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %r14, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd -4(%rbp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT leaq .LC7(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 cmpq %r15, %rbp jne .L23 movq %rbx, %rdi call free@PLT movq 8(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L14: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L24 call __stack_chk_fail@PLT .L24: addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3849: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z13initParticlesP6float4i" .LC9: .string "_Z12bubbleSort4DP6float4i" .LC10: .string "precalc_xorwow_matrix" .LC11: .string "precalc_xorwow_offset_matrix" .LC12: .string "mrg32k3aM1" .LC13: .string "mrg32k3aM2" .LC14: .string "mrg32k3aM1SubSeq" .LC15: .string "mrg32k3aM2SubSeq" .LC16: .string "mrg32k3aM1Seq" .LC17: .string "mrg32k3aM2Seq" .LC18: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3879: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z13initParticlesP6float4i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC9(%rip), %rdx orl $-1, %r8d leaq _Z12bubbleSort4DP6float4i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC10(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC15(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC18(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3879: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_080759.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi # -- Begin function _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi .type _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi,@function _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi: # @_Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi, .Lfunc_end0-_Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi .cfi_endproc # -- End function .globl _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi # -- Begin function _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi .type _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi,@function _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi: # @_Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z13initParticlesP15HIP_vector_typeIfLj4EEi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi, .Lfunc_end1-_Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsp, %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB2_3 # %bb.1: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $37, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_7 # %bb.2: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_8 .LBB2_3: movabsq $4294967552, %rbx # imm = 0x100000100 leaq -252(%rbx), %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_5 # %bb.4: movq (%rsp), %rdi movl $1024, %esi # imm = 0x400 callq _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi .LBB2_5: callq hipGetLastError testl %eax, %eax je .LBB2_9 # %bb.6: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi jmp .LBB2_13 .LBB2_7: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB2_17 .LBB2_9: leaq -255(%rbx), %rdi movl $4096, %r8d # imm = 0x1000 movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_11 # %bb.10: movq (%rsp), %rdi movl $1024, %esi # imm = 0x400 callq _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi .LBB2_11: callq hipGetLastError testl %eax, %eax je .LBB2_19 # %bb.12: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi .LBB2_13: callq hipGetErrorString testq %rax, %rax je .LBB2_15 # %bb.14: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_16 .LBB2_15: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit41 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi callq hipFree .LBB2_17: movl $-1, %eax .LBB2_18: addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_19: .cfi_def_cfa_offset 48 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %rbx movq (%rsp), %rsi movl $16384, %edx # imm = 0x4000 movq %rax, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_22 # %bb.20: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $41, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_25 # %bb.21: movq %rax, %r14 movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_26 .LBB2_22: movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $12, %r15d .LBB2_23: # =>This Inner Loop Header: Depth=1 movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd -12(%rbx,%r15), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r14 movl $.L.str.6, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd -8(%rbx,%r15), %xmm0 movq %r14, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r14 movl $.L.str.6, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd -4(%rbx,%r15), %xmm0 movq %r14, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r14 movl $.L.str.6, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd (%rbx,%r15), %xmm0 movq %r14, %rdi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r14 movl $.L.str.7, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r14), %rax movq -24(%rax), %rdi addq %r14, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r14, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv addq $16, %r15 cmpq $16396, %r15 # imm = 0x400C jne .LBB2_23 # %bb.24: movq %rbx, %rdi callq free movq (%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB2_18 .LBB2_25: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_26: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45 movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq free jmp .LBB2_17 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13initParticlesP15HIP_vector_typeIfLj4EEi, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi,@object # @_Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .section .rodata,"a",@progbits .globl _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .p2align 3, 0x0 _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi: .quad _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi .size _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi, 8 .type _Z13initParticlesP15HIP_vector_typeIfLj4EEi,@object # @_Z13initParticlesP15HIP_vector_typeIfLj4EEi .globl _Z13initParticlesP15HIP_vector_typeIfLj4EEi .p2align 3, 0x0 _Z13initParticlesP15HIP_vector_typeIfLj4EEi: .quad _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi .size _Z13initParticlesP15HIP_vector_typeIfLj4EEi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate memory on device: " .size .L.str, 38 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to initialize particles: " .size .L.str.1, 33 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to sort particles: " .size .L.str.2, 27 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy data from device to host: " .size .L.str.3, 42 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Sorted particles:" .size .L.str.4, 18 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "(" .size .L.str.5, 2 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz ", " .size .L.str.6, 3 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz ")" .size .L.str.7, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi" .size .L__unnamed_1, 43 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z13initParticlesP15HIP_vector_typeIfLj4EEi" .size .L__unnamed_2, 44 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__bubbleSort4DP15HIP_vector_typeIfLj4EEi .addrsig_sym _Z28__device_stub__initParticlesP15HIP_vector_typeIfLj4EEi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12bubbleSort4DP15HIP_vector_typeIfLj4EEi .addrsig_sym _Z13initParticlesP15HIP_vector_typeIfLj4EEi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
7,775
7,490
113,486
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R14, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R14, R14, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R14, c[0x0][0x188], PT ; @P0 EXIT ; HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; LDG.E R19, [R2.64] ; LDG.E R16, [R2.64+0x4] ; BSSY B0, 0xe20 ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; SHF.R.S32.HI R17, RZ, 0x1f, R14 ; ISETP.GT.AND P0, PT, R16, R19, PT ; @!P0 BRA 0xe10 ; IADD3 R0, -R19, R16, RZ ; BSSY B1, 0x310 ; LOP3.LUT R3, RZ, R19, RZ, 0x33, !PT ; LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ; IADD3 R3, R16, R3, RZ ; MOV R8, RZ ; ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; @!P1 BRA 0x300 ; IMAD.WIDE R2, R19, R15, c[0x0][0x168] ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; IMAD.WIDE R4, R19, R15, c[0x0][0x170] ; MOV R9, R2 ; MOV R12, R3 ; MOV R7, R4 ; MOV R10, R5 ; MOV R4, R9 ; MOV R5, R12 ; LDG.E R2, [R4.64] ; MOV R4, R7 ; MOV R5, R10 ; LDG.E R6, [R4.64] ; IMAD.WIDE R2, R2, R15, c[0x0][0x178] ; LDG.E R3, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P1, PT, R0, RZ, PT ; IADD3 R9, P2, R9, 0x4, RZ ; IADD3 R7, P3, R7, 0x4, RZ ; IADD3 R19, R19, 0x1, RZ ; IADD3.X R12, RZ, R12, RZ, P2, !PT ; IADD3.X R10, RZ, R10, RZ, P3, !PT ; FFMA R8, R3, R6, R8 ; @P1 BRA 0x1f0 ; BSYNC B1 ; @!P0 BRA 0xe10 ; IADD3 R0, R16, -R19, RZ ; IMAD.WIDE R2, R19, R15, c[0x2][0x0] ; BSSY B1, 0x970 ; ISETP.GT.AND P1, PT, R0, 0xc, PT ; IADD3 R4, P0, R2.reuse, c[0x0][0x170], RZ ; IADD3 R6, P2, R2, c[0x0][0x168], RZ ; IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; IADD3.X R7, R3, c[0x0][0x16c], RZ, P2, !PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x960 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R18, R16, -0xc, RZ ; LDG.E R24, [R6.64+-0x8] ; LDG.E R10, [R6.64+-0x4] ; LDG.E R20, [R6.64] ; LDG.E R22, [R6.64+0x4] ; LDG.E R26, [R6.64+0x8] ; LDG.E R3, [R4.64+-0x8] ; LDG.E R12, [R4.64+-0x4] ; LDG.E R13, [R6.64+0xc] ; LDG.E R28, [R6.64+0x10] ; LDG.E R29, [R4.64] ; LDG.E R2, [R4.64+0x4] ; IMAD.WIDE R24, R24, R15, c[0x0][0x178] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R0, [R24.64] ; IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x178] ; LDG.E R9, [R10.64] ; LDG.E R21, [R20.64] ; IMAD.WIDE R22, R22, R15, c[0x0][0x178] ; LDG.E R24, [R6.64+0x18] ; IMAD.WIDE R26, R26, R15, c[0x0][0x178] ; LDG.E R25, [R22.64] ; LDG.E R20, [R6.64+0x14] ; LDG.E R10, [R26.64] ; LDG.E R11, [R4.64+0x8] ; LDG.E R23, [R4.64+0xc] ; LDG.E R22, [R6.64+0x20] ; LDG.E R26, [R6.64+0x30] ; FFMA R0, R0, R3, R8 ; LDG.E R3, [R4.64+0x14] ; FFMA R0, R9, R12, R0 ; IMAD.WIDE R12, R13, R15, c[0x0][0x178] ; IMAD.WIDE R8, R28, R15, c[0x0][0x178] ; LDG.E R28, [R4.64+0x18] ; FFMA R0, R21, R29, R0 ; LDG.E R21, [R12.64] ; LDG.E R29, [R6.64+0x1c] ; LDG.E R9, [R8.64] ; IMAD.WIDE R12, R20, R15, c[0x0][0x178] ; LDG.E R20, [R4.64+0x10] ; FFMA R0, R25, R2, R0 ; LDG.E R27, [R12.64] ; IMAD.WIDE R24, R24, R15, c[0x0][0x178] ; LDG.E R2, [R6.64+0x24] ; LDG.E R8, [R6.64+0x28] ; FFMA R12, R10, R11, R0 ; LDG.E R11, [R24.64] ; LDG.E R10, [R6.64+0x2c] ; LDG.E R0, [R6.64+0x34] ; LDG.E R24, [R4.64+0x20] ; LDG.E R25, [R4.64+0x24] ; FFMA R21, R21, R23, R12 ; LDG.E R23, [R4.64+0x1c] ; IMAD.WIDE R12, R29, R15, c[0x0][0x178] ; LDG.E R29, [R4.64+0x28] ; FFMA R9, R9, R20, R21 ; IMAD.WIDE R20, R22, R15, c[0x0][0x178] ; LDG.E R22, [R12.64] ; FFMA R27, R27, R3, R9 ; IMAD.WIDE R2, R2, R15.reuse, c[0x0][0x178] ; LDG.E R21, [R20.64] ; IMAD.WIDE R8, R8, R15, c[0x0][0x178] ; LDG.E R2, [R2.64] ; FFMA R28, R11, R28, R27 ; LDG.E R8, [R8.64] ; IMAD.WIDE R10, R10, R15, c[0x0][0x178] ; LDG.E R20, [R4.64+0x2c] ; IMAD.WIDE R12, R26, R15, c[0x0][0x178] ; LDG.E R11, [R10.64] ; IMAD.WIDE R26, R0, R15, c[0x0][0x178] ; LDG.E R13, [R12.64] ; LDG.E R0, [R4.64+0x30] ; LDG.E R26, [R26.64] ; LDG.E R3, [R4.64+0x34] ; IADD3 R19, R19, 0x10, RZ ; ISETP.GE.AND P1, PT, R19, R18, PT ; IADD3 R6, P3, R6, 0x40, RZ ; IADD3 R9, P2, R4, 0x40, RZ ; IADD3.X R7, RZ, R7, RZ, P3, !PT ; IADD3.X R5, RZ, R5, RZ, P2, !PT ; MOV R4, R9 ; FFMA R22, R22, R23, R28 ; FFMA R21, R21, R24, R22 ; FFMA R2, R2, R25, R21 ; FFMA R2, R8, R29, R2 ; FFMA R2, R11, R20, R2 ; FFMA R0, R13, R0, R2 ; FFMA R8, R26, R3, R0 ; @!P1 BRA 0x3e0 ; BSYNC B1 ; IADD3 R0, R16, -R19, RZ ; BSSY B1, 0xcb0 ; ISETP.GT.AND P1, PT, R0, 0x4, PT ; @!P1 BRA 0xca0 ; LDG.E R22, [R6.64+-0x8] ; LDG.E R28, [R6.64+-0x4] ; LDG.E R2, [R6.64] ; LDG.E R3, [R6.64+0x4] ; LDG.E R10, [R6.64+0x8] ; LDG.E R12, [R6.64+0xc] ; LDG.E R20, [R6.64+0x10] ; LDG.E R24, [R6.64+0x14] ; LDG.E R0, [R4.64+-0x8] ; LDG.E R18, [R4.64+-0x4] ; LDG.E R27, [R4.64] ; IMAD.WIDE R22, R22, R15, c[0x0][0x178] ; IMAD.WIDE R28, R28, R15.reuse, c[0x0][0x178] ; LDG.E R9, [R22.64] ; LDG.E R25, [R28.64] ; IMAD.WIDE R22, R2, R15, c[0x0][0x178] ; IMAD.WIDE R2, R3, R15.reuse, c[0x0][0x178] ; LDG.E R26, [R22.64] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R29, [R4.64+0xc] ; LDG.E R2, [R2.64] ; IMAD.WIDE R12, R12, R15, c[0x0][0x178] ; LDG.E R10, [R10.64] ; IMAD.WIDE R20, R20, R15, c[0x0][0x178] ; LDG.E R12, [R12.64] ; LDG.E R3, [R4.64+0x4] ; LDG.E R11, [R4.64+0x8] ; IMAD.WIDE R22, R24, R15, c[0x0][0x178] ; LDG.E R20, [R20.64] ; LDG.E R24, [R4.64+0x10] ; LDG.E R22, [R22.64] ; LDG.E R28, [R4.64+0x14] ; IADD3 R6, P2, R6, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R7, RZ, R7, RZ, P2, !PT ; IADD3 R19, R19, 0x8, RZ ; FFMA R0, R9, R0, R8 ; FFMA R0, R25, R18, R0 ; FFMA R0, R26, R27, R0 ; FFMA R0, R2, R3, R0 ; FFMA R0, R10, R11, R0 ; FFMA R29, R12, R29, R0 ; IADD3 R0, P1, R4, 0x20, RZ ; FFMA R29, R20, R24, R29 ; IADD3.X R5, RZ, R5, RZ, P1, !PT ; MOV R4, R0 ; FFMA R8, R22, R28, R29 ; BSYNC B1 ; ISETP.LT.OR P0, PT, R19, R16, P0 ; @!P0 BRA 0xe10 ; LDG.E R2, [R6.64+-0x8] ; LDG.E R10, [R6.64+-0x4] ; LDG.E R12, [R6.64] ; LDG.E R18, [R6.64+0x4] ; LDG.E R0, [R4.64+-0x8] ; LDG.E R9, [R4.64+-0x4] ; LDG.E R6, [R4.64+0x4] ; IMAD.WIDE R2, R2, R15, c[0x0][0x178] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R3, [R2.64] ; IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x178] ; LDG.E R11, [R10.64] ; IMAD.WIDE R18, R18, R15, c[0x0][0x178] ; LDG.E R13, [R12.64] ; LDG.E R15, [R4.64] ; LDG.E R19, [R18.64] ; FFMA R0, R3, R0, R8 ; FFMA R0, R11, R9, R0 ; FFMA R0, R13, R15, R0 ; FFMA R8, R19, R6, R0 ; BSYNC B0 ; LEA R2, P0, R14, c[0x0][0x180], 0x2 ; LEA.HI.X R3, R14, c[0x0][0x184], R17, 0x2, P0 ; STG.E [R2.64], R8 ; EXIT ; BRA 0xe60; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi ; -- Begin function _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .globl _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .p2align 8 .type _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi,@function _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi: ; @_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x3c s_load_b32 s3, s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_6 ; %bb.1: s_load_b256 s[4:11], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[2:3], s[0:1], 0x20 v_mov_b32_e32 v8, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_cmpx_lt_i32_e64 v2, v3 s_cbranch_execz .LBB0_5 ; %bb.2: ; %.lr.ph.preheader v_ashrrev_i32_e32 v5, 31, v2 v_mov_b32_e32 v4, v2 v_mov_b32_e32 v8, 0 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[4:5] v_add_co_u32 v4, vcc_lo, s8, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo v_add_co_u32 v6, vcc_lo, s6, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b32 v9, v[6:7], off v_add_nc_u32_e32 v2, 1, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s0, v2, v3 s_or_b32 s4, s0, s4 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v10, 31, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[9:10], 2, v[9:10] v_add_co_u32 v9, vcc_lo, s10, v9 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo global_load_b32 v11, v[4:5], off global_load_b32 v9, v[9:10], off v_add_co_u32 v4, vcc_lo, v4, 4 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo v_add_co_u32 v6, vcc_lo, v6, 4 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo s_waitcnt vmcnt(0) v_fmac_f32_e32 v8, v11, v9 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_3 ; %bb.4: ; %Flow s_or_b32 exec_lo, exec_lo, s4 .LBB0_5: ; %Flow47 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v8, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi, .Lfunc_end0-_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 364 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00142f97_00000000-6_cuda_code_067941.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi .type _Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi, @function _Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi: .LFB3660: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) leaq 72(%rsp), %rdi movq %rsi, 32(%rsp) leaq 84(%rsp), %rsi movq %rdx, 24(%rsp) leaq 56(%rsp), %rdx movq %rcx, 16(%rsp) leaq 64(%rsp), %rcx movq %r8, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 80(%rsp) movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 4(%rsp), %rax movq %rax, 160(%rsp) movabsq $4294967297, %rax movq %rax, 72(%rsp) movq %rax, 84(%rsp) movl $1, 92(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 64(%rsp) .cfi_def_cfa_offset 200 leaq _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi(%rip), %rdi pushq 64(%rsp) .cfi_def_cfa_offset 208 movq 100(%rsp), %rcx movl 108(%rsp), %r8d movq 88(%rsp), %rsi movl 96(%rsp), %edx leaq 136(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 200 popq %rdx .cfi_def_cfa_offset 192 .L2: movq 168(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $184, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi, .-_Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi .globl _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .type _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi, @function _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi: .LFB3661: .cfi_startproc endbr64 jmp _Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi .cfi_endproc .LFE3661: .size _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi, .-_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "CUDA error: " .LC2: .string "Result vector y: " .LC3: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $20, %esi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $504, %rsp .cfi_def_cfa_offset 544 movq %fs:40, %rax movq %rax, 488(%rsp) movabsq $4294967296, %rax movq %rsp, %rdi movl $3, 116(%rsp) movl $4, 372(%rsp) movq $3, 108(%rsp) movl $0x41000000, 244(%rsp) movq %rax, 356(%rsp) movabsq $8589934593, %rax movq %rax, 364(%rsp) decq %rax movq %rax, 100(%rsp) movabsq $4656722015783223296, %rax movq %rax, 228(%rsp) movabsq $4674736414296899584, %rax movq %rax, 236(%rsp) movabsq $4575657222473777152, %rax movq %rax, 68(%rsp) movq %rax, 76(%rsp) call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT movq (%rsp), %rdi xorl %r8d, %r8d leaq 356(%rsp), %rsi movl $1, %ecx movl $20, %edx call cudaMemcpyAsync@PLT movq 8(%rsp), %rdi xorl %r8d, %r8d leaq 100(%rsp), %rsi movl $1, %ecx movl $32, %edx call cudaMemcpyAsync@PLT movq 16(%rsp), %rdi xorl %r8d, %r8d leaq 228(%rsp), %rsi movl $1, %ecx movl $32, %edx call cudaMemcpyAsync@PLT movq 24(%rsp), %rdi xorl %r8d, %r8d leaq 68(%rsp), %rsi movl $1, %ecx movl $16, %edx call cudaMemcpyAsync@PLT movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d salq $8, %rdx movl $1, %ecx movabsq $4294967297, %rdi movl $1, %esi movq %rdx, 56(%rsp) movl $1, 64(%rsp) movq %rdi, 44(%rsp) movl $1, 52(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L9 movq 32(%rsp), %r8 movq 24(%rsp), %rcx movl $4, %r9d movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z48__device_stub__Z15spmv_csr_kernelPKiS0_PKfS2_PfiPKiS0_PKfS2_Pfi .L9: movq 32(%rsp), %rsi leaq 84(%rsp), %r12 xorl %r8d, %r8d movl $2, %ecx movl $16, %edx movq %r12, %rdi call cudaMemcpyAsync@PLT call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L10 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L10: leaq _ZSt4cout(%rip), %rbp leaq .LC2(%rip), %rsi xorl %ebx, %ebx movq %rbp, %rdi leaq .LC3(%rip), %r13 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L12: movq %rbp, %rdi cvtss2sd (%r12,%rbx,4), %xmm0 incq %rbx call _ZNSo9_M_insertIdEERSoT_@PLT movq %r13, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $4, %rbx jne .L12 movq %rbp, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L8: movq 488(%rsp), %rdx subq %fs:40, %rdx je .L13 call __stack_chk_fail@PLT .L13: addq $504, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC4(%rip), %rdx movq %rax, %rdi leaq _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_067941.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi # -- Begin function _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi .type _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi,@function _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi: # @_Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 4(%rsp), %r8 movl %r9d, (%r8) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) movq %r8, 40(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi, .Lfunc_end0-_Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .long 0 # 0x0 .long 1 # 0x1 .long 1 # 0x1 .long 2 # 0x2 .LCPI1_1: .long 0 # 0x0 .long 2 # 0x2 .long 3 # 0x3 .long 0 # 0x0 .LCPI1_2: .long 0x40800000 # float 4 .long 0x40a00000 # float 5 .long 0x40c00000 # float 6 .long 0x40e00000 # float 7 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $480, %rsp # imm = 0x1E0 .cfi_def_cfa_offset 528 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rsp, %r13 movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [0,1,1,2] movaps %xmm0, 336(%rsp) movl $4, 352(%rsp) movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [0,2,3,0] movaps %xmm0, 208(%rsp) movl $3, 224(%rsp) movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0] movaps %xmm0, 80(%rsp) movl $1090519040, 96(%rsp) # imm = 0x41000000 xorl %eax, %eax .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, 64(%rsp,%rax,4) # imm = 0x3F800000 incq %rax cmpq $4, %rax jne .LBB1_1 # %bb.2: leaq 40(%rsp), %r12 movl $20, %esi movq %r12, %rdi callq hipMalloc leaq 32(%rsp), %r15 movl $32, %esi movq %r15, %rdi callq hipMalloc leaq 24(%rsp), %r14 movl $32, %esi movq %r14, %rdi callq hipMalloc leaq 16(%rsp), %rbx movl $16, %esi movq %rbx, %rdi callq hipMalloc leaq 8(%rsp), %rdi movl $16, %esi callq hipMalloc movq (%r12), %rdi leaq 336(%rsp), %rsi movl $20, %edx movl $1, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movq (%r15), %rdi leaq 208(%rsp), %rsi movl $32, %edx movl $1, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movq (%r14), %rdi leaq 80(%rsp), %rsi movl $32, %edx movl $1, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movq (%rbx), %rdi leaq 64(%rsp), %rsi movl $16, %edx movl $1, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 40(%rsp), %rdi movq 32(%rsp), %rsi movq 24(%rsp), %rdx movq 16(%rsp), %rcx movq 8(%rsp), %r8 movl $4, %r9d callq _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi .LBB1_4: movq 8(%rsp), %rsi leaq 48(%rsp), %rdi movl $16, %edx movl $2, %ecx xorl %r8d, %r8d callq hipMemcpyAsync callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax je .LBB1_9 # %bb.5: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_6 # %bb.7: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_8 .LBB1_9: movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %ebx, %ebx .LBB1_10: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtss2sd 48(%rsp,%rbx,4), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %rbx cmpq $4, %rbx jne .LBB1_10 # %bb.11: movq _ZSt4cout(%rip), %rax movl $_ZSt4cout, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_12 .LBB1_6: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_12: movq %r13, %rsp addq $480, %rsp # imm = 0x1E0 .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi,@object # @_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .section .rodata,"a",@progbits .globl _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .p2align 3, 0x0 _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi: .quad _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi .size _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Result vector y: " .size .L.str.1, 18 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz " " .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15spmv_csr_kernelPKiS0_PKfS2_Pfi" .size .L__unnamed_1, 35 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__spmv_csr_kernelPKiS0_PKfS2_Pfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15spmv_csr_kernelPKiS0_PKfS2_Pfi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,152
5,234
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z9dfsKernelPiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; @P0 EXIT ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; MOV R8, c[0x0][0x168] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; MOV R20, 0xe0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0xf0 ; EXIT ; IADD3 R1, R1, -0x48, RZ ; STL [R1+0x44], R37 ; STL [R1+0x40], R36 ; STL [R1+0x3c], R31 ; STL [R1+0x38], R30 ; STL [R1+0x34], R29 ; IMAD.MOV.U32 R31, RZ, RZ, R7 ; STL [R1+0x30], R28 ; MOV R30, R6 ; STL [R1+0x2c], R26 ; IMAD.MOV.U32 R29, RZ, RZ, R9 ; STL [R1+0x28], R25 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; STL [R1+0x24], R24 ; STL [R1+0x20], R23 ; BMOV.32.CLEAR R25, B8 ; STL [R1+0x1c], R22 ; BMOV.32.CLEAR R24, B7 ; STL [R1+0x18], R21 ; STL [R1+0x14], R20 ; BMOV.32.CLEAR R22, B6 ; STL [R1+0x10], R19 ; STL [R1+0xc], R18 ; STL [R1+0x8], R17 ; STL [R1+0x4], R16 ; STL [R1], R2 ; IMAD.MOV.U32 R17, RZ, RZ, R4 ; MOV R2, R5 ; IMAD.WIDE R4, R17, 0x4, R30 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R0, [R4.64] ; BSSY B8, 0xac0 ; IMAD.MOV.U32 R23, RZ, RZ, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @P0 BRA 0xab0 ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; ULDC.64 UR4, c[0x0][0x118] ; HFMA2.MMA R23, -RZ, RZ, 0, 5.9604644775390625e-08 ; STG.E [R4.64], R3 ; @!P0 BRA 0xab0 ; IADD3 R0, R2.reuse, -0x1, RZ ; BSSY B7, 0x8f0 ; LOP3.LUT R19, R2, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R23, RZ, RZ, 0x1 ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; @!P0 BRA 0x8e0 ; IMAD R5, R17, R2.reuse, RZ ; IADD3 R16, -R19, R2, RZ ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; MOV R23, 0x1 ; IMAD.WIDE R4, R5, 0x4, R28 ; IMAD.MOV.U32 R36, RZ, RZ, R4 ; IMAD.MOV.U32 R37, RZ, RZ, R5 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R0, [R36.64] ; IADD3 R16, R16, -0x4, RZ ; BSSY B6, 0x590 ; ISETP.NE.AND P1, PT, R16, RZ, PT ; P2R R26, PR, RZ, 0x2 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 BRA 0x580 ; IMAD.MOV.U32 R4, RZ, RZ, R18 ; MOV R6, R30 ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; MOV R9, R29 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; MOV R20, 0x570 ; IMAD.MOV.U32 R5, RZ, RZ, R2 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0xf0 ; IADD3 R23, R23, R4, RZ ; BSYNC B6 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R0, [R36.64+0x4] ; BSSY B6, 0x690 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 BRA 0x680 ; HFMA2.MMA R21, -RZ, RZ, 0, 0 ; IADD3 R4, R18, 0x1, RZ ; IMAD.MOV.U32 R6, RZ, RZ, R30 ; MOV R8, R28 ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; MOV R20, 0x670 ; IMAD.MOV.U32 R9, RZ, RZ, R29 ; IMAD.MOV.U32 R5, RZ, RZ, R2 ; CALL.REL.NOINC 0xf0 ; IMAD.IADD R23, R23, 0x1, R4 ; BSYNC B6 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R0, [R36.64+0x8] ; BSSY B6, 0x790 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 BRA 0x780 ; IADD3 R4, R18, 0x2, RZ ; IMAD.MOV.U32 R6, RZ, RZ, R30 ; MOV R7, R31 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; MOV R5, R2 ; IMAD.MOV.U32 R9, RZ, RZ, R29 ; MOV R20, 0x770 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0xf0 ; IMAD.IADD R23, R23, 0x1, R4 ; BSYNC B6 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R0, [R36.64+0xc] ; BSSY B6, 0x890 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 BRA 0x880 ; IADD3 R4, R18, 0x3, RZ ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; MOV R6, R30 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; MOV R9, R29 ; IMAD.MOV.U32 R5, RZ, RZ, R2 ; MOV R20, 0x870 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0xf0 ; IADD3 R23, R23, R4, RZ ; BSYNC B6 ; ISETP.NE.AND P1, PT, R26, RZ, PT ; IADD3 R36, P0, R36, 0x10, RZ ; IADD3 R18, R18, 0x4, RZ ; IMAD.X R37, RZ, RZ, R37, P0 ; @P1 BRA 0x460 ; BSYNC B7 ; ISETP.NE.AND P0, PT, R19, RZ, PT ; @!P0 BRA 0xab0 ; IMAD R3, R17, R2, R18 ; MOV R17, R29 ; IMAD.MOV.U32 R16, RZ, RZ, R28 ; IMAD.WIDE R16, R3, 0x4, R16 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R0, [R16.64] ; BSSY B6, 0xa50 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 BRA 0xa40 ; IMAD.MOV.U32 R4, RZ, RZ, R18 ; MOV R7, R31 ; IMAD.MOV.U32 R6, RZ, RZ, R30 ; MOV R5, R2 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; MOV R20, 0xa30 ; IMAD.MOV.U32 R9, RZ, RZ, R29 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0xf0 ; IMAD.IADD R23, R23, 0x1, R4 ; BSYNC B6 ; IADD3 R19, R19, -0x1, RZ ; IADD3 R16, P1, R16, 0x4, RZ ; ISETP.NE.AND P0, PT, R19, RZ, PT ; IADD3 R18, R18, 0x1, RZ ; IADD3.X R17, RZ, R17, RZ, P1, !PT ; @P0 BRA 0x950 ; BSYNC B8 ; LDL R20, [R1+0x14] ; BMOV.32 B6, R22 ; BMOV.32 B7, R24 ; BMOV.32 B8, R25 ; LDL R21, [R1+0x18] ; IMAD.MOV.U32 R4, RZ, RZ, R23 ; LDL R2, [R1] ; LDL R16, [R1+0x4] ; LDL R17, [R1+0x8] ; LDL R18, [R1+0xc] ; LDL R19, [R1+0x10] ; LDL R22, [R1+0x1c] ; LDL R23, [R1+0x20] ; LDL R24, [R1+0x24] ; LDL R25, [R1+0x28] ; LDL R26, [R1+0x2c] ; LDL R28, [R1+0x30] ; LDL R29, [R1+0x34] ; LDL R30, [R1+0x38] ; LDL R31, [R1+0x3c] ; LDL R36, [R1+0x40] ; LDL R37, [R1+0x44] ; IADD3 R1, R1, 0x48, RZ ; RET.REL.NODEC R20 0x0 ; BRA 0xc40; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .p2align 2 ; -- Begin function _Z3dfsiPiS_i .type _Z3dfsiPiS_i,@function _Z3dfsiPiS_i: ; @_Z3dfsiPiS_i ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_mov_b32 s0, s33 s_mov_b32 s33, s32 s_or_saveexec_b32 s1, -1 scratch_store_b32 off, v56, s33 offset:32 ; 4-byte Folded Spill s_mov_b32 exec_lo, s1 v_writelane_b32 v56, s0, 7 s_add_i32 s32, s32, 48 s_clause 0x7 scratch_store_b32 off, v40, s33 offset:28 ; meta instruction scratch_store_b32 off, v41, s33 offset:24 ; meta instruction scratch_store_b32 off, v42, s33 offset:20 ; meta instruction scratch_store_b32 off, v43, s33 offset:16 ; meta instruction scratch_store_b32 off, v44, s33 offset:12 ; meta instruction scratch_store_b32 off, v45, s33 offset:8 ; meta instruction scratch_store_b32 off, v46, s33 offset:4 ; meta instruction scratch_store_b32 off, v47, s33 v_writelane_b32 v56, s34, 0 v_writelane_b32 v56, s35, 1 v_writelane_b32 v56, s36, 2 v_writelane_b32 v56, s37, 3 v_writelane_b32 v56, s38, 4 v_writelane_b32 v56, s30, 5 v_writelane_b32 v56, s31, 6 v_dual_mov_b32 v42, v1 :: v_dual_mov_b32 v43, v4 v_ashrrev_i32_e32 v1, 31, v0 v_dual_mov_b32 v40, v5 :: v_dual_mov_b32 v41, v2 v_dual_mov_b32 v44, v3 :: v_dual_mov_b32 v45, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[0:1] s_mov_b32 s34, exec_lo v_add_co_u32 v1, vcc_lo, v42, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v41, v2, vcc_lo flat_load_b32 v3, v[1:2] s_waitcnt vmcnt(0) lgkmcnt(0) v_cmpx_eq_u32_e32 0, v3 s_cbranch_execz .LBB0_8 ; %bb.1: v_mov_b32_e32 v45, 1 s_mov_b32 s35, exec_lo flat_store_b32 v[1:2], v45 v_cmpx_lt_i32_e32 0, v40 s_cbranch_execz .LBB0_7 ; %bb.2: ; %.lr.ph v_mul_lo_u32 v0, v40, v0 v_mov_b32_e32 v45, 1 s_mov_b32 s36, 0 s_mov_b32 s37, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v46, vcc_lo, v44, v0 v_add_co_ci_u32_e32 v47, vcc_lo, v43, v1, vcc_lo .LBB0_3: ; =>This Inner Loop Header: Depth=1 flat_load_b32 v0, v[46:47] s_mov_b32 s38, exec_lo s_waitcnt vmcnt(0) lgkmcnt(0) v_cmpx_ne_u32_e32 0, v0 s_cbranch_execz .LBB0_5 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 v_dual_mov_b32 v0, s37 :: v_dual_mov_b32 v1, v42 v_dual_mov_b32 v2, v41 :: v_dual_mov_b32 v3, v44 v_dual_mov_b32 v4, v43 :: v_dual_mov_b32 v5, v40 s_getpc_b64 s[0:1] s_add_u32 s0, s0, _Z3dfsiPiS_i@rel32@lo+4 s_addc_u32 s1, s1, _Z3dfsiPiS_i@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_swappc_b64 s[30:31], s[0:1] v_add_nc_u32_e32 v45, v0, v45 .LBB0_5: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s38 s_add_i32 s37, s37, 1 v_add_co_u32 v46, s0, v46, 4 v_cmp_eq_u32_e32 vcc_lo, s37, v40 v_add_co_ci_u32_e64 v47, s0, 0, v47, s0 s_or_b32 s36, vcc_lo, s36 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s36 s_cbranch_execnz .LBB0_3 ; %bb.6: ; %Flow s_or_b32 exec_lo, exec_lo, s36 .LBB0_7: ; %Flow24 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s35 .LBB0_8: ; %.loopexit s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s34 v_mov_b32_e32 v0, v45 s_clause 0x7 scratch_load_b32 v47, off, s33 scratch_load_b32 v46, off, s33 offset:4 scratch_load_b32 v45, off, s33 offset:8 scratch_load_b32 v44, off, s33 offset:12 scratch_load_b32 v43, off, s33 offset:16 scratch_load_b32 v42, off, s33 offset:20 scratch_load_b32 v41, off, s33 offset:24 scratch_load_b32 v40, off, s33 offset:28 v_readlane_b32 s30, v56, 5 v_readlane_b32 s31, v56, 6 v_readlane_b32 s38, v56, 4 v_readlane_b32 s37, v56, 3 v_readlane_b32 s36, v56, 2 v_readlane_b32 s35, v56, 1 v_readlane_b32 s34, v56, 0 v_readlane_b32 s0, v56, 7 s_or_saveexec_b32 s1, -1 scratch_load_b32 v56, off, s33 offset:32 ; 4-byte Folded Reload s_mov_b32 exec_lo, s1 s_addk_i32 s32, 0xffd0 s_mov_b32 s33, s0 s_waitcnt vmcnt(0) lgkmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end0: .size _Z3dfsiPiS_i, .Lfunc_end0-_Z3dfsiPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 632 ; NumSgprs: 41 ; NumVgprs: 57 ; ScratchSize: 48 ; MemoryBound: 0 .text .protected _Z9dfsKernelPiS_i ; -- Begin function _Z9dfsKernelPiS_i .globl _Z9dfsKernelPiS_i .p2align 8 .type _Z9dfsKernelPiS_i,@function _Z9dfsKernelPiS_i: ; @_Z9dfsKernelPiS_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x24 s_load_b32 s2, s[0:1], 0x10 v_mov_b32_e32 v2, v0 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3] s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v0 s_cbranch_execz .LBB1_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_mov_b32_e32 v5, s2 s_getpc_b64 s[0:1] s_add_u32 s0, s0, _Z3dfsiPiS_i@rel32@lo+4 s_addc_u32 s1, s1, _Z3dfsiPiS_i@rel32@hi+12 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5 v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7 s_swappc_b64 s[30:31], s[0:1] .LBB1_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9dfsKernelPiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 48 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 1 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 57 .amdhsa_next_free_sgpr 39 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z9dfsKernelPiS_i, .Lfunc_end1-_Z9dfsKernelPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 132 ; NumSgprs: 41 ; NumVgprs: 57 ; ScratchSize: 48 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 5 ; VGPRBlocks: 7 ; NumSGPRsForWavesPerEU: 41 ; NumVGPRsForWavesPerEU: 57 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9dfsKernelPiS_i .private_segment_fixed_size: 48 .sgpr_count: 41 .sgpr_spill_count: 0 .symbol: _Z9dfsKernelPiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: true .vgpr_count: 57 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
3,264
4,604
113,491
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0000d4b5_00000000-6_cuda_code_026225.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4017: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE4017: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z3dfsiPiS_i .type _Z3dfsiPiS_i, @function _Z3dfsiPiS_i: .LFB3998: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3998: .size _Z3dfsiPiS_i, .-_Z3dfsiPiS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3999: .cfi_startproc endbr64 testl %edi, %edi je .L4 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L4: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3999: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z31__device_stub__Z9dfsKernelPiS_iPiS_i .type _Z31__device_stub__Z9dfsKernelPiS_iPiS_i, @function _Z31__device_stub__Z9dfsKernelPiS_iPiS_i: .LFB4039: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movq %rsi, 16(%rsp) leaq 60(%rsp), %rsi movl %edx, 12(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L10 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z9dfsKernelPiS_i(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L10: movq 120(%rsp), %rax subq %fs:40, %rax je .L12 call __stack_chk_fail@PLT .L12: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4039: .size _Z31__device_stub__Z9dfsKernelPiS_iPiS_i, .-_Z31__device_stub__Z9dfsKernelPiS_iPiS_i .globl _Z9dfsKernelPiS_i .type _Z9dfsKernelPiS_i, @function _Z9dfsKernelPiS_i: .LFB4040: .cfi_startproc endbr64 jmp _Z31__device_stub__Z9dfsKernelPiS_iPiS_i .cfi_endproc .LFE4040: .size _Z9dfsKernelPiS_i, .-_Z9dfsKernelPiS_i .section .rodata.str1.1 .LC3: .string "cudaMalloc d_visited" .LC4: .string "cudaMalloc d_graph" .LC5: .string "cudaMemcpy graph" .LC6: .string "cudaMemcpy visited" .LC7: .string "dfsKernel launch failed" .LC8: .string "cudaDeviceSynchronize failed" .LC9: .string "cudaMemcpy visited back" .text .globl _Z8dfsOnGPUPiiS_i .type _Z8dfsOnGPUPiiS_i, @function _Z8dfsOnGPUPiiS_i: .LFB4000: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 movq %rdi, %r14 movl %ecx, %edi pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 movq %rdx, %r13 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 movslq %esi, %r12 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %r12, %rbx salq $2, %r12 movl %ebx, %ebp imull %ebx, %ebp subq $48, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call cudaSetDevice@PLT movq %rsp, %rdi movq %r12, %rsi movslq %ebp, %rbp call cudaMalloc@PLT salq $2, %rbp leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 8(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi movq %rbp, %rdx movq %r14, %rsi movl $1, %ecx call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%rsp), %rdi movq %r12, %rdx movq %r13, %rsi movl $1, %ecx call cudaMemcpy@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $256, %ecx xorl %r9d, %r9d xorl %r8d, %r8d leal 255(%rbx), %eax cltd idivl %ecx movl $16777217, %edx movl $1, %ecx salq $8, %rdx movl %eax, 16(%rsp) movabsq $4294967297, %rax movq %rax, 20(%rsp) movq 16(%rsp), %rdi movl 24(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L16 movq 8(%rsp), %rsi movq (%rsp), %rdi movl %ebx, %edx call _Z31__device_stub__Z9dfsKernelPiS_iPiS_i .L16: call cudaGetLastError@PLT leaq .LC7(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc call cudaDeviceSynchronize@PLT leaq .LC8(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%rsp), %rsi movq %r12, %rdx movq %r13, %rdi movl $2, %ecx call cudaMemcpy@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax je .L17 call __stack_chk_fail@PLT .L17: addq $48, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4000: .size _Z8dfsOnGPUPiiS_i, .-_Z8dfsOnGPUPiiS_i .section .rodata.str1.1 .LC10: .string "_Z9dfsKernelPiS_i" .section .text.startup,"ax",@progbits .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4042: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rax, %rdi leaq _Z9dfsKernelPiS_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE4042: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .rodata._ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.str1.1,"aMS",@progbits,1 .LC11: .string "cannot create std::vector larger than max_size()" .section .text._ZNSt6vectorIiSaIiEEC2EmRKiRKS0_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC5EmRKiRKS0_,comdat .align 2 .weak _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_ .type _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_, @function _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_: .LFB4353: .cfi_startproc endbr64 movabsq $2305843009213693951, %rax pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 pushq %rcx .cfi_def_cfa_offset 48 cmpq %rsi, %rax jnb .L22 leaq .LC11(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L22: movq %rdx, %r13 xorl %edx, %edx movq %rdi, %rbx movq %rsi, %rbp movq %rdx, (%rdi) leaq 0(,%rsi,4), %r12 xorl %eax, %eax movq %rdx, 8(%rdi) movq %rdx, 16(%rdi) testq %rsi, %rsi je .L23 movq %r12, %rdi call _Znwm@PLT .L23: addq %rax, %r12 movq %rax, (%rbx) movq %r12, 16(%rbx) testq %rbp, %rbp je .L24 movl 0(%r13), %edx .L25: cmpq %rax, %r12 je .L24 movl %edx, (%rax) addq $4, %rax jmp .L25 .L24: movq %rax, 8(%rbx) popq %rax .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4353: .size _ZNSt6vectorIiSaIiEEC2EmRKiRKS0_, .-_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_ .weak _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .set _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_,_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_ .section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat .align 2 .weak _ZNSt6vectorIiSaIiEED2Ev .type _ZNSt6vectorIiSaIiEED2Ev, @function _ZNSt6vectorIiSaIiEED2Ev: .LFB4356: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L33 movq 16(%rdi), %rsi movq %rax, %rdi subq %rax, %rsi jmp _ZdlPvm@PLT .L33: ret .cfi_endproc .LFE4356: .size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev .weak _ZNSt6vectorIiSaIiEED1Ev .set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev .section .rodata.str1.1 .LC12: .string "Total visited nodes: " .section .text.startup .globl main .type main, @function main: .LFB4001: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4001 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 xorl %edi, %edi movl $4194304, %esi pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $200, %rsp .cfi_def_cfa_offset 256 movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 88(%rsp), %r12 leaq 40(%rsp), %rax movl %edi, 112(%rsp) leaq 112(%rsp), %r13 movq %rax, %rdi movq %r12, %rcx movq %rax, 8(%rsp) movq %r13, %rdx .LEHB0: call _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .LEHE0: movq 40(%rsp), %rbp xorl %eax, %eax .L38: addq $8196, %rax cmpq $16785408, %rax jne .L36 xorl %esi, %esi leaq 64(%rsp), %rax movq %r12, %rcx movq %r13, %rdx movl %esi, 112(%rsp) movq %rax, %rdi movl $2048, %esi movq %rax, 16(%rsp) .LEHB1: call _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ .LEHE1: xorl %ecx, %ecx leaq 136(%rsp), %rbx leaq 35(%rsp), %r15 movq %rcx, 136(%rsp) leaq 184(%rsp), %r14 movq %rcx, 144(%rsp) movq %rcx, 152(%rsp) movq %rcx, 160(%rsp) movq %rcx, 168(%rsp) movq %rcx, 176(%rsp) movq %rbx, 24(%rsp) jmp .L39 .L36: movl $1, -8192(%rbp,%rax) jmp .L38 .L55: movq 88(%rsp), %rsi movq (%rbx), %rcx movq %r13, %rdi addq $24, %rbx movq -16(%rbx), %rdx movq -8(%rbx), %rax movq %rsi, -24(%rbx) movq 96(%rsp), %rsi movq %rax, 128(%rsp) xorl %eax, %eax movq %rsi, -16(%rbx) movq 104(%rsp), %rsi movq %rcx, 112(%rsp) movq %rsi, -8(%rbx) movq %rdx, 120(%rsp) movq %rax, 88(%rsp) movq %rax, 96(%rsp) movq %rax, 104(%rsp) call _ZNSt6vectorIiSaIiEED1Ev movq %r12, %rdi call _ZNSt6vectorIiSaIiEED1Ev cmpq %r14, %rbx je .L54 .L39: xorl %edx, %edx movq %r15, %rcx movl $1024, %esi movq %r12, %rdi movl %edx, 36(%rsp) leaq 36(%rsp), %rdx .LEHB2: call _ZNSt6vectorIiSaIiEEC1EmRKiRKS0_ jmp .L55 .L54: movq 136(%rsp), %r12 xorl %ecx, %ecx movl $1024, %esi movq %rbp, %rdi movq %r12, %rdx call _Z8dfsOnGPUPiiS_i movq 160(%rsp), %rbx movl $1, %ecx movl $1024, %esi leaq 8388608(%rbp), %rdi movq %rbx, %rdx call _Z8dfsOnGPUPiiS_i xorl %eax, %eax xorl %edx, %edx .L40: addl (%r12,%rax,4), %edx incq %rax cmpq $1024, %rax jne .L40 xorl %eax, %eax .L41: addl (%rbx,%rax,4), %edx incq %rax movl %edx, %ebp cmpq $1024, %rax jne .L41 leaq .LC12(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebp, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .LEHE2: leaq 160(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 24(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 16(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 8(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 184(%rsp), %rax subq %fs:40, %rax je .L45 jmp .L52 .L47: endbr64 movq %rax, %rbx .L42: leaq 160(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 24(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 16(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev jmp .L43 .L46: endbr64 movq %rax, %rbx .L43: movq 8(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev movq 184(%rsp), %rax subq %fs:40, %rax jne .L52 movq %rbx, %rdi .LEHB3: call _Unwind_Resume@PLT .LEHE3: .L52: call __stack_chk_fail@PLT .L45: addq $200, %rsp .cfi_def_cfa_offset 56 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4001: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA4001: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4001-.LLSDACSB4001 .LLSDACSB4001: .uleb128 .LEHB0-.LFB4001 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB4001 .uleb128 .LEHE1-.LEHB1 .uleb128 .L46-.LFB4001 .uleb128 0 .uleb128 .LEHB2-.LFB4001 .uleb128 .LEHE2-.LEHB2 .uleb128 .L47-.LFB4001 .uleb128 0 .uleb128 .LEHB3-.LFB4001 .uleb128 .LEHE3-.LEHB3 .uleb128 0 .uleb128 0 .LLSDACSE4001: .section .text.startup .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_026225.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__dfsKernelPiS_i # -- Begin function _Z24__device_stub__dfsKernelPiS_i .type _Z24__device_stub__dfsKernelPiS_i,@function _Z24__device_stub__dfsKernelPiS_i: # @_Z24__device_stub__dfsKernelPiS_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rcx movq %rsi, (%rcx) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z9dfsKernelPiS_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z24__device_stub__dfsKernelPiS_i, .Lfunc_end0-_Z24__device_stub__dfsKernelPiS_i .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl _Z8dfsOnGPUPiiS_i # -- Begin function _Z8dfsOnGPUPiiS_i .type _Z8dfsOnGPUPiiS_i,@function _Z8dfsOnGPUPiiS_i: # @_Z8dfsOnGPUPiiS_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, %r13 movq %rdi, %r12 movl %esi, 12(%rsp) # 4-byte Spill movslq %esi, %r15 leaq (,%r15,4), %r14 movl %r15d, %ebp imull %ebp, %ebp shlq $2, %rbp movl %ecx, %edi callq hipSetDevice movq %rsp, %rdi movq %r14, %rsi callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 16(%rsp), %rbx movq %rbx, %rdi movq %rbp, %rsi callq hipMalloc movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rbx), %rdi movq %r12, %rsi movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rsp, %rax movq (%rax), %rdi movq %r13, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leal 255(%r15), %eax addl $510, %r15d # imm = 0x1FE testl %eax, %eax cmovnsl %eax, %r15d sarl $8, %r15d btsq $32, %r15 movabsq $4294967296, %rdx # imm = 0x100000000 orq $256, %rdx # imm = 0x100 movq %r15, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movq (%rsp), %rdi movq 16(%rsp), %rsi movl 12(%rsp), %edx # 4-byte Reload callq _Z24__device_stub__dfsKernelPiS_i .LBB2_2: callq hipGetLastError movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc callq hipDeviceSynchronize movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rsi movq %r13, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z8dfsOnGPUPiiS_i, .Lfunc_end2-_Z8dfsOnGPUPiiS_i .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: # %.noexc pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $56, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $16777216, %edi # imm = 0x1000000 callq _Znwm movq %rax, %rbx movl $16777216, %edx # imm = 0x1000000 movq %rax, %rdi xorl %esi, %esi callq memset@PLT movq $-16785408, %rax # imm = 0xFEFFE000 .LBB3_1: # =>This Inner Loop Header: Depth=1 cmpq $-8196, %rax # imm = 0xDFFC je .LBB3_3 # %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit # in Loop: Header=BB3_1 Depth=1 movl $1, 16785412(%rbx,%rax) addq $8196, %rax # imm = 0x2004 jne .LBB3_1 .LBB3_3: # %.lr.ph.i.i.i.i.i.i.i.i.i54.preheader xorps %xmm0, %xmm0 movaps %xmm0, 32(%rsp) movaps %xmm0, 16(%rsp) movaps %xmm0, (%rsp) movb $1, %bpl xorl %r15d, %r15d .LBB3_4: # %.preheader108 # =>This Inner Loop Header: Depth=1 .Ltmp0: movl $4096, %edi # imm = 0x1000 callq _Znwm .Ltmp1: # %bb.5: # %.noexc62 # in Loop: Header=BB3_4 Depth=1 movq %rax, %r14 movl $4096, %edx # imm = 0x1000 movq %rax, %rdi xorl %esi, %esi callq memset@PLT movq %r14, %rax addq $4096, %rax # imm = 0x1000 leaq (%r15,%r15,2), %rcx movq (%rsp,%rcx,8), %rdi movq %r14, (%rsp,%rcx,8) movq %rax, 8(%rsp,%rcx,8) movq %rax, 16(%rsp,%rcx,8) testq %rdi, %rdi je .LBB3_7 # %bb.6: # in Loop: Header=BB3_4 Depth=1 callq _ZdlPv .LBB3_7: # %_ZNSt6vectorIiSaIiEED2Ev.exit # in Loop: Header=BB3_4 Depth=1 movl $1, %r15d testb $1, %bpl movl $0, %ebp jne .LBB3_4 # %bb.8: # %.preheader107.preheader movb $1, %r15b xorl %ecx, %ecx .LBB3_9: # %.preheader107 # =>This Inner Loop Header: Depth=1 movq %rcx, %rdi shlq $23, %rdi addq %rbx, %rdi leaq (%rcx,%rcx,2), %rax movq (%rsp,%rax,8), %rdx .Ltmp3: movl $1024, %esi # imm = 0x400 # kill: def $ecx killed $ecx killed $rcx callq _Z8dfsOnGPUPiiS_i .Ltmp4: # %bb.10: # in Loop: Header=BB3_9 Depth=1 movl $1, %ecx xorl %r14d, %r14d testb $1, %r15b movl $0, %r15d jne .LBB3_9 # %bb.11: # %.preheader.preheader movb $1, %al xorl %ecx, %ecx .LBB3_12: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB3_13 Depth 2 leaq (%rcx,%rcx,2), %rcx movq (%rsp,%rcx,8), %rcx xorl %edx, %edx .LBB3_13: # Parent Loop BB3_12 Depth=1 # => This Inner Loop Header: Depth=2 addl (%rcx,%rdx,4), %r14d incq %rdx cmpq $1024, %rdx # imm = 0x400 jne .LBB3_13 # %bb.14: # in Loop: Header=BB3_12 Depth=1 movl $1, %ecx testb $1, %al movl $0, %eax jne .LBB3_12 # %bb.15: .Ltmp6: movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $21, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp7: # %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit .Ltmp8: movl $_ZSt4cout, %edi movl %r14d, %esi callq _ZNSolsEi .Ltmp9: # %bb.17: movq %rax, %r14 movq (%rax), %rax movq -24(%rax), %rdi addq %r14, %rdi .Ltmp10: movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc .Ltmp11: # %bb.18: # %.noexc83 .Ltmp12: movsbl %al, %esi movq %r14, %rdi callq _ZNSo3putEc .Ltmp13: # %bb.19: # %.noexc84 .Ltmp14: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp15: # %bb.20: # %_ZNSolsEPFRSoS_E.exit.preheader movl $24, %r14d .LBB3_21: # %_ZNSolsEPFRSoS_E.exit # =>This Inner Loop Header: Depth=1 movq (%rsp,%r14), %rdi testq %rdi, %rdi je .LBB3_23 # %bb.22: # in Loop: Header=BB3_21 Depth=1 callq _ZdlPv .LBB3_23: # %_ZNSt6vectorIiSaIiEED2Ev.exit67 # in Loop: Header=BB3_21 Depth=1 addq $-24, %r14 cmpq $-24, %r14 jne .LBB3_21 # %bb.24: # %_ZNSt6vectorIiSaIiEED2Ev.exit71 movq %rbx, %rdi callq _ZdlPv xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_32: .cfi_def_cfa_offset 96 .Ltmp16: jmp .LBB3_26 .LBB3_31: .Ltmp5: jmp .LBB3_26 .LBB3_25: .Ltmp2: .LBB3_26: movq %rax, %r14 movl $24, %r15d .LBB3_27: # =>This Inner Loop Header: Depth=1 movq (%rsp,%r15), %rdi testq %rdi, %rdi je .LBB3_29 # %bb.28: # in Loop: Header=BB3_27 Depth=1 callq _ZdlPv .LBB3_29: # %_ZNSt6vectorIiSaIiEED2Ev.exit73 # in Loop: Header=BB3_27 Depth=1 addq $-24, %r15 cmpq $-24, %r15 jne .LBB3_27 # %bb.30: # %_ZNSt6vectorIiSaIiEED2Ev.exit75 movq %rbx, %rdi callq _ZdlPv movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table3: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5 .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15 .uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16 .byte 0 # On action: cleanup .uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Lfunc_end3-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end3 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9dfsKernelPiS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z9dfsKernelPiS_i,@object # @_Z9dfsKernelPiS_i .section .rodata,"a",@progbits .globl _Z9dfsKernelPiS_i .p2align 3, 0x0 _Z9dfsKernelPiS_i: .quad _Z24__device_stub__dfsKernelPiS_i .size _Z9dfsKernelPiS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMalloc d_visited" .size .L.str.3, 20 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipMalloc d_graph" .size .L.str.4, 18 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipMemcpy graph" .size .L.str.5, 16 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "hipMemcpy visited" .size .L.str.6, 18 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "dfsKernel launch failed" .size .L.str.7, 24 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "hipDeviceSynchronize failed" .size .L.str.8, 28 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipMemcpy visited back" .size .L.str.9, 23 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Total visited nodes: " .size .L.str.10, 22 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9dfsKernelPiS_i" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__dfsKernelPiS_i .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z9dfsKernelPiS_i .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
7,992
7,917
113,492
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z16checkBloomFilterPjjPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.GT.AND P0, PT, R0, 0x7f, PT ; @P0 EXIT ; ULDC UR6, c[0x0][0x168] ; UIMAD UR4, UR6, 0x4c, URZ ; ULDC.64 UR8, c[0x0][0x160] ; ULOP3.LUT UR4, UR4, 0x1fc, URZ, 0xc0, !UPT ; UIADD3 UR4, UP0, UR4, UR8, URZ ; UIADD3.X UR5, URZ, UR9, URZ, UP0, !UPT ; MOV R2, UR4 ; ULDC.64 UR8, c[0x0][0x118] ; IMAD.U32 R3, RZ, RZ, UR5 ; LDG.E R2, [R2.64] ; UIMAD UR4, UR6, 0x13, URZ ; UMOV UR5, 0x1 ; USHF.L.W.U32 UR4, UR5, UR4, URZ ; LOP3.LUT P0, RZ, R2, UR4, RZ, 0xc0, !PT ; @P0 EXIT ; MOV R2, c[0x0][0x170] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; STG.E [R2.64], RZ ; EXIT ; BRA 0x170; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z21insertIntoBloomFilterPjj .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.GT.AND P0, PT, R0, 0x7f, PT ; @P0 EXIT ; ULDC UR4, c[0x0][0x168] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; UIMAD UR5, UR4, 0x13, URZ ; S2R R2, SR_LANEID ; UIMAD UR4, UR4, 0x4c, URZ ; ULDC.64 UR6, c[0x0][0x160] ; SHF.L.W.U32 R0, R0, UR5, RZ ; VOTEU.ANY UR5, UPT, PT ; UFLO.U32 UR5, UR5 ; REDUX.OR UR8, R0 ; ULOP3.LUT UR4, UR4, 0x1fc, URZ, 0xc0, !UPT ; UIADD3 UR4, UP0, UR4, UR6, URZ ; ISETP.EQ.U32.AND P0, PT, R2, UR5, PT ; UIADD3.X UR5, URZ, UR7, URZ, UP0, !UPT ; MOV R2, UR4 ; IMAD.U32 R3, RZ, RZ, UR5 ; ULDC.64 UR4, c[0x0][0x118] ; MOV R5, UR8 ; @P0 RED.E.OR.STRONG.GPU [R2.64], R5 ; EXIT ; BRA 0x180; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z15initBloomFilterPj .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_TID.X ; ISETP.GT.AND P0, PT, R2, 0x7f, PT ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; STG.E [R2.64], RZ ; EXIT ; BRA 0x90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15initBloomFilterPj ; -- Begin function _Z15initBloomFilterPj .globl _Z15initBloomFilterPj .p2align 8 .type _Z15initBloomFilterPj,@function _Z15initBloomFilterPj: ; @_Z15initBloomFilterPj ; %bb.0: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 0x80, v0 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15initBloomFilterPj .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 8 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 3 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15initBloomFilterPj, .Lfunc_end0-_Z15initBloomFilterPj ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 56 ; NumSgprs: 3 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 3 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z21insertIntoBloomFilterPjj ; -- Begin function _Z21insertIntoBloomFilterPjj .globl _Z21insertIntoBloomFilterPjj .p2align 8 .type _Z21insertIntoBloomFilterPjj,@function _Z21insertIntoBloomFilterPjj: ; @_Z21insertIntoBloomFilterPjj ; %bb.0: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 0x80, v0 s_cbranch_execz .LBB1_3 ; %bb.1: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_3 ; %bb.2: s_clause 0x1 s_load_b32 s2, s[0:1], 0x8 s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s2, 19 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_and_b32 s3, s2, 0x7f s_lshl_b32 s2, 1, s2 s_lshl_b32 s3, s3, 2 v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v0, s3 global_atomic_or_b32 v0, v1, s[0:1] .LBB1_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21insertIntoBloomFilterPjj .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 12 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 4 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z21insertIntoBloomFilterPjj, .Lfunc_end1-_Z21insertIntoBloomFilterPjj ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 116 ; NumSgprs: 6 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 6 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z16checkBloomFilterPjjPi ; -- Begin function _Z16checkBloomFilterPjjPi .globl _Z16checkBloomFilterPjjPi .p2align 8 .type _Z16checkBloomFilterPjjPi,@function _Z16checkBloomFilterPjjPi: ; @_Z16checkBloomFilterPjjPi ; %bb.0: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 0x80, v0 s_cbranch_execz .LBB2_2 ; %bb.1: s_clause 0x1 s_load_b32 s4, s[0:1], 0x8 s_load_b64 s[2:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_mul_i32 s4, s4, 19 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s5, s4, 0x7f s_lshl_b32 s5, s5, 2 s_load_b32 s2, s[2:3], s5 offset:0x0 s_waitcnt lgkmcnt(0) s_lshr_b32 s2, s2, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_bitcmp1_b32 s2, 0 s_cselect_b32 s2, -1, 0 s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB2_3 .LBB2_2: s_endpgm .LBB2_3: s_load_b64 s[0:1], s[0:1], 0x10 v_mov_b32_e32 v0, 0 s_waitcnt lgkmcnt(0) global_store_b32 v0, v0, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16checkBloomFilterPjjPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 6 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z16checkBloomFilterPjjPi, .Lfunc_end2-_Z16checkBloomFilterPjjPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 136 ; NumSgprs: 8 ; NumVgprs: 1 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 1 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 8 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15initBloomFilterPj .private_segment_fixed_size: 0 .sgpr_count: 3 .sgpr_spill_count: 0 .symbol: _Z15initBloomFilterPj.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 12 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21insertIntoBloomFilterPjj .private_segment_fixed_size: 0 .sgpr_count: 6 .sgpr_spill_count: 0 .symbol: _Z21insertIntoBloomFilterPjj.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16checkBloomFilterPjjPi .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z16checkBloomFilterPjjPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 1 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_001066ae_00000000-6_cuda_code_019774.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3852: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3852: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4511: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4511: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z35__device_stub__Z15initBloomFilterPjPj .type _Z35__device_stub__Z15initBloomFilterPjPj, @function _Z35__device_stub__Z15initBloomFilterPjPj: .LFB3874: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 40(%rsp) movq %rax, 80(%rsp) movabsq $4294967297, %rax movq %rax, 32(%rsp) movq %rax, 44(%rsp) movl $1, 52(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 24(%rsp) .cfi_def_cfa_offset 120 leaq _Z15initBloomFilterPj(%rip), %rdi pushq 24(%rsp) .cfi_def_cfa_offset 128 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq 96(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 120 popq %rdx .cfi_def_cfa_offset 112 .L3: movq 88(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $104, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3874: .size _Z35__device_stub__Z15initBloomFilterPjPj, .-_Z35__device_stub__Z15initBloomFilterPjPj .globl _Z15initBloomFilterPj .type _Z15initBloomFilterPj, @function _Z15initBloomFilterPj: .LFB3875: .cfi_startproc endbr64 jmp _Z35__device_stub__Z15initBloomFilterPjPj .cfi_endproc .LFE3875: .size _Z15initBloomFilterPj, .-_Z15initBloomFilterPj .globl _Z42__device_stub__Z21insertIntoBloomFilterPjjPjj .type _Z42__device_stub__Z21insertIntoBloomFilterPjjPjj, @function _Z42__device_stub__Z21insertIntoBloomFilterPjjPjj: .LFB3876: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L9 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z21insertIntoBloomFilterPjj(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L9: movq 104(%rsp), %rax subq %fs:40, %rax je .L11 call __stack_chk_fail@PLT .L11: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3876: .size _Z42__device_stub__Z21insertIntoBloomFilterPjjPjj, .-_Z42__device_stub__Z21insertIntoBloomFilterPjjPjj .globl _Z21insertIntoBloomFilterPjj .type _Z21insertIntoBloomFilterPjj, @function _Z21insertIntoBloomFilterPjj: .LFB3877: .cfi_startproc endbr64 jmp _Z42__device_stub__Z21insertIntoBloomFilterPjjPjj .cfi_endproc .LFE3877: .size _Z21insertIntoBloomFilterPjj, .-_Z21insertIntoBloomFilterPjj .globl _Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi .type _Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi, @function _Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi: .LFB3878: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) leaq 40(%rsp), %rcx leaq 48(%rsp), %rdi movl %esi, 20(%rsp) leaq 60(%rsp), %rsi movq %rdx, 8(%rsp) leaq 32(%rsp), %rdx movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 56(%rsp) movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movabsq $4294967297, %rax movq %rax, 48(%rsp) movq %rax, 60(%rsp) movl $1, 68(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L14 pushq 40(%rsp) .cfi_def_cfa_offset 152 leaq _Z16checkBloomFilterPjjPi(%rip), %rdi pushq 40(%rsp) .cfi_def_cfa_offset 160 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq 112(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 152 popq %rdx .cfi_def_cfa_offset 144 .L14: movq 120(%rsp), %rax subq %fs:40, %rax je .L16 call __stack_chk_fail@PLT .L16: addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3878: .size _Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi, .-_Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi .globl _Z16checkBloomFilterPjjPi .type _Z16checkBloomFilterPjjPi, @function _Z16checkBloomFilterPjjPi: .LFB3879: .cfi_startproc endbr64 jmp _Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi .cfi_endproc .LFE3879: .size _Z16checkBloomFilterPjjPi, .-_Z16checkBloomFilterPjjPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Failed to allocate device memory for bloom filter" .LC1: .string "Failed to allocate device memory for result" .LC2: .string "Kernel launch failed: " .LC3: .string "Element " .LC4: .string " is possibly in the bloom filter." .LC5: .string " is definitely not in the bloom filter." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3849: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movl $4, %edi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $56, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $512, %esi movq %rsp, %rdi movl $1, (%rax) movq %rax, %rbx call cudaMalloc@PLT leaq .LC0(%rip), %rsi testl %eax, %eax jne .L34 leaq 8(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT testl %eax, %eax je .L22 leaq .LC1(%rip), %rsi .L34: leaq _ZSt4cerr(%rip), %rdi .L35: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L19 .L22: movl $33554433, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $7, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 36(%rsp) movq %rdx, 28(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L24 movq (%rsp), %rdi call _Z35__device_stub__Z15initBloomFilterPjPj .L24: call cudaGetLastError@PLT movl %eax, %ebp testl %eax, %eax jne .L37 movl $33554433, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $7, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 36(%rsp) movq %rdx, 28(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L26 movq (%rsp), %rdi movl $42, %esi call _Z42__device_stub__Z21insertIntoBloomFilterPjjPjj .L26: call cudaGetLastError@PLT movl %eax, %ebp testl %eax, %eax jne .L37 movl $33554433, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $7, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 36(%rsp) movq %rdx, 28(%rsp) movq %rdi, 16(%rsp) movl $1, 24(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L28 movq 8(%rsp), %rdx movq (%rsp), %rdi movl $42, %esi call _Z39__device_stub__Z16checkBloomFilterPjjPiPjjPi .L28: call cudaGetLastError@PLT movl %eax, %ebp testl %eax, %eax je .L29 .L37: leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebp, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi jmp .L35 .L29: movq 8(%rsp), %rsi movq %rbx, %rdi movl $2, %ecx movl $4, %edx call cudaMemcpy@PLT cmpl $1, (%rbx) leaq .LC3(%rip), %rsi leaq _ZSt4cout(%rip), %rdi jne .L30 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $42, %esi movq %rax, %rdi call _ZNSo9_M_insertImEERSoT_@PLT leaq .LC4(%rip), %rsi movq %rax, %rdi jmp .L36 .L30: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $42, %esi movq %rax, %rdi call _ZNSo9_M_insertImEERSoT_@PLT leaq .LC5(%rip), %rsi movq %rax, %rdi .L36: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call _ZdaPv@PLT xorl %eax, %eax .L19: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L32 call __stack_chk_fail@PLT .L32: addq $56, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3849: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z16checkBloomFilterPjjPi" .LC7: .string "_Z21insertIntoBloomFilterPjj" .LC8: .string "_Z15initBloomFilterPj" .LC9: .string "precalc_xorwow_matrix" .LC10: .string "precalc_xorwow_offset_matrix" .LC11: .string "mrg32k3aM1" .LC12: .string "mrg32k3aM2" .LC13: .string "mrg32k3aM1SubSeq" .LC14: .string "mrg32k3aM2SubSeq" .LC15: .string "mrg32k3aM1Seq" .LC16: .string "mrg32k3aM2Seq" .LC17: .string "__cr_lgamma_table" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3881: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC6(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z16checkBloomFilterPjjPi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC7(%rip), %rdx orl $-1, %r8d leaq _Z21insertIntoBloomFilterPjj(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r9d, %r9d pushq $0 .cfi_def_cfa_offset 24 leaq .LC8(%rip), %rdx orl $-1, %r8d leaq _Z15initBloomFilterPj(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC9(%rip), %rdx movl $102400, %r9d leaq _ZL21precalc_xorwow_matrix(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $102400, %r9d leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM1(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC12(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL10mrg32k3aM2(%rip), %rsi call __cudaRegisterVar@PLT popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %r11 .cfi_def_cfa_offset 24 popq %rax .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2016, %r9d leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC15(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM1Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC16(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $2304, %r9d leaq _ZL13mrg32k3aM2Seq(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 popq %r8 .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 leaq .LC17(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $72, %r9d movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r9 .cfi_def_cfa_offset 24 popq %r10 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3881: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_019774.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__initBloomFilterPj # -- Begin function _Z30__device_stub__initBloomFilterPj .type _Z30__device_stub__initBloomFilterPj,@function _Z30__device_stub__initBloomFilterPj: # @_Z30__device_stub__initBloomFilterPj .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $64, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) movq %rsp, %rbx movq %rax, (%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15initBloomFilterPj, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $80, %rsp .cfi_adjust_cfa_offset -80 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__initBloomFilterPj, .Lfunc_end0-_Z30__device_stub__initBloomFilterPj .cfi_endproc # -- End function .globl _Z36__device_stub__insertIntoBloomFilterPjj # -- Begin function _Z36__device_stub__insertIntoBloomFilterPjj .type _Z36__device_stub__insertIntoBloomFilterPjj,@function _Z36__device_stub__insertIntoBloomFilterPjj: # @_Z36__device_stub__insertIntoBloomFilterPjj .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z21insertIntoBloomFilterPjj, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z36__device_stub__insertIntoBloomFilterPjj, .Lfunc_end1-_Z36__device_stub__insertIntoBloomFilterPjj .cfi_endproc # -- End function .globl _Z31__device_stub__checkBloomFilterPjjPi # -- Begin function _Z31__device_stub__checkBloomFilterPjjPi .type _Z31__device_stub__checkBloomFilterPjjPi,@function _Z31__device_stub__checkBloomFilterPjjPi: # @_Z31__device_stub__checkBloomFilterPjjPi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 12(%rsp), %rcx movl %esi, (%rcx) leaq 32(%rsp), %rsi movq %rdx, (%rsi) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) movq %rsi, 16(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z16checkBloomFilterPjjPi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z31__device_stub__checkBloomFilterPjjPi, .Lfunc_end2-_Z31__device_stub__checkBloomFilterPjjPi .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $24, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4, %edi callq _Znam movq %rax, %rbx movl $1, (%rax) leaq 8(%rsp), %rdi movl $512, %esi # imm = 0x200 callq hipMalloc testl %eax, %eax je .LBB3_2 # %bb.1: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $49, %edx jmp .LBB3_4 .LBB3_2: leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc testl %eax, %eax je .LBB3_8 # %bb.3: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $43, %edx .LBB3_4: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi .LBB3_5: movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB3_6: movl $-1, %eax .LBB3_7: addq $24, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_8: .cfi_def_cfa_offset 64 movabsq $4294967297, %r15 # imm = 0x100000001 leaq 127(%r15), %r14 movq %r15, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_10 # %bb.9: movq 8(%rsp), %rdi callq _Z30__device_stub__initBloomFilterPj .LBB3_10: callq hipGetLastError testl %eax, %eax jne .LBB3_14 # %bb.11: movq %r15, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_13 # %bb.12: movq 8(%rsp), %rdi movl $42, %esi callq _Z36__device_stub__insertIntoBloomFilterPjj .LBB3_13: callq hipGetLastError testl %eax, %eax je .LBB3_18 .LBB3_14: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB3_16 # %bb.15: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB3_17 .LBB3_16: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB3_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi jmp .LBB3_5 .LBB3_18: movq %r15, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_20 # %bb.19: movq 8(%rsp), %rdi movq 16(%rsp), %rdx movl $42, %esi callq _Z31__device_stub__checkBloomFilterPjjPi .LBB3_20: callq hipGetLastError testl %eax, %eax je .LBB3_22 # %bb.21: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB3_6 .LBB3_22: movq 16(%rsp), %rsi movl $4, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl (%rbx), %ebp movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $8, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl $42, %esi callq _ZNSo9_M_insertImEERSoT_ movq %rax, %r14 cmpl $1, %ebp jne .LBB3_24 # %bb.23: movl $.L.str.4, %esi movl $33, %edx jmp .LBB3_25 .LBB3_24: movl $.L.str.5, %esi movl $39, %edx .LBB3_25: movq %r14, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %r14, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB3_7 .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15initBloomFilterPj, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21insertIntoBloomFilterPjj, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16checkBloomFilterPjjPi, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z15initBloomFilterPj,@object # @_Z15initBloomFilterPj .section .rodata,"a",@progbits .globl _Z15initBloomFilterPj .p2align 3, 0x0 _Z15initBloomFilterPj: .quad _Z30__device_stub__initBloomFilterPj .size _Z15initBloomFilterPj, 8 .type _Z21insertIntoBloomFilterPjj,@object # @_Z21insertIntoBloomFilterPjj .globl _Z21insertIntoBloomFilterPjj .p2align 3, 0x0 _Z21insertIntoBloomFilterPjj: .quad _Z36__device_stub__insertIntoBloomFilterPjj .size _Z21insertIntoBloomFilterPjj, 8 .type _Z16checkBloomFilterPjjPi,@object # @_Z16checkBloomFilterPjjPi .globl _Z16checkBloomFilterPjjPi .p2align 3, 0x0 _Z16checkBloomFilterPjjPi: .quad _Z31__device_stub__checkBloomFilterPjjPi .size _Z16checkBloomFilterPjjPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device memory for bloom filter" .size .L.str, 50 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate device memory for result" .size .L.str.1, 44 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Kernel launch failed: " .size .L.str.2, 23 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Element " .size .L.str.3, 9 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz " is possibly in the bloom filter." .size .L.str.4, 34 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz " is definitely not in the bloom filter." .size .L.str.5, 40 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15initBloomFilterPj" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z21insertIntoBloomFilterPjj" .size .L__unnamed_2, 29 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z16checkBloomFilterPjjPi" .size .L__unnamed_3, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__initBloomFilterPj .addrsig_sym _Z36__device_stub__insertIntoBloomFilterPjj .addrsig_sym _Z31__device_stub__checkBloomFilterPjjPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15initBloomFilterPj .addrsig_sym _Z21insertIntoBloomFilterPjj .addrsig_sym _Z16checkBloomFilterPjjPi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z24homomorphicEncryptKernelPfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; LDG.E R0, [R2.64] ; FADD R5, R0, 1 ; STG.E [R2.64], R5 ; EXIT ; BRA 0xd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z24homomorphicEncryptKernelPfi ; -- Begin function _Z24homomorphicEncryptKernelPfi .globl _Z24homomorphicEncryptKernelPfi .p2align 8 .type _Z24homomorphicEncryptKernelPfi,@function _Z24homomorphicEncryptKernelPfi: ; @_Z24homomorphicEncryptKernelPfi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[0:1], off s_waitcnt vmcnt(0) v_add_f32_e32 v2, 1.0, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z24homomorphicEncryptKernelPfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z24homomorphicEncryptKernelPfi, .Lfunc_end0-_Z24homomorphicEncryptKernelPfi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 140 ; NumSgprs: 18 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z24homomorphicEncryptKernelPfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z24homomorphicEncryptKernelPfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0012628b_00000000-6_cuda_code_063887.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB3635: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE3635: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi .type _Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi, @function _Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi: .LFB3661: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) leaq 32(%rsp), %rcx leaq 24(%rsp), %rdx movl %esi, 4(%rsp) leaq 40(%rsp), %rdi leaq 52(%rsp), %rsi movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movl $1, 48(%rsp) movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movabsq $4294967297, %rax movq %rax, 40(%rsp) movq %rax, 52(%rsp) movl $1, 60(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 32(%rsp) .cfi_def_cfa_offset 136 leaq _Z24homomorphicEncryptKernelPfi(%rip), %rdi pushq 32(%rsp) .cfi_def_cfa_offset 144 movq 68(%rsp), %rcx movl 76(%rsp), %r8d movq 56(%rsp), %rsi movl 64(%rsp), %edx leaq 104(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 136 popq %rdx .cfi_def_cfa_offset 128 .L8: movq 104(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi, .-_Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi .globl _Z24homomorphicEncryptKernelPfi .type _Z24homomorphicEncryptKernelPfi, @function _Z24homomorphicEncryptKernelPfi: .LFB3662: .cfi_startproc endbr64 jmp _Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi .cfi_endproc .LFE3662: .size _Z24homomorphicEncryptKernelPfi, .-_Z24homomorphicEncryptKernelPfi .section .rodata.str1.1 .LC3: .string "Failed to allocate device memory" .LC4: .string "Failed to create start event" .LC5: .string "Failed to create stop event" .LC6: .string "Failed to record start event" .LC7: .string "Failed to copy data to device" .LC8: .string "Kernel launch failed" .LC9: .string "Failed to copy data from device" .LC10: .string "Failed to record stop event" .LC11: .string "Failed to synchronize stop event" .LC13: .string "Failed to get elapsed time" .LC14: .string "First 10 results after encryption:" .LC15: .string " " .LC16: .string "Time taken: " .LC17: .string " ms" .LC18: .string "Failed to free device memory" .LC19: .string "Failed to destroy start event" .LC20: .string "Failed to destroy stop event" .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 movl $4194304, %edi pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call _Znam@PLT movl $4194304, %edi movq %rax, %rbp call _Znam@PLT movq %rax, %rbx xorl %eax, %eax .L14: cvtsi2ssl %eax, %xmm0 movss %xmm0, 0(%rbp,%rax,4) incq %rax cmpq $1048576, %rax jne .L14 leaq 8(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 16(%rsp), %rdi call cudaEventCreate@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 24(%rsp), %rdi call cudaEventCreate@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rdi xorl %esi, %esi call cudaEventRecord@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi xorl %r8d, %r8d movq %rbp, %rsi movl $1, %ecx movl $4194304, %edx call cudaMemcpyAsync@PLT leaq .LC7(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1048577, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $12, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L15 movq 8(%rsp), %rdi movl $1048576, %esi call _Z45__device_stub__Z24homomorphicEncryptKernelPfiPfi .L15: call cudaGetLastError@PLT leaq .LC8(%rip), %rsi leaq _ZSt4cout(%rip), %r12 xorl %r13d, %r13d movl %eax, %edi leaq .LC15(%rip), %r14 call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rsi xorl %r8d, %r8d movq %rbx, %rdi movl $2, %ecx movl $4194304, %edx call cudaMemcpyAsync@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rdi xorl %esi, %esi call cudaEventRecord@PLT leaq .LC10(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rdi call cudaEventSynchronize@PLT leaq .LC11(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rdx movq 16(%rsp), %rsi leaq 4(%rsp), %rdi movl $0x00000000, 4(%rsp) call cudaEventElapsedTime@PLT leaq .LC13(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq .LC14(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .L16: movq %r12, %rdi cvtss2sd (%rbx,%r13,4), %xmm0 incq %r13 call _ZNSo9_M_insertIdEERSoT_@PLT movq %r14, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $10, %r13 jne .L16 movq %r12, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC16(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cvtss2sd 4(%rsp), %xmm0 movq %rax, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT leaq .LC17(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC18(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 16(%rsp), %rdi call cudaEventDestroy@PLT leaq .LC19(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 24(%rsp), %rdi call cudaEventDestroy@PLT leaq .LC20(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 56(%rsp), %rax subq %fs:40, %rax je .L17 call __stack_chk_fail@PLT .L17: addq $64, %rsp .cfi_def_cfa_offset 48 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC21: .string "_Z24homomorphicEncryptKernelPfi" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC21(%rip), %rdx movq %rax, %rdi leaq _Z24homomorphicEncryptKernelPfi(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_063887.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z39__device_stub__homomorphicEncryptKernelPfi # -- Begin function _Z39__device_stub__homomorphicEncryptKernelPfi .type _Z39__device_stub__homomorphicEncryptKernelPfi,@function _Z39__device_stub__homomorphicEncryptKernelPfi: # @_Z39__device_stub__homomorphicEncryptKernelPfi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $80, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 24(%rsp), %rax movq %rdi, (%rax) leaq 4(%rsp), %rcx movl %esi, (%rcx) leaq 64(%rsp), %rbx movq %rax, (%rbx) movq %rcx, 8(%rbx) leaq 48(%rsp), %r14 leaq 32(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z24homomorphicEncryptKernelPfi, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $96, %rsp .cfi_adjust_cfa_offset -96 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z39__device_stub__homomorphicEncryptKernelPfi, .Lfunc_end0-_Z39__device_stub__homomorphicEncryptKernelPfi .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $40, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $4194304, %edi # imm = 0x400000 callq _Znam movq %rax, %rbx movl $4194304, %edi # imm = 0x400000 callq _Znam movq %rax, %r14 xorl %eax, %eax .LBB2_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $1048576, %rax # imm = 0x100000 jne .LBB2_1 # %bb.2: leaq 16(%rsp), %r15 movl $4194304, %esi # imm = 0x400000 movq %r15, %rdi callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 32(%rsp), %r12 movq %r12, %rdi callq hipEventCreate movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 8(%rsp), %rdi callq hipEventCreate movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r12), %rdi xorl %esi, %esi callq hipEventRecord movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r15), %rdi movl $4194304, %edx # imm = 0x400000 movq %rbx, %rsi movl $1, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $4294967552, %rdx # imm = 0x100000100 leaq 3840(%rdx), %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: movq 16(%rsp), %rdi movl $1048576, %esi # imm = 0x100000 callq _Z39__device_stub__homomorphicEncryptKernelPfi .LBB2_4: callq hipGetLastError movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 16(%rsp), %rsi xorl %r15d, %r15d movl $4194304, %edx # imm = 0x400000 movq %r14, %rdi movl $2, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl $.L.str.10, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi callq hipEventSynchronize movl $.L.str.11, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc leaq 28(%rsp), %rdi movl $0, (%rdi) movq 32(%rsp), %rsi movq 8(%rsp), %rdx callq hipEventElapsedTime movl $.L.str.12, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movl $_ZSt4cout, %r12d movl $_ZSt4cout, %edi movl $.L.str.13, %esi movl $34, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %r12, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB2_5: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtss2sd (%r14,%r15,4), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.14, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r15 cmpq $10, %r15 jne .LBB2_5 # %bb.6: movq _ZSt4cout(%rip), %rax movl $_ZSt4cout, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.15, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtss2sd 28(%rsp), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.16, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r15), %rax movq -24(%rax), %rdi addq %r15, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq 16(%rsp), %rdi callq hipFree movl $.L.str.17, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 32(%rsp), %rdi callq hipEventDestroy movl $.L.str.18, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi callq hipEventDestroy movl $.L.str.19, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc xorl %eax, %eax addq $40, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z24homomorphicEncryptKernelPfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z24homomorphicEncryptKernelPfi,@object # @_Z24homomorphicEncryptKernelPfi .section .rodata,"a",@progbits .globl _Z24homomorphicEncryptKernelPfi .p2align 3, 0x0 _Z24homomorphicEncryptKernelPfi: .quad _Z39__device_stub__homomorphicEncryptKernelPfi .size _Z24homomorphicEncryptKernelPfi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate device memory" .size .L.str.3, 33 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to create start event" .size .L.str.4, 29 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to create stop event" .size .L.str.5, 28 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to record start event" .size .L.str.6, 29 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to copy data to device" .size .L.str.7, 30 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Kernel launch failed" .size .L.str.8, 21 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to copy data from device" .size .L.str.9, 32 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Failed to record stop event" .size .L.str.10, 28 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Failed to synchronize stop event" .size .L.str.11, 33 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "Failed to get elapsed time" .size .L.str.12, 27 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "First 10 results after encryption:" .size .L.str.13, 35 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz " " .size .L.str.14, 2 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "Time taken: " .size .L.str.15, 13 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz " ms" .size .L.str.16, 4 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "Failed to free device memory" .size .L.str.17, 29 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "Failed to destroy start event" .size .L.str.18, 30 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "Failed to destroy stop event" .size .L.str.19, 29 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z24homomorphicEncryptKernelPfi" .size .L__unnamed_1, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z39__device_stub__homomorphicEncryptKernelPfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z24homomorphicEncryptKernelPfi .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15sparseMatVecMulPiS_PfS0_S0_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R6, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R6, 0x1fff, PT ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R8, R6, R5, c[0x0][0x168] ; LDG.E R8, [R8.64] ; IMAD.WIDE R2, R6, R5, c[0x0][0x160] ; IMAD.WIDE R6, R6, R5.reuse, c[0x0][0x170] ; LDG.E R2, [R2.64] ; LDG.E R7, [R6.64] ; IMAD.WIDE R10, R8, R5, c[0x0][0x178] ; LDG.E R10, [R10.64] ; IMAD.WIDE R4, R2, R5, c[0x0][0x180] ; FMUL R13, R10, R7 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R13 ; EXIT ; BRA 0x140; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15sparseMatVecMulPiS_PfS0_S0_ ; -- Begin function _Z15sparseMatVecMulPiS_PfS0_S0_ .globl _Z15sparseMatVecMulPiS_PfS0_S0_ .p2align 8 .type _Z15sparseMatVecMulPiS_PfS0_S0_,@function _Z15sparseMatVecMulPiS_PfS0_S0_: ; @_Z15sparseMatVecMulPiS_PfS0_S0_ ; %bb.0: s_load_b32 s2, s[0:1], 0x34 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x2000, v1 s_cbranch_execz .LBB0_3 ; %bb.1: s_load_b256 s[4:11], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x20 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v6, vcc_lo, s8, v0 global_load_b32 v2, v[2:3], off global_load_b32 v4, v[4:5], off v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo s_waitcnt vmcnt(1) v_ashrrev_i32_e32 v3, 31, v2 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[2:3] v_lshlrev_b64 v[0:1], 2, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, s10, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v4, v[6:7], off global_load_b32 v2, v[2:3], off global_load_b32 v3, v[0:1], off s_mov_b32 s0, 0 s_waitcnt vmcnt(1) v_mul_f32_e32 v4, v4, v2 .LBB0_2: ; %atomicrmw.start ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v2, v3, v4 global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v2, v3 v_mov_b32_e32 v3, v2 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_2 .LBB0_3: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15sparseMatVecMulPiS_PfS0_S0_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15sparseMatVecMulPiS_PfS0_S0_, .Lfunc_end0-_Z15sparseMatVecMulPiS_PfS0_S0_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 296 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15sparseMatVecMulPiS_PfS0_S0_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15sparseMatVecMulPiS_PfS0_S0_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_0015147a_00000000-6_cuda_code_004067.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_ .type _Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_, @function _Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_: .LFB3660: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) leaq 64(%rsp), %rdi movq %rsi, 32(%rsp) leaq 76(%rsp), %rsi movq %rdx, 24(%rsp) leaq 48(%rsp), %rdx movq %rcx, 16(%rsp) leaq 56(%rsp), %rcx movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 72(%rsp) movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movabsq $4294967297, %rax movq %rax, 64(%rsp) movq %rax, 76(%rsp) movl $1, 84(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L2 pushq 56(%rsp) .cfi_def_cfa_offset 184 leaq _Z15sparseMatVecMulPiS_PfS0_S0_(%rip), %rdi pushq 56(%rsp) .cfi_def_cfa_offset 192 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq 128(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 184 popq %rdx .cfi_def_cfa_offset 176 .L2: movq 152(%rsp), %rax subq %fs:40, %rax je .L4 call __stack_chk_fail@PLT .L4: addq $168, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_, .-_Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_ .globl _Z15sparseMatVecMulPiS_PfS0_S0_ .type _Z15sparseMatVecMulPiS_PfS0_S0_, @function _Z15sparseMatVecMulPiS_PfS0_S0_: .LFB3661: .cfi_startproc endbr64 jmp _Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_ .cfi_endproc .LFE3661: .size _Z15sparseMatVecMulPiS_PfS0_S0_, .-_Z15sparseMatVecMulPiS_PfS0_S0_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "CUDA error: " .LC2: .string "Result vector y (first 10 elements): " .LC3: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 leaq -106496(%rsp), %r11 .cfi_def_cfa 11, 106544 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $80, %rsp .cfi_def_cfa_offset 106624 movl $1024, %ecx movss .LC0(%rip), %xmm0 movq %fs:40, %rax movq %rax, 106568(%rsp) xorl %eax, %eax leaq 4168(%rsp), %rdi leaq 4168(%rsp), %rbp leaq 8264(%rsp), %r14 leaq 41032(%rsp), %r13 leaq 73800(%rsp), %r12 rep stosl xorl %eax, %eax .L9: movl %eax, %edx movss %xmm0, (%r12,%rax,4) andl $1023, %edx movl %edx, (%r14,%rax,4) leal (%rax,%rax,2), %edx andl $1023, %edx movl %edx, 0(%r13,%rax,4) incq %rax cmpq $8192, %rax jne .L9 xorl %eax, %eax .L10: leaq 72(%rsp), %rbx movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $1024, %rax jne .L10 leaq 8(%rsp), %rdi movl $32768, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $32768, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $32768, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movq 8(%rsp), %rdi movl $1, %ecx movq %r14, %rsi movl $32768, %edx call cudaMemcpy@PLT movq 16(%rsp), %rdi movl $1, %ecx movq %r13, %rsi movl $32768, %edx call cudaMemcpy@PLT movq 24(%rsp), %rdi movl $1, %ecx movq %r12, %rsi movl $32768, %edx call cudaMemcpy@PLT movq 32(%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $4096, %edx call cudaMemcpy@PLT movq 40(%rsp), %rdi movl $1, %ecx movq %rbp, %rsi movl $4096, %edx call cudaMemcpy@PLT movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $134217729, %edi salq $8, %rdx movl $1, %ecx movl $1, %esi salq $5, %rdi movq %rdx, 60(%rsp) movl $1, 68(%rsp) movq %rdi, 48(%rsp) movl $1, 56(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L11 movq 40(%rsp), %r8 movq 32(%rsp), %rcx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z45__device_stub__Z15sparseMatVecMulPiS_PfS0_S0_PiS_PfS0_S0_ .L11: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax je .L12 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT orl $-1, %eax jmp .L8 .L12: movq 40(%rsp), %rsi movl $2, %ecx movq %rbp, %rdi xorl %ebx, %ebx movl $4096, %edx leaq _ZSt4cout(%rip), %r12 leaq .LC3(%rip), %r13 call cudaMemcpy@PLT leaq .LC2(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT .L14: movq %r12, %rdi cvtss2sd 0(%rbp,%rbx,4), %xmm0 incq %rbx call _ZNSo9_M_insertIdEERSoT_@PLT movq %r13, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $10, %rbx jne .L14 movq %r12, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L8: movq 106568(%rsp), %rdx subq %fs:40, %rdx je .L15 call __stack_chk_fail@PLT .L15: addq $106576, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z15sparseMatVecMulPiS_PfS0_S0_" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC4(%rip), %rdx movq %rax, %rdi leaq _Z15sparseMatVecMulPiS_PfS0_S0_(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_004067.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ # -- Begin function _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ .type _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_,@function _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_: # @_Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15sparseMatVecMulPiS_PfS0_S0_, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_, .Lfunc_end0-_Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $106544, %rsp # imm = 0x1A030 .cfi_def_cfa_offset 106592 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 48(%rsp), %rdi xorl %ebx, %ebx movl $4096, %edx # imm = 0x1000 xorl %esi, %esi callq memset@PLT movl $1023, %eax # imm = 0x3FF xorl %ecx, %ecx .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %ecx, %edx andl %eax, %edx movl %edx, 73776(%rsp,%rcx,4) movl %ebx, %edx andl %eax, %edx movl %edx, 41008(%rsp,%rcx,4) movl $1065353216, 8240(%rsp,%rcx,4) # imm = 0x3F800000 incq %rcx addl $3, %ebx cmpq $8192, %rcx # imm = 0x2000 jne .LBB1_1 # %bb.2: # %.preheader.preheader xorl %eax, %eax .LBB1_3: # %.preheader # =>This Inner Loop Header: Depth=1 movl $1065353216, 4144(%rsp,%rax,4) # imm = 0x3F800000 incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB1_3 # %bb.4: leaq 40(%rsp), %r13 movl $32768, %esi # imm = 0x8000 movq %r13, %rdi callq hipMalloc leaq 32(%rsp), %r12 movl $32768, %esi # imm = 0x8000 movq %r12, %rdi callq hipMalloc leaq 24(%rsp), %r15 movl $32768, %esi # imm = 0x8000 movq %r15, %rdi callq hipMalloc leaq 16(%rsp), %r14 movl $4096, %esi # imm = 0x1000 movq %r14, %rdi callq hipMalloc leaq 8(%rsp), %rbx movl $4096, %esi # imm = 0x1000 movq %rbx, %rdi callq hipMalloc movq (%r13), %rdi leaq 73776(%rsp), %rsi movl $32768, %edx # imm = 0x8000 movl $1, %ecx callq hipMemcpy movq (%r12), %rdi leaq 41008(%rsp), %rsi movl $32768, %edx # imm = 0x8000 movl $1, %ecx callq hipMemcpy movq (%r15), %rdi leaq 8240(%rsp), %rsi movl $32768, %edx # imm = 0x8000 movl $1, %ecx callq hipMemcpy movq (%r14), %rdi leaq 4144(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movl $1, %ecx callq hipMemcpy movq (%rbx), %rdi leaq 48(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movl $1, %ecx callq hipMemcpy movabsq $4294967328, %rdi # imm = 0x100000020 leaq 224(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 40(%rsp), %rdi movq 32(%rsp), %rsi movq 24(%rsp), %rdx movq 16(%rsp), %rcx movq 8(%rsp), %r8 callq _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ .LBB1_6: callq hipGetLastError testl %eax, %eax je .LBB1_11 # %bb.7: movl %eax, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebx, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_8 # %bb.9: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_10 .LBB1_11: movq 8(%rsp), %rsi leaq 48(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $37, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %ebx, %ebx .LBB1_12: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtss2sd 48(%rsp,%rbx,4), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %rbx cmpq $10, %rbx jne .LBB1_12 # %bb.13: movq _ZSt4cout(%rip), %rax movl $_ZSt4cout, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_14 .LBB1_8: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $-1, %eax .LBB1_14: addq $106544, %rsp # imm = 0x1A030 .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15sparseMatVecMulPiS_PfS0_S0_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15sparseMatVecMulPiS_PfS0_S0_,@object # @_Z15sparseMatVecMulPiS_PfS0_S0_ .section .rodata,"a",@progbits .globl _Z15sparseMatVecMulPiS_PfS0_S0_ .p2align 3, 0x0 _Z15sparseMatVecMulPiS_PfS0_S0_: .quad _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ .size _Z15sparseMatVecMulPiS_PfS0_S0_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Result vector y (first 10 elements): " .size .L.str.1, 38 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz " " .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15sparseMatVecMulPiS_PfS0_S0_" .size .L__unnamed_1, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__sparseMatVecMulPiS_PfS0_S0_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15sparseMatVecMulPiS_PfS0_S0_ .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z14matrixMultiplyPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R21, SR_CTAID.X ; MOV R0, c[0x0][0x178] ; ULDC.64 UR6, c[0x0][0x118] ; HFMA2.MMA R7, -RZ, RZ, 0, 0 ; S2R R19, SR_TID.X ; ISETP.GE.AND P1, PT, R0, -0x1e, PT ; S2R R22, SR_CTAID.Y ; S2R R20, SR_TID.Y ; IMAD R21, R21, c[0x0][0x0], R19 ; ISETP.GE.AND P0, PT, R21, c[0x0][0x178], PT ; IMAD R22, R22, c[0x0][0x4], R20 ; ISETP.GE.OR P0, PT, R22, c[0x0][0x178], P0 ; @!P1 BRA 0x790 ; IADD3 R0, R0, -0x1, RZ ; IMAD R17, R20, c[0x0][0x178], R21 ; MOV R7, RZ ; IMAD R16, R22, c[0x0][0x178], R19 ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; UMOV UR4, 0xffffffff ; LEA R2, R19, 0x1000, 0x2 ; LEA.HI R18, R3, R0, RZ, 0x5 ; SHF.L.U32 R0, R20, 0x7, RZ ; SHF.R.S32.HI R18, RZ, 0x5, R18 ; LEA R3, R19, R0, 0x2 ; ISETP.GE.U32.AND P2, PT, R19, c[0x0][0x178], PT ; HFMA2.MMA R6, -RZ, RZ, 0, 0 ; ISETP.GE.U32.AND P1, PT, R20, c[0x0][0x178], PT ; ISETP.GE.OR P2, PT, R22, c[0x0][0x178], P2 ; ISETP.GE.OR P1, PT, R21, c[0x0][0x178], P1 ; MOV R29, RZ ; @!P2 MOV R5, 0x4 ; @!P1 MOV R26, 0x4 ; @!P2 IMAD.WIDE.U32 R4, R16, R5, c[0x0][0x160] ; @!P1 IMAD.WIDE.U32 R26, R17, R26, c[0x0][0x168] ; @!P2 LDG.E R6, [R4.64] ; @!P1 LDG.E R29, [R26.64] ; UIADD3 UR4, UR4, 0x1, URZ ; IADD3 R20, R20, 0x20, RZ ; IADD3 R19, R19, 0x20, RZ ; IADD3 R16, R16, 0x20, RZ ; ISETP.LE.AND P1, PT, R18, UR4, PT ; STS [R3], R6 ; STS [R3+0x1000], R29 ; BAR.SYNC 0x0 ; LDS R4, [R2] ; LDS.128 R8, [R0] ; LDS R5, [R2+0x80] ; LDS R27, [R2+0x100] ; LDS R28, [R2+0x180] ; LDS R25, [R2+0x200] ; LDS.128 R12, [R0+0x10] ; LDS R24, [R2+0x280] ; LDS R23, [R2+0x300] ; LDS R26, [R2+0x380] ; LDS R29, [R2+0x900] ; FFMA R4, R4, R8, R7 ; LDS R8, [R2+0x480] ; FFMA R5, R5, R9, R4 ; LDS R9, [R2+0x400] ; FFMA R10, R27, R10, R5 ; LDS.128 R4, [R0+0x20] ; FFMA R10, R28, R11, R10 ; LDS R11, [R2+0x500] ; LDS R27, [R2+0x800] ; FFMA R10, R25, R12, R10 ; LDS R25, [R2+0x700] ; FFMA R10, R24, R13, R10 ; LDS R24, [R2+0x580] ; FFMA R10, R23, R14, R10 ; LDS R23, [R2+0x600] ; FFMA R10, R26, R15, R10 ; LDS.128 R12, [R0+0x30] ; LDS R26, [R2+0x680] ; LDS R28, [R2+0xa80] ; FFMA R9, R9, R4, R10 ; LDS R4, [R2+0x780] ; FFMA R5, R8, R5, R9 ; FFMA R5, R11, R6, R5 ; LDS.128 R8, [R0+0x40] ; FFMA R5, R24, R7, R5 ; LDS R24, [R2+0x880] ; FFMA R5, R23, R12, R5 ; LDS R23, [R2+0xa00] ; FFMA R5, R26, R13, R5 ; LDS R26, [R2+0x980] ; FFMA R5, R25, R14, R5 ; LDS R25, [R2+0xb00] ; FFMA R15, R4, R15, R5 ; LDS.128 R4, [R0+0x50] ; FFMA R15, R27, R8, R15 ; LDS R8, [R2+0xb80] ; FFMA R9, R24, R9, R15 ; LDS.128 R12, [R0+0x60] ; FFMA R10, R29, R10, R9 ; LDS R9, [R2+0xc00] ; LDS R24, [R2+0xd80] ; FFMA R11, R26, R11, R10 ; LDS R10, [R2+0xc80] ; FFMA R4, R23, R4, R11 ; LDS R11, [R2+0xd00] ; FFMA R4, R28, R5, R4 ; LDS R23, [R2+0xf00] ; FFMA R4, R25, R6, R4 ; LDS R25, [R2+0xe00] ; FFMA R26, R8, R7, R4 ; LDS.128 R4, [R0+0x70] ; LDS R8, [R2+0xe80] ; FFMA R9, R9, R12, R26 ; LDS R12, [R2+0xf80] ; FFMA R9, R10, R13, R9 ; FFMA R9, R11, R14, R9 ; FFMA R9, R24, R15, R9 ; FFMA R4, R25, R4, R9 ; FFMA R4, R8, R5, R4 ; MOV R8, c[0x0][0x178] ; FFMA R4, R23, R6, R4 ; LEA R17, R8, R17, 0x5 ; FFMA R7, R12, R7, R4 ; BAR.SYNC 0x0 ; @!P1 BRA 0x190 ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R2, R22, c[0x0][0x178], R21 ; IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; STG.E [R2.64], R7 ; EXIT ; BRA 0x7f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14matrixMultiplyPfS_S_i ; -- Begin function _Z14matrixMultiplyPfS_S_i .globl _Z14matrixMultiplyPfS_S_i .p2align 8 .type _Z14matrixMultiplyPfS_S_i,@function _Z14matrixMultiplyPfS_S_i: ; @_Z14matrixMultiplyPfS_S_i ; %bb.0: s_clause 0x3 s_load_b32 s9, s[0:1], 0x2c s_load_b32 s8, s[0:1], 0x18 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_bfe_u32 v3, v0, 10, 10 v_and_b32_e32 v4, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s0, s9, 16 s_and_b32 s1, s9, 0xffff s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s15, s0, v[3:4] v_mad_u64_u32 v[1:2], null, s14, s1, v[4:5] v_mov_b32_e32 v2, 0 s_cmpk_lt_i32 s8, 0xffe2 s_cbranch_scc1 .LBB0_14 ; %bb.1: ; %.lr.ph v_lshlrev_b32_e32 v2, 2, v4 s_add_i32 s0, s8, -1 v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v7, 7, v3 s_ashr_i32 s1, s0, 31 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v8, 0x1000, v2 v_mul_lo_u32 v10, v0, s8 s_lshr_b32 s1, s1, 27 v_cmp_gt_i32_e32 vcc_lo, s8, v0 s_add_i32 s1, s0, s1 v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2 v_cmp_gt_i32_e64 s0, s8, v1 v_add_nc_u32_e32 v11, v8, v7 s_ashr_i32 s9, s1, 5 s_mov_b32 s10, 0 .LBB0_2: ; =>This Loop Header: Depth=1 ; Child Loop BB0_11 Depth 2 v_mov_b32_e32 v5, 0 s_and_saveexec_b32 s11, vcc_lo s_cbranch_execz .LBB0_6 ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 v_lshl_add_u32 v12, s10, 5, v4 v_mov_b32_e32 v5, 0 s_mov_b32 s12, exec_lo s_delay_alu instid0(VALU_DEP_2) v_cmpx_gt_u32_e64 s8, v12 s_cbranch_execz .LBB0_5 ; %bb.4: ; in Loop: Header=BB0_2 Depth=1 v_add_nc_u32_e32 v5, v12, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], 2, v[5:6] v_add_co_u32 v12, s1, s4, v12 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v13, s1, s5, v13, s1 global_load_b32 v5, v[12:13], off .LBB0_5: ; %Flow68 ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 .LBB0_6: ; in Loop: Header=BB0_2 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v12, 0 s_waitcnt vmcnt(0) ds_store_b32 v9, v5 s_and_saveexec_b32 s11, s0 s_cbranch_execz .LBB0_10 ; %bb.7: ; in Loop: Header=BB0_2 Depth=1 v_lshl_add_u32 v5, s10, 5, v3 v_mov_b32_e32 v12, 0 s_mov_b32 s12, exec_lo s_delay_alu instid0(VALU_DEP_2) v_cmpx_gt_u32_e64 s8, v5 s_cbranch_execz .LBB0_9 ; %bb.8: ; in Loop: Header=BB0_2 Depth=1 v_mad_u64_u32 v[12:13], null, v5, s8, v[1:2] v_mov_b32_e32 v13, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], 2, v[12:13] v_add_co_u32 v12, s1, s6, v12 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v13, s1, s7, v13, s1 global_load_b32 v12, v[12:13], off .LBB0_9: ; %Flow ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 .LBB0_10: ; in Loop: Header=BB0_2 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v5, v8 s_mov_b32 s1, 0 s_waitcnt vmcnt(0) ds_store_b32 v11, v12 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_11: ; Parent Loop BB0_2 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v12, s1, v7 s_add_i32 s1, s1, 4 ds_load_b32 v13, v5 ds_load_b32 v12, v12 v_add_nc_u32_e32 v5, 0x80, v5 s_cmpk_eq_i32 s1, 0x80 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v2, v12, v13 s_cbranch_scc0 .LBB0_11 ; %bb.12: ; in Loop: Header=BB0_2 Depth=1 s_add_i32 s1, s10, 1 s_cmp_eq_u32 s10, s9 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_14 ; %bb.13: ; in Loop: Header=BB0_2 Depth=1 s_mov_b32 s10, s1 s_branch .LBB0_2 .LBB0_14: ; %Flow70 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_max_i32_e32 v3, v1, v0 s_mov_b32 s0, exec_lo v_cmpx_gt_i32_e64 s8, v3 s_cbranch_execz .LBB0_16 ; %bb.15: v_mad_u64_u32 v[3:4], null, v0, s8, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_16: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14matrixMultiplyPfS_S_i .amdhsa_group_segment_fixed_size 8192 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14matrixMultiplyPfS_S_i, .Lfunc_end0-_Z14matrixMultiplyPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 600 ; NumSgprs: 18 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 8192 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 8192 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14matrixMultiplyPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14matrixMultiplyPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000daaaf_00000000-6_cuda_code_026189.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6835: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6835: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB7717: .cfi_startproc jmp *%rsi .cfi_endproc .LFE7717: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i .type _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i, @function _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i: .LFB6857: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movq %rdx, 8(%rsp) leaq 40(%rsp), %rdx movl %ecx, 4(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z14matrixMultiplyPfS_S_i(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L3: movq 136(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6857: .size _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i .globl _Z14matrixMultiplyPfS_S_i .type _Z14matrixMultiplyPfS_S_i, @function _Z14matrixMultiplyPfS_S_i: .LFB6858: .cfi_startproc endbr64 jmp _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i .cfi_endproc .LFE6858: .size _Z14matrixMultiplyPfS_S_i, .-_Z14matrixMultiplyPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Error allocating device memory for d_A: " .LC2: .string "Error allocating device memory for d_B: " .LC3: .string "Error allocating device memory for d_C: " .LC4: .string "Error copying h_A to d_A: " .LC5: .string "Error copying h_B to d_B: " .LC6: .string "Error launching kernel: " .LC7: .string "Error copying d_C to h_C: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6832: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $4096, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 xorl %r12d, %r12d pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $72, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call malloc@PLT movl $4096, %edi movq %rax, %rbp call malloc@PLT movl $4096, %edi movq %rax, %rbx call malloc@PLT movq %rax, %r13 .L10: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, 0(%rbp,%r12) call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movss %xmm0, (%rbx,%r12) addq $4, %r12 cmpq $4096, %r12 jne .L10 movl $4096, %esi leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq .LC1(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L24 leaq 16(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax je .L13 leaq .LC2(%rip), %rsi .L24: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r12d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L9 .L13: movl $4096, %esi leaq 24(%rsp), %rdi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L24 movq 8(%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $4096, %edx call cudaMemcpy@PLT leaq .LC4(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L24 movq 16(%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $4096, %edx call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L24 xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movl $1, %esi movabsq $137438953504, %rdx movabsq $4294967297, %rdi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $32, %ecx movq 8(%rsp), %rdi call _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i .L18: call cudaGetLastError@PLT leaq .LC6(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L24 movq 24(%rsp), %rsi movl $2, %ecx movl $4096, %edx movq %r13, %rdi call cudaMemcpy@PLT leaq .LC7(%rip), %rsi movl %eax, %r12d testl %eax, %eax jne .L24 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r13, %rdi call free@PLT xorl %eax, %eax .L9: movq 56(%rsp), %rdx subq %fs:40, %rdx je .L21 call __stack_chk_fail@PLT .L21: addq $72, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6832: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z14matrixMultiplyPfS_S_i" .LC9: .string "_ZN50_INTERNAL_4bca3a00_19_cuda_code_026189_cu_74137dcf4cuda3std3__419piecewise_constructE" .LC10: .string "_ZN50_INTERNAL_4bca3a00_19_cuda_code_026189_cu_74137dcf4cuda3std6ranges3__45__cpo4swapE" .LC11: .string "_ZN50_INTERNAL_4bca3a00_19_cuda_code_026189_cu_74137dcf4cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6860: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC8(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z14matrixMultiplyPfS_S_i(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC9(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC10(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6860: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 805306368 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_026189.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z29__device_stub__matrixMultiplyPfS_S_i # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_i .type _Z29__device_stub__matrixMultiplyPfS_S_i,@function _Z29__device_stub__matrixMultiplyPfS_S_i: # @_Z29__device_stub__matrixMultiplyPfS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 24(%rsp), %rsi movq %rdx, (%rsi) leaq 4(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z14matrixMultiplyPfS_S_i, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z29__device_stub__matrixMultiplyPfS_S_i, .Lfunc_end0-_Z29__device_stub__matrixMultiplyPfS_S_i .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x30000000 # float 4.65661287E-10 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $32, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r14 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r15 xorl %r12d, %r12d .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm0 movss %xmm0, (%rbx,%r12,4) callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI1_0(%rip), %xmm0 movss %xmm0, (%r14,%r12,4) incq %r12 cmpq $1024, %r12 # imm = 0x400 jne .LBB1_1 # %bb.2: leaq 24(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax je .LBB1_4 # %bb.3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi jmp .LBB1_8 .LBB1_4: leaq 16(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax je .LBB1_6 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi jmp .LBB1_8 .LBB1_6: leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax je .LBB1_15 # %bb.7: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi .LBB1_8: movl $40, %edx .LBB1_9: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_11 # %bb.10: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_12 .LBB1_11: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_13: movl $-1, %eax .LBB1_14: addq $32, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_15: .cfi_def_cfa_offset 80 movq 24(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_17 # %bb.16: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $26, %edx jmp .LBB1_9 .LBB1_17: movq 16(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_20 # %bb.18: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi .LBB1_19: movl $26, %edx jmp .LBB1_24 .LBB1_20: movabsq $4294967297, %rdi # imm = 0x100000001 movabsq $137438953504, %rdx # imm = 0x2000000020 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_22 # %bb.21: movq 24(%rsp), %rdi movq 16(%rsp), %rsi movq 8(%rsp), %rdx movl $32, %ecx callq _Z29__device_stub__matrixMultiplyPfS_S_i .LBB1_22: callq hipGetLastError testl %eax, %eax je .LBB1_25 # %bb.23: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $24, %edx .LBB1_24: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB1_13 .LBB1_25: movq 8(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_27 # %bb.26: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.6, %esi jmp .LBB1_19 .LBB1_27: movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax jmp .LBB1_14 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14matrixMultiplyPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z14matrixMultiplyPfS_S_i,@object # @_Z14matrixMultiplyPfS_S_i .section .rodata,"a",@progbits .globl _Z14matrixMultiplyPfS_S_i .p2align 3, 0x0 _Z14matrixMultiplyPfS_S_i: .quad _Z29__device_stub__matrixMultiplyPfS_S_i .size _Z14matrixMultiplyPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error allocating device memory for d_A: " .size .L.str, 41 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error allocating device memory for d_B: " .size .L.str.1, 41 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Error allocating device memory for d_C: " .size .L.str.2, 41 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Error copying h_A to d_A: " .size .L.str.3, 27 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error copying h_B to d_B: " .size .L.str.4, 27 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Error launching kernel: " .size .L.str.5, 25 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Error copying d_C to h_C: " .size .L.str.6, 27 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14matrixMultiplyPfS_S_i" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14matrixMultiplyPfS_S_i .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
4,958
5,115
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z15sparseMatVecMulPKiS0_PKfS2_Pf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R14, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R14, R14, c[0x0][0x0], R3 ; ISETP.GT.AND P0, PT, R14, 0xff, PT ; @P0 EXIT ; HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; LDG.E R19, [R2.64] ; LDG.E R16, [R2.64+0x4] ; BSSY B0, 0xe40 ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; SHF.R.S32.HI R17, RZ, 0x1f, R14 ; ISETP.GE.AND P0, PT, R19, R16, PT ; @P0 BRA 0xe30 ; IADD3 R3, R19.reuse, 0x1, RZ ; BSSY B1, 0x330 ; MOV R8, RZ ; IMNMX R0, R16, R3, !PT ; LOP3.LUT R3, RZ, R19, RZ, 0x33, !PT ; IADD3 R2, -R19, R0, RZ ; IADD3 R3, R0, R3, RZ ; LOP3.LUT P1, R0, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; @!P1 BRA 0x320 ; IMAD.WIDE R2, R19, R15, c[0x0][0x168] ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; IMAD.WIDE R4, R19, R15, c[0x0][0x170] ; MOV R9, R2 ; MOV R12, R3 ; MOV R7, R4 ; MOV R10, R5 ; MOV R4, R9 ; MOV R5, R12 ; LDG.E R2, [R4.64] ; MOV R4, R7 ; MOV R5, R10 ; LDG.E R6, [R4.64] ; IMAD.WIDE R2, R2, R15, c[0x0][0x178] ; LDG.E R3, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P1, PT, R0, RZ, PT ; IADD3 R9, P2, R9, 0x4, RZ ; IADD3 R7, P3, R7, 0x4, RZ ; IADD3 R19, R19, 0x1, RZ ; IADD3.X R12, RZ, R12, RZ, P2, !PT ; IADD3.X R10, RZ, R10, RZ, P3, !PT ; FFMA R8, R3, R6, R8 ; @P1 BRA 0x210 ; BSYNC B1 ; @!P0 BRA 0xe30 ; IADD3 R0, R16, -R19, RZ ; IMAD.WIDE R2, R19, R15, c[0x2][0x0] ; BSSY B1, 0x990 ; ISETP.GT.AND P1, PT, R0, 0xc, PT ; IADD3 R4, P0, R2.reuse, c[0x0][0x170], RZ ; IADD3 R6, P2, R2, c[0x0][0x168], RZ ; IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; IADD3.X R7, R3, c[0x0][0x16c], RZ, P2, !PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x980 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R18, R16, -0xc, RZ ; LDG.E R24, [R6.64+-0x8] ; LDG.E R10, [R6.64+-0x4] ; LDG.E R20, [R6.64] ; LDG.E R22, [R6.64+0x4] ; LDG.E R26, [R6.64+0x8] ; LDG.E R3, [R4.64+-0x8] ; LDG.E R12, [R4.64+-0x4] ; LDG.E R13, [R6.64+0xc] ; LDG.E R28, [R6.64+0x10] ; LDG.E R29, [R4.64] ; LDG.E R2, [R4.64+0x4] ; IMAD.WIDE R24, R24, R15, c[0x0][0x178] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R0, [R24.64] ; IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x178] ; LDG.E R9, [R10.64] ; LDG.E R21, [R20.64] ; IMAD.WIDE R22, R22, R15, c[0x0][0x178] ; LDG.E R24, [R6.64+0x18] ; IMAD.WIDE R26, R26, R15, c[0x0][0x178] ; LDG.E R25, [R22.64] ; LDG.E R20, [R6.64+0x14] ; LDG.E R10, [R26.64] ; LDG.E R11, [R4.64+0x8] ; LDG.E R23, [R4.64+0xc] ; LDG.E R22, [R6.64+0x20] ; LDG.E R26, [R6.64+0x30] ; FFMA R0, R0, R3, R8 ; LDG.E R3, [R4.64+0x14] ; FFMA R0, R9, R12, R0 ; IMAD.WIDE R12, R13, R15, c[0x0][0x178] ; IMAD.WIDE R8, R28, R15, c[0x0][0x178] ; LDG.E R28, [R4.64+0x18] ; FFMA R0, R21, R29, R0 ; LDG.E R21, [R12.64] ; LDG.E R29, [R6.64+0x1c] ; LDG.E R9, [R8.64] ; IMAD.WIDE R12, R20, R15, c[0x0][0x178] ; LDG.E R20, [R4.64+0x10] ; FFMA R0, R25, R2, R0 ; LDG.E R27, [R12.64] ; IMAD.WIDE R24, R24, R15, c[0x0][0x178] ; LDG.E R2, [R6.64+0x24] ; LDG.E R8, [R6.64+0x28] ; FFMA R12, R10, R11, R0 ; LDG.E R11, [R24.64] ; LDG.E R10, [R6.64+0x2c] ; LDG.E R0, [R6.64+0x34] ; LDG.E R24, [R4.64+0x20] ; LDG.E R25, [R4.64+0x24] ; FFMA R21, R21, R23, R12 ; LDG.E R23, [R4.64+0x1c] ; IMAD.WIDE R12, R29, R15, c[0x0][0x178] ; LDG.E R29, [R4.64+0x28] ; FFMA R9, R9, R20, R21 ; IMAD.WIDE R20, R22, R15, c[0x0][0x178] ; LDG.E R22, [R12.64] ; FFMA R27, R27, R3, R9 ; IMAD.WIDE R2, R2, R15.reuse, c[0x0][0x178] ; LDG.E R21, [R20.64] ; IMAD.WIDE R8, R8, R15, c[0x0][0x178] ; LDG.E R2, [R2.64] ; FFMA R28, R11, R28, R27 ; LDG.E R8, [R8.64] ; IMAD.WIDE R10, R10, R15, c[0x0][0x178] ; LDG.E R20, [R4.64+0x2c] ; IMAD.WIDE R12, R26, R15, c[0x0][0x178] ; LDG.E R11, [R10.64] ; IMAD.WIDE R26, R0, R15, c[0x0][0x178] ; LDG.E R13, [R12.64] ; LDG.E R0, [R4.64+0x30] ; LDG.E R26, [R26.64] ; LDG.E R3, [R4.64+0x34] ; IADD3 R19, R19, 0x10, RZ ; ISETP.GE.AND P1, PT, R19, R18, PT ; IADD3 R6, P3, R6, 0x40, RZ ; IADD3 R9, P2, R4, 0x40, RZ ; IADD3.X R7, RZ, R7, RZ, P3, !PT ; IADD3.X R5, RZ, R5, RZ, P2, !PT ; MOV R4, R9 ; FFMA R22, R22, R23, R28 ; FFMA R21, R21, R24, R22 ; FFMA R2, R2, R25, R21 ; FFMA R2, R8, R29, R2 ; FFMA R2, R11, R20, R2 ; FFMA R0, R13, R0, R2 ; FFMA R8, R26, R3, R0 ; @!P1 BRA 0x400 ; BSYNC B1 ; IADD3 R0, R16, -R19, RZ ; BSSY B1, 0xcd0 ; ISETP.GT.AND P1, PT, R0, 0x4, PT ; @!P1 BRA 0xcc0 ; LDG.E R22, [R6.64+-0x8] ; LDG.E R28, [R6.64+-0x4] ; LDG.E R2, [R6.64] ; LDG.E R3, [R6.64+0x4] ; LDG.E R10, [R6.64+0x8] ; LDG.E R12, [R6.64+0xc] ; LDG.E R20, [R6.64+0x10] ; LDG.E R24, [R6.64+0x14] ; LDG.E R0, [R4.64+-0x8] ; LDG.E R18, [R4.64+-0x4] ; LDG.E R27, [R4.64] ; IMAD.WIDE R22, R22, R15, c[0x0][0x178] ; IMAD.WIDE R28, R28, R15.reuse, c[0x0][0x178] ; LDG.E R9, [R22.64] ; LDG.E R25, [R28.64] ; IMAD.WIDE R22, R2, R15, c[0x0][0x178] ; IMAD.WIDE R2, R3, R15.reuse, c[0x0][0x178] ; LDG.E R26, [R22.64] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R29, [R4.64+0xc] ; LDG.E R2, [R2.64] ; IMAD.WIDE R12, R12, R15, c[0x0][0x178] ; LDG.E R10, [R10.64] ; IMAD.WIDE R20, R20, R15, c[0x0][0x178] ; LDG.E R12, [R12.64] ; LDG.E R3, [R4.64+0x4] ; LDG.E R11, [R4.64+0x8] ; IMAD.WIDE R22, R24, R15, c[0x0][0x178] ; LDG.E R20, [R20.64] ; LDG.E R24, [R4.64+0x10] ; LDG.E R22, [R22.64] ; LDG.E R28, [R4.64+0x14] ; IADD3 R6, P2, R6, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R7, RZ, R7, RZ, P2, !PT ; IADD3 R19, R19, 0x8, RZ ; FFMA R0, R9, R0, R8 ; FFMA R0, R25, R18, R0 ; FFMA R0, R26, R27, R0 ; FFMA R0, R2, R3, R0 ; FFMA R0, R10, R11, R0 ; FFMA R29, R12, R29, R0 ; IADD3 R0, P1, R4, 0x20, RZ ; FFMA R29, R20, R24, R29 ; IADD3.X R5, RZ, R5, RZ, P1, !PT ; MOV R4, R0 ; FFMA R8, R22, R28, R29 ; BSYNC B1 ; ISETP.LT.OR P0, PT, R19, R16, P0 ; @!P0 BRA 0xe30 ; LDG.E R2, [R6.64+-0x8] ; LDG.E R10, [R6.64+-0x4] ; LDG.E R12, [R6.64] ; LDG.E R18, [R6.64+0x4] ; LDG.E R0, [R4.64+-0x8] ; LDG.E R9, [R4.64+-0x4] ; LDG.E R6, [R4.64+0x4] ; IMAD.WIDE R2, R2, R15, c[0x0][0x178] ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x178] ; LDG.E R3, [R2.64] ; IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x178] ; LDG.E R11, [R10.64] ; IMAD.WIDE R18, R18, R15, c[0x0][0x178] ; LDG.E R13, [R12.64] ; LDG.E R15, [R4.64] ; LDG.E R19, [R18.64] ; FFMA R0, R3, R0, R8 ; FFMA R0, R11, R9, R0 ; FFMA R0, R13, R15, R0 ; FFMA R8, R19, R6, R0 ; BSYNC B0 ; LEA R2, P0, R14, c[0x0][0x180], 0x2 ; LEA.HI.X R3, R14, c[0x0][0x184], R17, 0x2, P0 ; STG.E [R2.64], R8 ; EXIT ; BRA 0xe80; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15sparseMatVecMulPKiS0_PKfS2_Pf ; -- Begin function _Z15sparseMatVecMulPKiS0_PKfS2_Pf .globl _Z15sparseMatVecMulPKiS0_PKfS2_Pf .p2align 8 .type _Z15sparseMatVecMulPKiS0_PKfS2_Pf,@function _Z15sparseMatVecMulPKiS0_PKfS2_Pf: ; @_Z15sparseMatVecMulPKiS0_PKfS2_Pf ; %bb.0: s_load_b32 s2, s[0:1], 0x34 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x100, v1 s_cbranch_execz .LBB0_6 ; %bb.1: s_load_b256 s[4:11], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[2:3], s[0:1], 0x20 v_mov_b32_e32 v8, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_cmpx_lt_i32_e64 v2, v3 s_cbranch_execz .LBB0_5 ; %bb.2: ; %.lr.ph.preheader v_ashrrev_i32_e32 v5, 31, v2 v_mov_b32_e32 v4, v2 v_mov_b32_e32 v8, 0 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[4:5] v_add_co_u32 v4, vcc_lo, s8, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo v_add_co_u32 v6, vcc_lo, s6, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b32 v9, v[6:7], off v_add_nc_u32_e32 v2, 1, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s0, v2, v3 s_or_b32 s4, s0, s4 s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v10, 31, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[9:10], 2, v[9:10] v_add_co_u32 v9, vcc_lo, s10, v9 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo global_load_b32 v11, v[4:5], off global_load_b32 v9, v[9:10], off v_add_co_u32 v4, vcc_lo, v4, 4 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo v_add_co_u32 v6, vcc_lo, v6, 4 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo s_waitcnt vmcnt(0) v_fmac_f32_e32 v8, v11, v9 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_3 ; %bb.4: ; %Flow s_or_b32 exec_lo, exec_lo, s4 .LBB0_5: ; %Flow42 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b32 v[0:1], v8, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15sparseMatVecMulPKiS0_PKfS2_Pf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15sparseMatVecMulPKiS0_PKfS2_Pf, .Lfunc_end0-_Z15sparseMatVecMulPKiS0_PKfS2_Pf ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 352 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15sparseMatVecMulPKiS0_PKfS2_Pf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15sparseMatVecMulPKiS0_PKfS2_Pf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000fcce8_00000000-6_cuda_code_043544.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3638: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3638: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4293: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4293: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .type _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf, @function _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf: .LFB3660: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) leaq 64(%rsp), %rdi movq %rsi, 32(%rsp) leaq 76(%rsp), %rsi movq %rdx, 24(%rsp) leaq 48(%rsp), %rdx movq %rcx, 16(%rsp) leaq 56(%rsp), %rcx movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movl $1, 72(%rsp) movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movabsq $4294967297, %rax movq %rax, 64(%rsp) movq %rax, 76(%rsp) movl $1, 84(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L3 pushq 56(%rsp) .cfi_def_cfa_offset 184 leaq _Z15sparseMatVecMulPKiS0_PKfS2_Pf(%rip), %rdi pushq 56(%rsp) .cfi_def_cfa_offset 192 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq 128(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 184 popq %rdx .cfi_def_cfa_offset 176 .L3: movq 152(%rsp), %rax subq %fs:40, %rax je .L5 call __stack_chk_fail@PLT .L5: addq $168, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3660: .size _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf, .-_Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .globl _Z15sparseMatVecMulPKiS0_PKfS2_Pf .type _Z15sparseMatVecMulPKiS0_PKfS2_Pf, @function _Z15sparseMatVecMulPKiS0_PKfS2_Pf: .LFB3661: .cfi_startproc endbr64 jmp _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .cfi_endproc .LFE3661: .size _Z15sparseMatVecMulPKiS0_PKfS2_Pf, .-_Z15sparseMatVecMulPKiS0_PKfS2_Pf .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Failed to allocate memory for d_rowPtr" .LC2: .string "Failed to allocate memory for d_colIdx" .LC3: .string "Failed to allocate memory for d_values" .LC4: .string "Failed to allocate memory for d_x" .LC5: .string "Failed to allocate memory for d_y" .LC6: .string "Failed to copy rowPtr to device" .LC7: .string "Failed to copy colIdx to device" .LC8: .string "Failed to copy values to device" .LC9: .string "Failed to copy x to device" .LC10: .string "Failed to launch sparseMatVecMul kernel" .LC11: .string "Failed to copy y to host" .LC12: .string "Result vector y:" .LC13: .string " " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3635: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 leaq -32768(%rsp), %r11 .cfi_def_cfa 11, 32808 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $3160, %rsp .cfi_def_cfa_offset 35968 movss .LC0(%rip), %xmm0 xorl %ecx, %ecx movq %fs:40, %rax movq %rax, 35912(%rsp) xorl %eax, %eax leaq 2116(%rsp), %rbp .L12: movl %eax, 0(%rbp,%rcx,4) xorl %edx, %edx .L11: testb $31, %dl jne .L10 movslq %eax, %rsi incl %eax movl %edx, 3144(%rsp,%rsi,4) movss %xmm0, 19528(%rsp,%rsi,4) .L10: incl %edx cmpl $256, %edx jne .L11 incq %rcx cmpq $256, %rcx jne .L12 movss .LC0(%rip), %xmm0 movl %eax, 3140(%rsp) xorl %eax, %eax .L13: leaq 68(%rsp), %rbx movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $256, %rax jne .L13 movq %rsp, %rdi movl $1028, %esi call cudaMalloc@PLT testl %eax, %eax je .L14 leaq .LC1(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 jmp .L15 .L14: leaq 8(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT testl %eax, %eax je .L16 leaq .LC2(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi .L35: call cudaFree@PLT .L15: orl $-1, %eax jmp .L9 .L16: leaq 16(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT testl %eax, %eax je .L18 leaq .LC3(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi jmp .L35 .L18: leaq 24(%rsp), %rdi movl $1024, %esi call cudaMalloc@PLT testl %eax, %eax je .L19 leaq .LC4(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi jmp .L35 .L19: leaq 32(%rsp), %rdi movl $1024, %esi call cudaMalloc@PLT testl %eax, %eax je .L20 leaq .LC5(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi jmp .L35 .L20: movq (%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $1028, %edx call cudaMemcpy@PLT leaq .LC6(%rip), %rsi testl %eax, %eax jne .L36 movq 8(%rsp), %rdi movl $1, %ecx movl $16384, %edx leaq 3144(%rsp), %rsi call cudaMemcpy@PLT leaq .LC7(%rip), %rsi testl %eax, %eax jne .L36 movq 16(%rsp), %rdi movl $1, %ecx movl $16384, %edx leaq 19528(%rsp), %rsi call cudaMemcpy@PLT leaq .LC8(%rip), %rsi testl %eax, %eax jne .L36 movq 24(%rsp), %rdi movq %rbx, %rsi movl $1, %ecx movl $1024, %edx call cudaMemcpy@PLT leaq .LC9(%rip), %rsi testl %eax, %eax jne .L36 movl $16777217, %edx xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx salq $8, %rdx movl $1, %esi movabsq $4294967297, %rdi movl $1, 64(%rsp) movq %rdx, 56(%rsp) movq %rdi, 44(%rsp) movl $1, 52(%rsp) call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L25 movq 32(%rsp), %r8 movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z47__device_stub__Z15sparseMatVecMulPKiS0_PKfS2_PfPKiS0_PKfS2_Pf .L25: call cudaGetLastError@PLT leaq .LC10(%rip), %rsi testl %eax, %eax jne .L36 movq 32(%rsp), %rsi movl $2, %ecx movl $1024, %edx leaq 1092(%rsp), %r12 movq %r12, %rdi call cudaMemcpy@PLT testl %eax, %eax je .L27 leaq .LC11(%rip), %rsi .L36: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi jmp .L35 .L27: leaq _ZSt4cout(%rip), %rbp leaq .LC12(%rip), %rsi xorl %ebx, %ebx movq %rbp, %rdi leaq .LC13(%rip), %r13 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 .L28: movq %rbp, %rdi cvtss2sd (%r12,%rbx,4), %xmm0 incq %rbx call _ZNSo9_M_insertIdEERSoT_@PLT movq %r13, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpq $256, %rbx jne .L28 movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rbp, %rdi call _ZNSolsEPFRSoS_E.isra.0 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT xorl %eax, %eax .L9: movq 35912(%rsp), %rdx subq %fs:40, %rdx je .L29 call __stack_chk_fail@PLT .L29: addq $35928, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size main, .-main .section .rodata.str1.1 .LC14: .string "_Z15sparseMatVecMulPKiS0_PKfS2_Pf" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3663: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rax, %rdi leaq _Z15sparseMatVecMulPKiS0_PKfS2_Pf(%rip), %rsi pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi addq $32, %rsp .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rdx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3663: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_043544.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf # -- Begin function _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .type _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf,@function _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf: # @_Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $144, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 56(%rsp), %rax movq %rdi, (%rax) leaq 48(%rsp), %rdi movq %rsi, (%rdi) leaq 40(%rsp), %rsi movq %rdx, (%rsi) leaq 32(%rsp), %rdx movq %rcx, (%rdx) leaq 24(%rsp), %rcx movq %r8, (%rcx) leaq 96(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) movq %rcx, 32(%rbx) leaq 80(%rsp), %r14 leaq 64(%rsp), %r15 leaq 16(%rsp), %r12 leaq 8(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z15sparseMatVecMulPKiS0_PKfS2_Pf, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $160, %rsp .cfi_adjust_cfa_offset -160 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf, .Lfunc_end0-_Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $35904, %rsp # imm = 0x8C40 .cfi_def_cfa_offset 35920 .cfi_offset %rbx, -16 xorl %eax, %eax xorl %ecx, %ecx .LBB1_1: # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 movl %ecx, 48(%rsp,%rax,4) xorl %edx, %edx .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 testb $31, %dl jne .LBB1_4 # %bb.3: # in Loop: Header=BB1_2 Depth=2 movslq %ecx, %rcx movl %edx, 19520(%rsp,%rcx,4) movl $1065353216, 3136(%rsp,%rcx,4) # imm = 0x3F800000 incl %ecx .LBB1_4: # in Loop: Header=BB1_2 Depth=2 incl %edx cmpl $256, %edx # imm = 0x100 jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 incq %rax cmpq $256, %rax # imm = 0x100 jne .LBB1_1 # %bb.6: movl %ecx, 1072(%rsp) xorl %eax, %eax .LBB1_7: # =>This Inner Loop Header: Depth=1 movl $1065353216, 2112(%rsp,%rax,4) # imm = 0x3F800000 incq %rax cmpq $256, %rax # imm = 0x100 jne .LBB1_7 # %bb.8: leaq 8(%rsp), %rdi movl $1028, %esi # imm = 0x404 callq hipMalloc testl %eax, %eax je .LBB1_10 # %bb.9: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $38, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv jmp .LBB1_27 .LBB1_10: leaq 16(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB1_12 # %bb.11: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $38, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi jmp .LBB1_26 .LBB1_12: leaq 24(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc testl %eax, %eax je .LBB1_14 # %bb.13: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $38, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi jmp .LBB1_26 .LBB1_14: leaq 32(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc testl %eax, %eax je .LBB1_16 # %bb.15: movl $_ZSt4cerr, %ebx movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $33, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi jmp .LBB1_26 .LBB1_16: leaq 40(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc testl %eax, %eax je .LBB1_18 # %bb.17: movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $33, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi jmp .LBB1_26 .LBB1_18: movq 8(%rsp), %rdi leaq 48(%rsp), %rsi movl $1028, %edx # imm = 0x404 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_20 # %bb.19: movl $_ZSt4cerr, %edi movl $.L.str.5, %esi jmp .LBB1_24 .LBB1_20: movq 16(%rsp), %rdi leaq 19520(%rsp), %rsi movl $16384, %edx # imm = 0x4000 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_22 # %bb.21: movl $_ZSt4cerr, %edi movl $.L.str.6, %esi jmp .LBB1_24 .LBB1_22: movq 24(%rsp), %rdi leaq 3136(%rsp), %rsi movl $16384, %edx # imm = 0x4000 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_29 # %bb.23: movl $_ZSt4cerr, %edi movl $.L.str.7, %esi .LBB1_24: movl $31, %edx .LBB1_25: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cerr, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi .LBB1_26: callq hipFree .LBB1_27: movl $-1, %eax .LBB1_28: addq $35904, %rsp # imm = 0x8C40 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_29: .cfi_def_cfa_offset 35920 movq 32(%rsp), %rdi leaq 2112(%rsp), %rsi movl $1024, %edx # imm = 0x400 movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_31 # %bb.30: movl $_ZSt4cerr, %edi movl $.L.str.8, %esi movl $26, %edx jmp .LBB1_25 .LBB1_31: movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_33 # %bb.32: movq 8(%rsp), %rdi movq 16(%rsp), %rsi movq 24(%rsp), %rdx movq 32(%rsp), %rcx movq 40(%rsp), %r8 callq _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .LBB1_33: callq hipGetLastError testl %eax, %eax je .LBB1_35 # %bb.34: movl $_ZSt4cerr, %edi movl $.L.str.9, %esi movl $39, %edx jmp .LBB1_25 .LBB1_35: movq 40(%rsp), %rsi leaq 1088(%rsp), %rdi movl $1024, %edx # imm = 0x400 movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_37 # %bb.36: movl $_ZSt4cerr, %edi movl $.L.str.10, %esi movl $24, %edx jmp .LBB1_25 .LBB1_37: movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $16, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ xorl %ebx, %ebx .LBB1_38: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtss2sd 1088(%rsp,%rbx,4), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.12, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %rbx cmpq $256, %rbx # imm = 0x100 jne .LBB1_38 # %bb.39: movl $_ZSt4cout, %edi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree xorl %eax, %eax jmp .LBB1_28 .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15sparseMatVecMulPKiS0_PKfS2_Pf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15sparseMatVecMulPKiS0_PKfS2_Pf,@object # @_Z15sparseMatVecMulPKiS0_PKfS2_Pf .section .rodata,"a",@progbits .globl _Z15sparseMatVecMulPKiS0_PKfS2_Pf .p2align 3, 0x0 _Z15sparseMatVecMulPKiS0_PKfS2_Pf: .quad _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .size _Z15sparseMatVecMulPKiS0_PKfS2_Pf, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate memory for d_rowPtr" .size .L.str, 39 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate memory for d_colIdx" .size .L.str.1, 39 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate memory for d_values" .size .L.str.2, 39 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate memory for d_x" .size .L.str.3, 34 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate memory for d_y" .size .L.str.4, 34 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy rowPtr to device" .size .L.str.5, 32 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to copy colIdx to device" .size .L.str.6, 32 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to copy values to device" .size .L.str.7, 32 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Failed to copy x to device" .size .L.str.8, 27 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to launch sparseMatVecMul kernel" .size .L.str.9, 40 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Failed to copy y to host" .size .L.str.10, 25 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Result vector y:" .size .L.str.11, 17 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz " " .size .L.str.12, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15sparseMatVecMulPKiS0_PKfS2_Pf" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__sparseMatVecMulPKiS0_PKfS2_Pf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15sparseMatVecMulPKiS0_PKfS2_Pf .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
5,681
6,774
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Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z16simpleUnetKernelPfS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.Y ; S2R R4, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R7, SR_TID.X ; IMAD R5, R5, c[0x0][0x4], R4 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; IMAD R0, R0, c[0x0][0x0], R7 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; @P0 EXIT ; UMOV UR6, 0x1 ; ULDC.64 UR4, c[0x0][0x170] ; UIADD3 UR5, -UR6, UR5, URZ ; UIADD3 UR4, -UR6, UR4, URZ ; ULDC.64 UR8, c[0x0][0x118] ; ISETP.GE.AND P0, PT, R5, UR5, PT ; ISETP.GE.OR P0, PT, R0, UR4, P0 ; ULDC.64 UR4, c[0x0][0x0] ; @!P0 MOV R3, 0x4 ; @!P0 IMAD R2, R5, c[0x0][0x170], R0 ; @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @!P0 LDG.E R2, [R2.64] ; UIADD3 UR4, -UR6, UR4, URZ ; LEA R11, R4, R7, 0x4 ; ISETP.GE.U32.AND P1, PT, R7, UR4, PT ; UIADD3 UR4, -UR6, UR5, URZ ; ISETP.EQ.OR P1, PT, R7, RZ, P1 ; ISETP.EQ.OR P1, PT, R4, RZ, P1 ; ISETP.GE.U32.OR P1, PT, R4, UR4, P1 ; @!P0 STS [R11.X4], R2 ; BAR.SYNC 0x0 ; @P1 EXIT ; LDS R2, [R11.X4+-0x4] ; HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; LDS R3, [R11.X4+0x4] ; LDS R7, [R11.X4+-0x40] ; LDS R9, [R11.X4+0x40] ; FADD R2, RZ, R2 ; FADD R2, R2, R3 ; IMAD R3, R5, c[0x0][0x170], R0 ; FADD R2, R2, R7 ; FADD R9, R2, R9 ; IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; FMUL R9, R9, 0.25 ; STG.E [R2.64], R9 ; EXIT ; BRA 0x2e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16simpleUnetKernelPfS_ii ; -- Begin function _Z16simpleUnetKernelPfS_ii .globl _Z16simpleUnetKernelPfS_ii .p2align 8 .type _Z16simpleUnetKernelPfS_ii,@function _Z16simpleUnetKernelPfS_ii: ; @_Z16simpleUnetKernelPfS_ii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[8:9], s[0:1], 0x10 v_and_b32_e32 v4, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s10, s2, 0xffff s_lshr_b32 s3, s2, 16 v_mad_u64_u32 v[0:1], null, s14, s10, v[4:5] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s8, v0 v_cmp_gt_i32_e64 s2, s9, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s4, s2 s_cbranch_execz .LBB0_5 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 s_add_i32 s0, s8, -1 s_add_i32 s1, s9, -1 v_cmp_gt_i32_e32 vcc_lo, s0, v0 v_cmp_gt_i32_e64 s0, s1, v1 v_lshlrev_b32_e32 v2, 2, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s1, vcc_lo, s0 s_and_saveexec_b32 s0, s1 s_cbranch_execz .LBB0_3 ; %bb.2: v_mad_u64_u32 v[5:6], null, v1, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v6, 31, v5 v_lshlrev_b64 v[5:6], 2, v[5:6] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b32 v5, v[5:6], off v_lshl_add_u32 v6, v3, 6, v2 s_waitcnt vmcnt(0) ds_store_b32 v6, v5 .LBB0_3: s_or_b32 exec_lo, exec_lo, s0 v_cmp_ne_u32_e32 vcc_lo, 0, v4 s_add_i32 s10, s10, -1 v_cmp_ne_u32_e64 s0, 0, v3 v_cmp_gt_u32_e64 s1, s10, v4 s_add_i32 s3, s3, -1 s_waitcnt lgkmcnt(0) v_cmp_gt_u32_e64 s2, s3, v3 s_and_b32 s0, vcc_lo, s0 s_barrier s_and_b32 s0, s0, s1 buffer_gl0_inv s_and_b32 s0, s0, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s0 s_cbranch_execz .LBB0_5 ; %bb.4: v_lshl_add_u32 v4, v3, 6, v2 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v2, -4, v4 ds_load_b32 v5, v2 ds_load_2addr_b32 v[2:3], v4 offset0:1 offset1:16 v_subrev_nc_u32_e32 v4, 64, v4 ds_load_b32 v6, v4 s_waitcnt lgkmcnt(2) v_add_f32_e32 v7, 0, v5 v_mad_u64_u32 v[4:5], null, v1, s8, v[0:1] s_waitcnt lgkmcnt(1) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v0, v7, v2 v_ashrrev_i32_e32 v5, 31, v4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v0, v0, v6 v_add_f32_e32 v2, v0, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[4:5] v_mul_f32_e32 v2, 0x3e800000, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_5: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16simpleUnetKernelPfS_ii .amdhsa_group_segment_fixed_size 1024 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16simpleUnetKernelPfS_ii, .Lfunc_end0-_Z16simpleUnetKernelPfS_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 448 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 1024 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 1024 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16simpleUnetKernelPfS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16simpleUnetKernelPfS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
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Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_000e5c2c_00000000-6_cuda_code_005191.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB6836: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE6836: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA error: " .LC1: .string " (" .LC2: .string ")" .text .globl _Z14checkCudaError9cudaErrorPKc .type _Z14checkCudaError9cudaErrorPKc, @function _Z14checkCudaError9cudaErrorPKc: .LFB6832: .cfi_startproc endbr64 testl %edi, %edi je .L2 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsi, %rbp leaq .LC0(%rip), %rsi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 movl %edi, %ebx leaq _ZSt4cerr(%rip), %rdi pushq %rax .cfi_def_cfa_offset 32 call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbp, %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq .LC2(%rip), %rsi movq %rax, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .L2: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE6832: .size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc .globl _Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii .type _Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii, @function _Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii: .LFB6858: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movl %edx, 12(%rsp) leaq 40(%rsp), %rdx movl %ecx, 8(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L8 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z16simpleUnetKernelPfS_ii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L8: movq 136(%rsp), %rax subq %fs:40, %rax je .L10 call __stack_chk_fail@PLT .L10: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6858: .size _Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii, .-_Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii .globl _Z16simpleUnetKernelPfS_ii .type _Z16simpleUnetKernelPfS_ii, @function _Z16simpleUnetKernelPfS_ii: .LFB6859: .cfi_startproc endbr64 jmp _Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii .cfi_endproc .LFE6859: .size _Z16simpleUnetKernelPfS_ii, .-_Z16simpleUnetKernelPfS_ii .section .rodata.str1.1 .LC3: .string "cudaMalloc d_input" .LC4: .string "cudaMalloc d_output" .LC5: .string "cudaMemcpy d_input" .LC6: .string "simpleUnetKernel launch failed" .LC7: .string "cudaMemcpy d_output" .LC8: .string "cudaFree d_input" .LC9: .string "cudaFree d_output" .LC10: .string "Kernel execution completed successfully." .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB6833: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movl $262144, %edi pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $56, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $262144, %edi movq %rax, %rbx call _Znam@PLT movq %rax, %rbp xorl %eax, %eax .L14: cvtsi2ssl %eax, %xmm0 movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $65536, %rax jne .L14 movq %rsp, %rdi movl $262144, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc leaq 8(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq .LC4(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%rsp), %rdi movl $1, %ecx movq %rbx, %rsi movl $262144, %edx call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movabsq $68719476752, %rdi movl $1, %esi movq %rdi, %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L15 movq 8(%rsp), %rsi movq (%rsp), %rdi movl $256, %ecx movl $256, %edx call _Z40__device_stub__Z16simpleUnetKernelPfS_iiPfS_ii .L15: call cudaGetLastError@PLT leaq .LC6(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rsi movl $2, %ecx movq %rbp, %rdi movl $262144, %edx call cudaMemcpy@PLT leaq .LC7(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq (%rsp), %rdi call cudaFree@PLT leaq .LC8(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC9(%rip), %rsi movl %eax, %edi call _Z14checkCudaError9cudaErrorPKc movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT leaq _ZSt4cout(%rip), %rdi leaq .LC10(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 40(%rsp), %rax subq %fs:40, %rax je .L16 call __stack_chk_fail@PLT .L16: addq $56, %rsp .cfi_def_cfa_offset 24 xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6833: .size main, .-main .section .rodata.str1.1 .LC11: .string "_Z16simpleUnetKernelPfS_ii" .LC12: .string "_ZN50_INTERNAL_c0d326bf_19_cuda_code_005191_cu_f25873f84cuda3std3__419piecewise_constructE" .LC13: .string "_ZN50_INTERNAL_c0d326bf_19_cuda_code_005191_cu_f25873f84cuda3std6ranges3__45__cpo4swapE" .LC14: .string "_ZN50_INTERNAL_c0d326bf_19_cuda_code_005191_cu_f25873f84cuda3std6ranges3__45__cpo9iter_moveE" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6861: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC11(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z16simpleUnetKernelPfS_ii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC12(%rip), %rdx movl $1, %r9d leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi pushq $0 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC13(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movq %rdx, %rcx movl $1, %r9d leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi call __cudaRegisterVar@PLT popq %rcx .cfi_def_cfa_offset 24 popq %rsi .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rbx, %rdi xorl %r8d, %r8d movl $1, %r9d movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi call __cudaRegisterVar@PLT popq %rdi .cfi_def_cfa_offset 24 movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %r8 .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE6861: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_005191.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z31__device_stub__simpleUnetKernelPfS_ii # -- Begin function _Z31__device_stub__simpleUnetKernelPfS_ii .type _Z31__device_stub__simpleUnetKernelPfS_ii,@function _Z31__device_stub__simpleUnetKernelPfS_ii: # @_Z31__device_stub__simpleUnetKernelPfS_ii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 8(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z16simpleUnetKernelPfS_ii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z31__device_stub__simpleUnetKernelPfS_ii, .Lfunc_end0-_Z31__device_stub__simpleUnetKernelPfS_ii .cfi_endproc # -- End function .globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc .type _Z14checkCudaError10hipError_tPKc,@function _Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB1_2 # %bb.1: retq .LBB1_2: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movl %edi, %ebx movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movq %r14, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.1, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebx, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.2, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end1: .size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc .cfi_endproc # -- End function .globl main # -- Begin function main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $16, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %rbx movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %r14 xorl %eax, %eax .LBB2_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $65536, %rax # imm = 0x10000 jne .LBB2_1 # %bb.2: leaq 8(%rsp), %r15 movl $262144, %esi # imm = 0x40000 movq %r15, %rdi callq hipMalloc movl $.L.str.3, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rsp, %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc movl $.L.str.4, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%r15), %rdi movl $262144, %edx # imm = 0x40000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.5, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movabsq $68719476752, %rdi # imm = 0x1000000010 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: movq 8(%rsp), %rdi movq (%rsp), %rsi movl $256, %edx # imm = 0x100 movl $256, %ecx # imm = 0x100 callq _Z31__device_stub__simpleUnetKernelPfS_ii .LBB2_4: callq hipGetLastError movl $.L.str.6, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rsi movl $262144, %edx # imm = 0x40000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $.L.str.7, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq 8(%rsp), %rdi callq hipFree movl $.L.str.8, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq (%rsp), %rdi callq hipFree movl $.L.str.9, %esi movl %eax, %edi callq _Z14checkCudaError10hipError_tPKc movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $40, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rdi addq %rbx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $16, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rdi movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16simpleUnetKernelPfS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z16simpleUnetKernelPfS_ii,@object # @_Z16simpleUnetKernelPfS_ii .section .rodata,"a",@progbits .globl _Z16simpleUnetKernelPfS_ii .p2align 3, 0x0 _Z16simpleUnetKernelPfS_ii: .quad _Z31__device_stub__simpleUnetKernelPfS_ii .size _Z16simpleUnetKernelPfS_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA error: " .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " (" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz ")" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMalloc d_input" .size .L.str.3, 18 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipMalloc d_output" .size .L.str.4, 19 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipMemcpy d_input" .size .L.str.5, 18 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "simpleUnetKernel launch failed" .size .L.str.6, 31 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipMemcpy d_output" .size .L.str.7, 19 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "hipFree d_input" .size .L.str.8, 16 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipFree d_output" .size .L.str.9, 17 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Kernel execution completed successfully." .size .L.str.10, 41 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z16simpleUnetKernelPfS_ii" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__simpleUnetKernelPfS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z16simpleUnetKernelPfS_ii .addrsig_sym _ZSt4cerr .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
5,020
4,754
113,510
Convert the following CUDA device assembly code to AMD device assembly: ```cudaasm code for sm_80 Function : _Z16applyGaborFilterPKfPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.Y ; S2R R3, SR_TID.Y ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R4, R4, c[0x0][0x4], R3 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; @P0 EXIT ; IADD3 R23, R4, -0x7, RZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IADD3 R6, R5.reuse, -0x7, RZ ; IMAD.MOV.U32 R19, RZ, RZ, RZ ; IADD3 R7, R5.reuse, -0x6, RZ ; IMAD.MOV.U32 R25, RZ, RZ, RZ ; IADD3 R8, R5, -0x5, RZ ; IMAD R22, R23, c[0x0][0x170], R5 ; IADD3 R9, R5.reuse, -0x4, RZ ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R10, R5, -0x3, RZ ; IADD3 R11, R5.reuse, -0x2, RZ ; IADD3 R12, R5.reuse, -0x1, RZ ; IADD3 R13, R5.reuse, 0x1, RZ ; IADD3 R14, R5.reuse, 0x2, RZ ; IADD3 R15, R5.reuse, 0x3, RZ ; IADD3 R16, R5, 0x4, RZ ; IADD3 R17, R5.reuse, 0x5, RZ ; IADD3 R18, R5.reuse, 0x6, RZ ; IADD3 R20, R5, 0x7, RZ ; LOP3.LUT R2, R6, R23, RZ, 0xfc, !PT ; IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; ISETP.GE.AND P5, PT, R2, RZ, PT ; IMAD R2, R25, c[0x0][0x170], R22 ; ISETP.GE.OR P5, PT, R6, c[0x0][0x170], !P5 ; IMAD.WIDE R2, R2, R21, c[0x0][0x160] ; ISETP.GE.OR P5, PT, R23, c[0x0][0x174], P5 ; @!P5 LDG.E R24, [R2.64+-0x1c] ; LOP3.LUT R26, R7, R23.reuse, RZ, 0xfc, !PT ; LOP3.LUT R27, R8, R23, RZ, 0xfc, !PT ; ISETP.GE.AND P1, PT, R26, RZ, PT ; ISETP.GE.AND P4, PT, R27, RZ, PT ; ISETP.GE.OR P1, PT, R7, c[0x0][0x170], !P1 ; ISETP.GE.OR P4, PT, R8, c[0x0][0x170], !P4 ; ISETP.GE.OR P1, PT, R23.reuse, c[0x0][0x174], P1 ; ISETP.GE.OR P4, PT, R23, c[0x0][0x174], P4 ; LOP3.LUT R26, R9.reuse, R23.reuse, RZ, 0xfc, !PT ; LOP3.LUT R28, R10, R23, RZ, 0xfc, !PT ; ISETP.GE.AND P6, PT, R26, RZ, PT ; @!P5 LDC R27, c[0x3][R19] ; @!P1 LDG.E R37, [R2.64+-0x18] ; ISETP.GE.OR P6, PT, R9, c[0x0][0x170], !P6 ; LOP3.LUT R26, R11, R23, RZ, 0xfc, !PT ; @!P4 LDG.E R31, [R2.64+-0x14] ; ISETP.GE.AND P3, PT, R28, RZ, PT ; ISETP.GE.OR P6, PT, R23, c[0x0][0x174], P6 ; ISETP.GE.AND P0, PT, R26, RZ, PT ; ISETP.GE.OR P3, PT, R10, c[0x0][0x170], !P3 ; ISETP.GE.OR P0, PT, R11, c[0x0][0x170], !P0 ; ISETP.GE.OR P3, PT, R23.reuse, c[0x0][0x174], P3 ; ISETP.GE.OR P0, PT, R23, c[0x0][0x174], P0 ; LOP3.LUT R26, R12, R23, RZ, 0xfc, !PT ; @!P6 LDG.E R35, [R2.64+-0x10] ; ISETP.GE.AND P2, PT, R26, RZ, PT ; @!P3 LDG.E R29, [R2.64+-0xc] ; ISETP.GT.OR P2, PT, R5.reuse, c[0x0][0x170], !P2 ; LOP3.LUT R26, R5, R23, RZ, 0xfc, !PT ; ISETP.GE.OR P2, PT, R23, c[0x0][0x174], P2 ; @!P2 LDG.E R33, [R2.64+-0x4] ; @!P5 FFMA R0, R27, R24, R0 ; @!P0 LDG.E R24, [R2.64+-0x8] ; ISETP.GE.AND P5, PT, R23, c[0x0][0x174], PT ; ISETP.LT.OR P5, PT, R26, RZ, P5 ; @!P5 LDG.E R27, [R2.64] ; @!P1 LDC R26, c[0x3][R19+0x4] ; @!P4 LDC R28, c[0x3][R19+0x8] ; @!P6 LDC R30, c[0x3][R19+0xc] ; @!P1 FFMA R0, R26, R37, R0 ; @!P3 LDC R26, c[0x3][R19+0x10] ; @!P4 FFMA R0, R28, R31, R0 ; LOP3.LUT R28, R13, R23, RZ, 0xfc, !PT ; @!P0 LDC R31, c[0x3][R19+0x14] ; ISETP.GE.AND P1, PT, R28, RZ, PT ; ISETP.GE.OR P1, PT, R13, c[0x0][0x170], !P1 ; ISETP.GE.OR P1, PT, R23, c[0x0][0x174], P1 ; @!P6 FFMA R0, R30, R35, R0 ; LOP3.LUT R28, R14, R23, RZ, 0xfc, !PT ; @!P2 LDC R30, c[0x3][R19+0x18] ; @!P3 FFMA R0, R26, R29, R0 ; ISETP.GE.AND P4, PT, R28, RZ, PT ; LOP3.LUT R26, R15, R23, RZ, 0xfc, !PT ; @!P5 LDC R28, c[0x3][R19+0x1c] ; ISETP.GE.OR P4, PT, R14, c[0x0][0x170], !P4 ; @!P1 LDG.E R29, [R2.64+0x4] ; ISETP.GE.AND P3, PT, R26, RZ, PT ; ISETP.GE.OR P4, PT, R23, c[0x0][0x174], P4 ; ISETP.GE.OR P3, PT, R15, c[0x0][0x170], !P3 ; ISETP.GE.OR P3, PT, R23, c[0x0][0x174], P3 ; @!P0 FFMA R0, R31, R24, R0 ; LOP3.LUT R24, R16, R23.reuse, RZ, 0xfc, !PT ; LOP3.LUT R31, R17, R23, RZ, 0xfc, !PT ; ISETP.GE.AND P6, PT, R24, RZ, PT ; ISETP.GE.AND P0, PT, R31, RZ, PT ; ISETP.GE.OR P6, PT, R16, c[0x0][0x170], !P6 ; @!P2 FFMA R0, R30, R33, R0 ; ISETP.GE.OR P0, PT, R17, c[0x0][0x170], !P0 ; @!P4 LDG.E R31, [R2.64+0x8] ; ISETP.GE.OR P6, PT, R23, c[0x0][0x174], P6 ; LOP3.LUT R24, R18, R23.reuse, RZ, 0xfc, !PT ; ISETP.GE.OR P0, PT, R23, c[0x0][0x174], P0 ; @!P5 FFMA R0, R27, R28, R0 ; ISETP.GE.AND P2, PT, R24, RZ, PT ; @!P3 LDG.E R27, [R2.64+0xc] ; LOP3.LUT R24, R20, R23, RZ, 0xfc, !PT ; ISETP.GE.OR P2, PT, R18, c[0x0][0x170], !P2 ; ISETP.GE.AND P5, PT, R24, RZ, PT ; @!P6 LDG.E R37, [R2.64+0x10] ; ISETP.GE.OR P2, PT, R23, c[0x0][0x174], P2 ; ISETP.GE.OR P5, PT, R20, c[0x0][0x170], !P5 ; @!P0 LDG.E R35, [R2.64+0x14] ; ISETP.GE.OR P5, PT, R23, c[0x0][0x174], P5 ; @!P2 LDG.E R33, [R2.64+0x18] ; @!P5 LDG.E R30, [R2.64+0x1c] ; @!P1 LDC R24, c[0x3][R19+0x20] ; @!P4 LDC R26, c[0x3][R19+0x24] ; @!P3 LDC R28, c[0x3][R19+0x28] ; @!P1 FFMA R0, R24, R29, R0 ; @!P6 LDC R24, c[0x3][R19+0x2c] ; @!P0 LDC R29, c[0x3][R19+0x30] ; IADD3 R23, R23, 0x1, RZ ; @!P4 FFMA R0, R26, R31, R0 ; @!P2 LDC R26, c[0x3][R19+0x34] ; @!P3 FFMA R0, R28, R27, R0 ; @!P5 LDC R31, c[0x3][R19+0x38] ; @!P6 FFMA R0, R24, R37, R0 ; @!P0 FFMA R0, R29, R35, R0 ; ISETP.NE.AND P0, PT, R25.reuse, 0xe, PT ; IADD3 R25, R25, 0x1, RZ ; IADD3 R19, R19, 0x3c, RZ ; @!P2 FFMA R0, R26, R33, R0 ; @!P5 FFMA R0, R31, R30, R0 ; @P0 BRA 0x1e0 ; IMAD R2, R4, c[0x0][0x170], R5 ; IMAD.WIDE R2, R2, R21, c[0x0][0x168] ; STG.E [R2.64], R0 ; EXIT ; BRA 0x920; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... ```
```amdasm .text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16applyGaborFilterPKfPfii ; -- Begin function _Z16applyGaborFilterPKfPfii .globl _Z16applyGaborFilterPKfPfii .p2align 8 .type _Z16applyGaborFilterPKfPfii,@function _Z16applyGaborFilterPKfPfii: ; @_Z16applyGaborFilterPKfPfii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[8:9], s[0:1], 0x10 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s8, v0 v_cmp_gt_i32_e64 s2, s9, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_10 ; %bb.1: ; %.preheader.preheader s_load_b128 s[4:7], s[0:1], 0x0 v_add_nc_u32_e32 v2, -7, v1 v_add_nc_u32_e32 v4, -7, v0 s_mov_b32 s12, -7 s_getpc_b64 s[2:3] s_add_u32 s2, s2, gaborFilter@rel32@lo+4 s_addc_u32 s3, s3, gaborFilter@rel32@hi+12 v_mul_lo_u32 v3, s8, v2 v_mov_b32_e32 v2, 0 .LBB0_2: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_3 Depth 2 v_add_nc_u32_e32 v5, s12, v1 s_mov_b64 s[10:11], 0 s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v5 v_cmp_gt_i32_e64 s0, s9, v5 v_mov_b32_e32 v5, v4 .LBB0_3: ; Parent Loop BB0_2 Depth=1 ; => This Inner Loop Header: Depth=2 s_mov_b32 s13, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_i32_e32 -1, v5 s_cbranch_execz .LBB0_7 ; %bb.4: ; in Loop: Header=BB0_3 Depth=2 v_cmp_gt_i32_e64 s1, s8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s1, s1, vcc_lo s_and_b32 s1, s1, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s14, s1 s_cbranch_execz .LBB0_6 ; %bb.5: ; in Loop: Header=BB0_3 Depth=2 v_add_nc_u32_e32 v6, v3, v5 s_add_u32 s16, s2, s10 s_addc_u32 s17, s3, s11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[6:7], 2, v[6:7] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v6, s1, s4, v6 v_add_co_ci_u32_e64 v7, s1, s5, v7, s1 s_load_b32 s1, s[16:17], 0x0 global_load_b32 v6, v[6:7], off s_waitcnt vmcnt(0) lgkmcnt(0) v_fmac_f32_e32 v2, s1, v6 .LBB0_6: ; %Flow ; in Loop: Header=BB0_3 Depth=2 s_or_b32 exec_lo, exec_lo, s14 .LBB0_7: ; in Loop: Header=BB0_3 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s13 v_add_nc_u32_e32 v5, 1, v5 s_add_u32 s10, s10, 4 s_addc_u32 s11, s11, 0 s_cmp_eq_u32 s10, 60 s_cbranch_scc0 .LBB0_3 ; %bb.8: ; in Loop: Header=BB0_2 Depth=1 s_add_i32 s12, s12, 1 v_add_nc_u32_e32 v3, s8, v3 s_add_u32 s2, s2, 60 s_addc_u32 s3, s3, 0 s_cmp_eq_u32 s12, 8 s_cbranch_scc0 .LBB0_2 ; %bb.9: v_mad_u64_u32 v[3:4], null, v1, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16applyGaborFilterPKfPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16applyGaborFilterPKfPfii, .Lfunc_end0-_Z16applyGaborFilterPKfPfii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 428 ; NumSgprs: 20 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 20 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected gaborFilter ; @gaborFilter .type gaborFilter,@object .section .bss,"aw",@nobits .globl gaborFilter .p2align 4, 0x0 gaborFilter: .zero 900 .size gaborFilter, 900 .type __hip_cuid_,@object ; @__hip_cuid_ .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym gaborFilter .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16applyGaborFilterPKfPfii .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z16applyGaborFilterPKfPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata ```
3,500
3,839
113,511
Convert the following CUDA host assembly code to AMD host assembly: ```cudaasm .file "tmpxft_00034127_00000000-6_cuda_code_041969.cudafe1.cpp" .text .globl _ZSt21ios_base_library_initv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3639: .cfi_startproc endbr64 movq _ZL20__cudaFatCubinHandle(%rip), %rdi jmp __cudaUnregisterFatBinary@PLT .cfi_endproc .LFE3639: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .type _ZNSolsEPFRSoS_E.isra.0, @function _ZNSolsEPFRSoS_E.isra.0: .LFB4294: .cfi_startproc jmp *%rsi .cfi_endproc .LFE4294: .size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0 .globl _Z19generateGaborFilterPffffff .type _Z19generateGaborFilterPffffff, @function _Z19generateGaborFilterPffffff: .LFB3635: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 movd %xmm4, %r15d pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 movd %xmm2, %r14d pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 movl $-7, %r12d pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %rbx subq $420, %rbx subq $48, %rsp .cfi_def_cfa_offset 96 movss %xmm0, 12(%rsp) leaq 44(%rsp), %rdi movaps %xmm1, %xmm0 leaq 40(%rsp), %rsi movss %xmm3, 8(%rsp) call sincosf@PLT movss 12(%rsp), %xmm5 movss 40(%rsp), %xmm3 movss 44(%rsp), %xmm4 movaps %xmm5, %xmm1 movaps %xmm5, %xmm0 divss 8(%rsp), %xmm0 addss %xmm5, %xmm1 mulss %xmm5, %xmm1 movss %xmm1, 16(%rsp) movaps %xmm0, %xmm1 addss %xmm0, %xmm1 mulss %xmm0, %xmm1 movss %xmm1, 20(%rsp) .L4: cvtsi2ssl %r12d, %xmm0 movq $-7, %rbp movaps %xmm0, %xmm6 mulss %xmm4, %xmm6 mulss %xmm3, %xmm0 movss %xmm6, 8(%rsp) movss %xmm0, 12(%rsp) .L5: movl %ebp, %eax cvtsi2ssl %ebp, %xmm1 movss %xmm3, 36(%rsp) negl %eax movss %xmm4, 32(%rsp) cvtsi2ssl %eax, %xmm2 mulss %xmm3, %xmm1 addss 8(%rsp), %xmm1 mulss %xmm4, %xmm2 addss 12(%rsp), %xmm2 movaps %xmm1, %xmm0 movss %xmm1, 28(%rsp) mulss %xmm1, %xmm0 mulss %xmm2, %xmm2 divss 16(%rsp), %xmm0 divss 20(%rsp), %xmm2 addss %xmm2, %xmm0 xorps .LC0(%rip), %xmm0 call expf@PLT movss 28(%rsp), %xmm1 movd %r14d, %xmm7 movss %xmm0, 24(%rsp) cvtss2sd %xmm1, %xmm0 mulsd .LC1(%rip), %xmm0 cvtss2sd %xmm7, %xmm1 movd %r15d, %xmm7 divsd %xmm1, %xmm0 cvtss2sd %xmm7, %xmm1 addsd %xmm1, %xmm0 call cos@PLT movss 24(%rsp), %xmm2 movss 32(%rsp), %xmm4 movaps %xmm0, %xmm1 movss 36(%rsp), %xmm3 cvtss2sd %xmm2, %xmm0 mulsd %xmm1, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, 448(%rbx,%rbp,4) incq %rbp cmpq $8, %rbp jne .L5 incl %r12d addq $60, %rbx cmpl $8, %r12d jne .L4 addq $48, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3635: .size _Z19generateGaborFilterPffffff, .-_Z19generateGaborFilterPffffff .globl _Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii .type _Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii, @function _Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii: .LFB3661: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) leaq 56(%rsp), %rdi movq %rsi, 16(%rsp) leaq 68(%rsp), %rsi movl %edx, 12(%rsp) leaq 40(%rsp), %rdx movl %ecx, 8(%rsp) leaq 48(%rsp), %rcx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movl $1, 64(%rsp) movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) movabsq $4294967297, %rax movq %rax, 56(%rsp) movq %rax, 68(%rsp) movl $1, 76(%rsp) call __cudaPopCallConfiguration@PLT testl %eax, %eax jne .L10 pushq 48(%rsp) .cfi_def_cfa_offset 168 leaq _Z16applyGaborFilterPKfPfii(%rip), %rdi pushq 48(%rsp) .cfi_def_cfa_offset 176 movq 84(%rsp), %rcx movl 92(%rsp), %r8d movq 72(%rsp), %rsi movl 80(%rsp), %edx leaq 120(%rsp), %r9 call cudaLaunchKernel@PLT popq %rax .cfi_def_cfa_offset 168 popq %rdx .cfi_def_cfa_offset 160 .L10: movq 136(%rsp), %rax subq %fs:40, %rax je .L12 call __stack_chk_fail@PLT .L12: addq $152, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3661: .size _Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii, .-_Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii .globl _Z16applyGaborFilterPKfPfii .type _Z16applyGaborFilterPKfPfii, @function _Z16applyGaborFilterPKfPfii: .LFB3662: .cfi_startproc endbr64 jmp _Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii .cfi_endproc .LFE3662: .size _Z16applyGaborFilterPKfPfii, .-_Z16applyGaborFilterPKfPfii .section .rodata.str1.1,"aMS",@progbits,1 .LC3: .string "Failed to allocate device input memory: " .LC4: .string "Failed to allocate device output memory: " .LC5: .string "Failed to copy input data to device: " .LC11: .string "Failed to copy Gabor filter to constant memory: " .LC12: .string "Kernel launch failed: " .LC13: .string "Failed to copy output data to host: " .section .text.startup,"ax",@progbits .globl main .type main, @function main: .LFB3636: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 movl $262144, %edi pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 xorl %ebx, %ebx subq $56, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Znam@PLT movl $262144, %edi movq %rax, %rbp call _Znam@PLT movq %rax, %r12 .L16: call rand@PLT cvtsi2ssl %eax, %xmm0 mulss .LC2(%rip), %xmm0 movss %xmm0, 0(%rbp,%rbx,4) incq %rbx cmpq $65536, %rbx jne .L16 movl $262144, %esi movq %rsp, %rdi call cudaMalloc@PLT leaq .LC3(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L29 leaq 8(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax je .L19 leaq .LC4(%rip), %rsi .L29: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %ebx, %edi movq %rax, %rbp call cudaGetErrorString@PLT movq %rbp, %rdi movq %rax, %rsi .L30: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi movq %rax, %rdi call _ZNSolsEPFRSoS_E.isra.0 orl $-1, %eax jmp .L15 .L19: movq (%rsp), %rdi movq %rbp, %rsi movl $1, %ecx movl $262144, %edx call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movl %eax, %ebx testl %eax, %eax jne .L29 movl $900, %edi call _Znam@PLT movss .LC7(%rip), %xmm3 xorps %xmm4, %xmm4 movss .LC8(%rip), %xmm2 movss .LC9(%rip), %xmm1 movss .LC10(%rip), %xmm0 movq %rax, %rbx movq %rax, %rdi call _Z19generateGaborFilterPffffff movq %rbx, %rsi movl $1, %r8d xorl %ecx, %ecx movl $900, %edx leaq _ZL11gaborFilter(%rip), %rdi call cudaMemcpyToSymbol@PLT leaq .LC11(%rip), %rsi movl %eax, %r13d testl %eax, %eax jne .L31 xorl %r9d, %r9d xorl %r8d, %r8d movl $1, %ecx movl $1, %esi movabsq $68719476752, %rdi movq %rdi, %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L23 movq 8(%rsp), %rsi movq (%rsp), %rdi movl $256, %ecx movl $256, %edx call _Z41__device_stub__Z16applyGaborFilterPKfPfiiPKfPfii .L23: call cudaGetLastError@PLT leaq .LC12(%rip), %rsi movl %eax, %r13d testl %eax, %eax jne .L31 movq 8(%rsp), %rsi movl $2, %ecx movl $262144, %edx movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %r13d testl %eax, %eax je .L25 leaq .LC13(%rip), %rsi .L31: leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl %r13d, %edi movq %rax, %rbx call cudaGetErrorString@PLT movq %rbx, %rdi movq %rax, %rsi jmp .L30 .L25: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %r12, %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT xorl %eax, %eax .L15: movq 40(%rsp), %rdx subq %fs:40, %rdx je .L26 call __stack_chk_fail@PLT .L26: addq $56, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3636: .size main, .-main .section .rodata.str1.1 .LC14: .string "_Z16applyGaborFilterPKfPfii" .LC15: .string "gaborFilter" .section .text.startup .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3664: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT pushq $0 .cfi_def_cfa_offset 24 xorl %r9d, %r9d orl $-1, %r8d pushq $0 .cfi_def_cfa_offset 32 leaq .LC14(%rip), %rdx movq %rax, %rdi movq %rax, %rbx pushq $0 .cfi_def_cfa_offset 40 movq %rdx, %rcx leaq _Z16applyGaborFilterPKfPfii(%rip), %rsi pushq $0 .cfi_def_cfa_offset 48 movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq %rbx, %rdi xorl %r8d, %r8d pushq $0 .cfi_def_cfa_offset 24 leaq .LC15(%rip), %rdx movl $900, %r9d leaq _ZL11gaborFilter(%rip), %rsi pushq $1 .cfi_def_cfa_offset 32 movq %rdx, %rcx call __cudaRegisterVar@PLT movq _ZL20__cudaFatCubinHandle(%rip), %rdi popq %rax .cfi_def_cfa_offset 24 popq %rdx .cfi_def_cfa_offset 16 call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi popq %rbx .cfi_def_cfa_offset 8 jmp atexit@PLT .cfi_endproc .LFE3664: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL11gaborFilter .comm _ZL11gaborFilter,900,32 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC0: .long -2147483648 .long 0 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC1: .long 1413754136 .long 1075388923 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 805306368 .align 4 .LC7: .long 1056964608 .align 4 .LC8: .long 1082130432 .align 4 .LC9: .long 1061752795 .align 4 .LC10: .long 1073741824 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: ```
```amdasm .text .file "cuda_code_041969.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z31__device_stub__applyGaborFilterPKfPfii # -- Begin function _Z31__device_stub__applyGaborFilterPKfPfii .type _Z31__device_stub__applyGaborFilterPKfPfii,@function _Z31__device_stub__applyGaborFilterPKfPfii: # @_Z31__device_stub__applyGaborFilterPKfPfii .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rax movq %rdi, (%rax) leaq 32(%rsp), %rdi movq %rsi, (%rdi) leaq 12(%rsp), %rsi movl %edx, (%rsi) leaq 8(%rsp), %rdx movl %ecx, (%rdx) leaq 80(%rsp), %rbx movq %rax, (%rbx) movq %rdi, 8(%rbx) movq %rsi, 16(%rbx) movq %rdx, 24(%rbx) leaq 64(%rsp), %r14 leaq 48(%rsp), %r15 leaq 24(%rsp), %r12 leaq 16(%rsp), %r13 movq %r14, %rdi movq %r15, %rsi movq %r12, %rdx movq %r13, %rcx callq __hipPopCallConfiguration movq (%r14), %rsi movl 8(%r14), %edx movq (%r15), %rcx movl 8(%r15), %r8d movl $_Z16applyGaborFilterPKfPfii, %edi movq %rbx, %r9 pushq (%r13) .cfi_adjust_cfa_offset 8 pushq (%r12) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $128, %rsp .cfi_adjust_cfa_offset -128 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z31__device_stub__applyGaborFilterPKfPfii, .Lfunc_end0-_Z31__device_stub__applyGaborFilterPKfPfii .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function _Z19generateGaborFilterPffffff .LCPI1_0: .long 0x80000000 # float -0 .long 0x80000000 # float -0 .long 0x80000000 # float -0 .long 0x80000000 # float -0 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_1: .quad 0x401921fb54442d18 # double 6.2831853071795862 .text .globl _Z19generateGaborFilterPffffff .type _Z19generateGaborFilterPffffff,@function _Z19generateGaborFilterPffffff: # @_Z19generateGaborFilterPffffff .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $56, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdi, %rbx movaps %xmm0, %xmm5 addss %xmm0, %xmm5 mulss %xmm0, %xmm5 movss %xmm5, 28(%rsp) # 4-byte Spill divss %xmm3, %xmm0 cvtss2sd %xmm1, %xmm1 movaps %xmm0, %xmm3 addss %xmm0, %xmm3 mulss %xmm0, %xmm3 movss %xmm3, 24(%rsp) # 4-byte Spill xorps %xmm0, %xmm0 cvtss2sd %xmm2, %xmm0 movsd %xmm0, 48(%rsp) # 8-byte Spill xorps %xmm0, %xmm0 cvtss2sd %xmm4, %xmm0 movsd %xmm0, 40(%rsp) # 8-byte Spill movq $-7, %r14 movsd %xmm1, 16(%rsp) # 8-byte Spill .LBB1_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 xorps %xmm0, %xmm0 cvtsi2sd %r14d, %xmm0 movsd %xmm0, 32(%rsp) # 8-byte Spill movl $7, %ebp xorl %r15d, %r15d .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 leal -7(%r15), %eax xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 movsd %xmm0, (%rsp) # 8-byte Spill movaps %xmm1, %xmm0 callq cos mulsd (%rsp), %xmm0 # 8-byte Folded Reload movsd %xmm0, (%rsp) # 8-byte Spill movsd 16(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero callq sin mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload addsd (%rsp), %xmm0 # 8-byte Folded Reload cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%rsp) # 4-byte Spill xorps %xmm0, %xmm0 cvtsi2sd %ebp, %xmm0 movsd %xmm0, 8(%rsp) # 8-byte Spill movsd 16(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero callq sin mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload movsd %xmm0, 8(%rsp) # 8-byte Spill movsd 16(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero callq cos mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload addsd 8(%rsp), %xmm0 # 8-byte Folded Reload cvtsd2ss %xmm0, %xmm0 movss (%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm1 divss 28(%rsp), %xmm1 # 4-byte Folded Reload mulss %xmm0, %xmm0 divss 24(%rsp), %xmm0 # 4-byte Folded Reload addss %xmm1, %xmm0 xorps .LCPI1_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 callq exp movsd %xmm0, 8(%rsp) # 8-byte Spill xorps %xmm0, %xmm0 cvtss2sd (%rsp), %xmm0 # 4-byte Folded Reload mulsd .LCPI1_1(%rip), %xmm0 divsd 48(%rsp), %xmm0 # 8-byte Folded Reload addsd 40(%rsp), %xmm0 # 8-byte Folded Reload callq cos movsd 16(%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%rbx,%r15,4) incq %r15 decl %ebp cmpq $15, %r15 jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 incq %r14 addq $60, %rbx cmpq $8, %r14 jne .LBB1_1 # %bb.4: addq $56, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z19generateGaborFilterPffffff, .Lfunc_end1-_Z19generateGaborFilterPffffff .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x30000000 # float 4.65661287E-10 .LCPI2_1: .long 0x40000000 # float 2 .LCPI2_2: .long 0x3f490fdb # float 0.785398185 .LCPI2_3: .long 0x40800000 # float 4 .LCPI2_4: .long 0x3f000000 # float 0.5 .text .globl main .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $24, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %rbx movl $262144, %edi # imm = 0x40000 callq _Znam movq %rax, %r14 xorl %r15d, %r15d .LBB2_1: # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI2_0(%rip), %xmm0 movss %xmm0, (%rbx,%r15,4) incq %r15 cmpq $65536, %r15 # imm = 0x10000 jne .LBB2_1 # %bb.2: leaq 16(%rsp), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc testl %eax, %eax je .LBB2_4 # %bb.3: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str, %esi movl $40, %edx jmp .LBB2_10 .LBB2_4: leaq 8(%rsp), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc testl %eax, %eax je .LBB2_6 # %bb.5: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $41, %edx jmp .LBB2_10 .LBB2_6: movq 16(%rsp), %rdi movl $262144, %edx # imm = 0x40000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_8 # %bb.7: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.2, %esi movl $37, %edx jmp .LBB2_10 .LBB2_8: movl $900, %edi # imm = 0x384 callq _Znam movq %rax, %r15 movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero movss .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero movss .LCPI2_4(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero xorps %xmm4, %xmm4 movq %rax, %rdi callq _Z19generateGaborFilterPffffff movl $gaborFilter, %edi movl $900, %edx # imm = 0x384 movq %r15, %rsi xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol testl %eax, %eax je .LBB2_16 # %bb.9: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.3, %esi movl $48, %edx .LBB2_10: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString testq %rax, %rax je .LBB2_12 # %bb.11: movq %rax, %rbx movq %rax, %rdi callq strlen movl $_ZSt4cerr, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_13 .LBB2_12: movq _ZSt4cerr(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cerr(%rax), %rdi movl 32(%rdi), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cerr(%rip), %rax movl $_ZSt4cerr, %ecx movq -24(%rax), %rdi addq %rcx, %rdi movl $10, %esi callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc movsbl %al, %esi movl $_ZSt4cerr, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB2_14: movl $-1, %eax .LBB2_15: addq $24, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_16: .cfi_def_cfa_offset 64 movabsq $68719476752, %rdi # imm = 0x1000000010 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_18 # %bb.17: movq 16(%rsp), %rdi movq 8(%rsp), %rsi movl $256, %edx # imm = 0x100 movl $256, %ecx # imm = 0x100 callq _Z31__device_stub__applyGaborFilterPKfPfii .LBB2_18: callq hipGetLastError testl %eax, %eax je .LBB2_20 # %bb.19: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.4, %esi movl $22, %edx jmp .LBB2_22 .LBB2_20: movq 8(%rsp), %rsi movl $262144, %edx # imm = 0x40000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB2_23 # %bb.21: movl %eax, %ebp movl $_ZSt4cerr, %edi movl $.L.str.5, %esi movl $36, %edx .LBB2_22: callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl %ebp, %edi callq hipGetErrorString movl $_ZSt4cerr, %edi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ jmp .LBB2_14 .LBB2_23: movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv movq %r15, %rdi callq _ZdaPv xorl %eax, %eax jmp .LBB2_15 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 movq __hip_gpubin_handle(%rip), %rbx testq %rbx, %rbx jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, %rbx movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16applyGaborFilterPKfPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $0, 8(%rsp) movl $1, (%rsp) movl $gaborFilter, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movl $900, %r9d # imm = 0x384 movq %rbx, %rdi xorl %r8d, %r8d callq __hipRegisterVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type gaborFilter,@object # @gaborFilter .local gaborFilter .comm gaborFilter,900,16 .type _Z16applyGaborFilterPKfPfii,@object # @_Z16applyGaborFilterPKfPfii .section .rodata,"a",@progbits .globl _Z16applyGaborFilterPKfPfii .p2align 3, 0x0 _Z16applyGaborFilterPKfPfii: .quad _Z31__device_stub__applyGaborFilterPKfPfii .size _Z16applyGaborFilterPKfPfii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to allocate device input memory: " .size .L.str, 41 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to allocate device output memory: " .size .L.str.1, 42 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to copy input data to device: " .size .L.str.2, 38 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to copy Gabor filter to constant memory: " .size .L.str.3, 49 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Kernel launch failed: " .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to copy output data to host: " .size .L.str.5, 37 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z16applyGaborFilterPKfPfii" .size .L__unnamed_1, 28 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "gaborFilter" .size .L__unnamed_2, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__applyGaborFilterPKfPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym gaborFilter .addrsig_sym _Z16applyGaborFilterPKfPfii .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_ ```
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