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wilyub 

updated a collection 3 days ago

VeriThoughts Models

Collection

7 items • Updated 3 days ago

wilyub 

updated a model 5 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Mix-Verilog-Reasoning-GT-7B

Text Generation • Updated 5 days ago • 3

wilyub 

published a model 5 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Mix-Verilog-Reasoning-GT-7B

Text Generation • Updated 5 days ago • 3

wilyub 

updated a model 5 days ago

nyu-dice-lab/VeriThought-Reasoning-14B

Text Generation • Updated 5 days ago • 3

wilyub 

published a model 5 days ago

nyu-dice-lab/VeriThought-Reasoning-14B

Text Generation • Updated 5 days ago • 3

wilyub 

updated 2 models 6 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B

Text Generation • Updated 6 days ago • 9

nyu-dice-lab/VeriThoughts-Reasoning-7B

Text Generation • Updated 6 days ago • 15 • 1

wilyub 

published 2 models 6 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B

Text Generation • Updated 6 days ago • 9

nyu-dice-lab/VeriThoughts-Reasoning-7B

Text Generation • Updated 6 days ago • 15 • 1

wilyub 

updated a model 6 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Unverified-Verilog-GT-7B

Text Generation • Updated 6 days ago • 9

wilyub 

published a model 6 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Unverified-Verilog-GT-7B

Text Generation • Updated 6 days ago • 9

wilyub 

updated a model 6 days ago

nyu-dice-lab/VeriThoughts-Instruct-7B

Text Generation • Updated 6 days ago • 20

wilyub 

published a model 6 days ago

nyu-dice-lab/VeriThoughts-Instruct-7B

Text Generation • Updated 6 days ago • 20

wilyub 

updated a model 7 days ago

nyu-dice-lab/Qwen-2.5-Instruct-Verilog-Reasoning-7B

Text Generation • Updated 7 days ago • 14