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[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: jaehyukk/Finger_Counting_Converter\n// Path: b_1_converter.v\nmodule b_1_converter(hs, n);\n\tinput [4:0] hs;\n\toutput [3:0] n;\n\n\t// fill in your implementation below\nwire [3:0] temp;\n\n// 2-level AND-OR circuit\nassign temp[0] = ((~hs[4])&(~hs[3])&(~hs[2])&(~hs[1])&hs[0])|((~hs[4])&(~hs[3])&hs[2]&hs[1]&hs[0])|(hs[4]&(~hs[3])&(~hs[2])&(~hs[1])&(~hs[0]))|(hs[4]&hs[3]&hs[2]&(~hs[1])&(~hs[0]))|(hs[4]&hs[3]&hs[2]&hs[1]&hs[0]); // first bit\nassign temp[1] = ((~hs[4])&(~hs[3])&hs[1]&hs[0])|(hs[4]&hs[3]&hs[2]&(~hs[0]))|((~hs[4])&(~hs[3])&(~hs[2])&(~hs[1])&(~hs[0])); // second bit\nassign temp[2] = ((~hs[4])&hs[3]&hs[2]&hs[1]&hs[0])|(hs[4]&hs[3]&hs[2]&hs[1])|(hs[4]&hs[3]&hs[2]&(~hs[0])); // third bit\nassign temp[3] = (hs[4]&(~hs[2])&(~hs[1])&(~hs[0]))|((~hs[4])&(~hs[3])&(~hs[2])&(~hs[1])&(~hs[0])); // forth bit\n\nassign n = temp[3:0]; // put the total output after combine the each bits\n\nendmodule\n\n\n// Path: b_2_converter.v\nmodule b_2_converter(hs, n);\r\n\tinput [4:0] hs;\r\n\toutput [3:0] n;\r\n\r\n\t// fill in your implementation below\r\nwire [3:0] n;\r\nreg [3:0] state; // store the 4-bit unsigned binary number\r\n\r\nalways @ (hs) begin\r\ncase(hs) // convert hand sign to 4-bit unsigned binary number\r\n5'b00001: state = 4'd1;\r\n5'b00011: state = 4'd2;\r\n5'b00111: state = 4'd3;\r\n5'b01111: state = 4'd4;\r\n5'b11111: state = 4'd5;\r\n5'b11110: state = 4'd6;\r5'b11100: state = 4'd7;\r\n5'b11000: state = 4'd8;\r\n5'b10000: state = 4'd9;\r\n5'b00000: state = 4'd10;\r\ndefault: state = 4'd0; // exception\r\nendcase\r\nend\r\n\r\nassign n = state[3:0]; // output the 4-bit unsigned binary number\r\n\r\nendmodule\r\n\n\n// Path: tb_converter.v\n`timescale 1ns/1ps\r\nmodule tb_converter();\r\n\treg [4:0] hs;\r\n\twire [3:0] n1, n2;\r\n\r\r\n\tb_1_converter converter1(hs, n1);\r\n\tb_2_converter converter2(hs, n2);\r\n\r\n\tinitial begin\r\n\t\ths = 5'd0;\r\n\t\t#10\r\n\t\ths = 5'd1;\r\n\t\t#10\r\n\t\ths = 5'd2;\r\n\t\t#10\r\n\t\ths = 5'd3;\r\n\t\t#10\r\n\t\ths = 5'd4;\r\n\t\t#10\r\n\t\ths = 5'd5;\r\n\t\t#10\r\n\t\ths = 5'd6;\r\n\t\t#10\r\n\t\ths = 5'd7;\r\n\t\t#10\r\n\t\ths = 5'd8;\r\n\t\t#10\r\n\t\ths = 5'd9;\r\n\t\t#10\r\n\t\ths = 5'd10;\r\n\t\t#10\r\n\t\ths = 5'd11;\r\n\t\t#10\r\n\t\ths = 5'd12;\r\n\t\t#10\r\n\t\ths = 5'd13;\r\n\t\t#10\r\n\t\ths = 5'd14;\r\n\t\t#10\r\n\t\ths = 5'd15;\r\n\t\t#10\r\n\t\ths = 5'd16;\r\n\t\t#10\r\n\t\ths = 5'd17;\r\n\t\t#10\r\n\t\ths = 5'd18;\r\n\t\t#10\r\n\t\ths = 5'd19;\r\n\t\t#10\r\n\t\ths = 5'd20;\r\n\t\t#10\r\n\t\ths = 5'd21;\r\n\t\t#10\r\n\t\ths = 5'd22;\r\n\t\t#10\r\n\t\ths = 5'd23;\r\n\t\t#10\r\n\t\ths = 5'd24;\r\n\t\t#10\r\n\t\ths = 5'd25;\r\n\t\t#10\r\n\t\ths = 5'd26;\r\n\t\t#10\r\n\t\ths = 5'd27;\r\n\t\t#10\r\n\t\ths = 5'd28;\r\n\t\t#10\r\n\t\ths = 5'd29;\r\n\t\t#10\r\n\t\ths = 5'd30;\r\n\t\t#10\r\n\t\ths = 5'd31;\r\n\tend\r\n\r\nendmodule\r\n\n\n// Path: tb_hamdec.v\n`timescale 1ns/1ps\r\nmodule tb_hamdec();\r\n\treg [8:0] cw;\r\n\twire [4:0] hs;\r\n\r\r\n\ta_hamdec hammind_decoder1(cw, hs);\r\n\r\n\tinitial begin\r\n\t\tcw = 9'b000001000;\t// information = 00000 , bit position of 1-bit error = 4\r\n\t\t#10\r\n\t\tcw = 9'b001000111;\t// information = 00001 , bit position of 1-bit error = 7\r\n\t\t#10\r\n\t\tcw = 9'b100011001;\t// information = 00010 , bit position of 1-bit error = 9\r\n\t\t#10\r\n\t\tcw = 9'b000011100;\t// information = 00011 , bit position of 1-bit error = 2\r\n\t\t#10\r\n\t\tcw = 9'b010101010;\t// information = 00100 , bit position of 1-bit error = 8\r\n\t\t#10\r\n\t\tcw = 9'b000001101;\t// information = 00101 , bit position of 1-bit error = 6\r\n\t\t#10\r\n\t\tcw = 9'b000111011;\t// information = 00110 , bit position of 1-bit error = 4\r\n\t\t#10\r\n\t\tcw = 9'b000110101;\t// information = 00111 , bit position of 1-bit error = 1\r\n\t\t#10\r\n\t\tcw = 9'b001011011;\t// information = 01000 , bit position of 1-bit error = 5\r\n\t\t#10\r\n\t\tcw = 9'b001001101;\t// information = 01001 , bit position of 1-bit error = 1\r\n\t\t#10\r\n\t\tcw = 9'b000010010;\t// information = 01010 , bit position of 1-bit error = 7\r\n\t\t#10\r\n\t\tcw = 9'b001110101;\t// information = 01011 , bit position of 1-bit error = 6\r\n\t\t#10\r\n\t\tcw = 9'b001100101;\t// information = 01100 , bit position of 1-bit error = 3\r\n\t\t#10\r\n\t\tcw = 9'b101100110;\t// information = 01101 , bit position of 1-bit error = 9\r\n\t\t#10\r\n\t\tcw = 9'b001111100;\t// information = 01110 , bit position of 1-bit error = 3\r\n\t\t#10\r\n\t\tcw = 9'b001011111;\t// information = 01111 , bit position of 1-bit error = 6\r\n\t\t#10\r\n\t\tcw = 9'b110000011;\t// information = 10000 , bit position of 1-bit error = 2\r\n\t\t#10\r\n\t\tcw = 9'b110100110;\t// information = 10001 , bit position of 1-bit error = 6\r\n\t\t#10\r\n\t\tcw = 9'b111011000;\t// information = 10010 , bit position of 1-bit error = 7\r\n\t\t#10\r\n\t\tcw = 9'b110011110;\t// information = 10011 , bit position of 1-bit error = 1\r\n\t\t#10\r\n\t\tcw = 9'b110101111;\t// information = 10100 , bit position of 1-bit error = 3\r\n\t\t#10\r\n\t\tcw = 9'b110001100;\t// information = 10101 , bit position of 1-bit error = 6\r\n\t\t#10\r\n\t\tcw = 9'b010110010;\t// information = 10110 , bit position of 1-bit error = 9\r\n\t\t#10\r\n\t\tcw = 9'b110110001;\t// information = 10111 , bit position of 1-bit error = 3\r\n\t\t#10\r\n\t\tcw = 9'b111000010;\t// information = 11000 , bit position of 1-bit error = 4\r\n\t\t#10\r\n\t\tcw = 9'b011001101;\t// information = 11001 , bit position of 1-bit error = 9\r\n\t\t#10\r\n\t\tcw = 9'b101010011;\t// information = 11010 , bit position of 1-bit error = 8\r\n\t\t#10\r\n\t\tcw = 9'b111010101;\t// information = 11011 , bit position of 1-bit error = 1\r\n\t\t#10\r\n\t\tcw = 9'b111110000;\t// information = 11100 , bit position of 1-bit error = 5\r\n\t\t#10\r\n\t\tcw = 9'b011100111;\t// information = 11101 , bit position of 1-bit error = 9\r\n\t\t#10\r\n\t\tcw = 9'b011111001;\t// information = 11110 , bit position of 1-bit error = 9\r\n\t\t#10\r\n\t\tcw = 9'b101111110;\t// information = 11111 , bit position of 1-bit error = 8\r\n\tend\r\n\r\nendmodule\r\n\n\n// Path: tb_top.v\n`timescale 1ns/1ps\nmodule tb_top();\n\treg [8:0] cw;\n\twire [3:0] result;\n\n\t// fill in your implementation below\ntop top_test (cw, result); // Module Instantiation\n\ninitial begin // Test Case\n\t\tcw = 9'b001000111;\t// information = 00001 , result = 0001\n\t\t#10\n\t\tcw = 9'b000011100;\t// information = 00011 , result = 0010\n\t\t#10\n\t\tcw = 9'b000110101;\t// information = 00111 , result = 0011\n\t\t#10\n\t\tcw = 9'b001011111;\t// information = 01111 , result = 0100\n\t\t#10\n\t\tcw = 9'b101111110;\t// information = 11111 , result = 0101\n #10\n\t\tcw = 9'b011111001;\t// information = 11110 , result = 0110\n\t\t#10\n\t\tcw = 9'b111110000;\t// information = 11100 , result = 0111\n\t\t#10\n\t\tcw = 9'b111000010;\t// information = 11000 , result = 1000\n\t\t#10\n\t\tcw = 9'b110000011;\t// information = 10000 , result = 1001\n\t\t#10\n\t\tcw = 9'b000001000;\t// information = 00000 , result = 1010\n\t\t#10\n cw = 9'b011001101;\t// information = 11001 , result = 0000\n\t\t#10\n\t\tcw = 9'b101010011;\t// information = 11010 , result = 0000\n\t\t#10\n\t\tcw = 9'b111010101;\t// information = 11011 , result = 0000\n\nend\n\nendmodule\n\n\n// Path: top.v\nmodule top(cw, result);\n\tinput [8:0] cw;\n\toutput [3:0] result;\n\n\t// fill in your implementation below\nwire [4:0] correct;\nwire [3:0] result;\n\na_hamdec hamdec (.cw(cw), .hs(correct)); // module instantiation\nb_1_converter converter1 (.hs(correct), .n(result)); \n\nendmodule\n\n\n// Path: a_hamdec.v\nmodule a_hamdec(cw, hs); //Error correcting, Decoding -> 5 bit original hand sign\tinput [8:0] cw;\toutput [4:0] hs;\t// fill in your implementation belowreg [4:0] infor; // information bitsreg [3:0] par; // parity bitsreg [3:0] even_par; // put the compared bits using the even parity codesreg [3:0] syndrome; // syndromealways @ (*) begininfor = { cw[8], cw[6:4], cw[2] }; // put information bitspar = { cw[7], cw[3], cw[1:0] }; // put parity bits//(A xor B xor C xor D)even_par[0] = infor[4]^infor[3]^infor[1]^infor[0]; // p1//(A xor B)C'+(AB+A'B')Ceven_par[1] = (infor[3]^infor[2])&(~infor[0])|(((infor[3]&infor[2])|((~infor[3])&(~infor[2])))&infor[0]); // p2even_par[2] = (infor[3]^infor[2])&(~infor[1])|(((infor[3]&infor[2])|((~infor[3])&(~infor[2])))&infor[1]); // p3even_par[3] = infor[4]; // p4syndrome[0] = even_par[0]^par[0]; // syndrome code(A'B+AB'=A xor B)syndrome[1] = even_par[1]^par[1];syndrome[2] = even_par[2]^par[2]; syndrome[3] = even_par[3]^par[3]; // put the corrected information bitsif (syndrome == 4'd3) begin // syndrome == 3 infor = { cw[8], cw[6:4], (~cw[2]) }; end else if (syndrome == 4'd5) begin // syndrome == 5infor = { cw[8], cw[6], cw[5], (~cw[4]), cw[2] }; endelse if (syndrome == 4'd6) begin // syndrome == 6infor = { cw[8], cw[6], (~cw[5]), cw[4], cw[2] }; endelse if (syndrome == 4'd7) begin // syndrome == 7infor = { cw[8], (~cw[6]), cw[5], cw[4], cw[2] }; endelse if (syndrome == 4'd9) begin // syndrome == 9"
}
] |
infor = { (~cw[8]), cw[6:4], cw[2] }; end
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: stephen-kao/course-lab_3\n// Path: bram/bram12.v\n// bram behavior code (can't be synthesis)\r\n// 11 words\r\nmodule bram12 \r\n(\r\n CLK,\r\n WE,\r\n EN,\r\n Di,\r\n Do,\r\n A\r\n);\r\n\r\n input wire CLK;\r\n input wire [3:0] WE;\r\n input wire EN;\r\n input wire [31:0] Di;\r\n output reg [31:0] Do;\r\n input wire [11:0] A; \r\n\r\n // 11 words\r\n\treg [31:0] RAM[0:11];\r\n reg [11:0] r_A;\r\n\r\n always @(posedge CLK) begin\r\n r_A <= A;\r\n end\r\n\r\n assign Do = 32{EN} & RAM[r_A>>2]; // read\r\n\r\n reg [31:0] Temp_D;\r\n always @(posedge CLK) begin\r\n if(EN) begin\r\n\t if(WE[0]) RAM[A>>2][7:0] <= Di[7:0];\r\n if(WE[1]) RAM[A>>2][15:8] <= Di[15:8];\r\n if(WE[2]) RAM[A>>2][23:16] <= Di[23:16];\r\n if(WE[3]) RAM[A>>2][31:24] <= Di[31:24];\r\n end\r\n end\r\n\r\nendmodule\r\n\n\n// Path: fir/rtl/fir.v\nmodule fir \n#( parameter pADDR_WIDTH = 12,\n parameter pDATA_WIDTH = 32,\n parameter Tape_Num = 11\n)\n(\n // System clock and Reset\n input wire axis_clk,\n input wire axis_rst_n,\n // AXI-Lite Protocal\n // write\n input wire [pADDR_WIDTH-1:0] awaddr,\n input wire awvalid,\n output reg awready,\n input wire [pDATA_WIDTH-1:0] wdata,\n input wire wvalid,\n output reg wready,\n // read\n input wire [pADDR_WIDTH-1:0] araddr,\n input wire arvalid,\n output reg arready,\n output reg [pDATA_WIDTH-1:0] rdata, \n output reg rvalid,\n input wire rready,\n // AXI-Stream Protocal\n // data in\n input wire ss_tvalid, \n input wire [pDATA_WIDTH-1:0] ss_tdata, \n input wire ss_tlast, \n output reg ss_tready, \n // data out\n input wire sm_tready, \n output reg sm_tvalid, \n output reg [pDATA_WIDTH-1:0] sm_tdata, \n output reg sm_tlast, \n // bram for tap RAM (store coefficient)\n output reg [3:0] tap_WE,\n output reg tap_EN,\n output reg [pDATA_WIDTH-1:0] tap_Di,\n output reg [pADDR_WIDTH-1:0] tap_A,\n input wire [pDATA_WIDTH-1:0] tap_Do,\n // bram for data RAM (store data?)\n output reg [3:0] data_WE,\n output reg data_EN,\n output reg [pDATA_WIDTH-1:0] data_Di,\n output reg [pADDR_WIDTH-1:0] data_A,\n input wire [pDATA_WIDTH-1:0] data_Do\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// LOCAL PARAMETER DECLARATION\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap signal\nreg ap_idle;\nreg ap_done;\nreg ap_start;\nreg next_ap_idle;\nreg next_ap_done;\nreg next_ap_start;\n// fsm\nreg [1:0] state;\nreg [1:0] next_state;\nreg finish;\n// counter\nreg [4:0] next_cnt;\nreg [4:0] cnt;\n// coefficient buffer and data buffer\nreg signed [pDATA_WIDTH-1:0] coeff [0:Tape_Num-1];\nreg signed [pDATA_WIDTH-1:0] data [0:Tape_Num-1];\ninteger i,j;\n// fir design\nwire [pDATA_WIDTH-1:0] temp_sum;\nwire [pDATA_WIDTH-1:0] cur_sum;\nreg [pDATA_WIDTH-1:0] prev_sum;\nreg [pDATA_WIDTH-1:0] cur_coef;\nreg [pDATA_WIDTH-1:0] cur_data;\n// fsm state\nlocalparam IDLE = 'd0;\nlocalparam LOAD = 'd1;\nlocalparam WORK = 'd2;\nlocalparam DONE = 'd3;\n// input buffer\nwire [pADDR_WIDTH-1:0] awaddr_d; \nwire awvalid_d; \nwire [pDATA_WIDTH-1:0] wdata_d; \nwire wvalid_d; \nwire [pADDR_WIDTH-1:0] araddr_d; \nwire arvalid_d; \nwire rready_d; \nwire ss_tvalid_d;\nwire [pDATA_WIDTH-1:0] ss_tdata_d; \nwire ss_tlast_d; \nwire sm_tready_d;\nwire [pDATA_WIDTH-1:0] tap_Do_d; \nwire [pDATA_WIDTH-1:0] data_Do_d; \n// counter\nreg [3:0] tap_addr_cnt;\nreg [3:0] load_addr_cnt;\nreg [9:0] data_num_cnt;\nreg [3:0] flag;\nreg [3:0] work_addr_cnt;\nreg [3:0] next_tap_addr_cnt;\nreg [3:0] next_load_addr_cnt;\nreg [9:0] next_data_num_cnt;\nreg [3:0] next_flag;\nreg [3:0] next_work_addr_cnt;\n\ninput_buffer \n#(\n .pADDR_WIDTH (pADDR_WIDTH),\n .pDATA_WIDTH (pDATA_WIDTH)\n) input_buf (\n .axis_clk (axis_clk),\n //////////////////////////////////////////////////////////////////////////////////\n // INPUT\n //////////////////////////////////////////////////////////////////////////////////\n // AXI_Lite protocal\n .awaddr (awaddr),\n .awvalid (awvalid),\n .wdata (wdata),\n .wvalid (wvalid),\n .araddr (araddr),\n .arvalid (arvalid),\n .rready (rready),\n // AXI_Stream protocal\n .ss_tvalid (ss_tvalid),\n .ss_tdata (ss_tdata),\n .ss_tlast (ss_tlast),\n .sm_tready (sm_tready),\n // tap sram\n .tap_Do (tap_Do),\n // data sram\n .data_Do (data_Do),\n //////////////////////////////////////////////////////////////////////////////////\n // OUTPUT\n //////////////////////////////////////////////////////////////////////////////////\n // AXI_Lite protocal\n .awaddr_d (awaddr_d),\n .awvalid_d (awvalid_d),\n .wdata_d (wdata_d),\n .wvalid_d (wvalid_d),\n .araddr_d (araddr_d),\n .arvalid_d (arvalid_d),\n .rready_d (rready_d),\n // AXI_Stream protocal\n .ss_tvalid_d (ss_tvalid_d),\n .ss_tdata_d (ss_tdata_d),\n .ss_tlast_d (ss_tlast_d),\n .sm_tready_d (sm_tready_d),\n // tap sram\n .tap_Do_d (tap_Do_d),\n // data sram\n .data_Do_d (data_Do_d)\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Handshake Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nwire next_awready;\nwire next_wready;\nwire next_arready;\nwire next_rvalid;\n// AXI-Lite handshake, 1 for handshake successfully\nreg write_handshake;\nreg read_handshake;\n// rvalid trigger delay \nwire next_rvalid_trigger;\nreg rvalid_trigger;\nreg rvalid_trigger_d;\n\n// AXI-Lite handshake whether successfully or not\nalways @(*) begin\n write_handshake = (awvalid_d && awready) && (wvalid_d && wready);\n read_handshake = (arvalid_d && arready);\nend\n\n// AXI-Lite handshake control\n// write\nassign next_awready = awvalid_d;\nassign next_wready = wvalid_d;\n// read\nassign next_arready = arvalid_d;\nassign next_rvalid = (rvalid) ? 1'b0 : (~rvalid && ~arvalid_d) ? 1'b0 : (rvalid_trigger_d) ? 1'b1 : 1'b0;\nassign next_rvalid_trigger = ((tap_EN == 1'b1 && tap_WE == 'd0) && arvalid_d) | (state==DONE);\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n rvalid_trigger <= 'd0;\n rvalid_trigger_d <= 'd0;\n end else if(~arvalid_d) begin\n rvalid_trigger <= 'd0;\n rvalid_trigger_d <= 'd0;\n end else begin\n rvalid_trigger <= next_rvalid_trigger;\n rvalid_trigger_d <= rvalid_trigger;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n awready <= 'd0;\n wready <= 'd0;\n arready <= 'd0;\n rvalid <= 'd0;\n end else begin\n awready <= next_awready;\n wready <= next_wready;\n arready <= next_arready;\n rvalid <= next_rvalid;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Protocal\n// Addr = 12'h00: AP_Signal (store in buffer)\n// Addr = 12'h10: data_length (store in buffer)\n// Addr = others: Coefficient (store in tap SRAM)\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap_signal\nreg [pDATA_WIDTH-1:0] ap_signal;\nwire [pDATA_WIDTH-1:0] next_ap_signal;\n// data_length\nreg [pDATA_WIDTH-1:0] data_length;\nwire [pDATA_WIDTH-1:0] next_data_length;\n// tap SRAM \nreg [pADDR_WIDTH-1:0] next_tap_A;\nreg next_tap_EN;\nreg [3:0] next_tap_WE;\nreg [pDATA_WIDTH-1:0] next_tap_Di;\n\n\n/////////////////////////////////////////\n// AP Signal\n/////////////////////////////////////////\nassign next_ap_signal = {{29{1'b0}}, next_ap_idle, next_ap_done, next_ap_start};\n// ap_start\nalways @(*) begin\n if(state==IDLE && awaddr == 12'h00 && awvalid && wvalid && wdata == 32'h0000_0001) begin\n // write ap_start for short pulse, deassert when the engine is not IDLE\n next_ap_start = 1;\n end else begin\n next_ap_start = 0;\n end\nend\n// ap_idle\nalways @(*) begin\n if(next_ap_start) begin\n next_ap_idle = 0;\n end else if(state == DONE) begin\n next_ap_idle = 1;\n end else begin\n next_ap_idle = ap_idle;\n end\nend\n// ap_done\nalways @(*) begin\n if(state == DONE) begin\n next_ap_done = 1;\n end else begin\n next_ap_done = ap_done;\n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ap_idle <= 1'b1;\n ap_done <= 1'b0;\n ap_start <= 1'b0;\n ap_signal <= {{29{1'b0}}, 1'b1, 1'b0, 1'b0}; // the three LSB order: {idle, done, start}\n end else begin\n ap_idle <= next_ap_idle;\n ap_done <= next_ap_done;\n ap_start <= next_ap_start;\n ap_signal <= next_ap_signal;\n end\nend\n\n/////////////////////////////////////////\n// Data Length buffer\n/////////////////////////////////////////\nassign next_data_length = (awaddr_d==12'h10 && write_handshake) ? wdata_d : data_length;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_length <= 'd0;\n end else begin\n data_length <= next_data_length;\n end\nend\n\n/////////////////////////////////////////\n// coefficient\n/////////////////////////////////////////\n// When Read addr = 0x00 should read out ap_signal\n// The others addr should read out the coefficient\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n rdata <= 'd0;\n end else if(araddr_d==12'h00) begin\n rdata <= ap_signal;\n end else begin\n rdata <= tap_Do_d;\n end\nend\n\n// Write / Read tap RAM from AXI-Lite protocal\nalways @(*) begin\n if(write_handshake && awaddr_d >= 12'h20) begin\n // WRITE\n if((awaddr_d != 12'h00) && (awaddr_d != 12'h10)) begin\n // Neither ap-signal nor data_length, write for coefficient\n next_tap_A = awaddr_d - 12'h20;\n next_tap_EN = 1'b1;\n next_tap_WE = 4'b1111;\n next_tap_Di = wdata_d;\n end else begin\n next_tap_A = 'd0;\n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end\n end else if (read_handshake && araddr_d >= 12'h20) begin\n // READ\n if((araddr_d != 12'h00) && (araddr_d != 12'h10)) begin\n // Neither ap-signal nor data_length, read for coefficient\n next_tap_A = araddr_d - 12'h20;\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end else if(araddr_d == 12'h00) begin\n next_tap_A = 'd0;\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end else begin\n next_tap_A = 'd0;\n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end\n end else if(state==WORK) begin\n next_tap_A = {tap_addr_cnt, {2'b0}};\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end else begin\n next_tap_A = 'd0; \n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n tap_A <= 'd0;\n tap_EN <= 'd0;\n tap_WE <= 'd0;\n tap_Di <= 'd0; \n end else begin\n tap_A <= next_tap_A;\n tap_EN <= next_tap_EN;\n tap_WE <= next_tap_WE;\n tap_Di <= next_tap_Di; \n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Stream Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nwire next_ss_tready;\nwire next_sm_tvalid;\nwire [pDATA_WIDTH-1:0] next_sm_tdata;\nwire next_sm_tlast;\n\nassign next_ss_tready = next_state==LOAD;\nassign next_sm_tvalid = ((state==WORK) && (tap_addr_cnt==4'd2) && (data_num_cnt != 'd1)) | (state==DONE && tap_addr_cnt >= 4'd3);\nassign next_sm_tdata = prev_sum;\nassign next_sm_tlast = (state==DONE && tap_addr_cnt >= 4'd3);\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ss_tready <= 'd0;\n sm_tvalid <= 'd0;\n sm_tdata <= 'd0;\n sm_tlast <= 'd0;\n end else begin\n ss_tready <= next_ss_tready;\n sm_tvalid <= next_sm_tvalid;\n sm_tdata <= next_sm_tdata;\n sm_tlast <= next_sm_tlast;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Counter\n//\n//////////////////////////////////////////////////////////////////////////////////\n\n// tap_addr_cnt\nalways @(*) begin\n if(state==LOAD | (state==WORK && next_state==DONE)) begin\n next_tap_addr_cnt = 'd0;\n end else if(((state==IDLE)&&awvalid) | (state==WORK) | (state==DONE)) begin\n next_tap_addr_cnt = tap_addr_cnt + 1;\n end else begin\n next_tap_addr_cnt = 'd0;\n end\nend\n// load_addr_cnt\nalways @(*) begin\n if(state==LOAD) begin\n if(load_addr_cnt==4'd10) begin\n next_load_addr_cnt = 'd0;\n end else begin\n next_load_addr_cnt = load_addr_cnt + 1;\n end\n end else begin\n next_load_addr_cnt = load_addr_cnt;\n end\nend\n// data_num_cnt\nalways @(*) begin\n if(state==LOAD) begin\n next_data_num_cnt = data_num_cnt + 1;\n end else begin\n next_data_num_cnt = data_num_cnt;\n end\nend\n// flag\nalways @(*) begin\n if(data_num_cnt<=4'd11) begin\n next_flag = 'd0;\n end else begin\n next_flag = load_addr_cnt + 1;\n end\nend\n// work_addr_cnt\nalways @(*) begin\n if(state==LOAD && next_state==WORK) begin\n if(load_addr_cnt==4'd10) begin\n next_work_addr_cnt = 4'd0;\n end else begin\n next_work_addr_cnt = load_addr_cnt + 1;\n end\n end else if(state==WORK) begin\n if(work_addr_cnt==4'd10) begin\n next_work_addr_cnt = 'd0;\n end else begin\n next_work_addr_cnt = work_addr_cnt + 1;\n end\n end else begin\n next_work_addr_cnt = 'd0;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n tap_addr_cnt <= 'd0;\n load_addr_cnt <= 'd0;\n work_addr_cnt <= 'd0;\n flag <= 'd0;\n data_num_cnt <= 'd0;\n end else begin\n tap_addr_cnt <= next_tap_addr_cnt;\n load_addr_cnt <= next_load_addr_cnt;\n work_addr_cnt <= next_work_addr_cnt;\n flag <= next_flag;\n data_num_cnt <= next_data_num_cnt;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Data SRAM Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nreg [pADDR_WIDTH-1:0] next_data_A;\nreg next_data_EN;\nreg [3:0] next_data_WE;\nreg [pDATA_WIDTH-1:0] next_data_Di;\n\nalways @(*) begin\n case(state) \n IDLE: begin\n next_data_A = araddr_d - 12'h20;\n next_data_EN = 1'b1;\n next_data_WE = 4'b1111;\n next_data_Di = 'd0;\n end\n LOAD: begin\n next_data_A = {load_addr_cnt, {2'b0}}; // which addr we should write the newest data\n next_data_EN = 1'b1;\n next_data_WE = 4'b1111;\n next_data_Di = ss_tdata_d;\n end\n WORK: begin\n next_data_A = {work_addr_cnt, {2'b0}}; // which addr we need to compute\n next_data_EN = 1'b1;\n next_data_WE = 'd0;\n next_data_Di = 'd0;\n end \n default: begin\n next_data_A = 'd0;\n next_data_EN = 'd0;\n next_data_WE = 'd0;\n next_data_Di = 'd0;\n end\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_A <= 'd0;\n data_EN <= 'd0;\n data_WE <= 'd0;\n data_Di <= 'd0;\n end else begin\n data_A <= next_data_A;\n data_EN <= next_data_EN;\n data_WE <= next_data_WE;\n data_Di <= next_data_Di;\n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FSM\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways@(posedge axis_clk) begin\n if(~axis_rst_n) begin\n finish <= 1'b0;\n end else if(state==LOAD && ss_tlast) begin\n finish <= 1'b1;\n end else begin\n finish <= finish;\n end\nend\nalways @(*) begin\n case(state)\n IDLE: next_state = (ap_start) ? LOAD: IDLE;\n LOAD: next_state = WORK;\n WORK: next_state = (tap_addr_cnt == Tape_Num-1) ? (finish) ? DONE : LOAD : WORK;\n DONE: next_state = DONE;\n default: next_state = IDLE;\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n state <= IDLE;\n end else begin\n state <= next_state;\n end\nend\n\n// //////////////////////////////////////////////////////////////////////////////////\n// //\n// // FIR computation\n// //\n// //////////////////////////////////////////////////////////////////////////////////\nassign temp_sum = cur_data * cur_coef;\nassign cur_sum = prev_sum + temp_sum;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state == WORK && tap_addr_cnt==4'd2) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state==WORK | state==LOAD | state==DONE) begin\n prev_sum <= cur_sum;\n cur_coef <= tap_Do_d;\n cur_data <= data_Do_d;\n end else begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end\nend\n\nendmodule\n\n// Path: fir/rtl/fir_v1.v\nmodule fir \n#( parameter pADDR_WIDTH = 12,\n parameter pDATA_WIDTH = 32,\n parameter Tape_Num = 11\n)\n(\n // System clock and Reset\n input wire axis_clk,\n input wire axis_rst_n,\n // AXI-Lite Protocal\n // write\n input wire [pADDR_WIDTH-1:0] awaddr,\n input wire awvalid,\n output wire awready,\n input wire [pDATA_WIDTH-1:0] wdata,\n input wire wvalid,\n output wire wready,\n // read\n input wire [pADDR_WIDTH-1:0] araddr,\n input wire arvalid,\n output wire arready,\n output wire [pDATA_WIDTH-1:0] rdata, \n output wire rvalid,\n input wire rready,\n // AXI-Stream Protocal\n // data in\n input wire ss_tvalid, \n input wire [pDATA_WIDTH-1:0] ss_tdata, \n input wire ss_tlast, \n output wire ss_tready, \n // data out\n input wire sm_tready, \n output wire sm_tvalid, \n output wire [pDATA_WIDTH-1:0] sm_tdata, \n output wire sm_tlast, \n // bram for tap RAM (store coefficient)\n output reg [3:0] tap_WE,\n output reg tap_EN,\n output reg [pDATA_WIDTH-1:0] tap_Di,\n output reg [pADDR_WIDTH-1:0] tap_A,\n input wire [pDATA_WIDTH-1:0] tap_Do,\n // bram for data RAM (store data?)\n output reg [3:0] data_WE,\n output reg data_EN,\n output reg [pDATA_WIDTH-1:0] data_Di,\n output reg [pADDR_WIDTH-1:0] data_A,\n input wire [pDATA_WIDTH-1:0] data_Do\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// LOCAL PARAMETER DECLARATION\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap signal\nwire [pDATA_WIDTH-1:0] ap_signal; // ap_signal = {29{1'b0}, ap_idle, ap_done, ap_start}\nreg ap_idle;\nreg ap_done;\nreg ap_start;\nreg next_ap_idle;\nreg next_ap_done;\nreg next_ap_start;\n// data length\nreg [pDATA_WIDTH-1:0] data_length;\n// fsm\nreg [1:0] state;\nreg [1:0] next_state;\nreg finish;\n// counter\nreg [4:0] next_cnt;\nreg [4:0] cnt;\n// coefficient buffer and data buffer\nreg signed [pDATA_WIDTH-1:0] coeff [0:Tape_Num-1];\nreg signed [pDATA_WIDTH-1:0] data [0:Tape_Num-1];\ninteger i,j;\n// fir design\nwire [pDATA_WIDTH-1:0] temp_sum;\nwire [pDATA_WIDTH-1:0] cur_sum;\nreg [pDATA_WIDTH-1:0] prev_sum;\nreg [pDATA_WIDTH-1:0] cur_coef;\nreg [pDATA_WIDTH-1:0] cur_data;\n// fsm state\nlocalparam IDLE = 'd0;\nlocalparam LOAD = 'd1;\nlocalparam WORK = 'd2;\nlocalparam DONE = 'd3;\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Handshake\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign awready = awvalid;\nassign wready = wvalid;\nassign arready = arvalid;\nassign rvalid = rready;\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Stream Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign ss_tready = state==LOAD;\nassign sm_tvalid = (state==LOAD && cnt==4'd11) | state==DONE;\nassign sm_tdata = prev_sum;\nassign sm_tlast = state==DONE;\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AP_SIGNAL\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign ap_signal = {{29{1'b0}}, ap_idle, ap_done, ap_start};\n// ap_start\nalways @(*) begin\n if(state==IDLE && awaddr == 12'h00 && awvalid && wvalid && wdata == 32'h0000_0001) begin\n // write ap_start for short pulse, deassert when the engine is not IDLE\n next_ap_start = 1;\n end else begin\n next_ap_start = 0;\n end\nend\n// ap_idle\nalways @(*) begin\n if(next_ap_start) begin\n next_ap_idle = 0;\n end else if(state == DONE) begin\n next_ap_idle = 1;\n end else begin\n next_ap_idle = ap_idle;\n end\nend\n// ap_done\nalways @(*) begin\n if(state == DONE) begin\n next_ap_done = 1;\n end else begin\n next_ap_done = ap_done;\n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ap_idle <= 1'b1;\n ap_done <= 1'b0;\n ap_start <= 1'b0;\n end else begin\n ap_idle <= next_ap_idle;\n ap_done <= next_ap_done;\n ap_start <= next_ap_start;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Coefficient from AXI-Lite and store into coeff buffer and tap RAM\n//\n//////////////////////////////////////////////////////////////////////////////////\n// When Read addr = 0x00 should read out ap_signal\n// The others addr should read out the coefficient\nassign rdata = (araddr == 12'h00) ? ap_signal : tap_Do;\n\n// Write / Read tap RAM from AXI-Lite protocal\nalways @(*) begin\n if(awvalid) begin\n // write\n if((awaddr != 12'h00) && (awaddr != 12'h10)) begin\n tap_A = awaddr - 12'h20;\n tap_EN = 1'b1;\n tap_WE = 4'b1111;\n tap_Di = wdata;\n end else begin\n tap_A = 'd0;\n tap_EN = 'd0;\n tap_WE = 'd0;\n tap_Di = 'd0; \n end\n end else if (arvalid) begin\n if(araddr != 12'h00 && araddr != 12'h10) begin\n tap_A = araddr - 12'h20;\n tap_EN = 1'b1;\n tap_WE = 'd0;\n tap_Di = 'd0;\n end else begin\n tap_A = 'd0;\n tap_EN = 'd0;\n tap_WE = 'd0;\n tap_Di = 'd0;\n end\n end else begin\n tap_A = 'd0;\n tap_EN = 'd0;\n tap_WE = 'd0;\n tap_Di = 'd0; \n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Data Length from AXI-Lite and store into data_length buffer\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_length <= 'd0;\n end else if(awaddr == 12'h10) begin\n data_length <= wdata;\n end else begin\n data_length <= data_length;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Coefficient buffer and Data buffer\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n for (i=0; i<Tape_Num; i=i+1) begin\n coeff[i] <= 0;\n end \n end else if(awvalid && (awaddr!=12'h00 && awaddr!=12'h10) && cnt=='d0) begin\n for (i=0; i<Tape_Num-1; i=i+1) begin\n coeff[i] <= coeff[i+1];\n end\n coeff[Tape_Num-1] <= wdata;\n end else begin\n for (i=0; i<Tape_Num; i=i+1) begin\n coeff[i] <= coeff[i];\n end \n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n for (j=0; j<Tape_Num; j=j+1) begin\n data[j] <= 'd0;\n end \n end else if(ss_tready) begin // data in, write into shift buffer\n for (j=0; j<Tape_Num-1; j=j+1) begin\n data[j] <= data[j+1];\n end\n data[Tape_Num-1] <= ss_tdata;\n end else begin\n for (j=0; j<Tape_Num; j=j+1) begin\n data[j] <= data[j];\n end \n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FSM\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways@(posedge axis_clk) begin\n if(~axis_rst_n) begin\n finish <= 1'b0;\n end else if(state==LOAD && ss_tlast) begin\n finish <= 1'b1;\n end else begin\n finish <= finish;\n end\nend\nalways @(*) begin\n case(state)\n IDLE: next_state = (ap_start) ? LOAD: IDLE;\n LOAD: next_state = WORK;\n WORK: next_state = (cnt == Tape_Num-1) ? (finish) ? DONE : LOAD : WORK;\n DONE: next_state = DONE;\n default: next_state = IDLE;\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n state <= IDLE;\n end else begin\n state <= next_state;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Counter\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways @(*) begin\n if(state==LOAD) begin\n next_cnt = 'd0;\n end else if(((state==IDLE)&&awvalid) | (state==WORK)) begin\n next_cnt = cnt + 1;\n end else begin\n next_cnt = 'd0;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n cnt <= 'd0;\n end else begin\n cnt <= next_cnt;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FIR computation\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign temp_sum = cur_data * cur_coef;\nassign cur_sum = prev_sum + temp_sum;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state == WORK) begin\n prev_sum <= cur_sum;\n cur_coef <= coeff[cnt];\n cur_data <= data[cnt];\n end else begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end\nend\n\nendmodule\n\n\n// Path: fir/rtl/input_buffer.v\nmodule input_buffer\r\n#( parameter pADDR_WIDTH = 12,\r\n parameter pDATA_WIDTH = 32\r\n)\r\n(\r\n input axis_clk,\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // INPUT\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // AXI_Lite protocal\r\n input [pADDR_WIDTH-1:0] awaddr, \r\n input awvalid, \r\n input [pDATA_WIDTH-1:0] wdata, \r\n input wvalid, \r\n input [pADDR_WIDTH-1:0] araddr, \r\n input arvalid, \r\n input rready, \r\n // AXI_Stream protocal\r\n input ss_tvalid, \r\n input [pDATA_WIDTH-1:0] ss_tdata, \r\n input ss_tlast, \r\n input sm_tready, \r\n // tap sram\r\n input [pDATA_WIDTH-1:0] tap_Do, \r\n // data sram\r\n input [pDATA_WIDTH-1:0] data_Do,\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // OUTPUT\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // AXI_Lite protocal\r\n output reg [pADDR_WIDTH-1:0] awaddr_d, \r\n output reg awvalid_d, \r\n output reg [pDATA_WIDTH-1:0] wdata_d, \r\n output reg wvalid_d, \r\n output reg [pADDR_WIDTH-1:0] araddr_d, \r\n output reg arvalid_d, \r\n output reg rready_d, \r\n // AXI_Stream protocal\r\n output reg ss_tvalid_d, \r\n output reg [pDATA_WIDTH-1:0] ss_tdata_d, \r\n output reg ss_tlast_d, \r\n output reg sm_tready_d, \r\n // tap sram\r\n output reg [pDATA_WIDTH-1:0] tap_Do_d, \r\n // data sram\r\n output reg [pDATA_WIDTH-1:0] data_Do_d\r\n);\r\n\r\nalways @(posedge axis_clk) begin\r\n // AXI_Lite protocal\r\n awaddr_d <= awaddr;\r\n awvalid_d <= awvalid;\r\n wdata_d <= wdata;\r\n wvalid_d <= wvalid;\r\n araddr_d <= araddr;\r\n arvalid_d <= arvalid;\r\n rready_d <= rready;\r\n // AXI_Stream protocal\r\n ss_tvalid_d <= ss_tvalid;\r\n ss_tdata_d <= ss_tdata;\r\n ss_tlast_d <= ss_tlast;\r\n sm_tready_d <= sm_tready;\r\n // tap sram\r\n tap_Do_d <= tap_Do;\r\n // data sram\r\n data_Do_d <= data_Do;\r\nend\r\n\r\nendmodule\n\n// Path: fir/tb/fir_tb.v\n`timescale 1ns / 1ps\r\n//////////////////////////////////////////////////////////////////////////////////\r\n// Company: \r\n// Engineer: \r\n// \r\n// Create Date: 08/20/2023 10:38:55 AM\r\n// Design Name: \r\n// Module Name: fir_tb\r\n// Project Name: \r\n// Target Devices: \r\n// Tool Versions: \r\n// Description: \r\n// \r\n// Dependencies: \r\n// \r\n// Revision:\r\n// Revision 0.01 - File Created\r\n// Additional Comments:\r\n// \r\n//////////////////////////////////////////////////////////////////////////////////\r\n`include \"/home/ubuntu/course-lab_3/bram/bram11.v\"\r\nmodule fir_tb\r\n#( parameter pADDR_WIDTH = 12,\r\n parameter pDATA_WIDTH = 32,\r\n parameter Tape_Num = 11,\r\n parameter Data_Num = 600\r\n)();\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// IO DECLARATION\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\n// System clk and rst\r\nreg axis_clk;\r\nreg axis_rst_n;\r\n// AXI4-Lite interface\r\n// Write\r\nreg [pADDR_WIDTH-1:0] awaddr;\r\nreg awvalid;\r\nwire awready;\r\nreg signed [pDATA_WIDTH-1:0] wdata;\r\nreg wvalid;\r\nwire wready;\r\n// Read\r\nreg [pADDR_WIDTH-1:0] araddr;\r\nreg arvalid;\r\nwire arready;\r\nwire signed [pDATA_WIDTH-1:0] rdata;\r\nwire rvalid;\r\nreg rready;\r\n// AXI4-Stream interface\r\nreg signed [pDATA_WIDTH-1:0] ss_tdata;\r\nreg ss_tvalid;\r\nreg ss_tlast;\r\nwire ss_tready;\r\nwire signed [pDATA_WIDTH-1:0] sm_tdata;\r\nwire sm_tvalid;\r\nwire sm_tlast;\r\nreg sm_tready;\r\n// bram for tap RAM (store coefficient)\r\nwire [3:0] tap_WE;\r\nwire tap_EN;\r\nwire [pDATA_WIDTH-1:0] tap_Di;\r\nwire [pADDR_WIDTH-1:0] tap_A;\r\nwire [pDATA_WIDTH-1:0] tap_Do;\r\n// bram for data RAM (store input data)\r\nwire [3:0] data_WE;\r\nwire data_EN;\r\nwire [pDATA_WIDTH-1:0] data_Di;\r\nwire [pADDR_WIDTH-1:0] data_A;\r\nwire [pDATA_WIDTH-1:0] data_Do;\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// FIR AND SRAM CIRCUIT \r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nfir fir_DUT (\r\n // System clk and rst\r\n .axis_clk (axis_clk),\r\n .axis_rst_n (axis_rst_n),\r\n // AXI4-Lite interface\r\n // Write\r\n .awaddr (awaddr),\r\n .awvalid (awvalid),\r\n .awready (awready),\r\n .wdata (wdata),\r\n .wvalid (wvalid),\r\n .wready (wready),\r\n // Read\r\n .araddr (araddr),\r\n .arvalid (arvalid),\r\n .arready (arready),\r\n .rdata (rdata),\r\n .rvalid (rvalid),\r\n .rready (rready),\r\n // AXI4-Stream interface\r\n .ss_tdata (ss_tdata),\r\n .ss_tvalid (ss_tvalid),\r\n .ss_tlast (ss_tlast),\r\n .ss_tready (ss_tready),\r\n .sm_tdata (sm_tdata),\r\n .sm_tvalid (sm_tvalid),\r\n .sm_tlast (sm_tlast),\r\n .sm_tready (sm_tready),\r\n // bram for tap RAM (store coefficient)\r\n .tap_WE (tap_WE),\r\n .tap_EN (tap_EN),\r\n .tap_Di (tap_Di),\r\n .tap_A (tap_A),\r\n .tap_Do (tap_Do),\r\n // bram for data RAM (store input data)\r\n .data_WE (data_WE),\r\n .data_EN (data_EN),\r\n .data_Di (data_Di),\r\n .data_A (data_A),\r\n .data_Do (data_Do) \r\n);\r\n\r\n// RAM for tap\r\nbram11 tap_RAM (\r\n .CLK (axis_clk),\r\n .WE (tap_WE),\r\n .EN (tap_EN),\r\n .Di (tap_Di),\r\n .A (tap_A),\r\n .Do (tap_Do)\r\n);\r\n\r\n// RAM for data: choose bram11 or bram12\r\nbram11 data_RAM(\r\n .CLK (axis_clk),\r\n .WE (data_WE),\r\n .EN (data_EN),\r\n .Di (data_Di),\r\n .A (data_A),\r\n .Do (data_Do)\r\n);\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// DUMP FILE\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninitial begin\r\n $dumpfile(\"fir.vcd\");\r\n $dumpvars();\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// CLOCK AND RESET\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninitial begin\r\n axis_clk = 0;\r\n forever begin\r\n #5 axis_clk = (~axis_clk);\r\n end\r\nend\r\n\r\ninitial begin\r\n axis_rst_n = 0;\r\n @(posedge axis_clk); @(posedge axis_clk);\r\n axis_rst_n = 1;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// LOAD THE INPUT AND GOLDEN DATA\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nreg signed [pDATA_WIDTH-1:0] Din_list [0:Data_Num-1];\r\nreg signed [pDATA_WIDTH-1:0] golden_list [0:Data_Num-1];\r\nreg [31:0] data_length;\r\n\r\ninteger Din, golden, input_data, golden_data, m;\r\n\r\ninitial begin\r\n data_length = 0;\r\n Din = $fopen(\"/home/ubuntu/course-lab_3/fir/samples_triangular_wave.dat\",\"r\");\r\n golden = $fopen(\"/home/ubuntu/course-lab_3/fir/out_gold.dat\",\"r\");\r\n for (m=0; m<Data_Num; m=m+1) begin\r\n input_data = $fscanf(Din,\"%d\", Din_list[m]);\r\n golden_data = $fscanf(golden,\"%d\", golden_list[m]);\r\n data_length = data_length + 1;\r\n end\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// SIMULATION\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninteger i;\r\ninitial begin\r\n $display(\"------------Start simulation-----------\");\r\n ss_tvalid = 0;\r\n $display(\"----Start the data input(AXI-Stream)----\");\r\n // send data into FIR design\r\n wait(axis_rst_n);\r\n for(i=0; i<(data_length-1); i=i+1) begin\r\n ss_tlast = 0; ss(Din_list[i]);\r\n end\r\n\r\n config_read_check(12'h00, 32'h00, 32'h0000_000f); // check idle = 0\r\n ss_tlast = 1; ss(Din_list[(Data_Num-1)]);\r\n $display(\"------End the data input(AXI-Stream)------\");\r\nend\r\n\r\ninteger k;\r\nreg error;\r\nreg error_coef;\r\nreg status_error;\r\ninitial begin\r\n error = 0; status_error = 0;\r\n sm_tready = 1;\r\n wait (sm_tvalid);\r\n for(k=0; k<data_length; k=k+1) begin\r\n sm(golden_list[k],k);\r\n end\r\n $display(\"check\");\r\n config_read_check(12'h00, 32'h02, 32'h0000_0002); // check ap_done = 1 (0x00 [bit 1])\r\n config_read_check(12'h00, 32'h04, 32'h0000_0004); // check ap_idle = 1 (0x00 [bit 2])\r\n if (error == 0 & error_coef == 0) begin\r\n $display(\"---------------------------------------------\");\r\n $display(\"-----------Congratulations! Pass-------------\");\r\n end\r\n else begin\r\n $display(\"--------Simulation Failed---------\");\r\n end\r\n $finish;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// Prevent hang, set up the maximum cycle number\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninteger timeout = (1000000);\r\ninitial begin\r\n while(timeout > 0) begin\r\n @(posedge axis_clk);\r\n timeout = timeout - 1;\r\n end\r\n $display($time, \"Simualtion Hang ....\");\r\n $finish;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// Coefficient \r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nreg signed [31:0] coef[0:10]; // fill in coef \r\ninitial begin\r\n coef[0] = 32'd0;\r\n coef[1] = -32'd10;\r\n coef[2] = -32'd9;\r\n coef[3] = 32'd23;\r\n coef[4] = 32'd56;\r\n coef[5] = 32'd63;\r\n coef[6] = 32'd56;\r\n coef[7] = 32'd23;\r\n coef[8] = -32'd9;\r\n coef[9] = -32'd10;\r\n coef[10] = 32'd0;\r\nend\r\n\r\ninitial begin\r\n error_coef = 0;\r\n $display(\"----Start the coefficient input(AXI-lite)----\");\r\n awvalid <= 0;\r\n wvalid <= 0;\r\n wait(axis_rst_n);\r\n config_write(12'h10, data_length);\r\n for(k=0; k< Tape_Num; k=k+1) begin\r\n config_write(12'h20+4*k, coef[k]);\r\n end\r\n awvalid <= 0; wvalid <= 0;\r\n // read-back and check\r\n $display(\" Check Coefficient ...\");\r\n for(k=0; k < Tape_Num; k=k+1) begin\r\n config_read_check(12'h20+4*k, coef[k], 32'hffffffff);\r\n end\r\n arvalid <= 0;\r\n $display(\" Tape programming done ...\");\r\n $display(\" Start FIR\");\r\n @(posedge axis_clk) config_write(12'h00, 32'h0000_0001); // ap_start = 1\r\n $display(\"----End the coefficient input(AXI-lite)----\");\r\nend\r\n\r\ntask config_write;\r\n input [11:0] addr;\r\n input [31:0] data;\r\n begin\r\n awvalid <= 0; wvalid <= 0;\r\n @(posedge axis_clk);\r\n awvalid <= 1; awaddr <= addr;\r\n wvalid <= 1; wdata <= data;\r\n @(posedge axis_clk);\r\n @(negedge axis_clk);\r\n while (!wready) @(posedge axis_clk);\r\n awvalid <= 0; wvalid <= 0;\r\n end\r\nendtask\r\n\r\ntask config_read_check;\r\n input [11:0] addr;\r\n input signed [31:0] exp_data;\r\n input [31:0] mask;\r\n begin\r\n arvalid <= 0;\r\n @(posedge axis_clk);\r\n arvalid <= 1; araddr <= addr;\r\n rready <= 1;\r\n @(posedge axis_clk);\r\n wait(rvalid);\r\n @(negedge axis_clk);\r\n if( (rdata & mask) != (exp_data & mask)) begin\r\n $display(\"ERROR: exp = %d, rdata = %d\", exp_data, rdata);\r\n error_coef <= 1;\r\n end else begin\r\n $display(\"OK: exp = %d, rdata = %d\", exp_data, rdata);\r\n end\r\n end\r\nendtask\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// AXI4-STREAM INTERFACE, WRITE DATA IN OR READ DATA OUT FROM FIR DESIGN\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\n\r\ntask ss;\r\n input signed [31:0] in1;\r\n begin\r\n ss_tvalid <= 1;\r\n ss_tdata <= in1;\r\n @(posedge axis_clk);\r\n while (!ss_tready) begin\r\n @(posedge axis_clk);\r\n end\r\n end\r\nendtask\r\n\r\ntask sm;\r\n input signed [31:0] in2; // golden data\r\n input [31:0] pcnt; // pattern count\r\n begin\r\n sm_tready <= 1;\r\n @(posedge axis_clk) \r\n wait(sm_tvalid);\r\n while(!sm_tvalid) @(posedge axis_clk);\r\n if (sm_tdata != in2) begin\r\n $display(\"[ERROR] [Pattern %d] Golden answer: %d, Your answer: %d\", pcnt, in2, sm_tdata);\r\n error <= 1;\r\n end\r\n else begin\r\n $display(\"[PASS] [Pattern %d] Golden answer: %d, Your answer: %d\", pcnt, in2, sm_tdata);\r\n end\r\n @(posedge axis_clk);\r\n end\r\nendtask\r\n\r\nendmodule\r\n\n\n// Path: project_1/project_1.sim/sim_1/behav/xsim/glbl.v\n// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n parameter GRES_WIDTH = 10000;\n parameter GRES_START = 10000;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n wire GRESTORE;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n reg GRESTORE_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (strong1, weak0) GSR = GSR_int;\n assign (strong1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\n initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n end\n\nendmodule\n`endif\n\n\n// Path: bram/bram11.v\n// bram behavior code (can't be synthesis)\r// 11 words\rmodule bram11 \r(\r CLK,\r WE,\r EN,\r Di,\r Do,\r A\r);\r\r input wire CLK;\r input wire [3:0] WE;\r input wire EN;\r input wire [31:0] Di;\r output wire [31:0] Do;"
}
] |
input wire [11:0] A;
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: stephen-kao/course-lab_3\n// Path: bram/bram11.v\n// bram behavior code (can't be synthesis)\r\n// 11 words\r\nmodule bram11 \r\n(\r\n CLK,\r\n WE,\r\n EN,\r\n Di,\r\n Do,\r\n A\r\n);\r\n\r\n input wire CLK;\r\n input wire [3:0] WE;\r\n input wire EN;\r\n input wire [31:0] Di;\r\n output wire [31:0] Do;\r\n input wire [11:0] A; \r\n\r\n // 11 words\r\n\treg [31:0] RAM [0:10];\r\n reg [11:0] r_A;\r\n\r\n always @(posedge CLK) begin\r\n r_A <= A;\r\n end\r\n\r\n assign Do = {32{EN}} & RAM[r_A>>2]; // read\r\n\r\n reg [31:0] Temp_D;\r\n always @(posedge CLK) begin\r\n if(EN) begin\r\n if(WE[0]) RAM[A>>2][ 7: 0] <= Di[ 7: 0];\r\n if(WE[1]) RAM[A>>2][15: 8] <= Di[15: 8];\r\n if(WE[2]) RAM[A>>2][23:16] <= Di[23:16];\r\n if(WE[3]) RAM[A>>2][31:24] <= Di[31:24];\r\n end\r\n end\r\n\r\nendmodule\r\n\n\n// Path: fir/rtl/fir.v\nmodule fir \n#( parameter pADDR_WIDTH = 12,\n parameter pDATA_WIDTH = 32,\n parameter Tape_Num = 11\n)\n(\n // System clock and Reset\n input wire axis_clk,\n input wire axis_rst_n,\n // AXI-Lite Protocal\n // write\n input wire [pADDR_WIDTH-1:0] awaddr,\n input wire awvalid,\n output reg awready,\n input wire [pDATA_WIDTH-1:0] wdata,\n input wire wvalid,\n output reg wready,\n // read\n input wire [pADDR_WIDTH-1:0] araddr,\n input wire arvalid,\n output reg arready,\n output reg [pDATA_WIDTH-1:0] rdata, \n output reg rvalid,\n input wire rready,\n // AXI-Stream Protocal\n // data in\n input wire ss_tvalid, \n input wire [pDATA_WIDTH-1:0] ss_tdata, \n input wire ss_tlast, \n output reg ss_tready, \n // data out\n input wire sm_tready, \n output reg sm_tvalid, \n output reg [pDATA_WIDTH-1:0] sm_tdata, \n output reg sm_tlast, \n // bram for tap RAM (store coefficient)\n output reg [3:0] tap_WE,\n output reg tap_EN,\n output reg [pDATA_WIDTH-1:0] tap_Di,\n output reg [pADDR_WIDTH-1:0] tap_A,\n input wire [pDATA_WIDTH-1:0] tap_Do,\n // bram for data RAM (store data?)\n output reg [3:0] data_WE,\n output reg data_EN,\n output reg [pDATA_WIDTH-1:0] data_Di,\n output reg [pADDR_WIDTH-1:0] data_A,\n input wire [pDATA_WIDTH-1:0] data_Do\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// LOCAL PARAMETER DECLARATION\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap signal\nreg ap_idle;\nreg ap_done;\nreg ap_start;\nreg next_ap_idle;\nreg next_ap_done;\nreg next_ap_start;\n// fsm\nreg [1:0] state;\nreg [1:0] next_state;\nreg finish;\n// counter\nreg [4:0] next_cnt;\nreg [4:0] cnt;\n// coefficient buffer and data buffer\nreg signed [pDATA_WIDTH-1:0] coeff [0:Tape_Num-1];\nreg signed [pDATA_WIDTH-1:0] data [0:Tape_Num-1];\ninteger i,j;\n// fir design\nwire [pDATA_WIDTH-1:0] temp_sum;\nwire [pDATA_WIDTH-1:0] cur_sum;\nreg [pDATA_WIDTH-1:0] prev_sum;\nreg [pDATA_WIDTH-1:0] cur_coef;\nreg [pDATA_WIDTH-1:0] cur_data;\n// fsm state\nlocalparam IDLE = 'd0;\nlocalparam LOAD = 'd1;\nlocalparam WORK = 'd2;\nlocalparam DONE = 'd3;\n// input buffer\nwire [pADDR_WIDTH-1:0] awaddr_d; \nwire awvalid_d; \nwire [pDATA_WIDTH-1:0] wdata_d; \nwire wvalid_d; \nwire [pADDR_WIDTH-1:0] araddr_d; \nwire arvalid_d; \nwire rready_d; \nwire ss_tvalid_d;\nwire [pDATA_WIDTH-1:0] ss_tdata_d; \nwire ss_tlast_d; \nwire sm_tready_d;\nwire [pDATA_WIDTH-1:0] tap_Do_d; \nwire [pDATA_WIDTH-1:0] data_Do_d; \n// counter\nreg [3:0] tap_addr_cnt;\nreg [3:0] load_addr_cnt;\nreg [9:0] data_num_cnt;\nreg [3:0] flag;\nreg [3:0] work_addr_cnt;\nreg [3:0] next_tap_addr_cnt;\nreg [3:0] next_load_addr_cnt;\nreg [9:0] next_data_num_cnt;\nreg [3:0] next_flag;\nreg [3:0] next_work_addr_cnt;\n\ninput_buffer \n#(\n .pADDR_WIDTH (pADDR_WIDTH),\n .pDATA_WIDTH (pDATA_WIDTH)\n) input_buf (\n .axis_clk (axis_clk),\n //////////////////////////////////////////////////////////////////////////////////\n // INPUT\n //////////////////////////////////////////////////////////////////////////////////\n // AXI_Lite protocal\n .awaddr (awaddr),\n .awvalid (awvalid),\n .wdata (wdata),\n .wvalid (wvalid),\n .araddr (araddr),\n .arvalid (arvalid),\n .rready (rready),\n // AXI_Stream protocal\n .ss_tvalid (ss_tvalid),\n .ss_tdata (ss_tdata),\n .ss_tlast (ss_tlast),\n .sm_tready (sm_tready),\n // tap sram\n .tap_Do (tap_Do),\n // data sram\n .data_Do (data_Do),\n //////////////////////////////////////////////////////////////////////////////////\n // OUTPUT\n //////////////////////////////////////////////////////////////////////////////////\n // AXI_Lite protocal\n .awaddr_d (awaddr_d),\n .awvalid_d (awvalid_d),\n .wdata_d (wdata_d),\n .wvalid_d (wvalid_d),\n .araddr_d (araddr_d),\n .arvalid_d (arvalid_d),\n .rready_d (rready_d),\n // AXI_Stream protocal\n .ss_tvalid_d (ss_tvalid_d),\n .ss_tdata_d (ss_tdata_d),\n .ss_tlast_d (ss_tlast_d),\n .sm_tready_d (sm_tready_d),\n // tap sram\n .tap_Do_d (tap_Do_d),\n // data sram\n .data_Do_d (data_Do_d)\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Handshake Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nwire next_awready;\nwire next_wready;\nwire next_arready;\nwire next_rvalid;\n// AXI-Lite handshake, 1 for handshake successfully\nreg write_handshake;\nreg read_handshake;\n// rvalid trigger delay \nwire next_rvalid_trigger;\nreg rvalid_trigger;\nreg rvalid_trigger_d;\n\n// AXI-Lite handshake whether successfully or not\nalways @(*) begin\n write_handshake = (awvalid_d && awready) && (wvalid_d && wready);\n read_handshake = (arvalid_d && arready);\nend\n\n// AXI-Lite handshake control\n// write\nassign next_awready = awvalid_d;\nassign next_wready = wvalid_d;\n// read\nassign next_arready = arvalid_d;\nassign next_rvalid = (rvalid) ? 1'b0 : (~rvalid && ~arvalid_d) ? 1'b0 : (rvalid_trigger_d) ? 1'b1 : 1'b0;\nassign next_rvalid_trigger = ((tap_EN == 1'b1 && tap_WE == 'd0) && arvalid_d) | (state==DONE);\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n rvalid_trigger <= 'd0;\n rvalid_trigger_d <= 'd0;\n end else if(~arvalid_d) begin\n rvalid_trigger <= 'd0;\n rvalid_trigger_d <= 'd0;\n end else begin\n rvalid_trigger <= next_rvalid_trigger;\n rvalid_trigger_d <= rvalid_trigger;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n awready <= 'd0;\n wready <= 'd0;\n arready <= 'd0;\n rvalid <= 'd0;\n end else begin\n awready <= next_awready;\n wready <= next_wready;\n arready <= next_arready;\n rvalid <= next_rvalid;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Protocal\n// Addr = 12'h00: AP_Signal (store in buffer)\n// Addr = 12'h10: data_length (store in buffer)\n// Addr = others: Coefficient (store in tap SRAM)\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap_signal\nreg [pDATA_WIDTH-1:0] ap_signal;\nwire [pDATA_WIDTH-1:0] next_ap_signal;\n// data_length\nreg [pDATA_WIDTH-1:0] data_length;\nwire [pDATA_WIDTH-1:0] next_data_length;\n// tap SRAM \nreg [pADDR_WIDTH-1:0] next_tap_A;\nreg next_tap_EN;\nreg [3:0] next_tap_WE;\nreg [pDATA_WIDTH-1:0] next_tap_Di;\n\n\n/////////////////////////////////////////\n// AP Signal\n/////////////////////////////////////////\nassign next_ap_signal = {{29{1'b0}}, next_ap_idle, next_ap_done, next_ap_start};\n// ap_start\nalways @(*) begin\n if(state==IDLE && awaddr == 12'h00 && awvalid && wvalid && wdata == 32'h0000_0001) begin\n // write ap_start for short pulse, deassert when the engine is not IDLE\n next_ap_start = 1;\n end else begin\n next_ap_start = 0;\n end\nend\n// ap_idle\nalways @(*) begin\n if(next_ap_start) begin\n next_ap_idle = 0;\n end else if(state == DONE) begin\n next_ap_idle = 1;\n end else begin\n next_ap_idle = ap_idle;\n end\nend\n// ap_done\nalways @(*) begin\n if(state == DONE) begin\n next_ap_done = 1;\n end else begin\n next_ap_done = ap_done;\n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ap_idle <= 1'b1;\n ap_done <= 1'b0;\n ap_start <= 1'b0;\n ap_signal <= {{29{1'b0}}, 1'b1, 1'b0, 1'b0}; // the three LSB order: {idle, done, start}\n end else begin\n ap_idle <= next_ap_idle;\n ap_done <= next_ap_done;\n ap_start <= next_ap_start;\n ap_signal <= next_ap_signal;\n end\nend\n\n/////////////////////////////////////////\n// Data Length buffer\n/////////////////////////////////////////\nassign next_data_length = (awaddr_d==12'h10 && write_handshake) ? wdata_d : data_length;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_length <= 'd0;\n end else begin\n data_length <= next_data_length;\n end\nend\n\n/////////////////////////////////////////\n// coefficient\n/////////////////////////////////////////\n// When Read addr = 0x00 should read out ap_signal\n// The others addr should read out the coefficient\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n rdata <= 'd0;\n end else if(araddr_d==12'h00) begin\n rdata <= ap_signal;\n end else begin\n rdata <= tap_Do_d;\n end\nend\n\n// Write / Read tap RAM from AXI-Lite protocal\nalways @(*) begin\n if(write_handshake && awaddr_d >= 12'h20) begin\n // WRITE\n if((awaddr_d != 12'h00) && (awaddr_d != 12'h10)) begin\n // Neither ap-signal nor data_length, write for coefficient\n next_tap_A = awaddr_d - 12'h20;\n next_tap_EN = 1'b1;\n next_tap_WE = 4'b1111;\n next_tap_Di = wdata_d;\n end else begin\n next_tap_A = 'd0;\n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end\n end else if (read_handshake && araddr_d >= 12'h20) begin\n // READ\n if((araddr_d != 12'h00) && (araddr_d != 12'h10)) begin\n // Neither ap-signal nor data_length, read for coefficient\n next_tap_A = araddr_d - 12'h20;\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end else if(araddr_d == 12'h00) begin\n next_tap_A = 'd0;\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end else begin\n next_tap_A = 'd0;\n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end\n end else if(state==WORK) begin\n next_tap_A = {tap_addr_cnt, {2'b0}};\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end else begin\n next_tap_A = 'd0; \n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n tap_A <= 'd0;\n tap_EN <= 'd0;\n tap_WE <= 'd0;\n tap_Di <= 'd0; \n end else begin\n tap_A <= next_tap_A;\n tap_EN <= next_tap_EN;\n tap_WE <= next_tap_WE;\n tap_Di <= next_tap_Di; \n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Stream Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nwire next_ss_tready;\nwire next_sm_tvalid;\nwire [pDATA_WIDTH-1:0] next_sm_tdata;\nwire next_sm_tlast;\n\nassign next_ss_tready = next_state==LOAD;\nassign next_sm_tvalid = ((state==WORK) && (tap_addr_cnt==4'd2) && (data_num_cnt != 'd1)) | (state==DONE && tap_addr_cnt >= 4'd3);\nassign next_sm_tdata = prev_sum;\nassign next_sm_tlast = (state==DONE && tap_addr_cnt >= 4'd3);\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ss_tready <= 'd0;\n sm_tvalid <= 'd0;\n sm_tdata <= 'd0;\n sm_tlast <= 'd0;\n end else begin\n ss_tready <= next_ss_tready;\n sm_tvalid <= next_sm_tvalid;\n sm_tdata <= next_sm_tdata;\n sm_tlast <= next_sm_tlast;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Counter\n//\n//////////////////////////////////////////////////////////////////////////////////\n\n// tap_addr_cnt\nalways @(*) begin\n if(state==LOAD | (state==WORK && next_state==DONE)) begin\n next_tap_addr_cnt = 'd0;\n end else if(((state==IDLE)&&awvalid) | (state==WORK) | (state==DONE)) begin\n next_tap_addr_cnt = tap_addr_cnt + 1;\n end else begin\n next_tap_addr_cnt = 'd0;\n end\nend\n// load_addr_cnt\nalways @(*) begin\n if(state==LOAD) begin\n if(load_addr_cnt==4'd10) begin\n next_load_addr_cnt = 'd0;\n end else begin\n next_load_addr_cnt = load_addr_cnt + 1;\n end\n end else begin\n next_load_addr_cnt = load_addr_cnt;\n end\nend\n// data_num_cnt\nalways @(*) begin\n if(state==LOAD) begin\n next_data_num_cnt = data_num_cnt + 1;\n end else begin\n next_data_num_cnt = data_num_cnt;\n end\nend\n// flag\nalways @(*) begin\n if(data_num_cnt<=4'd11) begin\n next_flag = 'd0;\n end else begin\n next_flag = load_addr_cnt + 1;\n end\nend\n// work_addr_cnt\nalways @(*) begin\n if(state==LOAD && next_state==WORK) begin\n if(load_addr_cnt==4'd10) begin\n next_work_addr_cnt = 4'd0;\n end else begin\n next_work_addr_cnt = load_addr_cnt + 1;\n end\n end else if(state==WORK) begin\n if(work_addr_cnt==4'd10) begin\n next_work_addr_cnt = 'd0;\n end else begin\n next_work_addr_cnt = work_addr_cnt + 1;\n end\n end else begin\n next_work_addr_cnt = 'd0;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n tap_addr_cnt <= 'd0;\n load_addr_cnt <= 'd0;\n work_addr_cnt <= 'd0;\n flag <= 'd0;\n data_num_cnt <= 'd0;\n end else begin\n tap_addr_cnt <= next_tap_addr_cnt;\n load_addr_cnt <= next_load_addr_cnt;\n work_addr_cnt <= next_work_addr_cnt;\n flag <= next_flag;\n data_num_cnt <= next_data_num_cnt;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Data SRAM Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nreg [pADDR_WIDTH-1:0] next_data_A;\nreg next_data_EN;\nreg [3:0] next_data_WE;\nreg [pDATA_WIDTH-1:0] next_data_Di;\n\nalways @(*) begin\n case(state) \n IDLE: begin\n next_data_A = araddr_d - 12'h20;\n next_data_EN = 1'b1;\n next_data_WE = 4'b1111;\n next_data_Di = 'd0;\n end\n LOAD: begin\n next_data_A = {load_addr_cnt, {2'b0}}; // which addr we should write the newest data\n next_data_EN = 1'b1;\n next_data_WE = 4'b1111;\n next_data_Di = ss_tdata_d;\n end\n WORK: begin\n next_data_A = {work_addr_cnt, {2'b0}}; // which addr we need to compute\n next_data_EN = 1'b1;\n next_data_WE = 'd0;\n next_data_Di = 'd0;\n end \n default: begin\n next_data_A = 'd0;\n next_data_EN = 'd0;\n next_data_WE = 'd0;\n next_data_Di = 'd0;\n end\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_A <= 'd0;\n data_EN <= 'd0;\n data_WE <= 'd0;\n data_Di <= 'd0;\n end else begin\n data_A <= next_data_A;\n data_EN <= next_data_EN;\n data_WE <= next_data_WE;\n data_Di <= next_data_Di;\n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FSM\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways@(posedge axis_clk) begin\n if(~axis_rst_n) begin\n finish <= 1'b0;\n end else if(state==LOAD && ss_tlast) begin\n finish <= 1'b1;\n end else begin\n finish <= finish;\n end\nend\nalways @(*) begin\n case(state)\n IDLE: next_state = (ap_start) ? LOAD: IDLE;\n LOAD: next_state = WORK;\n WORK: next_state = (tap_addr_cnt == Tape_Num-1) ? (finish) ? DONE : LOAD : WORK;\n DONE: next_state = DONE;\n default: next_state = IDLE;\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n state <= IDLE;\n end else begin\n state <= next_state;\n end\nend\n\n// //////////////////////////////////////////////////////////////////////////////////\n// //\n// // FIR computation\n// //\n// //////////////////////////////////////////////////////////////////////////////////\nassign temp_sum = cur_data * cur_coef;\nassign cur_sum = prev_sum + temp_sum;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state == WORK && tap_addr_cnt==4'd2) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state==WORK | state==LOAD | state==DONE) begin\n prev_sum <= cur_sum;\n cur_coef <= tap_Do_d;\n cur_data <= data_Do_d;\n end else begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end\nend\n\nendmodule\n\n// Path: fir/rtl/fir_v1.v\nmodule fir \n#( parameter pADDR_WIDTH = 12,\n parameter pDATA_WIDTH = 32,\n parameter Tape_Num = 11\n)\n(\n // System clock and Reset\n input wire axis_clk,\n input wire axis_rst_n,\n // AXI-Lite Protocal\n // write\n input wire [pADDR_WIDTH-1:0] awaddr,\n input wire awvalid,\n output wire awready,\n input wire [pDATA_WIDTH-1:0] wdata,\n input wire wvalid,\n output wire wready,\n // read\n input wire [pADDR_WIDTH-1:0] araddr,\n input wire arvalid,\n output wire arready,\n output wire [pDATA_WIDTH-1:0] rdata, \n output wire rvalid,\n input wire rready,\n // AXI-Stream Protocal\n // data in\n input wire ss_tvalid, \n input wire [pDATA_WIDTH-1:0] ss_tdata, \n input wire ss_tlast, \n output wire ss_tready, \n // data out\n input wire sm_tready, \n output wire sm_tvalid, \n output wire [pDATA_WIDTH-1:0] sm_tdata, \n output wire sm_tlast, \n // bram for tap RAM (store coefficient)\n output reg [3:0] tap_WE,\n output reg tap_EN,\n output reg [pDATA_WIDTH-1:0] tap_Di,\n output reg [pADDR_WIDTH-1:0] tap_A,\n input wire [pDATA_WIDTH-1:0] tap_Do,\n // bram for data RAM (store data?)\n output reg [3:0] data_WE,\n output reg data_EN,\n output reg [pDATA_WIDTH-1:0] data_Di,\n output reg [pADDR_WIDTH-1:0] data_A,\n input wire [pDATA_WIDTH-1:0] data_Do\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// LOCAL PARAMETER DECLARATION\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap signal\nwire [pDATA_WIDTH-1:0] ap_signal; // ap_signal = {29{1'b0}, ap_idle, ap_done, ap_start}\nreg ap_idle;\nreg ap_done;\nreg ap_start;\nreg next_ap_idle;\nreg next_ap_done;\nreg next_ap_start;\n// data length\nreg [pDATA_WIDTH-1:0] data_length;\n// fsm\nreg [1:0] state;\nreg [1:0] next_state;\nreg finish;\n// counter\nreg [4:0] next_cnt;\nreg [4:0] cnt;\n// coefficient buffer and data buffer\nreg signed [pDATA_WIDTH-1:0] coeff [0:Tape_Num-1];\nreg signed [pDATA_WIDTH-1:0] data [0:Tape_Num-1];\ninteger i,j;\n// fir design\nwire [pDATA_WIDTH-1:0] temp_sum;\nwire [pDATA_WIDTH-1:0] cur_sum;\nreg [pDATA_WIDTH-1:0] prev_sum;\nreg [pDATA_WIDTH-1:0] cur_coef;\nreg [pDATA_WIDTH-1:0] cur_data;\n// fsm state\nlocalparam IDLE = 'd0;\nlocalparam LOAD = 'd1;\nlocalparam WORK = 'd2;\nlocalparam DONE = 'd3;\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Handshake\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign awready = awvalid;\nassign wready = wvalid;\nassign arready = arvalid;\nassign rvalid = rready;\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Stream Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign ss_tready = state==LOAD;\nassign sm_tvalid = (state==LOAD && cnt==4'd11) | state==DONE;\nassign sm_tdata = prev_sum;\nassign sm_tlast = state==DONE;\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AP_SIGNAL\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign ap_signal = {{29{1'b0}}, ap_idle, ap_done, ap_start};\n// ap_start\nalways @(*) begin\n if(state==IDLE && awaddr == 12'h00 && awvalid && wvalid && wdata == 32'h0000_0001) begin\n // write ap_start for short pulse, deassert when the engine is not IDLE\n next_ap_start = 1;\n end else begin\n next_ap_start = 0;\n end\nend\n// ap_idle\nalways @(*) begin\n if(next_ap_start) begin\n next_ap_idle = 0;\n end else if(state == DONE) begin\n next_ap_idle = 1;\n end else begin\n next_ap_idle = ap_idle;\n end\nend\n// ap_done\nalways @(*) begin\n if(state == DONE) begin\n next_ap_done = 1;\n end else begin\n next_ap_done = ap_done;\n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ap_idle <= 1'b1;\n ap_done <= 1'b0;\n ap_start <= 1'b0;\n end else begin\n ap_idle <= next_ap_idle;\n ap_done <= next_ap_done;\n ap_start <= next_ap_start;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Coefficient from AXI-Lite and store into coeff buffer and tap RAM\n//\n//////////////////////////////////////////////////////////////////////////////////\n// When Read addr = 0x00 should read out ap_signal\n// The others addr should read out the coefficient\nassign rdata = (araddr == 12'h00) ? ap_signal : tap_Do;\n\n// Write / Read tap RAM from AXI-Lite protocal\nalways @(*) begin\n if(awvalid) begin\n // write\n if((awaddr != 12'h00) && (awaddr != 12'h10)) begin\n tap_A = awaddr - 12'h20;\n tap_EN = 1'b1;\n tap_WE = 4'b1111;\n tap_Di = wdata;\n end else begin\n tap_A = 'd0;\n tap_EN = 'd0;\n tap_WE = 'd0;\n tap_Di = 'd0; \n end\n end else if (arvalid) begin\n if(araddr != 12'h00 && araddr != 12'h10) begin\n tap_A = araddr - 12'h20;\n tap_EN = 1'b1;\n tap_WE = 'd0;\n tap_Di = 'd0;\n end else begin\n tap_A = 'd0;\n tap_EN = 'd0;\n tap_WE = 'd0;\n tap_Di = 'd0;\n end\n end else begin\n tap_A = 'd0;\n tap_EN = 'd0;\n tap_WE = 'd0;\n tap_Di = 'd0; \n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Data Length from AXI-Lite and store into data_length buffer\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_length <= 'd0;\n end else if(awaddr == 12'h10) begin\n data_length <= wdata;\n end else begin\n data_length <= data_length;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Coefficient buffer and Data buffer\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n for (i=0; i<Tape_Num; i=i+1) begin\n coeff[i] <= 0;\n end \n end else if(awvalid && (awaddr!=12'h00 && awaddr!=12'h10) && cnt=='d0) begin\n for (i=0; i<Tape_Num-1; i=i+1) begin\n coeff[i] <= coeff[i+1];\n end\n coeff[Tape_Num-1] <= wdata;\n end else begin\n for (i=0; i<Tape_Num; i=i+1) begin\n coeff[i] <= coeff[i];\n end \n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n for (j=0; j<Tape_Num; j=j+1) begin\n data[j] <= 'd0;\n end \n end else if(ss_tready) begin // data in, write into shift buffer\n for (j=0; j<Tape_Num-1; j=j+1) begin\n data[j] <= data[j+1];\n end\n data[Tape_Num-1] <= ss_tdata;\n end else begin\n for (j=0; j<Tape_Num; j=j+1) begin\n data[j] <= data[j];\n end \n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FSM\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways@(posedge axis_clk) begin\n if(~axis_rst_n) begin\n finish <= 1'b0;\n end else if(state==LOAD && ss_tlast) begin\n finish <= 1'b1;\n end else begin\n finish <= finish;\n end\nend\nalways @(*) begin\n case(state)\n IDLE: next_state = (ap_start) ? LOAD: IDLE;\n LOAD: next_state = WORK;\n WORK: next_state = (cnt == Tape_Num-1) ? (finish) ? DONE : LOAD : WORK;\n DONE: next_state = DONE;\n default: next_state = IDLE;\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n state <= IDLE;\n end else begin\n state <= next_state;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Counter\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways @(*) begin\n if(state==LOAD) begin\n next_cnt = 'd0;\n end else if(((state==IDLE)&&awvalid) | (state==WORK)) begin\n next_cnt = cnt + 1;\n end else begin\n next_cnt = 'd0;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n cnt <= 'd0;\n end else begin\n cnt <= next_cnt;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FIR computation\n//\n//////////////////////////////////////////////////////////////////////////////////\nassign temp_sum = cur_data * cur_coef;\nassign cur_sum = prev_sum + temp_sum;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state == WORK) begin\n prev_sum <= cur_sum;\n cur_coef <= coeff[cnt];\n cur_data <= data[cnt];\n end else begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end\nend\n\nendmodule\n\n\n// Path: fir/rtl/input_buffer.v\nmodule input_buffer\r\n#( parameter pADDR_WIDTH = 12,\r\n parameter pDATA_WIDTH = 32\r\n)\r\n(\r\n input axis_clk,\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // INPUT\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // AXI_Lite protocal\r\n input [pADDR_WIDTH-1:0] awaddr, \r\n input awvalid, \r\n input [pDATA_WIDTH-1:0] wdata, \r\n input wvalid, \r\n input [pADDR_WIDTH-1:0] araddr, \r\n input arvalid, \r\n input rready, \r\n // AXI_Stream protocal\r\n input ss_tvalid, \r\n input [pDATA_WIDTH-1:0] ss_tdata, \r\n input ss_tlast, \r\n input sm_tready, \r\n // tap sram\r\n input [pDATA_WIDTH-1:0] tap_Do, \r\n // data sram\r\n input [pDATA_WIDTH-1:0] data_Do,\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // OUTPUT\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // AXI_Lite protocal\r\n output reg [pADDR_WIDTH-1:0] awaddr_d, \r\n output reg awvalid_d, \r\n output reg [pDATA_WIDTH-1:0] wdata_d, \r\n output reg wvalid_d, \r\n output reg [pADDR_WIDTH-1:0] araddr_d, \r\n output reg arvalid_d, \r\n output reg rready_d, \r\n // AXI_Stream protocal\r\n output reg ss_tvalid_d, \r\n output reg [pDATA_WIDTH-1:0] ss_tdata_d, \r\n output reg ss_tlast_d, \r\n output reg sm_tready_d, \r\n // tap sram\r\n output reg [pDATA_WIDTH-1:0] tap_Do_d, \r\n // data sram\r\n output reg [pDATA_WIDTH-1:0] data_Do_d\r\n);\r\n\r\nalways @(posedge axis_clk) begin\r\n // AXI_Lite protocal\r\n awaddr_d <= awaddr;\r\n awvalid_d <= awvalid;\r\n wdata_d <= wdata;\r\n wvalid_d <= wvalid;\r\n araddr_d <= araddr;\r\n arvalid_d <= arvalid;\r\n rready_d <= rready;\r\n // AXI_Stream protocal\r\n ss_tvalid_d <= ss_tvalid;\r\n ss_tdata_d <= ss_tdata;\r\n ss_tlast_d <= ss_tlast;\r\n sm_tready_d <= sm_tready;\r\n // tap sram\r\n tap_Do_d <= tap_Do;\r\n // data sram\r\n data_Do_d <= data_Do;\r\nend\r\n\r\nendmodule\n\n// Path: fir/tb/fir_tb.v\n`timescale 1ns / 1ps\r\n//////////////////////////////////////////////////////////////////////////////////\r\n// Company: \r\n// Engineer: \r\n// \r\n// Create Date: 08/20/2023 10:38:55 AM\r\n// Design Name: \r\n// Module Name: fir_tb\r\n// Project Name: \r\n// Target Devices: \r\n// Tool Versions: \r\n// Description: \r\n// \r\n// Dependencies: \r\n// \r\n// Revision:\r\n// Revision 0.01 - File Created\r\n// Additional Comments:\r\n// \r\n//////////////////////////////////////////////////////////////////////////////////\r\n`include \"/home/ubuntu/course-lab_3/bram/bram11.v\"\r\nmodule fir_tb\r\n#( parameter pADDR_WIDTH = 12,\r\n parameter pDATA_WIDTH = 32,\r\n parameter Tape_Num = 11,\r\n parameter Data_Num = 600\r\n)();\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// IO DECLARATION\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\n// System clk and rst\r\nreg axis_clk;\r\nreg axis_rst_n;\r\n// AXI4-Lite interface\r\n// Write\r\nreg [pADDR_WIDTH-1:0] awaddr;\r\nreg awvalid;\r\nwire awready;\r\nreg signed [pDATA_WIDTH-1:0] wdata;\r\nreg wvalid;\r\nwire wready;\r\n// Read\r\nreg [pADDR_WIDTH-1:0] araddr;\r\nreg arvalid;\r\nwire arready;\r\nwire signed [pDATA_WIDTH-1:0] rdata;\r\nwire rvalid;\r\nreg rready;\r\n// AXI4-Stream interface\r\nreg signed [pDATA_WIDTH-1:0] ss_tdata;\r\nreg ss_tvalid;\r\nreg ss_tlast;\r\nwire ss_tready;\r\nwire signed [pDATA_WIDTH-1:0] sm_tdata;\r\nwire sm_tvalid;\r\nwire sm_tlast;\r\nreg sm_tready;\r\n// bram for tap RAM (store coefficient)\r\nwire [3:0] tap_WE;\r\nwire tap_EN;\r\nwire [pDATA_WIDTH-1:0] tap_Di;\r\nwire [pADDR_WIDTH-1:0] tap_A;\r\nwire [pDATA_WIDTH-1:0] tap_Do;\r\n// bram for data RAM (store input data)\r\nwire [3:0] data_WE;\r\nwire data_EN;\r\nwire [pDATA_WIDTH-1:0] data_Di;\r\nwire [pADDR_WIDTH-1:0] data_A;\r\nwire [pDATA_WIDTH-1:0] data_Do;\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// FIR AND SRAM CIRCUIT \r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nfir fir_DUT (\r\n // System clk and rst\r\n .axis_clk (axis_clk),\r\n .axis_rst_n (axis_rst_n),\r\n // AXI4-Lite interface\r\n // Write\r\n .awaddr (awaddr),\r\n .awvalid (awvalid),\r\n .awready (awready),\r\n .wdata (wdata),\r\n .wvalid (wvalid),\r\n .wready (wready),\r\n // Read\r\n .araddr (araddr),\r\n .arvalid (arvalid),\r\n .arready (arready),\r\n .rdata (rdata),\r\n .rvalid (rvalid),\r\n .rready (rready),\r\n // AXI4-Stream interface\r\n .ss_tdata (ss_tdata),\r\n .ss_tvalid (ss_tvalid),\r\n .ss_tlast (ss_tlast),\r\n .ss_tready (ss_tready),\r\n .sm_tdata (sm_tdata),\r\n .sm_tvalid (sm_tvalid),\r\n .sm_tlast (sm_tlast),\r\n .sm_tready (sm_tready),\r\n // bram for tap RAM (store coefficient)\r\n .tap_WE (tap_WE),\r\n .tap_EN (tap_EN),\r\n .tap_Di (tap_Di),\r\n .tap_A (tap_A),\r\n .tap_Do (tap_Do),\r\n // bram for data RAM (store input data)\r\n .data_WE (data_WE),\r\n .data_EN (data_EN),\r\n .data_Di (data_Di),\r\n .data_A (data_A),\r\n .data_Do (data_Do) \r\n);\r\n\r\n// RAM for tap\r\nbram11 tap_RAM (\r\n .CLK (axis_clk),\r\n .WE (tap_WE),\r\n .EN (tap_EN),\r\n .Di (tap_Di),\r\n .A (tap_A),\r\n .Do (tap_Do)\r\n);\r\n\r\n// RAM for data: choose bram11 or bram12\r\nbram11 data_RAM(\r\n .CLK (axis_clk),\r\n .WE (data_WE),\r\n .EN (data_EN),\r\n .Di (data_Di),\r\n .A (data_A),\r\n .Do (data_Do)\r\n);\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// DUMP FILE\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninitial begin\r\n $dumpfile(\"fir.vcd\");\r\n $dumpvars();\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// CLOCK AND RESET\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninitial begin\r\n axis_clk = 0;\r\n forever begin\r\n #5 axis_clk = (~axis_clk);\r\n end\r\nend\r\n\r\ninitial begin\r\n axis_rst_n = 0;\r\n @(posedge axis_clk); @(posedge axis_clk);\r\n axis_rst_n = 1;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// LOAD THE INPUT AND GOLDEN DATA\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nreg signed [pDATA_WIDTH-1:0] Din_list [0:Data_Num-1];\r\nreg signed [pDATA_WIDTH-1:0] golden_list [0:Data_Num-1];\r\nreg [31:0] data_length;\r\n\r\ninteger Din, golden, input_data, golden_data, m;\r\n\r\ninitial begin\r\n data_length = 0;\r\n Din = $fopen(\"/home/ubuntu/course-lab_3/fir/samples_triangular_wave.dat\",\"r\");\r\n golden = $fopen(\"/home/ubuntu/course-lab_3/fir/out_gold.dat\",\"r\");\r\n for (m=0; m<Data_Num; m=m+1) begin\r\n input_data = $fscanf(Din,\"%d\", Din_list[m]);\r\n golden_data = $fscanf(golden,\"%d\", golden_list[m]);\r\n data_length = data_length + 1;\r\n end\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// SIMULATION\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninteger i;\r\ninitial begin\r\n $display(\"------------Start simulation-----------\");\r\n ss_tvalid = 0;\r\n $display(\"----Start the data input(AXI-Stream)----\");\r\n // send data into FIR design\r\n wait(axis_rst_n);\r\n for(i=0; i<(data_length-1); i=i+1) begin\r\n ss_tlast = 0; ss(Din_list[i]);\r\n end\r\n\r\n config_read_check(12'h00, 32'h00, 32'h0000_000f); // check idle = 0\r\n ss_tlast = 1; ss(Din_list[(Data_Num-1)]);\r\n $display(\"------End the data input(AXI-Stream)------\");\r\nend\r\n\r\ninteger k;\r\nreg error;\r\nreg error_coef;\r\nreg status_error;\r\ninitial begin\r\n error = 0; status_error = 0;\r\n sm_tready = 1;\r\n wait (sm_tvalid);\r\n for(k=0; k<data_length; k=k+1) begin\r\n sm(golden_list[k],k);\r\n end\r\n $display(\"check\");\r\n config_read_check(12'h00, 32'h02, 32'h0000_0002); // check ap_done = 1 (0x00 [bit 1])\r\n config_read_check(12'h00, 32'h04, 32'h0000_0004); // check ap_idle = 1 (0x00 [bit 2])\r\n if (error == 0 & error_coef == 0) begin\r\n $display(\"---------------------------------------------\");\r\n $display(\"-----------Congratulations! Pass-------------\");\r\n end\r\n else begin\r\n $display(\"--------Simulation Failed---------\");\r\n end\r\n $finish;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// Prevent hang, set up the maximum cycle number\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninteger timeout = (1000000);\r\ninitial begin\r\n while(timeout > 0) begin\r\n @(posedge axis_clk);\r\n timeout = timeout - 1;\r\n end\r\n $display($time, \"Simualtion Hang ....\");\r\n $finish;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// Coefficient \r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nreg signed [31:0] coef[0:10]; // fill in coef \r\ninitial begin\r\n coef[0] = 32'd0;\r\n coef[1] = -32'd10;\r\n coef[2] = -32'd9;\r\n coef[3] = 32'd23;\r\n coef[4] = 32'd56;\r\n coef[5] = 32'd63;\r\n coef[6] = 32'd56;\r\n coef[7] = 32'd23;\r\n coef[8] = -32'd9;\r\n coef[9] = -32'd10;\r\n coef[10] = 32'd0;\r\nend\r\n\r\ninitial begin\r\n error_coef = 0;\r\n $display(\"----Start the coefficient input(AXI-lite)----\");\r\n awvalid <= 0;\r\n wvalid <= 0;\r\n wait(axis_rst_n);\r\n config_write(12'h10, data_length);\r\n for(k=0; k< Tape_Num; k=k+1) begin\r\n config_write(12'h20+4*k, coef[k]);\r\n end\r\n awvalid <= 0; wvalid <= 0;\r\n // read-back and check\r\n $display(\" Check Coefficient ...\");\r\n for(k=0; k < Tape_Num; k=k+1) begin\r\n config_read_check(12'h20+4*k, coef[k], 32'hffffffff);\r\n end\r\n arvalid <= 0;\r\n $display(\" Tape programming done ...\");\r\n $display(\" Start FIR\");\r\n @(posedge axis_clk) config_write(12'h00, 32'h0000_0001); // ap_start = 1\r\n $display(\"----End the coefficient input(AXI-lite)----\");\r\nend\r\n\r\ntask config_write;\r\n input [11:0] addr;\r\n input [31:0] data;\r\n begin\r\n awvalid <= 0; wvalid <= 0;\r\n @(posedge axis_clk);\r\n awvalid <= 1; awaddr <= addr;\r\n wvalid <= 1; wdata <= data;\r\n @(posedge axis_clk);\r\n @(negedge axis_clk);\r\n while (!wready) @(posedge axis_clk);\r\n awvalid <= 0; wvalid <= 0;\r\n end\r\nendtask\r\n\r\ntask config_read_check;\r\n input [11:0] addr;\r\n input signed [31:0] exp_data;\r\n input [31:0] mask;\r\n begin\r\n arvalid <= 0;\r\n @(posedge axis_clk);\r\n arvalid <= 1; araddr <= addr;\r\n rready <= 1;\r\n @(posedge axis_clk);\r\n wait(rvalid);\r\n @(negedge axis_clk);\r\n if( (rdata & mask) != (exp_data & mask)) begin\r\n $display(\"ERROR: exp = %d, rdata = %d\", exp_data, rdata);\r\n error_coef <= 1;\r\n end else begin\r\n $display(\"OK: exp = %d, rdata = %d\", exp_data, rdata);\r\n end\r\n end\r\nendtask\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// AXI4-STREAM INTERFACE, WRITE DATA IN OR READ DATA OUT FROM FIR DESIGN\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\n\r\ntask ss;\r\n input signed [31:0] in1;\r\n begin\r\n ss_tvalid <= 1;\r\n ss_tdata <= in1;\r\n @(posedge axis_clk);\r\n while (!ss_tready) begin\r\n @(posedge axis_clk);\r\n end\r\n end\r\nendtask\r\n\r\ntask sm;\r\n input signed [31:0] in2; // golden data\r\n input [31:0] pcnt; // pattern count\r\n begin\r\n sm_tready <= 1;\r\n @(posedge axis_clk) \r\n wait(sm_tvalid);\r\n while(!sm_tvalid) @(posedge axis_clk);\r\n if (sm_tdata != in2) begin\r\n $display(\"[ERROR] [Pattern %d] Golden answer: %d, Your answer: %d\", pcnt, in2, sm_tdata);\r\n error <= 1;\r\n end\r\n else begin\r\n $display(\"[PASS] [Pattern %d] Golden answer: %d, Your answer: %d\", pcnt, in2, sm_tdata);\r\n end\r\n @(posedge axis_clk);\r\n end\r\nendtask\r\n\r\nendmodule\r\n\n\n// Path: project_1/project_1.sim/sim_1/behav/xsim/glbl.v\n// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n parameter GRES_WIDTH = 10000;\n parameter GRES_START = 10000;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n wire GRESTORE;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n reg GRESTORE_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (strong1, weak0) GSR = GSR_int;\n assign (strong1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\n initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n end\n\nendmodule\n`endif\n\n\n// Path: bram/bram12.v\n// bram behavior code (can't be synthesis)\r// 11 words\rmodule bram12 \r(\r CLK,\r WE,\r EN,\r Di,\r Do,\r A\r);\r\r input wire CLK;\r input wire [3:0] WE;\r input wire EN;\r input wire [31:0] Di;"
}
] |
output reg [31:0] Do;
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: stephen-kao/course-lab_3\n// Path: bram/bram11.v\n// bram behavior code (can't be synthesis)\r\n// 11 words\r\nmodule bram11 \r\n(\r\n CLK,\r\n WE,\r\n EN,\r\n Di,\r\n Do,\r\n A\r\n);\r\n\r\n input wire CLK;\r\n input wire [3:0] WE;\r\n input wire EN;\r\n input wire [31:0] Di;\r\n output wire [31:0] Do;\r\n input wire [11:0] A; \r\n\r\n // 11 words\r\n\treg [31:0] RAM [0:10];\r\n reg [11:0] r_A;\r\n\r\n always @(posedge CLK) begin\r\n r_A <= A;\r\n end\r\n\r\n assign Do = {32{EN}} & RAM[r_A>>2]; // read\r\n\r\n reg [31:0] Temp_D;\r\n always @(posedge CLK) begin\r\n if(EN) begin\r\n if(WE[0]) RAM[A>>2][ 7: 0] <= Di[ 7: 0];\r\n if(WE[1]) RAM[A>>2][15: 8] <= Di[15: 8];\r\n if(WE[2]) RAM[A>>2][23:16] <= Di[23:16];\r\n if(WE[3]) RAM[A>>2][31:24] <= Di[31:24];\r\n end\r\n end\r\n\r\nendmodule\r\n\n\n// Path: bram/bram12.v\n// bram behavior code (can't be synthesis)\r\n// 11 words\r\nmodule bram12 \r\n(\r\n CLK,\r\n WE,\r\n EN,\r\n Di,\r\n Do,\r\n A\r\n);\r\n\r\n input wire CLK;\r\n input wire [3:0] WE;\r\n input wire EN;\r\n input wire [31:0] Di;\r\n output reg [31:0] Do;\r\n input wire [11:0] A; \r\n\r\n // 11 words\r\n\treg [31:0] RAM[0:11];\r\n reg [11:0] r_A;\r\n\r\n always @(posedge CLK) begin\r\n r_A <= A;\r\n end\r\n\r\n assign Do = 32{EN} & RAM[r_A>>2]; // read\r\n\r\n reg [31:0] Temp_D;\r\n always @(posedge CLK) begin\r\n if(EN) begin\r\n\t if(WE[0]) RAM[A>>2][7:0] <= Di[7:0];\r\n if(WE[1]) RAM[A>>2][15:8] <= Di[15:8];\r\n if(WE[2]) RAM[A>>2][23:16] <= Di[23:16];\r\n if(WE[3]) RAM[A>>2][31:24] <= Di[31:24];\r\n end\r\n end\r\n\r\nendmodule\r\n\n\n// Path: fir/rtl/fir.v\nmodule fir \n#( parameter pADDR_WIDTH = 12,\n parameter pDATA_WIDTH = 32,\n parameter Tape_Num = 11\n)\n(\n // System clock and Reset\n input wire axis_clk,\n input wire axis_rst_n,\n // AXI-Lite Protocal\n // write\n input wire [pADDR_WIDTH-1:0] awaddr,\n input wire awvalid,\n output reg awready,\n input wire [pDATA_WIDTH-1:0] wdata,\n input wire wvalid,\n output reg wready,\n // read\n input wire [pADDR_WIDTH-1:0] araddr,\n input wire arvalid,\n output reg arready,\n output reg [pDATA_WIDTH-1:0] rdata, \n output reg rvalid,\n input wire rready,\n // AXI-Stream Protocal\n // data in\n input wire ss_tvalid, \n input wire [pDATA_WIDTH-1:0] ss_tdata, \n input wire ss_tlast, \n output reg ss_tready, \n // data out\n input wire sm_tready, \n output reg sm_tvalid, \n output reg [pDATA_WIDTH-1:0] sm_tdata, \n output reg sm_tlast, \n // bram for tap RAM (store coefficient)\n output reg [3:0] tap_WE,\n output reg tap_EN,\n output reg [pDATA_WIDTH-1:0] tap_Di,\n output reg [pADDR_WIDTH-1:0] tap_A,\n input wire [pDATA_WIDTH-1:0] tap_Do,\n // bram for data RAM (store data?)\n output reg [3:0] data_WE,\n output reg data_EN,\n output reg [pDATA_WIDTH-1:0] data_Di,\n output reg [pADDR_WIDTH-1:0] data_A,\n input wire [pDATA_WIDTH-1:0] data_Do\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// LOCAL PARAMETER DECLARATION\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap signal\nreg ap_idle;\nreg ap_done;\nreg ap_start;\nreg next_ap_idle;\nreg next_ap_done;\nreg next_ap_start;\n// fsm\nreg [1:0] state;\nreg [1:0] next_state;\nreg finish;\n// counter\nreg [4:0] next_cnt;\nreg [4:0] cnt;\n// coefficient buffer and data buffer\nreg signed [pDATA_WIDTH-1:0] coeff [0:Tape_Num-1];\nreg signed [pDATA_WIDTH-1:0] data [0:Tape_Num-1];\ninteger i,j;\n// fir design\nwire [pDATA_WIDTH-1:0] temp_sum;\nwire [pDATA_WIDTH-1:0] cur_sum;\nreg [pDATA_WIDTH-1:0] prev_sum;\nreg [pDATA_WIDTH-1:0] cur_coef;\nreg [pDATA_WIDTH-1:0] cur_data;\n// fsm state\nlocalparam IDLE = 'd0;\nlocalparam LOAD = 'd1;\nlocalparam WORK = 'd2;\nlocalparam DONE = 'd3;\n// input buffer\nwire [pADDR_WIDTH-1:0] awaddr_d; \nwire awvalid_d; \nwire [pDATA_WIDTH-1:0] wdata_d; \nwire wvalid_d; \nwire [pADDR_WIDTH-1:0] araddr_d; \nwire arvalid_d; \nwire rready_d; \nwire ss_tvalid_d;\nwire [pDATA_WIDTH-1:0] ss_tdata_d; \nwire ss_tlast_d; \nwire sm_tready_d;\nwire [pDATA_WIDTH-1:0] tap_Do_d; \nwire [pDATA_WIDTH-1:0] data_Do_d; \n// counter\nreg [3:0] tap_addr_cnt;\nreg [3:0] load_addr_cnt;\nreg [9:0] data_num_cnt;\nreg [3:0] flag;\nreg [3:0] work_addr_cnt;\nreg [3:0] next_tap_addr_cnt;\nreg [3:0] next_load_addr_cnt;\nreg [9:0] next_data_num_cnt;\nreg [3:0] next_flag;\nreg [3:0] next_work_addr_cnt;\n\ninput_buffer \n#(\n .pADDR_WIDTH (pADDR_WIDTH),\n .pDATA_WIDTH (pDATA_WIDTH)\n) input_buf (\n .axis_clk (axis_clk),\n //////////////////////////////////////////////////////////////////////////////////\n // INPUT\n //////////////////////////////////////////////////////////////////////////////////\n // AXI_Lite protocal\n .awaddr (awaddr),\n .awvalid (awvalid),\n .wdata (wdata),\n .wvalid (wvalid),\n .araddr (araddr),\n .arvalid (arvalid),\n .rready (rready),\n // AXI_Stream protocal\n .ss_tvalid (ss_tvalid),\n .ss_tdata (ss_tdata),\n .ss_tlast (ss_tlast),\n .sm_tready (sm_tready),\n // tap sram\n .tap_Do (tap_Do),\n // data sram\n .data_Do (data_Do),\n //////////////////////////////////////////////////////////////////////////////////\n // OUTPUT\n //////////////////////////////////////////////////////////////////////////////////\n // AXI_Lite protocal\n .awaddr_d (awaddr_d),\n .awvalid_d (awvalid_d),\n .wdata_d (wdata_d),\n .wvalid_d (wvalid_d),\n .araddr_d (araddr_d),\n .arvalid_d (arvalid_d),\n .rready_d (rready_d),\n // AXI_Stream protocal\n .ss_tvalid_d (ss_tvalid_d),\n .ss_tdata_d (ss_tdata_d),\n .ss_tlast_d (ss_tlast_d),\n .sm_tready_d (sm_tready_d),\n // tap sram\n .tap_Do_d (tap_Do_d),\n // data sram\n .data_Do_d (data_Do_d)\n);\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Handshake Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nwire next_awready;\nwire next_wready;\nwire next_arready;\nwire next_rvalid;\n// AXI-Lite handshake, 1 for handshake successfully\nreg write_handshake;\nreg read_handshake;\n// rvalid trigger delay \nwire next_rvalid_trigger;\nreg rvalid_trigger;\nreg rvalid_trigger_d;\n\n// AXI-Lite handshake whether successfully or not\nalways @(*) begin\n write_handshake = (awvalid_d && awready) && (wvalid_d && wready);\n read_handshake = (arvalid_d && arready);\nend\n\n// AXI-Lite handshake control\n// write\nassign next_awready = awvalid_d;\nassign next_wready = wvalid_d;\n// read\nassign next_arready = arvalid_d;\nassign next_rvalid = (rvalid) ? 1'b0 : (~rvalid && ~arvalid_d) ? 1'b0 : (rvalid_trigger_d) ? 1'b1 : 1'b0;\nassign next_rvalid_trigger = ((tap_EN == 1'b1 && tap_WE == 'd0) && arvalid_d) | (state==DONE);\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n rvalid_trigger <= 'd0;\n rvalid_trigger_d <= 'd0;\n end else if(~arvalid_d) begin\n rvalid_trigger <= 'd0;\n rvalid_trigger_d <= 'd0;\n end else begin\n rvalid_trigger <= next_rvalid_trigger;\n rvalid_trigger_d <= rvalid_trigger;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n awready <= 'd0;\n wready <= 'd0;\n arready <= 'd0;\n rvalid <= 'd0;\n end else begin\n awready <= next_awready;\n wready <= next_wready;\n arready <= next_arready;\n rvalid <= next_rvalid;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Lite Protocal\n// Addr = 12'h00: AP_Signal (store in buffer)\n// Addr = 12'h10: data_length (store in buffer)\n// Addr = others: Coefficient (store in tap SRAM)\n//\n//////////////////////////////////////////////////////////////////////////////////\n// ap_signal\nreg [pDATA_WIDTH-1:0] ap_signal;\nwire [pDATA_WIDTH-1:0] next_ap_signal;\n// data_length\nreg [pDATA_WIDTH-1:0] data_length;\nwire [pDATA_WIDTH-1:0] next_data_length;\n// tap SRAM \nreg [pADDR_WIDTH-1:0] next_tap_A;\nreg next_tap_EN;\nreg [3:0] next_tap_WE;\nreg [pDATA_WIDTH-1:0] next_tap_Di;\n\n\n/////////////////////////////////////////\n// AP Signal\n/////////////////////////////////////////\nassign next_ap_signal = {{29{1'b0}}, next_ap_idle, next_ap_done, next_ap_start};\n// ap_start\nalways @(*) begin\n if(state==IDLE && awaddr == 12'h00 && awvalid && wvalid && wdata == 32'h0000_0001) begin\n // write ap_start for short pulse, deassert when the engine is not IDLE\n next_ap_start = 1;\n end else begin\n next_ap_start = 0;\n end\nend\n// ap_idle\nalways @(*) begin\n if(next_ap_start) begin\n next_ap_idle = 0;\n end else if(state == DONE) begin\n next_ap_idle = 1;\n end else begin\n next_ap_idle = ap_idle;\n end\nend\n// ap_done\nalways @(*) begin\n if(state == DONE) begin\n next_ap_done = 1;\n end else begin\n next_ap_done = ap_done;\n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ap_idle <= 1'b1;\n ap_done <= 1'b0;\n ap_start <= 1'b0;\n ap_signal <= {{29{1'b0}}, 1'b1, 1'b0, 1'b0}; // the three LSB order: {idle, done, start}\n end else begin\n ap_idle <= next_ap_idle;\n ap_done <= next_ap_done;\n ap_start <= next_ap_start;\n ap_signal <= next_ap_signal;\n end\nend\n\n/////////////////////////////////////////\n// Data Length buffer\n/////////////////////////////////////////\nassign next_data_length = (awaddr_d==12'h10 && write_handshake) ? wdata_d : data_length;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_length <= 'd0;\n end else begin\n data_length <= next_data_length;\n end\nend\n\n/////////////////////////////////////////\n// coefficient\n/////////////////////////////////////////\n// When Read addr = 0x00 should read out ap_signal\n// The others addr should read out the coefficient\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n rdata <= 'd0;\n end else if(araddr_d==12'h00) begin\n rdata <= ap_signal;\n end else begin\n rdata <= tap_Do_d;\n end\nend\n\n// Write / Read tap RAM from AXI-Lite protocal\nalways @(*) begin\n if(write_handshake && awaddr_d >= 12'h20) begin\n // WRITE\n if((awaddr_d != 12'h00) && (awaddr_d != 12'h10)) begin\n // Neither ap-signal nor data_length, write for coefficient\n next_tap_A = awaddr_d - 12'h20;\n next_tap_EN = 1'b1;\n next_tap_WE = 4'b1111;\n next_tap_Di = wdata_d;\n end else begin\n next_tap_A = 'd0;\n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end\n end else if (read_handshake && araddr_d >= 12'h20) begin\n // READ\n if((araddr_d != 12'h00) && (araddr_d != 12'h10)) begin\n // Neither ap-signal nor data_length, read for coefficient\n next_tap_A = araddr_d - 12'h20;\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end else if(araddr_d == 12'h00) begin\n next_tap_A = 'd0;\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end else begin\n next_tap_A = 'd0;\n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0;\n end\n end else if(state==WORK) begin\n next_tap_A = {tap_addr_cnt, {2'b0}};\n next_tap_EN = 1'b1;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end else begin\n next_tap_A = 'd0; \n next_tap_EN = 'd0;\n next_tap_WE = 'd0;\n next_tap_Di = 'd0; \n end\nend\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n tap_A <= 'd0;\n tap_EN <= 'd0;\n tap_WE <= 'd0;\n tap_Di <= 'd0; \n end else begin\n tap_A <= next_tap_A;\n tap_EN <= next_tap_EN;\n tap_WE <= next_tap_WE;\n tap_Di <= next_tap_Di; \n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// AXI-Stream Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nwire next_ss_tready;\nwire next_sm_tvalid;\nwire [pDATA_WIDTH-1:0] next_sm_tdata;\nwire next_sm_tlast;\n\nassign next_ss_tready = next_state==LOAD;\nassign next_sm_tvalid = ((state==WORK) && (tap_addr_cnt==4'd2) && (data_num_cnt != 'd1)) | (state==DONE && tap_addr_cnt >= 4'd3);\nassign next_sm_tdata = prev_sum;\nassign next_sm_tlast = (state==DONE && tap_addr_cnt >= 4'd3);\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n ss_tready <= 'd0;\n sm_tvalid <= 'd0;\n sm_tdata <= 'd0;\n sm_tlast <= 'd0;\n end else begin\n ss_tready <= next_ss_tready;\n sm_tvalid <= next_sm_tvalid;\n sm_tdata <= next_sm_tdata;\n sm_tlast <= next_sm_tlast;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Counter\n//\n//////////////////////////////////////////////////////////////////////////////////\n\n// tap_addr_cnt\nalways @(*) begin\n if(state==LOAD | (state==WORK && next_state==DONE)) begin\n next_tap_addr_cnt = 'd0;\n end else if(((state==IDLE)&&awvalid) | (state==WORK) | (state==DONE)) begin\n next_tap_addr_cnt = tap_addr_cnt + 1;\n end else begin\n next_tap_addr_cnt = 'd0;\n end\nend\n// load_addr_cnt\nalways @(*) begin\n if(state==LOAD) begin\n if(load_addr_cnt==4'd10) begin\n next_load_addr_cnt = 'd0;\n end else begin\n next_load_addr_cnt = load_addr_cnt + 1;\n end\n end else begin\n next_load_addr_cnt = load_addr_cnt;\n end\nend\n// data_num_cnt\nalways @(*) begin\n if(state==LOAD) begin\n next_data_num_cnt = data_num_cnt + 1;\n end else begin\n next_data_num_cnt = data_num_cnt;\n end\nend\n// flag\nalways @(*) begin\n if(data_num_cnt<=4'd11) begin\n next_flag = 'd0;\n end else begin\n next_flag = load_addr_cnt + 1;\n end\nend\n// work_addr_cnt\nalways @(*) begin\n if(state==LOAD && next_state==WORK) begin\n if(load_addr_cnt==4'd10) begin\n next_work_addr_cnt = 4'd0;\n end else begin\n next_work_addr_cnt = load_addr_cnt + 1;\n end\n end else if(state==WORK) begin\n if(work_addr_cnt==4'd10) begin\n next_work_addr_cnt = 'd0;\n end else begin\n next_work_addr_cnt = work_addr_cnt + 1;\n end\n end else begin\n next_work_addr_cnt = 'd0;\n end\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n tap_addr_cnt <= 'd0;\n load_addr_cnt <= 'd0;\n work_addr_cnt <= 'd0;\n flag <= 'd0;\n data_num_cnt <= 'd0;\n end else begin\n tap_addr_cnt <= next_tap_addr_cnt;\n load_addr_cnt <= next_load_addr_cnt;\n work_addr_cnt <= next_work_addr_cnt;\n flag <= next_flag;\n data_num_cnt <= next_data_num_cnt;\n end\nend\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Data SRAM Control\n//\n//////////////////////////////////////////////////////////////////////////////////\nreg [pADDR_WIDTH-1:0] next_data_A;\nreg next_data_EN;\nreg [3:0] next_data_WE;\nreg [pDATA_WIDTH-1:0] next_data_Di;\n\nalways @(*) begin\n case(state) \n IDLE: begin\n next_data_A = araddr_d - 12'h20;\n next_data_EN = 1'b1;\n next_data_WE = 4'b1111;\n next_data_Di = 'd0;\n end\n LOAD: begin\n next_data_A = {load_addr_cnt, {2'b0}}; // which addr we should write the newest data\n next_data_EN = 1'b1;\n next_data_WE = 4'b1111;\n next_data_Di = ss_tdata_d;\n end\n WORK: begin\n next_data_A = {work_addr_cnt, {2'b0}}; // which addr we need to compute\n next_data_EN = 1'b1;\n next_data_WE = 'd0;\n next_data_Di = 'd0;\n end \n default: begin\n next_data_A = 'd0;\n next_data_EN = 'd0;\n next_data_WE = 'd0;\n next_data_Di = 'd0;\n end\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n data_A <= 'd0;\n data_EN <= 'd0;\n data_WE <= 'd0;\n data_Di <= 'd0;\n end else begin\n data_A <= next_data_A;\n data_EN <= next_data_EN;\n data_WE <= next_data_WE;\n data_Di <= next_data_Di;\n end\nend\n\n//////////////////////////////////////////////////////////////////////////////////\n//\n// FSM\n//\n//////////////////////////////////////////////////////////////////////////////////\nalways@(posedge axis_clk) begin\n if(~axis_rst_n) begin\n finish <= 1'b0;\n end else if(state==LOAD && ss_tlast) begin\n finish <= 1'b1;\n end else begin\n finish <= finish;\n end\nend\nalways @(*) begin\n case(state)\n IDLE: next_state = (ap_start) ? LOAD: IDLE;\n LOAD: next_state = WORK;\n WORK: next_state = (tap_addr_cnt == Tape_Num-1) ? (finish) ? DONE : LOAD : WORK;\n DONE: next_state = DONE;\n default: next_state = IDLE;\n endcase\nend\n\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n state <= IDLE;\n end else begin\n state <= next_state;\n end\nend\n\n// //////////////////////////////////////////////////////////////////////////////////\n// //\n// // FIR computation\n// //\n// //////////////////////////////////////////////////////////////////////////////////\nassign temp_sum = cur_data * cur_coef;\nassign cur_sum = prev_sum + temp_sum;\nalways @(posedge axis_clk) begin\n if(~axis_rst_n) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state == WORK && tap_addr_cnt==4'd2) begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end else if(state==WORK | state==LOAD | state==DONE) begin\n prev_sum <= cur_sum;\n cur_coef <= tap_Do_d;\n cur_data <= data_Do_d;\n end else begin\n prev_sum <= 'd0;\n cur_coef <= 'd0;\n cur_data <= 'd0;\n end\nend\n\nendmodule\n\n// Path: fir/rtl/input_buffer.v\nmodule input_buffer\r\n#( parameter pADDR_WIDTH = 12,\r\n parameter pDATA_WIDTH = 32\r\n)\r\n(\r\n input axis_clk,\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // INPUT\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // AXI_Lite protocal\r\n input [pADDR_WIDTH-1:0] awaddr, \r\n input awvalid, \r\n input [pDATA_WIDTH-1:0] wdata, \r\n input wvalid, \r\n input [pADDR_WIDTH-1:0] araddr, \r\n input arvalid, \r\n input rready, \r\n // AXI_Stream protocal\r\n input ss_tvalid, \r\n input [pDATA_WIDTH-1:0] ss_tdata, \r\n input ss_tlast, \r\n input sm_tready, \r\n // tap sram\r\n input [pDATA_WIDTH-1:0] tap_Do, \r\n // data sram\r\n input [pDATA_WIDTH-1:0] data_Do,\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // OUTPUT\r\n //////////////////////////////////////////////////////////////////////////////////\r\n // AXI_Lite protocal\r\n output reg [pADDR_WIDTH-1:0] awaddr_d, \r\n output reg awvalid_d, \r\n output reg [pDATA_WIDTH-1:0] wdata_d, \r\n output reg wvalid_d, \r\n output reg [pADDR_WIDTH-1:0] araddr_d, \r\n output reg arvalid_d, \r\n output reg rready_d, \r\n // AXI_Stream protocal\r\n output reg ss_tvalid_d, \r\n output reg [pDATA_WIDTH-1:0] ss_tdata_d, \r\n output reg ss_tlast_d, \r\n output reg sm_tready_d, \r\n // tap sram\r\n output reg [pDATA_WIDTH-1:0] tap_Do_d, \r\n // data sram\r\n output reg [pDATA_WIDTH-1:0] data_Do_d\r\n);\r\n\r\nalways @(posedge axis_clk) begin\r\n // AXI_Lite protocal\r\n awaddr_d <= awaddr;\r\n awvalid_d <= awvalid;\r\n wdata_d <= wdata;\r\n wvalid_d <= wvalid;\r\n araddr_d <= araddr;\r\n arvalid_d <= arvalid;\r\n rready_d <= rready;\r\n // AXI_Stream protocal\r\n ss_tvalid_d <= ss_tvalid;\r\n ss_tdata_d <= ss_tdata;\r\n ss_tlast_d <= ss_tlast;\r\n sm_tready_d <= sm_tready;\r\n // tap sram\r\n tap_Do_d <= tap_Do;\r\n // data sram\r\n data_Do_d <= data_Do;\r\nend\r\n\r\nendmodule\n\n// Path: fir/tb/fir_tb.v\n`timescale 1ns / 1ps\r\n//////////////////////////////////////////////////////////////////////////////////\r\n// Company: \r\n// Engineer: \r\n// \r\n// Create Date: 08/20/2023 10:38:55 AM\r\n// Design Name: \r\n// Module Name: fir_tb\r\n// Project Name: \r\n// Target Devices: \r\n// Tool Versions: \r\n// Description: \r\n// \r\n// Dependencies: \r\n// \r\n// Revision:\r\n// Revision 0.01 - File Created\r\n// Additional Comments:\r\n// \r\n//////////////////////////////////////////////////////////////////////////////////\r\n`include \"/home/ubuntu/course-lab_3/bram/bram11.v\"\r\nmodule fir_tb\r\n#( parameter pADDR_WIDTH = 12,\r\n parameter pDATA_WIDTH = 32,\r\n parameter Tape_Num = 11,\r\n parameter Data_Num = 600\r\n)();\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// IO DECLARATION\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\n// System clk and rst\r\nreg axis_clk;\r\nreg axis_rst_n;\r\n// AXI4-Lite interface\r\n// Write\r\nreg [pADDR_WIDTH-1:0] awaddr;\r\nreg awvalid;\r\nwire awready;\r\nreg signed [pDATA_WIDTH-1:0] wdata;\r\nreg wvalid;\r\nwire wready;\r\n// Read\r\nreg [pADDR_WIDTH-1:0] araddr;\r\nreg arvalid;\r\nwire arready;\r\nwire signed [pDATA_WIDTH-1:0] rdata;\r\nwire rvalid;\r\nreg rready;\r\n// AXI4-Stream interface\r\nreg signed [pDATA_WIDTH-1:0] ss_tdata;\r\nreg ss_tvalid;\r\nreg ss_tlast;\r\nwire ss_tready;\r\nwire signed [pDATA_WIDTH-1:0] sm_tdata;\r\nwire sm_tvalid;\r\nwire sm_tlast;\r\nreg sm_tready;\r\n// bram for tap RAM (store coefficient)\r\nwire [3:0] tap_WE;\r\nwire tap_EN;\r\nwire [pDATA_WIDTH-1:0] tap_Di;\r\nwire [pADDR_WIDTH-1:0] tap_A;\r\nwire [pDATA_WIDTH-1:0] tap_Do;\r\n// bram for data RAM (store input data)\r\nwire [3:0] data_WE;\r\nwire data_EN;\r\nwire [pDATA_WIDTH-1:0] data_Di;\r\nwire [pADDR_WIDTH-1:0] data_A;\r\nwire [pDATA_WIDTH-1:0] data_Do;\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// FIR AND SRAM CIRCUIT \r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nfir fir_DUT (\r\n // System clk and rst\r\n .axis_clk (axis_clk),\r\n .axis_rst_n (axis_rst_n),\r\n // AXI4-Lite interface\r\n // Write\r\n .awaddr (awaddr),\r\n .awvalid (awvalid),\r\n .awready (awready),\r\n .wdata (wdata),\r\n .wvalid (wvalid),\r\n .wready (wready),\r\n // Read\r\n .araddr (araddr),\r\n .arvalid (arvalid),\r\n .arready (arready),\r\n .rdata (rdata),\r\n .rvalid (rvalid),\r\n .rready (rready),\r\n // AXI4-Stream interface\r\n .ss_tdata (ss_tdata),\r\n .ss_tvalid (ss_tvalid),\r\n .ss_tlast (ss_tlast),\r\n .ss_tready (ss_tready),\r\n .sm_tdata (sm_tdata),\r\n .sm_tvalid (sm_tvalid),\r\n .sm_tlast (sm_tlast),\r\n .sm_tready (sm_tready),\r\n // bram for tap RAM (store coefficient)\r\n .tap_WE (tap_WE),\r\n .tap_EN (tap_EN),\r\n .tap_Di (tap_Di),\r\n .tap_A (tap_A),\r\n .tap_Do (tap_Do),\r\n // bram for data RAM (store input data)\r\n .data_WE (data_WE),\r\n .data_EN (data_EN),\r\n .data_Di (data_Di),\r\n .data_A (data_A),\r\n .data_Do (data_Do) \r\n);\r\n\r\n// RAM for tap\r\nbram11 tap_RAM (\r\n .CLK (axis_clk),\r\n .WE (tap_WE),\r\n .EN (tap_EN),\r\n .Di (tap_Di),\r\n .A (tap_A),\r\n .Do (tap_Do)\r\n);\r\n\r\n// RAM for data: choose bram11 or bram12\r\nbram11 data_RAM(\r\n .CLK (axis_clk),\r\n .WE (data_WE),\r\n .EN (data_EN),\r\n .Di (data_Di),\r\n .A (data_A),\r\n .Do (data_Do)\r\n);\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// DUMP FILE\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninitial begin\r\n $dumpfile(\"fir.vcd\");\r\n $dumpvars();\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// CLOCK AND RESET\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninitial begin\r\n axis_clk = 0;\r\n forever begin\r\n #5 axis_clk = (~axis_clk);\r\n end\r\nend\r\n\r\ninitial begin\r\n axis_rst_n = 0;\r\n @(posedge axis_clk); @(posedge axis_clk);\r\n axis_rst_n = 1;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// LOAD THE INPUT AND GOLDEN DATA\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nreg signed [pDATA_WIDTH-1:0] Din_list [0:Data_Num-1];\r\nreg signed [pDATA_WIDTH-1:0] golden_list [0:Data_Num-1];\r\nreg [31:0] data_length;\r\n\r\ninteger Din, golden, input_data, golden_data, m;\r\n\r\ninitial begin\r\n data_length = 0;\r\n Din = $fopen(\"/home/ubuntu/course-lab_3/fir/samples_triangular_wave.dat\",\"r\");\r\n golden = $fopen(\"/home/ubuntu/course-lab_3/fir/out_gold.dat\",\"r\");\r\n for (m=0; m<Data_Num; m=m+1) begin\r\n input_data = $fscanf(Din,\"%d\", Din_list[m]);\r\n golden_data = $fscanf(golden,\"%d\", golden_list[m]);\r\n data_length = data_length + 1;\r\n end\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// SIMULATION\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninteger i;\r\ninitial begin\r\n $display(\"------------Start simulation-----------\");\r\n ss_tvalid = 0;\r\n $display(\"----Start the data input(AXI-Stream)----\");\r\n // send data into FIR design\r\n wait(axis_rst_n);\r\n for(i=0; i<(data_length-1); i=i+1) begin\r\n ss_tlast = 0; ss(Din_list[i]);\r\n end\r\n\r\n config_read_check(12'h00, 32'h00, 32'h0000_000f); // check idle = 0\r\n ss_tlast = 1; ss(Din_list[(Data_Num-1)]);\r\n $display(\"------End the data input(AXI-Stream)------\");\r\nend\r\n\r\ninteger k;\r\nreg error;\r\nreg error_coef;\r\nreg status_error;\r\ninitial begin\r\n error = 0; status_error = 0;\r\n sm_tready = 1;\r\n wait (sm_tvalid);\r\n for(k=0; k<data_length; k=k+1) begin\r\n sm(golden_list[k],k);\r\n end\r\n $display(\"check\");\r\n config_read_check(12'h00, 32'h02, 32'h0000_0002); // check ap_done = 1 (0x00 [bit 1])\r\n config_read_check(12'h00, 32'h04, 32'h0000_0004); // check ap_idle = 1 (0x00 [bit 2])\r\n if (error == 0 & error_coef == 0) begin\r\n $display(\"---------------------------------------------\");\r\n $display(\"-----------Congratulations! Pass-------------\");\r\n end\r\n else begin\r\n $display(\"--------Simulation Failed---------\");\r\n end\r\n $finish;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// Prevent hang, set up the maximum cycle number\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\ninteger timeout = (1000000);\r\ninitial begin\r\n while(timeout > 0) begin\r\n @(posedge axis_clk);\r\n timeout = timeout - 1;\r\n end\r\n $display($time, \"Simualtion Hang ....\");\r\n $finish;\r\nend\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// Coefficient \r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\nreg signed [31:0] coef[0:10]; // fill in coef \r\ninitial begin\r\n coef[0] = 32'd0;\r\n coef[1] = -32'd10;\r\n coef[2] = -32'd9;\r\n coef[3] = 32'd23;\r\n coef[4] = 32'd56;\r\n coef[5] = 32'd63;\r\n coef[6] = 32'd56;\r\n coef[7] = 32'd23;\r\n coef[8] = -32'd9;\r\n coef[9] = -32'd10;\r\n coef[10] = 32'd0;\r\nend\r\n\r\ninitial begin\r\n error_coef = 0;\r\n $display(\"----Start the coefficient input(AXI-lite)----\");\r\n awvalid <= 0;\r\n wvalid <= 0;\r\n wait(axis_rst_n);\r\n config_write(12'h10, data_length);\r\n for(k=0; k< Tape_Num; k=k+1) begin\r\n config_write(12'h20+4*k, coef[k]);\r\n end\r\n awvalid <= 0; wvalid <= 0;\r\n // read-back and check\r\n $display(\" Check Coefficient ...\");\r\n for(k=0; k < Tape_Num; k=k+1) begin\r\n config_read_check(12'h20+4*k, coef[k], 32'hffffffff);\r\n end\r\n arvalid <= 0;\r\n $display(\" Tape programming done ...\");\r\n $display(\" Start FIR\");\r\n @(posedge axis_clk) config_write(12'h00, 32'h0000_0001); // ap_start = 1\r\n $display(\"----End the coefficient input(AXI-lite)----\");\r\nend\r\n\r\ntask config_write;\r\n input [11:0] addr;\r\n input [31:0] data;\r\n begin\r\n awvalid <= 0; wvalid <= 0;\r\n @(posedge axis_clk);\r\n awvalid <= 1; awaddr <= addr;\r\n wvalid <= 1; wdata <= data;\r\n @(posedge axis_clk);\r\n @(negedge axis_clk);\r\n while (!wready) @(posedge axis_clk);\r\n awvalid <= 0; wvalid <= 0;\r\n end\r\nendtask\r\n\r\ntask config_read_check;\r\n input [11:0] addr;\r\n input signed [31:0] exp_data;\r\n input [31:0] mask;\r\n begin\r\n arvalid <= 0;\r\n @(posedge axis_clk);\r\n arvalid <= 1; araddr <= addr;\r\n rready <= 1;\r\n @(posedge axis_clk);\r\n wait(rvalid);\r\n @(negedge axis_clk);\r\n if( (rdata & mask) != (exp_data & mask)) begin\r\n $display(\"ERROR: exp = %d, rdata = %d\", exp_data, rdata);\r\n error_coef <= 1;\r\n end else begin\r\n $display(\"OK: exp = %d, rdata = %d\", exp_data, rdata);\r\n end\r\n end\r\nendtask\r\n\r\n//////////////////////////////////////////////////////////////////////////////////\r\n//\r\n// AXI4-STREAM INTERFACE, WRITE DATA IN OR READ DATA OUT FROM FIR DESIGN\r\n//\r\n//////////////////////////////////////////////////////////////////////////////////\r\n\r\ntask ss;\r\n input signed [31:0] in1;\r\n begin\r\n ss_tvalid <= 1;\r\n ss_tdata <= in1;\r\n @(posedge axis_clk);\r\n while (!ss_tready) begin\r\n @(posedge axis_clk);\r\n end\r\n end\r\nendtask\r\n\r\ntask sm;\r\n input signed [31:0] in2; // golden data\r\n input [31:0] pcnt; // pattern count\r\n begin\r\n sm_tready <= 1;\r\n @(posedge axis_clk) \r\n wait(sm_tvalid);\r\n while(!sm_tvalid) @(posedge axis_clk);\r\n if (sm_tdata != in2) begin\r\n $display(\"[ERROR] [Pattern %d] Golden answer: %d, Your answer: %d\", pcnt, in2, sm_tdata);\r\n error <= 1;\r\n end\r\n else begin\r\n $display(\"[PASS] [Pattern %d] Golden answer: %d, Your answer: %d\", pcnt, in2, sm_tdata);\r\n end\r\n @(posedge axis_clk);\r\n end\r\nendtask\r\n\r\nendmodule\r\n\n\n// Path: project_1/project_1.sim/sim_1/behav/xsim/glbl.v\n// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n parameter GRES_WIDTH = 10000;\n parameter GRES_START = 10000;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n wire GRESTORE;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n reg GRESTORE_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (strong1, weak0) GSR = GSR_int;\n assign (strong1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\n initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n end\n\nendmodule\n`endif\n\n\n// Path: fir/rtl/fir_v1.v\nmodule fir #( parameter pADDR_WIDTH = 12, parameter pDATA_WIDTH = 32, parameter Tape_Num = 11)( // System clock and Reset input wire axis_clk, input wire axis_rst_n, // AXI-Lite Protocal // write input wire [pADDR_WIDTH-1:0] awaddr, input wire awvalid, output wire awready, input wire [pDATA_WIDTH-1:0] wdata, input wire wvalid, output wire wready, // read input wire [pADDR_WIDTH-1:0] araddr, input wire arvalid, output wire arready, output wire [pDATA_WIDTH-1:0] rdata, output wire rvalid, input wire rready, // AXI-Stream Protocal // data in input wire ss_tvalid, input wire [pDATA_WIDTH-1:0] ss_tdata, input wire ss_tlast, output wire ss_tready, // data out input wire sm_tready, output wire sm_tvalid, output wire [pDATA_WIDTH-1:0] sm_tdata, output wire sm_tlast, // bram for tap RAM (store coefficient) output reg [3:0] tap_WE, output reg tap_EN, output reg [pDATA_WIDTH-1:0] tap_Di, output reg [pADDR_WIDTH-1:0] tap_A, input wire [pDATA_WIDTH-1:0] tap_Do, // bram for data RAM (store data?) output reg [3:0] data_WE, output reg data_EN, output reg [pDATA_WIDTH-1:0] data_Di, output reg [pADDR_WIDTH-1:0] data_A, input wire [pDATA_WIDTH-1:0] data_Do);////////////////////////////////////////////////////////////////////////////////////// LOCAL PARAMETER DECLARATION////////////////////////////////////////////////////////////////////////////////////// ap signalwire [pDATA_WIDTH-1:0] ap_signal; // ap_signal = {29{1'b0}, ap_idle, ap_done, ap_start}reg ap_idle;reg ap_done;reg ap_start;reg next_ap_idle;reg next_ap_done;reg next_ap_start;// data lengthreg [pDATA_WIDTH-1:0] data_length;// fsmreg [1:0] state;reg [1:0] next_state;reg finish;// counterreg [4:0] next_cnt;reg [4:0] cnt;// coefficient buffer and data bufferreg signed [pDATA_WIDTH-1:0] coeff [0:Tape_Num-1];reg signed [pDATA_WIDTH-1:0] data [0:Tape_Num-1];integer i,j;// fir designwire [pDATA_WIDTH-1:0] temp_sum;wire [pDATA_WIDTH-1:0] cur_sum;reg [pDATA_WIDTH-1:0] prev_sum;reg [pDATA_WIDTH-1:0] cur_coef;reg [pDATA_WIDTH-1:0] cur_data;// fsm statelocalparam IDLE = 'd0;localparam LOAD = 'd1;localparam WORK = 'd2;localparam DONE = 'd3;////////////////////////////////////////////////////////////////////////////////////// AXI-Lite Handshake////////////////////////////////////////////////////////////////////////////////////assign awready = awvalid;assign wready = wvalid;assign arready = arvalid;assign rvalid = rready;////////////////////////////////////////////////////////////////////////////////////// AXI-Stream Control////////////////////////////////////////////////////////////////////////////////////assign ss_tready = state==LOAD;assign sm_tvalid = (state==LOAD && cnt==4'd11) | state==DONE;assign sm_tdata = prev_sum;assign sm_tlast = state==DONE;////////////////////////////////////////////////////////////////////////////////////// AP_SIGNAL////////////////////////////////////////////////////////////////////////////////////assign ap_signal = {{29{1'b0}}, ap_idle, ap_done, ap_start};// ap_startalways @(*) begin if(state==IDLE && awaddr == 12'h00 && awvalid && wvalid && wdata == 32'h0000_0001) begin // write ap_start for short pulse, deassert when the engine is not IDLE next_ap_start = 1; end else begin next_ap_start = 0; endend// ap_idlealways @(*) begin if(next_ap_start) begin next_ap_idle = 0; end else if(state == DONE) begin next_ap_idle = 1; end else begin next_ap_idle = ap_idle; endend// ap_donealways @(*) begin if(state == DONE) begin next_ap_done = 1; end else begin next_ap_done = ap_done; endendalways @(posedge axis_clk) begin if(~axis_rst_n) begin ap_idle <= 1'b1; ap_done <= 1'b0; ap_start <= 1'b0; end else begin ap_idle <= next_ap_idle; ap_done <= next_ap_done; ap_start <= next_ap_start; endend////////////////////////////////////////////////////////////////////////////////////// Coefficient from AXI-Lite and store into coeff buffer and tap RAM////////////////////////////////////////////////////////////////////////////////////// When Read addr = 0x00 should read out ap_signal// The others addr should read out the coefficientassign rdata = (araddr == 12'h00) ? ap_signal : tap_Do;// Write / Read tap RAM from AXI-Lite protocalalways @(*) begin if(awvalid) begin // write if((awaddr != 12'h00) && (awaddr != 12'h10)) begin tap_A = awaddr - 12'h20; tap_EN = 1'b1; tap_WE = 4'b1111; tap_Di = wdata; end else begin tap_A = 'd0; tap_EN = 'd0; tap_WE = 'd0; tap_Di = 'd0; end end else if (arvalid) begin if(araddr != 12'h00 && araddr != 12'h10) begin tap_A = araddr - 12'h20; tap_EN = 1'b1; tap_WE = 'd0; tap_Di = 'd0; end else begin tap_A = 'd0; tap_EN = 'd0; tap_WE = 'd0; tap_Di = 'd0; end end else begin tap_A = 'd0; tap_EN = 'd0; tap_WE = 'd0; tap_Di = 'd0; endend////////////////////////////////////////////////////////////////////////////////////// Data Length from AXI-Lite and store into data_length buffer////////////////////////////////////////////////////////////////////////////////////always @(posedge axis_clk) begin if(~axis_rst_n) begin data_length <= 'd0;"
}
] |
end else if(awaddr == 12'h10) begin
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: suxijie/uart\n// Path: uart_rx.v\n`timescale 1ns / 1ps\nmodule uart_rx(\n\tinput \t\t\t clk_i , \t\n\tinput \t\t\t rst_n , \t\n\tinput uart_rx_i , \n\toutput [7:0] uart_rx_data_o, \n\toutput uart_rx_done\n);\nparameter [14:0] BAUD_DIV = 15'd867;//波特率时钟，115200bps，100Mhz/115200 - 1'b1=867\nparameter [14:0] STOP_DIV = 15'd830;\nparameter [9:0] BAUD_DIV_SAMP = 10'd59;//(BAUD_DIV/14 - 1'b1) 14次采样滤波去毛刺\n//reg define\nreg uart_rx_1 = 1'b1;\nreg uart_rx_2 = 1'b1;\nreg uart_rx_3 = 1'b1;\nreg [3:0] bit_cnt = 4'b0; \nreg [5:0] cap_cnt = 6'b0; \nreg start_div = 1'b0;\nreg start_work = 1'b0;\nreg rx_work = 1'b0;\nreg stop_work = 1'b0;\nreg data_stable = 1'b1;\nreg data_cap = 1'b1;\nreg [14:0] baud_div = 15'd0; //波特率设置计数器\nreg [6:0] samp_cnt = 7'b0 ; \nreg [6:0] rx_tmp = 7'd30; \nreg [7:0] uart_rx_data =8'b1111_1111 ;\nreg [7:0] rx_data_o =8'b1111_1111 ;\nwire bps_en = (baud_div == BAUD_DIV);\nwire stop_en = (baud_div == STOP_DIV);\nwire samp_en = (samp_cnt == BAUD_DIV_SAMP);\nwire edge_p = uart_rx_2 && !uart_rx_3;\nwire edge_n = !uart_rx_2 && uart_rx_3;\nassign uart_rx_data_o = rx_data_o;\nassign uart_rx_done = stop_work;\n\n//波特率时钟\nalways@(posedge clk_i)begin\n\tif( !rst_n)\n\t\tbaud_div <= 15'd0;\n\telse if( start_div&&baud_div < BAUD_DIV)\n\t\tbaud_div <= baud_div + 1'b1;\n\telse\n\t\tbaud_div <= 15'd0;\nend\n\n//一个波特率时钟周期中有14个采样时钟周期\nalways@(posedge clk_i)begin\n if(!rst_n||bps_en)\n samp_cnt <= 'd0; \n\telse if(start_div&&samp_cnt < BAUD_DIV_SAMP)\n\t\tsamp_cnt <= samp_cnt + 1'b1;\n\telse\n\t\tsamp_cnt <= 'd0;\nend\n\n//消除亚稳态\nalways@(posedge clk_i)begin\n\tif( !rst_n)begin\n\t\tuart_rx_1 <=1'b1;\n\t\tuart_rx_2 <=1'b1;\n\t\tuart_rx_3 <=1'b1;\n\t\tdata_stable<=1'b1;\n\tend\n\telse begin\n\t\tuart_rx_1<=uart_rx_i;\n\t\tuart_rx_2<=uart_rx_1;\n\t\tuart_rx_3<=uart_rx_2;\n\t\tdata_stable<= edge_n ? 1'd0 : edge_p ? 1'd1 :data_stable;\n\tend\nend\n\n//14次滤波采样\nalways@(posedge clk_i)begin\n if(!rst_n)begin\n cap_cnt <= 'd0;\n data_cap<= 'd1;\n rx_tmp <= 7'd30;\n end\n\telse if(samp_en)begin\n\t\tcap_cnt <= cap_cnt + 1'b1;\n\t\trx_tmp <= data_stable ? rx_tmp + 1'b1 : rx_tmp - 1'b1;\n\tend\n\telse if(bps_en) begin //每次波特率时钟使能，重新设置 rx_tmp 初值为 8\n\t\trx_tmp <= 7'd30;\n\t\tcap_cnt <= 4'd0;\n\tend\n\tif(cap_cnt==6'd11)begin\n\t data_cap <= (rx_tmp > 7'd30) ? 1 : 0;\n\tend\t\nend\n\n\n always@(posedge clk_i)begin\n \tif(!rst_n)begin\n\t\tbit_cnt <=4'd0;\n\t\tuart_rx_data<=8'b1111_1111 ;\n\tend\n\telse if(bps_en)begin\n uart_rx_data<={uart_rx_data[6:0],data_cap};\n\t bit_cnt <=bit_cnt+4'd1;\n\tend\n\telse if(stop_work&&stop_en)begin\n\t uart_rx_data<=8'b1111_1111 ;\n\t bit_cnt <=4'd0;\n\tend\n\telse\n\t\tbit_cnt <=bit_cnt;\nend \n \nalways@(posedge clk_i)begin\n\tif( !rst_n)begin\n\t\tstart_div <=1'b0;\n\t\tstart_work <=1'b0;\n\t\trx_work <=1'b0;\n\t\tstop_work <=1'b0;\n\t\trx_data_o <=8'b1111_1111 ;\n\tend\n else if(!start_div&&!data_stable)begin\n start_work <= 1'd1;\n start_div <= 1'd1;\n end\n else if(start_work&&bps_en)begin\n start_work <= 1'd0;\n rx_work <= 1'd1;\n end\n else if(rx_work&&bit_cnt==4'd9) begin\n rx_data_o <= uart_rx_data;\n\t rx_work <= 1'd0;\n\t\tstop_work <= 1'd1;\n end\n if(stop_work&&stop_en)begin\n stop_work <= 1'd0;\n start_div <= 1'd0;\n end \nend\nendmodule \n \n\n\n// Path: uart_tx.v\n`timescale 1ns / 1ps\nmodule uart_tx(\n\tinput \t\tclk_i ,\n\tinput \t rst_n ,\t \t\n\tinput [7:0] uart_tx_data_i, //待发送数据\n\tinput \t\tuart_tx_en_i , //发送发送使能信号\n\toutput \t\tuart_tx_o , \t\n\toutput \t\tuart_tx_busy\n);\nparameter [14:0] BAUD_DIV = 15'd867;//波特率时钟，115200bps，100Mhz/115200 - 1'b1=867 \nparameter [14:0] STOP_DIV = 15'd866; \n//reg define\nreg bps_start_en = 1'b0 ;\nreg uart_tx = 1'b1 ;\nreg [3:0] bit_cnt = 4'd0 ; \nreg [3:0] bit = 4'd0 ; \nreg [12:0] baud_div = 13'd0;\nwire bps_en = (baud_div == BAUD_DIV);\nwire stop_en = (bit_cnt==4'd9)&&(baud_div == STOP_DIV) ? 1'b1 : 1'b0;\nassign uart_tx_busy = bps_start_en;\nassign uart_tx_o = uart_tx;\n\nalways@(posedge clk_i)begin\n if(!rst_n)\n baud_div <= 13'd0;\n\telse if(bps_start_en && baud_div < BAUD_DIV)\n\t\tbaud_div <= baud_div + 1'b1; \n\telse\n\t\tbaud_div <= 13'd0;\nend\n\nalways@(posedge clk_i)begin\n if(!rst_n)\n bit_cnt <= 4'd0;\n\telse if(bps_en)\n\t\tbit_cnt <=bit_cnt+4'd1;\n\telse\n\t\tbit_cnt <=bit_cnt;\n\tif(bit_cnt==4'd9&&bps_en)\n\t bit_cnt <=4'd0;\nend\n\nalways@(posedge clk_i)begin\n if(!rst_n)begin\n bps_start_en <= 1'b0;\n uart_tx <= 1'b1;\n\t bit <= 4'b0;\n end\n else if(uart_tx_en_i) \n bps_start_en <= 1'b1;\n\telse if(bps_start_en&&bps_en&&(bit_cnt<4'd9)) begin\n\t bit <=4'd7 - bit_cnt;\n\t if(bit_cnt==4'd0) uart_tx <=1'b0;\n\t if((bit_cnt>=4'd1)&&(bit_cnt<=4'd8)) uart_tx<=uart_tx_data_i[bit];\n\tend \n if(bit_cnt==4'd9&&stop_en)begin\n\t uart_tx <= 1'b1;\n\t bit <= 4'b0;\n\t bps_start_en <= 1'b0;\n\tend\nend\nendmodule\n\n\n// Path: uart_top.v\n`timescale 1ns / 1psmodule uart_top(\tinput clk_i ,\tinput rst_n ,\tinput uart_rx_i,\toutput uart_tx_o);wire [7:0] uart_rx_data_o;wire uart_rx_done;wire uart_tx_busy;uart_rx u_uart_rx(\t.clk_i \t\t (clk_i ), \t.rst_n \t\t (rst_n ), \t .uart_rx_i\t \t (uart_rx_i), .uart_rx_data_o \t(uart_rx_data_o), .uart_rx_done (uart_rx_done));uart_tx u_uart_tx(\t.clk_i\t\t\t\t (clk_i ),"
}
] |
.rst_n (rst_n ),
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: suxijie/uart\n// Path: uart_rx.v\n`timescale 1ns / 1ps\nmodule uart_rx(\n\tinput \t\t\t clk_i , \t\n\tinput \t\t\t rst_n , \t\n\tinput uart_rx_i , \n\toutput [7:0] uart_rx_data_o, \n\toutput uart_rx_done\n);\nparameter [14:0] BAUD_DIV = 15'd867;//波特率时钟，115200bps，100Mhz/115200 - 1'b1=867\nparameter [14:0] STOP_DIV = 15'd830;\nparameter [9:0] BAUD_DIV_SAMP = 10'd59;//(BAUD_DIV/14 - 1'b1) 14次采样滤波去毛刺\n//reg define\nreg uart_rx_1 = 1'b1;\nreg uart_rx_2 = 1'b1;\nreg uart_rx_3 = 1'b1;\nreg [3:0] bit_cnt = 4'b0; \nreg [5:0] cap_cnt = 6'b0; \nreg start_div = 1'b0;\nreg start_work = 1'b0;\nreg rx_work = 1'b0;\nreg stop_work = 1'b0;\nreg data_stable = 1'b1;\nreg data_cap = 1'b1;\nreg [14:0] baud_div = 15'd0; //波特率设置计数器\nreg [6:0] samp_cnt = 7'b0 ; \nreg [6:0] rx_tmp = 7'd30; \nreg [7:0] uart_rx_data =8'b1111_1111 ;\nreg [7:0] rx_data_o =8'b1111_1111 ;\nwire bps_en = (baud_div == BAUD_DIV);\nwire stop_en = (baud_div == STOP_DIV);\nwire samp_en = (samp_cnt == BAUD_DIV_SAMP);\nwire edge_p = uart_rx_2 && !uart_rx_3;\nwire edge_n = !uart_rx_2 && uart_rx_3;\nassign uart_rx_data_o = rx_data_o;\nassign uart_rx_done = stop_work;\n\n//波特率时钟\nalways@(posedge clk_i)begin\n\tif( !rst_n)\n\t\tbaud_div <= 15'd0;\n\telse if( start_div&&baud_div < BAUD_DIV)\n\t\tbaud_div <= baud_div + 1'b1;\n\telse\n\t\tbaud_div <= 15'd0;\nend\n\n//一个波特率时钟周期中有14个采样时钟周期\nalways@(posedge clk_i)begin\n if(!rst_n||bps_en)\n samp_cnt <= 'd0; \n\telse if(start_div&&samp_cnt < BAUD_DIV_SAMP)\n\t\tsamp_cnt <= samp_cnt + 1'b1;\n\telse\n\t\tsamp_cnt <= 'd0;\nend\n\n//消除亚稳态\nalways@(posedge clk_i)begin\n\tif( !rst_n)begin\n\t\tuart_rx_1 <=1'b1;\n\t\tuart_rx_2 <=1'b1;\n\t\tuart_rx_3 <=1'b1;\n\t\tdata_stable<=1'b1;\n\tend\n\telse begin\n\t\tuart_rx_1<=uart_rx_i;\n\t\tuart_rx_2<=uart_rx_1;\n\t\tuart_rx_3<=uart_rx_2;\n\t\tdata_stable<= edge_n ? 1'd0 : edge_p ? 1'd1 :data_stable;\n\tend\nend\n\n//14次滤波采样\nalways@(posedge clk_i)begin\n if(!rst_n)begin\n cap_cnt <= 'd0;\n data_cap<= 'd1;\n rx_tmp <= 7'd30;\n end\n\telse if(samp_en)begin\n\t\tcap_cnt <= cap_cnt + 1'b1;\n\t\trx_tmp <= data_stable ? rx_tmp + 1'b1 : rx_tmp - 1'b1;\n\tend\n\telse if(bps_en) begin //每次波特率时钟使能，重新设置 rx_tmp 初值为 8\n\t\trx_tmp <= 7'd30;\n\t\tcap_cnt <= 4'd0;\n\tend\n\tif(cap_cnt==6'd11)begin\n\t data_cap <= (rx_tmp > 7'd30) ? 1 : 0;\n\tend\t\nend\n\n\n always@(posedge clk_i)begin\n \tif(!rst_n)begin\n\t\tbit_cnt <=4'd0;\n\t\tuart_rx_data<=8'b1111_1111 ;\n\tend\n\telse if(bps_en)begin\n uart_rx_data<={uart_rx_data[6:0],data_cap};\n\t bit_cnt <=bit_cnt+4'd1;\n\tend\n\telse if(stop_work&&stop_en)begin\n\t uart_rx_data<=8'b1111_1111 ;\n\t bit_cnt <=4'd0;\n\tend\n\telse\n\t\tbit_cnt <=bit_cnt;\nend \n \nalways@(posedge clk_i)begin\n\tif( !rst_n)begin\n\t\tstart_div <=1'b0;\n\t\tstart_work <=1'b0;\n\t\trx_work <=1'b0;\n\t\tstop_work <=1'b0;\n\t\trx_data_o <=8'b1111_1111 ;\n\tend\n else if(!start_div&&!data_stable)begin\n start_work <= 1'd1;\n start_div <= 1'd1;\n end\n else if(start_work&&bps_en)begin\n start_work <= 1'd0;\n rx_work <= 1'd1;\n end\n else if(rx_work&&bit_cnt==4'd9) begin\n rx_data_o <= uart_rx_data;\n\t rx_work <= 1'd0;\n\t\tstop_work <= 1'd1;\n end\n if(stop_work&&stop_en)begin\n stop_work <= 1'd0;\n start_div <= 1'd0;\n end \nend\nendmodule \n \n\n\n// Path: uart_top.v\n`timescale 1ns / 1ps\nmodule uart_top(\n\tinput clk_i ,\n\tinput rst_n ,\n\tinput uart_rx_i,\n\toutput uart_tx_o\n);\n\nwire [7:0] uart_rx_data_o;\nwire uart_rx_done;\nwire uart_tx_busy;\n\n\nuart_rx u_uart_rx\n(\n\t.clk_i \t\t (clk_i ), \n\t.rst_n \t\t (rst_n ), \t\n .uart_rx_i\t \t (uart_rx_i), \n .uart_rx_data_o \t(uart_rx_data_o),\n .uart_rx_done (uart_rx_done)\n\n);\n\nuart_tx u_uart_tx\n(\n\t.clk_i\t\t\t\t (clk_i ), \t\n\t.rst_n \t\t (rst_n ), \n .uart_tx_data_i\t\t (uart_rx_data_o),\n .uart_tx_en_i\t\t (uart_rx_done), \n\t.uart_tx_o\t\t\t (uart_tx_o), \t\n .uart_tx_busy (uart_tx_busy)\n\n);\n\nendmodule\n\n\n// Path: uart_tx.v\n`timescale 1ns / 1psmodule uart_tx(\tinput \t\tclk_i ,\tinput \t rst_n ,\t \t\tinput [7:0] uart_tx_data_i, //待发送数据\tinput \t\tuart_tx_en_i , //发送发送使能信号\toutput \t\tuart_tx_o , \t\toutput \t\tuart_tx_busy);parameter [14:0] BAUD_DIV = 15'd867;//波特率时钟，115200bps，100Mhz/115200 - 1'b1=867 parameter [14:0] STOP_DIV = 15'd866; //reg define"
}
] |
reg bps_start_en = 1'b0 ;
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: kbashus/Bashus_ECE128_Lab7\n// Path: Clock_divider.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/24/2023 11:58:26 AM\n// Design Name: \n// Module Name: Clock_divider\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule Clock_divider(clock_in, clock_out);\n input clock_in;\n output reg clock_out;\n reg[2:0] counter = 3'b0;\n \n parameter DIVISOR = 100 / 25;\n \n always @(posedge clock_in)\n \n begin\n counter <= counter + 1'b1;\n if(counter>=(DIVISOR-1))\n counter <= 3'b0;\n clock_out <= (counter<DIVISOR/2) ? 1'b1:1'b0;\n end\n \nendmodule\n\n// Path: Clock_divider_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/24/2023 11:58:43 AM\n// Design Name: \n// Module Name: Clock_divider_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule Clock_divider_tb();\n reg clock_in;\n wire clock_out;\n \n Clock_divider uut (.clock_in(clock_in),\n .clock_out(clock_out));\n \n initial begin\n clock_in = 0;\n forever #10 clock_in = ~clock_in;\n end\n\nendmodule\n\n\n// Path: D_Flipflop_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:15:04 PM\n// Design Name: \n// Module Name: D_Flipflop_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule D_Flipflop_tb();\n\n reg d;\n reg rstn;\n reg clk;\n wire q;\n\n //D_ff_sync uut (.d(d), .rstn(rstn), .clk(clk), .q(q));\n D_ff_async uut (.d(d), .rstn(rstn), .clk(clk), .q(q));\n \n initial begin\n clk=0;\n forever #10 clk = ~clk; \n end \n \n initial begin \n rstn=1;\n d <= 0;\n #200;\n #22 d <=1; #22 rstn=0;\n d <= 1;\n #100;\n d <= 0;\n #100;\n d <= 1;\n end \n\nendmodule\n\n\n// Path: SR_Flipflop.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 01:46:11 PM\n// Design Name: \n// Module Name: SR_Flipflop\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Flipflop(clk, rstn, S, R, q, qbar);\n input clk;\n input rstn;\n input S;\n input R;\n output reg q;\n output reg qbar;\n\n \n always @(posedge clk) begin\n \n if (rstn) begin\n q=1'b0;\n qbar=1'b1;\n \n end else begin\n \n case({S,R})\n {1'b0,1'b0}: begin q=q;qbar=qbar; end\n {1'b0,1'b1}: begin q=1'b0;qbar=1'b1; end\n {1'b1,1'b0}: begin q=1'b1;qbar=1'b0; end\n {1'b1,1'b1}: begin q=1'b0; qbar=1'b0; end\n endcase\n \n end\n \nend\nendmodule\n\n\n// Path: SR_Flipflop_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 02:19:46 PM\n// Design Name: \n// Module Name: SR_Flipflop_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Flipflop_tb();\n reg clk;\n reg rstn;\n reg s;\n reg r;\n wire q;\n wire qbar;\n\n SR_Flipflop sff (.clk(clk), .rstn(rstn), .S(s), .R(r), .q(q), .qbar(qbar));\n \n initial begin\n \n s = 1'b0;\n r = 1'b0;\n rstn = 1;\n clk=1;\n \n #10\n rstn=0;\n s=1'b1;\n r=1'b0;\n \n #100\n rstn=0;\n s=1'b0;\n r=1'b1;\n \n #100\n rstn=0;\n s=1'b1;\n r=1'b1;\n \n #100\n rstn=0;\n s=1'b0;\n r=1'b0;\n \n #100\n rstn=1;\n s=1'b1;\n r=1'b0;\n \nend\nalways #25 clk <= ~clk;\n\nendmodule\n \n\n// Path: SR_Latch.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 01:46:11 PM\n// Design Name: \n// Module Name: SR_Latch\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Latch(S, R, Q, Qbar);\n input S;\n input R;\n output Q;\n output Qbar;\n \n nor N1(Q, R, Qbar);\n nor N2(Qbar, S, Q);\n\nendmodule\n\n\n// Path: SR_Latch_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 01:48:15 PM\n// Design Name: \n// Module Name: SR_Latch_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Latch_tb();\n reg r, s;\n wire q, qbar;\n \n SR_Latch UUT(.S(s), .R(r), .Q(q), .Qbar(qbar));\n \n initial\n begin\n r=0; s=0;\n #5 s=1;\n #5 s=0;\n #5 r=1;\n #5 r=0; s=1;\n #5 s=0; r=1;\n #5 r=0;\n #5 r=1; s=1;\n end\n \n initial begin\n $dumpfile(\"dump.vcd\"); // record waveform\n $dumpvars(1); //display signals in testbench\n end\nendmodule\n\n// Path: T_Flipflop.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:45:25 PM\n// Design Name: \n// Module Name: T_Flipflop\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule T_Flipflop(rst,enable,clk,t,q,notq);\n input t;\n input clk;\n input enable;\n input rst;\n output reg q;\n output notq;\n assign notq=~q;\n \n always@(posedge clk or negedge rst)\n begin\n if(!rst)\n q<=0;\n else\n begin\n if(enable)\n begin\n if(t)\n q<=~q;\n else\n q<=1;\n end\n else\n q<=q;\n end\n end\nendmodule\n\n// Path: threebit_counter.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:54:08 PM\n// Design Name: \n// Module Name: threebit_counter\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule threebit_counter(clk,enable,rst,q);\n input clk;\n input enable;\n input rst;\n output [2:0] q;\n wire [2:0] nq;\n \n T_Flipflop uut0(rst,enable,clk,1'b1,q[0],nq[0]);\n T_Flipflop uut1(rst,enable,nq[0],1'b1,q[1],nq[1]);\n T_Flipflop uut2(rst,enable,nq[1],1'b1,q[2],nq[2]);\n\nendmodule\n\n\n// Path: threebit_counter_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:56:37 PM\n// Design Name: \n// Module Name: threebit_counter_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule threebit_counter_tb();\n reg rst;\n reg enable;\n reg clk;\n wire [2:0] q;\n \n threebit_counter uud1(.clk(clk),.enable(enable),.rst(rst),.q(q));\n \n initial\n begin\n clk=0;rst=1;enable=1;\n #2 rst=0;\n #4 rst=1;\n #100 enable=0;\n #40 \n $finish;\n end\n \n initial\n forever\n #2 clk=~clk;\n \n\nendmodule\n\n\n// Path: D_Flipflop.v\n`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 10/23/2023 05:13:34 PM// Design Name: // Module Name: D_Flipflop// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //////////////////////////////////////////////////////////////////////////////////module D_ff_sync(d, rstn, clk, q); //sync input d; input rstn; input clk; output reg q; always @ (posedge clk) if (rstn) q <= 0; else q <= d;endmodulemodule D_ff_async(d, rstn, clk, q); //async input d; input rstn; input clk; output reg q;"
}
] |
always @ (posedge clk or negedge rstn)
|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",
"content": "// Repo Name: kbashus/Bashus_ECE128_Lab7\n// Path: Clock_divider.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/24/2023 11:58:26 AM\n// Design Name: \n// Module Name: Clock_divider\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule Clock_divider(clock_in, clock_out);\n input clock_in;\n output reg clock_out;\n reg[2:0] counter = 3'b0;\n \n parameter DIVISOR = 100 / 25;\n \n always @(posedge clock_in)\n \n begin\n counter <= counter + 1'b1;\n if(counter>=(DIVISOR-1))\n counter <= 3'b0;\n clock_out <= (counter<DIVISOR/2) ? 1'b1:1'b0;\n end\n \nendmodule\n\n// Path: Clock_divider_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/24/2023 11:58:43 AM\n// Design Name: \n// Module Name: Clock_divider_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule Clock_divider_tb();\n reg clock_in;\n wire clock_out;\n \n Clock_divider uut (.clock_in(clock_in),\n .clock_out(clock_out));\n \n initial begin\n clock_in = 0;\n forever #10 clock_in = ~clock_in;\n end\n\nendmodule\n\n\n// Path: D_Flipflop.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:13:34 PM\n// Design Name: \n// Module Name: D_Flipflop\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule D_ff_sync(d, rstn, clk, q); //sync\n input d;\n input rstn;\n input clk;\n output reg q;\n \n always @ (posedge clk)\n if (rstn)\n q <= 0;\n else\n q <= d;\nendmodule\n\n\nmodule D_ff_async(d, rstn, clk, q); //async\n input d;\n input rstn;\n input clk;\n output reg q;\n \n always @ (posedge clk or negedge rstn)\n if (!rstn)\n q <= 0;\n else\n q <= d;\nendmodule\n\n// Path: SR_Flipflop.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 01:46:11 PM\n// Design Name: \n// Module Name: SR_Flipflop\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Flipflop(clk, rstn, S, R, q, qbar);\n input clk;\n input rstn;\n input S;\n input R;\n output reg q;\n output reg qbar;\n\n \n always @(posedge clk) begin\n \n if (rstn) begin\n q=1'b0;\n qbar=1'b1;\n \n end else begin\n \n case({S,R})\n {1'b0,1'b0}: begin q=q;qbar=qbar; end\n {1'b0,1'b1}: begin q=1'b0;qbar=1'b1; end\n {1'b1,1'b0}: begin q=1'b1;qbar=1'b0; end\n {1'b1,1'b1}: begin q=1'b0; qbar=1'b0; end\n endcase\n \n end\n \nend\nendmodule\n\n\n// Path: SR_Flipflop_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 02:19:46 PM\n// Design Name: \n// Module Name: SR_Flipflop_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Flipflop_tb();\n reg clk;\n reg rstn;\n reg s;\n reg r;\n wire q;\n wire qbar;\n\n SR_Flipflop sff (.clk(clk), .rstn(rstn), .S(s), .R(r), .q(q), .qbar(qbar));\n \n initial begin\n \n s = 1'b0;\n r = 1'b0;\n rstn = 1;\n clk=1;\n \n #10\n rstn=0;\n s=1'b1;\n r=1'b0;\n \n #100\n rstn=0;\n s=1'b0;\n r=1'b1;\n \n #100\n rstn=0;\n s=1'b1;\n r=1'b1;\n \n #100\n rstn=0;\n s=1'b0;\n r=1'b0;\n \n #100\n rstn=1;\n s=1'b1;\n r=1'b0;\n \nend\nalways #25 clk <= ~clk;\n\nendmodule\n \n\n// Path: SR_Latch.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 01:46:11 PM\n// Design Name: \n// Module Name: SR_Latch\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Latch(S, R, Q, Qbar);\n input S;\n input R;\n output Q;\n output Qbar;\n \n nor N1(Q, R, Qbar);\n nor N2(Qbar, S, Q);\n\nendmodule\n\n\n// Path: SR_Latch_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 01:48:15 PM\n// Design Name: \n// Module Name: SR_Latch_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule SR_Latch_tb();\n reg r, s;\n wire q, qbar;\n \n SR_Latch UUT(.S(s), .R(r), .Q(q), .Qbar(qbar));\n \n initial\n begin\n r=0; s=0;\n #5 s=1;\n #5 s=0;\n #5 r=1;\n #5 r=0; s=1;\n #5 s=0; r=1;\n #5 r=0;\n #5 r=1; s=1;\n end\n \n initial begin\n $dumpfile(\"dump.vcd\"); // record waveform\n $dumpvars(1); //display signals in testbench\n end\nendmodule\n\n// Path: T_Flipflop.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:45:25 PM\n// Design Name: \n// Module Name: T_Flipflop\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule T_Flipflop(rst,enable,clk,t,q,notq);\n input t;\n input clk;\n input enable;\n input rst;\n output reg q;\n output notq;\n assign notq=~q;\n \n always@(posedge clk or negedge rst)\n begin\n if(!rst)\n q<=0;\n else\n begin\n if(enable)\n begin\n if(t)\n q<=~q;\n else\n q<=1;\n end\n else\n q<=q;\n end\n end\nendmodule\n\n// Path: threebit_counter.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:54:08 PM\n// Design Name: \n// Module Name: threebit_counter\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule threebit_counter(clk,enable,rst,q);\n input clk;\n input enable;\n input rst;\n output [2:0] q;\n wire [2:0] nq;\n \n T_Flipflop uut0(rst,enable,clk,1'b1,q[0],nq[0]);\n T_Flipflop uut1(rst,enable,nq[0],1'b1,q[1],nq[1]);\n T_Flipflop uut2(rst,enable,nq[1],1'b1,q[2],nq[2]);\n\nendmodule\n\n\n// Path: threebit_counter_tb.v\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/23/2023 05:56:37 PM\n// Design Name: \n// Module Name: threebit_counter_tb\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule threebit_counter_tb();\n reg rst;\n reg enable;\n reg clk;\n wire [2:0] q;\n \n threebit_counter uud1(.clk(clk),.enable(enable),.rst(rst),.q(q));\n \n initial\n begin\n clk=0;rst=1;enable=1;\n #2 rst=0;\n #4 rst=1;\n #100 enable=0;\n #40 \n $finish;\n end\n \n initial\n forever\n #2 clk=~clk;\n \n\nendmodule\n\n\n// Path: D_Flipflop_tb.v\n`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 10/23/2023 05:15:04 PM// Design Name: // Module Name: D_Flipflop_tb// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //////////////////////////////////////////////////////////////////////////////////module D_Flipflop_tb(); reg d; reg rstn; reg clk; wire q; //D_ff_sync uut (.d(d), .rstn(rstn), .clk(clk), .q(q));"
}
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D_ff_async uut (.d(d), .rstn(rstn), .clk(clk), .q(q));
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[{"role":"system","content":"You are an expert RTL hardware engineer. Given code context from multip(...TRUNCATED) |
instr_32 = {7'b0000000, instr_16[6:2], 5'd0, 3'b000, instr_16[11:7], 7'b0110011};
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[{"role":"system","content":"You are an expert RTL hardware engineer. Given code context from multip(...TRUNCATED) |
(mstatus_sel && csrrs_op)? (mstatus_reg | csr_write_data):
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