I didn&#x27;t personally downvote you, but I&#x27;ll give you my best guesses:<p>1) The percentage of die used for decoding is actually already quite low. Per Anandtech 2014, it was at 10% for x86 and decreasing:<p><a href="http:&#x2F;&#x2F;www.anandtech.com&#x2F;show&#x2F;8776&#x2F;arm-challinging-intel-in-the-server-market-an-overview&#x2F;12" rel="nofollow">http:&#x2F;&#x2F;www.anandtech.com&#x2F;show&#x2F;8776&#x2F;arm-challinging-intel-in-...</a><p>Since there is a floor to the number of transistors needed for decoding, there might not be a whole lot to gain there.<p>2) Progress has already been made towards updating instruction sets to reflect what CPUs do quickly, well etc. It started with MMX back in the stone age, and has progressed through a plethora of SIMD and media acceleration instructions.<p>3) Instruction sets are already not designed as if they were supposed to be run directly. Quite to the contrary, they are abstracted -- the instruction set is the API, and the microoperations are the instructions. Designing them as if they were to run directly would mean exposing the micro-ops, which would require backwards compatibility breaking changes to the CPU each generation when there were changes to the micro ops.<p>4) The current system already pretty well levels energy consumption between competing ISAs. See: <a href="http:&#x2F;&#x2F;www.extremetech.com&#x2F;extreme&#x2F;188396-the-final-isa-showdown-is-arm-x86-or-mips-intrinsically-more-power-efficient" rel="nofollow">http:&#x2F;&#x2F;www.extremetech.com&#x2F;extreme&#x2F;188396-the-final-isa-show...</a><p>You&#x27;re describing something that sounds like a bytecode VM, but in essence, that&#x27;s what modern processors <i>already are</i>. Unfortunately, x86 (at least 32 bit) assembly is pretty unpleasant as an &#x27;API&#x27;, but ARM and PowerPC are both pretty good.<p>As far as pointer tagging, that&#x27;s something that&#x27;s probably mostly limited by memory bandwidth (it&#x27;s not a particularly compute heavy thing to do), so unless the HW support came in the form of a dedicated on-chip cache, it probably wouldn&#x27;t get you very much ... and then, if you&#x27;re going to the expense of adding a dedicated on-chip cache, it&#x27;s probably going to be more effective as a general purpose cache -- if the code is accessing the pointer metadata often, it will be in cache, and therefore accelerated.<p>Not trying to rain on your parade, I like seeing creative ideas, and I have no idea why people are downvoting you. Have an upvote on me :).<p>EDIT: Also, ARM has NEON.