&gt; While there are hardware mechanisms 2 to optimize context switches, they do not eliminate all the performance degradation. Context switches have indirect costs outside of the time used for the switch itself – all the previously-mentioned caches get utterly trashed.<p>This is an odd statement.  That footnote (2) directly refutes part of it.<p>Concretely, lots of CPUs have &quot;address-space identifiers&quot; that enable MMU contest switches without TLB flushes.  Intel Sandy Bridge and up has a limited form of this capability (Intel calls it PCID for incomprehensible reasons), and I&#x27;m working to enable it on Linux 4.6 or 4.7.<p>With ASID available, MMU context switches are a single inatruction and have negligible cache footprint.  The extra bookkeeping needed will be one or two cachelines.