It&#x27;s quite possible to catch random errors, with checking CPUs.  Some IBM mainframes have dual CPUs running in lockstep and compare the results.  Intel Xeon CPUs have checking on the on-chip memories [1] (caches, TLBs, etc.) but not the ALU.<p>Duplicated ALUs, instruction decoders, and retirement units checking each other are rarer than they should be.  It wouldn&#x27;t add that much cost, since most of the chip real estate today is memory cells for caches.  If you fault the CPU on a compare error, rather than trying to recover, it doesn&#x27;t slow down the CPU at all, or add much complexity. Backup and retry is tougher, but may be unnecessary. The important thing is to detect failure, fail fast, and move the work to another CPU.<p>[1] <a href="http:&#x2F;&#x2F;www.intel.com&#x2F;content&#x2F;dam&#x2F;www&#x2F;public&#x2F;us&#x2F;en&#x2F;documents&#x2F;white-papers&#x2F;xeon-e7-family-ras-server-paper.pdf" rel="nofollow">http:&#x2F;&#x2F;www.intel.com&#x2F;content&#x2F;dam&#x2F;www&#x2F;public&#x2F;us&#x2F;en&#x2F;documents&#x2F;...</a>