This stuff is really cool.  One of my college professors, Rajit Manohar, was one of the guys who did a lot of the major research into async VLSI in the 90s.  He and a few of his colleagues founded a company in San Jose (Achronix) that designs and builds async FPGAs.<p>It's an amazingly different way of thinking about computing.  Generally async designs take up more physical die space (because of things like dual-rail logic), but the power savings can be pretty significant since you're not running a clock... basically the logic runs as fast or as slow as it needs to, and doesn't do much of anything when idle.<p>I took a class where we designed and did a little layout for some CPU-subset blocks.  It was fun, but often very challenging.  At least at the time, there weren't many (any?) good test/validation tools.  A friend of mine has been working on one for the past 8 years or so (<a href="http://www.csl.cornell.edu/~fang/hackt/" rel="nofollow">http://www.csl.cornell.edu/~fang/hackt/</a>), first as a part of his PhD thesis, later as a part of his job.<p>It's been years since I've touched this stuff... if I'd continued down the EE path (like many others, I switched to software post-college) I'd (ideally) be doing async stuff now.