Years ago I tried to implement a simple CPU architecture in Xilinx Verilog on a Spartan3 where the aim was for it to be pedagogically simple inside and out, with extremely concise and expository HDL source.<p>I failed pretty miserably: It took me several rewrites before I got one to even synthesize, and dozens before I got it to place+route onto the physical chip (fucking traveling salesman problem!). I never got my CPU's JMP instruction to work correctly within my self-imposed ideological constraints, making it rather useless.<p>It took me a while to realize that the fundamental problem with my design was hidden asynchrony, despite having a clock.