Multithreaded processors have multiple hardware threads. An SMT processor schedules instructions, mostly ignoring which thread they come from. An SoEMT processor schedules hardware threads, usually switching on a cache miss or similar stall event.<p><a href="http://en.wikipedia.org/wiki/Multithreading_(computer_hardware)" rel="nofollow">http://en.wikipedia.org/wiki/Multithreading_(computer_hardwa...</a><p><i>Can't the CPU just signal an interrupt for those, and let the OS scheduler handle it?</i><p>This is usually not efficient because handling an interrupt takes nearly as long as a cache miss (and let us not consider the case where the interrupt handler itself triggers a cache miss), but Intel did a prototype on the Itanium that worked this way.