That book is detailed, but that's also the problem with it. The relevant signal is all but drowned in the noise of 114 pages of details of CAS/RAS, circuit diagrams for SRAM and DRAM cells, bus protocols for hardware transactional memory, descriptions of Linux APIs for configuring NUMA support, etc.; frankly, things that need not be known unless dealing with those issues specifically.<p>In the article of this post, on the other hand, a handful of key characteristics of the cache hierarchy are graphically displayed using pretty minimal code snippets and attractive graphs. I believe programmers would generally be better served by the intuitions gained from the blog post than daunted by the exhaustive detail and verbose presentation of Ulrich's book.<p>IOW, keep in mind simple things like: measure; be aware of the cheapness of adjacent accesses, of the possibility of false sharing with certain strides, of the cost of following pointers, of the pitfalls of concurrent access to adjacent memory locations, and even serial access to the same memory location (dependencies wrt ILP). Concentrate on building a mental model for providing intuitions of cache behaviour at the appropriate level of abstraction, but always be prepared to measure to verify intuitions, as the hardware changes all the time, and different architectures can give rise to surprisingly different results.