I think this is more like an ALU simulator (plus registers) than a CPU simulator.  There are no jumps, either conditional or unconditional, because it&#x27;s reading the instruction stream from standard input.<p><a href="https:&#x2F;&#x2F;github.com&#x2F;kragen&#x2F;calculusvaporis&#x2F;blob&#x2F;master&#x2F;cavosim.c" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;kragen&#x2F;calculusvaporis&#x2F;blob&#x2F;master&#x2F;cavosi...</a> is a CPU simulator in 70 lines of code, but it&#x27;s perhaps a bit impractical; you have to synthesize addition from subtraction, for example, and AND and OR from NAND.  The design objective of Calculus Vaporis, however, is to use as few <i>logic gates</i> as possible, rather than to be as simple as possible in C.<p><a href="http:&#x2F;&#x2F;canonical.org&#x2F;~kragen&#x2F;sw&#x2F;aspmisc&#x2F;brainfuck.c" rel="nofollow">http:&#x2F;&#x2F;canonical.org&#x2F;~kragen&#x2F;sw&#x2F;aspmisc&#x2F;brainfuck.c</a> is a 66-line BF interpreter, but BF is not a very good CPU design, in that it doesn&#x27;t support subroutines.