This PDF explains what I discuss below in more detail: <a href="http:&#x2F;&#x2F;moodle.technion.ac.il&#x2F;pluginfile.php&#x2F;315285&#x2F;mod_resource&#x2F;content&#x2F;1&#x2F;tutorial3_winter_2013.pdf" rel="nofollow">http:&#x2F;&#x2F;moodle.technion.ac.il&#x2F;pluginfile.php&#x2F;315285&#x2F;mod_resou...</a>. Prediction of aliasing is discussed on slide 25.<p>The patent in question pertains to an optimization of what these days you&#x27;d call &quot;memory disambiguation.&quot; In a processor executing instructions out of order, data dependencies can be known or ambiguous. A known data dependency is, for example, summing the results of two previous instructions that themselves each compute the product of two values. An ambiguous data dependency is usually a memory read after a memory write. The processor usually does not know the address of the store until it executes the store. So it can&#x27;t tell whether a subsequent load must wait behind the store (if it reads from the same address), or can safely be moved ahead of it (if it reads from a different address).<p>If you have the appropriate machinery, you can speculatively execute that later load instruction. But you need some mechanism to ensure that if you guess wrong--that subsequent load really does read from the same address as the earlier store--you can roll back the pipeline and re execute things in the correct order.<p>But flushing that work and replaying is slow. If you&#x27;ve got a dependent store-load pair, you want to avoid the situation where misspeculation causes you to have to flush and reply every time. The insight of the patent is that these dependent store-load pairs have temporal locality. Using a small table, you can avoid most misspeculations by tracking these pairs in the table and not speculating the subsequent load if you get a table hit. That specific use of a prediction table is what is claimed by the patent.<p>Maybe this is worth a patent, or maybe not. For what it&#x27;s worth, I don&#x27;t think anybody was doing memory disambiguation at all in 1996. Intel was one of the first (maybe the first) to do so commercially in the mid-2000&#x27;s. Apple&#x27;s Cyclone architecture also does it, and I think it was the first in the low-power SoC space to do it.