The x86 architecture was not amenable to a high performance pipelined implementation, so what Intel did since Pentium Pro is to JIT the x86 instructions into an internal RISCy instruction set that can be executed out-of-order with competitive performance.<p>The x86 architecture was limited to 32-bit, severely limiting the virtual address space as well as hampering OS implementation with hacks like PAE, so what AMD did is to extend it to 64-bit.<p>The x86 architecture was not designed for SMP scalability due to the rather strict memory ordering requirements, but most of the architectures with laxer memory models (in particular, Alpha, which was the most lax of all) are out of business today (in fact, of the commercially relevant server architectures today, only POWER has lax memory ordering; SPARC can in theory but is usually configured to run with TSO which is similar to x86).<p>The x86 architecture was not designed for OS virtualization because various instructions did not trap when executed in user mode, so what Intel and AMD did is define a new protection level (&quot;ring -1&quot;) to run the hypervisor so this works efficiently now.<p>What actual problem do you see with x86 that cannot be solved or worked around by some creative engineering at Intel&#x2F;AMD?