The future might be in an FPGA fabric tightly coupled with generic RISC cores (things like Zynq SoCs, but with a tighter integration, allowing a direct access from FPGA to the CPU internal registers, pipelines, etc.). Bigger macro cells (like entire ALUs, generic caches, etc.) might be useful too.<p>This way hot spots can be optimised (even in a JIT engine in runtime) into hardware circuits.<p>I played a bit with some crazy ideas like mixing HDLs with a low level C code (see the Mandelbrot example here:  <a href="https:&#x2F;&#x2F;github.com&#x2F;combinatorylogic&#x2F;soc&#x2F;tree&#x2F;master&#x2F;backends&#x2F;small1&#x2F;sw&#x2F;long_hdltests" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;combinatorylogic&#x2F;soc&#x2F;tree&#x2F;master&#x2F;backends...</a> ) - this sort of things can become practical with a tighter integration between a CPU  core and FPGA fabric (in my case it was a soft core, of course).