3.3 microseconds latency for the flash at the memory bus are about 11,000 cycles latency @ 3.3GHz. That is quite a lot compared to a normal DDR latency of about 150 cycles. Of course it&#x27;s much better than 100 microseconds or about 330,000 cycles for a normal SSD. I would guess that the overhead for a page fault would be around 1000 cycles.<p>Writing a block device for Linux so that the flash could be used as a cache or ram disk is quite easy (speaking from experience) and I assume that Diablo has already written one.<p>If Diablo had access to the memory controller inside the main CPU they could even run the DDR as a cache for the flash memory like some giant L4 cache. In such a scenario the DDR ram emulation would make sense...