I&#x27;m not sure this should be called &quot;RISC&quot;. It seems very tightly coupled to the particular processor pipeline being proposed:<p>It has dynamic typing (each register has a tag telling you what type of data it currently holds). Scalar, vector, FP, binary&#x2F;decimial FP, etc.<p>It has a set of &quot;Queue&quot; registers, which appear to be similar to Stack architectures or the Mill&#x27;s &quot;Belt&quot; architecture (operands are read in the order they were written).<p>Seems to think it can get away without needing branch prediction.<p>It uses multi-threading for fine-grain task switching. It does this by copying all register writebacks to a 4kB region of memory so it&#x27;s already performed the context before it&#x27;s required.