DEC hardware the power on self test (POST) which included a RAM test was itself tested prior to starting. And as computers used to be so much more unreliable in their hardware there was a lot of work dedicated to error checking the hardware.<p>In today&#x27;s hardware you can run a CRC check on your bootloader prior to starting it using only registers. When you start it, you can check a portion of memory from the bootloader, then using that memory, check the rest of memory. If you use ECC memory and initialize it properly, it will do a machine check if multiple bits get flipped. Multiple systems doing the same calculations should get the same answer, using three systems and flagging any system that disagrees with the consensus will identify failing hardware. I&#x2F;O channels can use ECC as well, and software that is running in ECC protected I&#x2F;O and memory can use data protocols to detect data corruption in flight (channel errors) or in situ (storage errors).<p>As with most things you can never be perfect (aka the halting problem) but you can make failure statistically rare enough that you are willing to risk it. It doesn&#x27;t mean that bad things will never happen. We live with risk every day and still drive to work.<p>And the trick is it is easier to just say &quot;Whoops, something isn&#x27;t right here, we&#x27;re resetting to a known state.&quot; but that can make functioning really difficult (see Kepler&#x27;s safe mode, or the challenges Armstrong had landing the LEM when it was constantly resetting the flight computer). Sometimes you just break. And in those situations the best you can do is to break in such a way that you don&#x27;t cause any additional harm.