So does this attempt to better utilize the multiple compute units which make up a single compute pipeline? For example Skylake technically has 4 FPU&#x27;s per <i>physical core</i> 1 SIMD, 3 x87 FPU-esque units, 1 branch processors, and 3-4ish IPU&#x27;s (branch processors have some IPU uOPs)?<p>Or is it just a compiler integrated green thread library?<p>The FAQ is really vague just says its makes interfacing with parallelism easier.