I agree on the memory model being the most interesting thing about this card. I sort of &quot;under-sold&quot; it on the &quot;better design&quot; part of my last bullet.<p>People&#x2F;manufacturers tend to look at clock rates, fill rates (for GPUs), FLOPs, &quot;crunching power&quot; in general, forgetting completely the memory part. For example, today most CPUs end up being bound by cache sizes and performance tuning focuses on being nice on the cache rather than being optimal in your instructions (see for example Abrash&#x27;s Pixomatic articles[0-2], which are about high performance assembly programming in &quot;modern environments&quot;).<p>With GPU and &quot;classic&quot; HPC (don&#x27;t know about the new systems with the &quot;compute fabric interconnects&quot;), memory usually becomes the bottleneck (except for embarrasingly paralell problems, of course). In fact, I&#x27;m pretty it was Cray who said that a supercomputer is a way to turn a CPU-bound problem into an IO-bound problem.<p>[0] <a href="http:&#x2F;&#x2F;www.drdobbs.com&#x2F;architecture-and-design&#x2F;optimizing-pixomatic-for-x86-processors&#x2F;184405765" rel="nofollow">http:&#x2F;&#x2F;www.drdobbs.com&#x2F;architecture-and-design&#x2F;optimizing-pi...</a><p>[1] <a href="http:&#x2F;&#x2F;www.drdobbs.com&#x2F;optimizing-pixomatic-for-modern-x86-proc&#x2F;184405807" rel="nofollow">http:&#x2F;&#x2F;www.drdobbs.com&#x2F;optimizing-pixomatic-for-modern-x86-p...</a><p>[2] <a href="http:&#x2F;&#x2F;www.drdobbs.com&#x2F;optimizing-pixomatic-for-modern-x86-proc&#x2F;184405848" rel="nofollow">http:&#x2F;&#x2F;www.drdobbs.com&#x2F;optimizing-pixomatic-for-modern-x86-p...</a>