Does the synthesizer care about one or two processes?
There are two popular ways of coding a state machine in VHDL: one process or two processes. There are rumors (and it is taught in some colleges) that two processes *might* result in better hardware. Does anybody have any hard evidence for this? My own preliminary tests show that there is no difference at all.

I'm looking for *reproducible experiments*: VHDL code for the two coding styles, and specifics on how to synthesize them (which tool, which parameters).

Please help me to either debunk or confirm the myth that two processes result in better synthesized hardware.
Does the synthesizer care about one or two processes?
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There are two popular ways of coding a state machine in VHDL: one process or two processes. There are rumors (and it is taught in some colleges) that two processes *might* result in better hardware. Does anybody have any hard evidence for this? My own preliminary tests show that there is no difference at all.

I'm looking for *reproducible experiments*: VHDL code for the two coding styles, and specifics on how to synthesize them (which tool, which parameters).

Please help me to either debunk or confirm the myth that two processes result in better synthesized hardware.