How to make a simple 4 bit parity checker in VHDL
I am trying to learn VHDL and I´m trying to make 4-bit parity checker. The idea is that the bits come from one input line (one bit per clock pulse) and the checker should find out if there is odd number of 1´s in the 4-bit sequence (i.e 1011 , 0100 , etc.) and send an error output(e.g error flag: error <=´1´) if there is.

Could someone please direct me to some website where it is shown how to do this or be so kind as to give me an example how it´s done, so that I can study it?

I have tried googling it, but all the discussions I found were related to something way more compilacated and I could not understant them...

Thank you very much!


 
How to make a simple 4 bit parity checker in VHDL
===

I am trying to learn VHDL and I´m trying to make 4-bit parity checker. The idea is that the bits come from one input line (one bit per clock pulse) and the checker should find out if there is odd number of 1´s in the 4-bit sequence (i.e 1011 , 0100 , etc.) and send an error output(e.g error flag: error <=´1´) if there is.

Could someone please direct me to some website where it is shown how to do this or be so kind as to give me an example how it´s done, so that I can study it?

I have tried googling it, but all the discussions I found were related to something way more compilacated and I could not understant them...

Thank you very much!


 