State to std_logic
I have defined my state as follows:

    type state_type is (s0, s1, s2, s3);
    signal state   : state_type;

Now I would like to use this state information to form another signal

    signal data : std_logic_vector(3 downto 0);
    signal data_plus_state : std_logic_vector(5 downto 0);
 
    ....
    data_plus_state <= data & state;

Does anyone know how I can concert state into a std_logic_vector so that I can concatenate these
two signals?

Many thanks,
Rob





							  
State to std_logic
===

I have defined my state as follows:

    type state_type is (s0, s1, s2, s3);
    signal state   : state_type;

Now I would like to use this state information to form another signal

    signal data : std_logic_vector(3 downto 0);
    signal data_plus_state : std_logic_vector(5 downto 0);
 
    ....
    data_plus_state <= data & state;

Does anyone know how I can concert state into a std_logic_vector so that I can concatenate these
two signals?

Many thanks,
Rob





							  