 +  let Opcode = opcode.Value;
 +}
 +
++class RVInstI_Ext<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
++              string opcodestr, string argstr, list<dag> pattern>
++    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatI> {
++  bits<12> imm12;
++  bits<5> rs1;
++  bits<5> rd;
++
++  let Inst{31-20} = imm12;
++  let Inst{19-15} = rs1;
++  let Inst{14-12} = funct3;
++  let Inst{11-7} = rd;
++  let Opcode = opcode.Value;
++}
++
++class RVInstS_Ext<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
++              string opcodestr, string argstr, list<dag> pattern>
++    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatS> {
++  bits<12> imm12;
++  bits<5> rs2;
++  bits<5> rs1;
++
++  let Inst{31-25} = imm12{11-5};
++  let Inst{24-20} = rs2;
++  let Inst{19-15} = rs1;
++  let Inst{14-12} = funct3;
++  let Inst{11-7} = imm12{4-0};
++  let Opcode = opcode.Value;
++}
++
++
 +def simm9 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<9>(Imm);}]> {
 +  let ParserMatchClass = SImmAsmOperand<9>;
 +  let EncoderMethod = "getImmOpValue";

From 3a9de9c042789b75d28b068966d9b6a9b1bd01c5 Mon Sep 17 00:00:00 2001
From: Min Chen <chenm003@163.com>
Date: Fri, 20 Oct 2017 17:17:41 -0500
Subject: [PATCH] x266 RISC-V Vector Extension

---
 include/llvm/IR/Intrinsics.td                      |    1 +
 include/llvm/IR/IntrinsicsRISCV.td                 |   29 ++++++
 lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp      |    9 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp       |   26 +++++
 lib/Target/RISCV/RISCVISelLowering.cpp             |   84 ++++++++++++++++
 lib/Target/RISCV/RISCVInstrInfo.td                 |    2 +
 lib/Target/RISCV/RISCVInstrInfoV.td                |  102 ++++++++++++++++++++
 lib/Target/RISCV/RISCVIntrinsics.td                |   40 ++++++++
 8 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/llvm/IR/IntrinsicsRISCV.td
 create mode 100644 lib/Target/RISCV/RISCVInstrInfoV.td
 create mode 100644 lib/Target/RISCV/RISCVIntrinsics.td

+//======
+// Load
+//======
+/*
+def V_LD32X8 : Vec0_LDvri<0b000000, "v.ld32x8", int_riscv_v_ld32x8>, Requires<[IsRV32]>;
+
+multiclass VecLdPat<PatFrag LoadOp, RVInst Inst> {
+  def : Pat<(v32i8 (LoadOp GPR:$rs1)), (Inst GPR:$rs1, 0)>;
