 +    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
 +    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
 +    // .. .. 
-+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E440D2U),
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
 +    // .. .. reg_ddrc_write_latency = 0x5
 +    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
 +    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U

+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U

+
--- /dev/null
+++ b/board/xilinx/zynq/zynq-7z100/ps7_init_gpl.h
@@ -0,0 +1,137 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
