 +		}
 +
 +		ret = of_clk_add_hw_provider(child_node, of_clk_hw_simple_get,
-+							     &clkout->clk_hw);
++							       &lcko->clk_hw);
 +		if (ret != 0)
 +			return ret;
 +		i++;

+	bitset1 = (*phase_mux << PHASE_MUX_POS);
+	bitset2 = (*delay_time << DELAY_TIME_POS);
+
+	if (clkout_nr == 0 && fract_cnt > 0) {
+		u16 clkout5_reg2_bitset;
+
+		litex_clk_calc_duty_fract(hw, true);
+		bitset2 |= (*fract_cnt << FRAC_POS)		|
+			   (*frac_en << FRAC_EN_POS)	|
+			   (*frac_wf_r << FRAC_WF_R_POS);
+

+/* Sets phase given in degrees on given clock output */
+int litex_clk_set_phase(struct clk_hw *hw, int degrees)
+{
+	struct litex_clk_clkout *lcko = clk_hw_to_litex_clk_clkout(hw);
+	int ret;
+	u16 bitset1, bitset2, reg2_mask;
+	u8 *phase_mux = &lcko->phase.phase_mux,
+	   *delay_time = &lcko->phase.delay_time,
+	   *frac = &lcko->frac.frac,
+	   *frac_en = &lcko->frac.frac_en,
+	   *frac_wf_f = &lcko->frac.frac_wf_f,
+	   *frac_wf_r = &lcko->frac.frac_wf_r,
+	   *phase_mux_f = &lcko->frac.phase_mux_f,
+	   clkout_nr = lcko->id;
+
+	lcko->ts_config.phase = degrees;
+	reg2_mask = REG2_PHASE_MASK;
+	pr_debug("set_phase: %u deg", degrees);
+
+	if (*frac > 0 && degrees != 0) {
+		pr_err("CLKOUT%d: cannot set phase on that frequency",
+								clkout_nr);
+		return -ENOSYS;
