  };
  
  static iomux_v3_cfg_t const wdog_pads[] = {
-@@ -242,12 +267,117 @@ static void setup_iomux_wdog(void)
+@@ -242,12 +267,130 @@ static void setup_iomux_wdog(void)
  	gpio_direction_input(WDT_TRG);
  }
  
 -static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
  
 -int board_mmc_getcd(struct mmc *mmc)
--{
--	return 1; /* Always present */
 +/*  __________________________________________________________________________
 + * |                                                                          |
 + * |                                   USDHC                                  |

 
 int board_eth_init(bd_t *bis)
 {
@@ -283,14 +413,6 @@ free_bus:
 	return ret;
 }
 

+#define USDHC3_CD_GPIO	IMX_GPIO_NR(7, 0)
+#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 5)
+
+
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC3_BASE_ADDR, 0, 4}, // FSL_SDHC: 0, uSD the primary boot medium when J27 is closed
+	{USDHC4_BASE_ADDR, 0, 8}, // FSL_SDHC: 1, eMMC (optional) the secondary boot medium when J27 is closed
+};
+
+enum mxc_clock usdhc_clk[CONFIG_SYS_FSL_USDHC_NUM] = {
