  		napi_schedule(&priv->napi);
  	}
  
-@@ -1093,8 +1098,7 @@
+@@ -1093,8 +1050,7 @@
  
  	at91_irq_err(dev);
  

 /*
  * theory of operation:
  *
@@ -871,8 +870,8 @@
 	 * we get a TX int for the last can frame directly before a
 	 * wrap around.
 	 */

+        napi_complete(napi);
+    }
 
-	/*
-	 * The error bits are clear on read,
-	 * so use saved value from irq handler.
-	 */
-	reg_sr |= priv->reg_sr;
-	if (reg_sr & AT91_IRQ_ERR_FRAME)
-		work_done += at91_poll_err(dev, quota - work_done, reg_sr);
-
-	if (work_done < quota) {
-		/* enable IRQs for frame errors and all mailboxes >= rx_next */
-		u32 reg_ier = AT91_IRQ_ERR_FRAME;
-		reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
-
-		napi_complete_done(napi, work_done);
-		at91_write(priv, AT91_IER, reg_ier);
-	}
-
-	return work_done;
+ 	return work_done;
 }
