 +		return 0;
 +	} else {
 +		pr_err("CLKOUT%d: cannot set duty cycle when fractional divider enabled!",
-+								clkout_nr);
++			clkout_nr);
 +		return -EACCES;
 +	}
 +

+ *
+ */
+static int litex_clk_change_value(struct clk_hw *clk_hw, u16 mask, u16 bitset,
+							  u8 clk_reg_addr)
+{
+	u16 DO_val, DI_val;
+	int ret;

+	if (ret != 0)
+		return ret;
+	ret = litex_clk_change_value(hw, LOCK23_MASK,
+			(((lock >> 16) & 0x1f) << 10) | 0x1, LOCK_REG2);
+	if (ret != 0)
+		return ret;
+	ret = litex_clk_change_value(hw, LOCK23_MASK,
+			(((lock >> 24) & 0x1f) << 10) | 0x3e9, LOCK_REG3);
+	if (ret != 0)
+		return ret;
+	return 0;
