 +    description: |
 +      System clock frequency
 +
++  litex,divclk-divide-min:
++    description: |
++      minimal global divider
++  litex,divclk-divide-max:
++    description: |
++      maximal global divider
++  litex,clkfbout-mult-min:
++    description: |
++      minimal global multiplier
++  litex,clkfbout-mult-max:
++    description: |
++      maximal global multiplier
++  litex,vco-freq-min:
++    description: |
++      minimal frequency after global divider and multiplier
++  litex,vco-freq-max:
++    description: |
++      maximal frequency after global divider and multiplier
++  litex,clkout-divide-min:
++    description: |
++      minimal clock output divider
++  litex,clkout-divide-max:
++    description: |
++      maximal clock output divider
++  litex,vco-margin:
++    description: |
++      tolerancy for vco frequency
++    const: 0
++
 +  CLKOUTx:
 +    description: |
 +      Child node representing configurable clock outputs of MMCM unit
 +
 +    properties:
 +      compatible:
-+        const: litex,clock
++        const: litex,clk
 +
 +      reg:
 +        description: |

+        description: |
+          default frequency in Hz for clock output
+
+        min: 1587000
+        max: 100000000
+
+      litex,clock-phase:
+        description: |
+          default phase offset given in degrees

+
+properties:
+  compatible:
+    const: litex,clk
+
+  reg:
+    description: Base address and lengths of the register space
