 +    }
 +  }
 +
-+  def LRXACC : F3_1<2, 0b000000,
-+                   (outs IntRegs:$rd), (ins),
-+                   "lrxacc $rd",
-+                   [(set i32:$rd, (int_sparc_lrxacc))]>;
++  let rs1 = 0, rs2 = 0, Uses = [XACC] in {
++    def LRXACC : F3_1<2, 0b000000,
++                     (outs IntRegs:$rd), (ins),
++                     "lrxacc $rd",
++                     [(set i32:$rd, (int_sparc_lrxacc))]>;
++  }
 +}
  //===----------------------------------------------------------------------===//
  // Non-Instruction Patterns

 
 // Floating-point registers
 def F0  : Rf< 0,  "F0">, DwarfRegNum<[32]>;

diff -urN -x '*.swp' llvm-src/include/llvm/IR/IntrinsicsSPARC.td llvm-dev/include/llvm/IR/IntrinsicsSPARC.td
--- llvm-src/include/llvm/IR/IntrinsicsSPARC.td	1970-01-01 03:00:00.000000000 +0300
+++ llvm-dev/include/llvm/IR/IntrinsicsSPARC.td	2016-11-12 01:26:59.386666666 +0300
@@ -0,0 +1,5 @@
+let TargetPrefix = "sparc" in {
+  def int_sparc_xmac : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
