 +include "RISCVIntrinsics.td"
 diff --git a/lib/Target/RISCV/RISCVInstrInfoV.td b/lib/Target/RISCV/RISCVInstrInfoV.td
 new file mode 100644
-index 0000000..e3d4d80
+index 0000000..f9a2711
 --- /dev/null
 +++ b/lib/Target/RISCV/RISCVInstrInfoV.td
-@@ -0,0 +1,102 @@
+@@ -0,0 +1,143 @@
 +//===- RV32InstrInfoV.td - Chen's RV Vector Instructions -------*- tblgen -*-==//
 +//
 +//                     The LLVM Compiler Infrastructure

+  let Opcode = opcode.Value;
+}
+
+def simm9 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<9>(Imm);}]> {
+  let ParserMatchClass = SImmAsmOperand<9>;
+  let EncoderMethod = "getImmOpValue";

+//======
+// Load
+//======
+/*
+def V_LD32X8 : Vec0_LDvri<0b000000, "v.ld32x8", int_riscv_v_ld32x8>, Requires<[IsRV32]>;
+
+multiclass VecLdPat<PatFrag LoadOp, RVInst Inst> {
+  def : Pat<(v32i8 (LoadOp GPR:$rs1)), (Inst GPR:$rs1, 0)>;
