 +		u32 *mr)
 +{
 +	*mr = MICRON_V_MR_165;
-+	/* we need peripheral clocks for i2c */
-+	per_clocks_enable();
++	/* we need timer early for i2c */
++	timer_init();
 +	switch (get_board_revision()) {
-+	case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
++	case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
 +		*mcfg = MICRON_V_MCFG_165(128 << 20);
 +		*ctrla = MICRON_V_ACTIMA_165;
 +		*ctrlb = MICRON_V_ACTIMB_165;
 +		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 +		break;
-+	case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
++	case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
 +		*mcfg = MICRON_V_MCFG_165(256 << 20);
 +		*ctrla = MICRON_V_ACTIMA_165;
 +		*ctrlb = MICRON_V_ACTIMB_165;
 +		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 +		break;
-+	case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
++	case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
 +		*mcfg = HYNIX_V_MCFG_165(256 << 20);
 +		*ctrla = HYNIX_V_ACTIMA_165;
 +		*ctrlb = HYNIX_V_ACTIMB_165;

 	int revision;
 
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	/* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
+	/* these boards should return a revision number of 0                  */
+	/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+	unsigned char data;
+
+	i2c_set_bus_num(TWL4030_I2C_BUS);
+	data = 0x01;
+	i2c_write(0x4B, 0x29, 1, &data, 1);

+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
 #endif				/* __CONFIG_H */
-- 
1.7.6.4

