 +		ret = devm_clk_hw_register(dev, &lcko->clk_hw);
 +		if (ret != 0) {
 +			pr_err("devm_clk_hw_register failure, %s ret: %d\n",
-+						child_node->name, ret);
++						     child_node->name, ret);
 +			return ret;
 +		}
 +

+	for (high_time_it = 1; high_time_it < divider; high_time_it++) {
+		for (edge_it = 0; edge_it < 2; edge_it++) {
+			synthetic_duty = (high_time_it * 100 + 50 * edge_it) /
+								divider;
+			delta_d = abs(synthetic_duty - high_duty);
+			/* check if low_time won't be above acceptable range */
+			if (delta_d < min_d && (divider - high_time_it) <=
+						    HIGH_LOW_TIME_REG_MAX) {
+				min_d = delta_d;
+				lcko->div.high_time = high_time_it;
+				lcko->div.low_time = divider - high_time_it;

+
+	if (*frac > 0 && degrees != 0) {
+		pr_err("CLKOUT%d: cannot set phase on that frequency",
+			clkout_nr);
+		return -ENOSYS;
+	}
+	ret = litex_clk_calc_phase(hw);
+	if (ret != 0) {
+		pr_err("CLKOUT%d: phase offset %d deg is too high for given frequency",
+			clkout_nr, degrees);
+		return ret;
+	}
+
