 +    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
 +    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
 +    // .. .. 
-+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
++    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
 +    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
 +    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
 +    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U

+
--- /dev/null
+++ b/board/xilinx/zynq/zynq-7z100/ps7_init_gpl.h
@@ -0,0 +1,136 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.

+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
