    /* 5 */ { 0, &BX_CPU_C::BxError }, // JMP16_Ep
    /* 6 */ { 0, &BX_CPU_C::PUSH_EwR },
    /* 7 */ { 0, &BX_CPU_C::BxError }
-@@ -2939,10 +2939,10 @@
+@@ -2957,10 +2953,10 @@
  static const BxOpcodeInfo_t BxOpcodeInfo64G5dM[8] = {
    /* 0 */ { BxLockable, &BX_CPU_C::INC_EdM },
    /* 1 */ { BxLockable, &BX_CPU_C::DEC_EdM },

   /* C8 /qm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
   /* C9 /qm */ { 0, &BX_CPU_C::LEAVE64 },
-  /* CA /qm */ { BxImmediate_Iw, &BX_CPU_C::RETfar64_Iw },
-  /* CB /qm */ { 0, &BX_CPU_C::RETfar64 },
-  /* CC /qm */ { 0, &BX_CPU_C::INT3 },
-  /* CD /qm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
+  /* CA /qm */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETfar64_Iw },
+  /* CB /qm */ { BxTraceEnd, &BX_CPU_C::RETfar64 },
+  /* CC /qm */ { BxTraceEnd, &BX_CPU_C::INT3 },
+  /* CD /qm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
   /* CE /qm */ { 0, &BX_CPU_C::BxError },

 // if 1, don't do gpf on MSRs that we don't implement
 #define BX_IGNORE_BAD_MSR 0
diff -ur bochs/configure.in bochs-trace-cache/configure.in
--- bochs/configure.in	2007-11-26 22:38:39.000000000 +0200
+++ bochs-trace-cache/configure.in	2007-11-28 00:16:43.312500000 +0200
@@ -1006,6 +1006,27 @@
     ]
   )
