 +				synthetic_phase = (d_t * global_period) +
 +				((p_m * ((global_period * 100) / 8) / 100));
 +
-+				delta_p = abs(synthetic_phase - *period_offset);
++				delta_p = abs(synthetic_phase - *period_off);
 +				if (delta_p < min_p) {
 +					min_p = delta_p;
 +					lcko->phase.phase_mux = p_m;

+	return container_of(clk_hw, struct litex_clk_clkout, clk_hw);
+}
+
+/* Clock control driver functions */
+static inline void litex_clk_set_reg(struct clk_hw *clk_hw, u32 reg, u32 val)
+{
+	struct litex_clk_clkout *l_clk = clk_hw_to_litex_clk_clkout(clk_hw);
+
+	litex_set_reg(l_clk->base + drp[reg].offset, drp[reg].size, val);
+}
+
+static inline u32 litex_clk_get_reg(struct clk_hw *clk_hw, u32 reg)
+{
+	struct litex_clk_clkout *l_clk = clk_hw_to_litex_clk_clkout(clk_hw);
+
+	return litex_get_reg(l_clk->base + drp[reg].offset, drp[reg].size);
+}
+
+static inline void litex_clk_assert_reg(struct clk_hw *clk_hw, u32 reg)

+/* Set default clock value from device tree for given clkout*/
+static int litex_clk_set_def_clkout(struct clk_hw *hw)
+{
+	struct litex_clk_clkout *lcko = clk_hw_to_litex_clk_clkout(hw);
+	int ret;
+
+	litex_clk_round_rate(hw, lcko->def.freq, 0);
+	ret = litex_clk_set_rate(hw, lcko->def.freq, 0);
+	if (ret != 0)
+		return ret;
+	ret = litex_clk_set_duty_cycle(hw, &lcko->def.duty);
+	if (ret != 0)
+		return ret;
+	return litex_clk_set_phase(hw, lcko->def.phase);
+}
+
+static int litex_clk_set_all_def_clkouts(void)
