 +#define ISPPRV_YC_MAX			0xFF
 +#define ISPPRV_YC_MIN			0x0
 +
-+
-+
-+
 +/* Define bit fields within selected registers */
-+
-+#define ISP_REVISION_SHIFT		0
-+
-+#define ISP_SYSCONFIG_AUTOIDLE		0
-+#define ISP_SYSCONFIG_SOFTRESET	(1<<1)
-+#define ISP_SYSCONFIG_MIdleMode_SHIFT	12
-+#define ISP_SYSCONFIG_MIdleMode_ForceStandBy	0x0
-+#define ISP_SYSCONFIG_MIdleMode_NoStandBy	0x1
-+#define ISP_SYSCONFIG_MIdleMode_SmartStandBy	0x2
-+
-+#define ISP_SYSSTATUS_ResetDone		0
++#define ISP_REVISION_SHIFT			0
++
++#define ISP_SYSCONFIG_AUTOIDLE			0
++#define ISP_SYSCONFIG_SOFTRESET			(1 << 1)
++#define ISP_SYSCONFIG_MIDLEMODE_SHIFT		12
++#define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY	0x0
++#define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY	0x1
++#define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY	0x2
++
++#define ISP_SYSSTATUS_RESETDONE			0
 +
 +#define IRQ0ENABLE_CSIA_IRQ			1
-+#define IRQ0ENABLE_CSIA_LC1_IRQ		(1<<1)
-+#define IRQ0ENABLE_CSIA_LC2_IRQ		(1<<2)
-+#define IRQ0ENABLE_CSIA_LC3_IRQ		(1<<3)
-+#define IRQ0ENABLE_CSIB_IRQ			(1<<4)
-+#define IRQ0ENABLE_CSIB_LC1_IRQ		(1<<5)
-+#define IRQ0ENABLE_CSIB_LC2_IRQ		(1<<6)
-+#define IRQ0ENABLE_CSIB_LC3_IRQ		(1<<7)
-+#define IRQ0ENABLE_CCDC_VD0_IRQ		(1<<8)
-+#define IRQ0ENABLE_CCDC_VD1_IRQ		(1<<9)
-+#define IRQ0ENABLE_CCDC_VD2_IRQ		(1<<10)
-+#define IRQ0ENABLE_CCDC_ERR_IRQ		(1<<11)
-+#define IRQ0ENABLE_H3A_AF_DONE_IRQ		(1<<12)
-+#define IRQ0ENABLE_H3A_AWB_DONE_IRQ		(1<<13)
-+#define IRQ0ENABLE_HIST_DONE_IRQ		(1<<16)
-+#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ		(1<<17)
-+#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ		(1<<18)
-+#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ		(1<<19)
-+#define IRQ0ENABLE_PRV_DONE_IRQ		(1<<20)
-+#define IRQ0ENABLE_RSZ_DONE_IRQ		(1<<24)
-+#define IRQ0ENABLE_OVF_IRQ			(1<<25)
-+#define IRQ0ENABLE_PING_IRQ			(1<<26)
-+#define IRQ0ENABLE_PONG_IRQ			(1<<27)
-+#define IRQ0ENABLE_MMU_ERR_IRQ		(1<<28)
-+#define IRQ0ENABLE_OCP_ERR_IRQ		(1<<29)
-+#define IRQ0ENABLE_SEC_ERR_IRQ			(1<<30)
-+#define IRQ0ENABLE_HS_VS_IRQ			(1<<31)
++#define IRQ0ENABLE_CSIA_LC1_IRQ			(1 << 1)
++#define IRQ0ENABLE_CSIA_LC2_IRQ			(1 << 2)
++#define IRQ0ENABLE_CSIA_LC3_IRQ			(1 << 3)
++#define IRQ0ENABLE_CSIB_IRQ			(1 << 4)
++#define IRQ0ENABLE_CSIB_LC1_IRQ			(1 << 5)
++#define IRQ0ENABLE_CSIB_LC2_IRQ			(1 << 6)
++#define IRQ0ENABLE_CSIB_LC3_IRQ			(1 << 7)
++#define IRQ0ENABLE_CCDC_VD0_IRQ			(1 << 8)
++#define IRQ0ENABLE_CCDC_VD1_IRQ			(1 << 9)
++#define IRQ0ENABLE_CCDC_VD2_IRQ			(1 << 10)
++#define IRQ0ENABLE_CCDC_ERR_IRQ			(1 << 11)
++#define IRQ0ENABLE_H3A_AF_DONE_IRQ		(1 << 12)
++#define IRQ0ENABLE_H3A_AWB_DONE_IRQ		(1 << 13)
++#define IRQ0ENABLE_HIST_DONE_IRQ		(1 << 16)
++#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ		(1 << 17)
++#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ	(1 << 18)
++#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ	(1 << 19)
++#define IRQ0ENABLE_PRV_DONE_IRQ			(1 << 20)
++#define IRQ0ENABLE_RSZ_DONE_IRQ			(1 << 24)
++#define IRQ0ENABLE_OVF_IRQ			(1 << 25)
++#define IRQ0ENABLE_PING_IRQ			(1 << 26)
++#define IRQ0ENABLE_PONG_IRQ			(1 << 27)
++#define IRQ0ENABLE_MMU_ERR_IRQ			(1 << 28)
++#define IRQ0ENABLE_OCP_ERR_IRQ			(1 << 29)
++#define IRQ0ENABLE_SEC_ERR_IRQ			(1 << 30)
++#define IRQ0ENABLE_HS_VS_IRQ			(1 << 31)
 +
 +#define IRQ0STATUS_CSIA_IRQ			1
-+#define IRQ0STATUS_CSIA_LC1_IRQ		(1<<1)
-+#define IRQ0STATUS_CSIA_LC2_IRQ		(1<<2)
-+#define IRQ0STATUS_CSIA_LC3_IRQ		(1<<3)
-+#define IRQ0STATUS_CSIB_IRQ			(1<<4)
-+#define IRQ0STATUS_CSIB_LC1_IRQ		(1<<5)
-+#define IRQ0STATUS_CSIB_LC2_IRQ		(1<<6)
-+#define IRQ0STATUS_CSIB_LC3_IRQ		(1<<7)
-+#define IRQ0STATUS_CCDC_VD0_IRQ		(1<<8)
-+#define IRQ0STATUS_CCDC_VD1_IRQ		(1<<9)
-+#define IRQ0STATUS_CCDC_VD2_IRQ		(1<<10)
-+#define IRQ0STATUS_CCDC_ERR_IRQ		(1<<11)
-+#define IRQ0STATUS_H3A_AF_DONE_IRQ		(1<<12)
-+#define IRQ0STATUS_H3A_AWB_DONE_IRQ		(1<<13)
-+#define IRQ0STATUS_HIST_DONE_IRQ		(1<<16)
-+#define IRQ0STATUS_PRV_DONE_IRQ		(1<<20)
-+#define IRQ0STATUS_RSZ_DONE_IRQ		(1<<24)
-+#define IRQ0STATUS_OVF_IRQ			(1<<25)
-+#define IRQ0STATUS_PING_IRQ			(1<<26)
-+#define IRQ0STATUS_PONG_IRQ			(1<<27)
-+#define IRQ0STATUS_MMU_ERR_IRQ		(1<<28)
-+#define IRQ0STATUS_OCP_ERR_IRQ			(1<<29)
-+#define IRQ0STATUS_SEC_ERR_IRQ			(1<<30)
-+#define IRQ0STATUS_HS_VS_IRQ			(1<<31)
++#define IRQ0STATUS_CSIA_LC1_IRQ			(1 << 1)
++#define IRQ0STATUS_CSIA_LC2_IRQ			(1 << 2)
++#define IRQ0STATUS_CSIA_LC3_IRQ			(1 << 3)
++#define IRQ0STATUS_CSIB_IRQ			(1 << 4)
++#define IRQ0STATUS_CSIB_LC1_IRQ			(1 << 5)
++#define IRQ0STATUS_CSIB_LC2_IRQ			(1 << 6)
++#define IRQ0STATUS_CSIB_LC3_IRQ			(1 << 7)
++#define IRQ0STATUS_CCDC_VD0_IRQ			(1 << 8)
++#define IRQ0STATUS_CCDC_VD1_IRQ			(1 << 9)
++#define IRQ0STATUS_CCDC_VD2_IRQ			(1 << 10)
++#define IRQ0STATUS_CCDC_ERR_IRQ			(1 << 11)
++#define IRQ0STATUS_H3A_AF_DONE_IRQ		(1 << 12)
++#define IRQ0STATUS_H3A_AWB_DONE_IRQ		(1 << 13)
++#define IRQ0STATUS_HIST_DONE_IRQ		(1 << 16)
++#define IRQ0STATUS_PRV_DONE_IRQ			(1 << 20)
++#define IRQ0STATUS_RSZ_DONE_IRQ			(1 << 24)
++#define IRQ0STATUS_OVF_IRQ			(1 << 25)
++#define IRQ0STATUS_PING_IRQ			(1 << 26)
++#define IRQ0STATUS_PONG_IRQ			(1 << 27)
++#define IRQ0STATUS_MMU_ERR_IRQ			(1 << 28)
++#define IRQ0STATUS_OCP_ERR_IRQ			(1 << 29)
++#define IRQ0STATUS_SEC_ERR_IRQ			(1 << 30)
++#define IRQ0STATUS_HS_VS_IRQ			(1 << 31)
 +
 +#define TCTRL_GRESET_LEN			0
 +
 +#define TCTRL_PSTRB_REPLAY_DELAY		0
 +#define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT	25
 +
-+#define ISPCTRL_PAR_SER_CLK_SEL_parallel	0x0
++#define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL	0x0
 +#define ISPCTRL_PAR_SER_CLK_SEL_CSIA		0x1
 +#define ISPCTRL_PAR_SER_CLK_SEL_CSIB		0x2
 +#define ISPCTRL_PAR_SER_CLK_SEL_MASK		0xFFFFFFFC
 +
-+#define ISPCTRL_PAR_BRIDGE_SHIFT	2
-+#define ISPCTRL_PAR_BRIDGE_DISABLE	(0x0 << 2)
-+#define ISPCTRL_PAR_BRIDGE_LENDIAN	(0x2 << 2)
-+#define ISPCTRL_PAR_BRIDGE_BENDIAN	(0x3 << 2)
-+
-+#define ISPCTRL_PAR_CLK_POL_SHIFT	4
-+#define ISPCTRL_PAR_CLK_POL_INV	(1 << 4)
-+#define ISPCTRL_PING_PONG_EN		(1 << 5)
-+#define ISPCTRL_SHIFT_SHIFT		6
-+#define ISPCTRL_SHIFT_0			(0x0 << 6)
-+#define ISPCTRL_SHIFT_2			(0x1 << 6)
-+#define ISPCTRL_SHIFT_4			(0x2 << 6)
-+#define ISPCTRL_SHIFT_MASK		(~(0x3 << 6))
-+
-+#define ISPCTRL_CCDC_CLK_EN		(1 << 8)
-+#define ISPCTRL_SCMP_CLK_EN		(1 << 9)
-+#define ISPCTRL_H3A_CLK_EN		(1 << 10)
-+#define ISPCTRL_HIST_CLK_EN		(1 << 11)
-+#define ISPCTRL_PREV_CLK_EN		(1 << 12)
-+#define ISPCTRL_RSZ_CLK_EN		(1 << 13)
-+#define ISPCTRL_SYNC_DETECT_SHIFT	14
-+#define ISPCTRL_SYNC_DETECT_HSFALL	0x0
-+#define ISPCTRL_SYNC_DETECT_HSRISE	0x1
-+#define ISPCTRL_SYNC_DETECT_VSFALL	0x2
-+#define ISPCTRL_SYNC_DETECT_VSRISE	0x3
++#define ISPCTRL_PAR_BRIDGE_SHIFT		2
++#define ISPCTRL_PAR_BRIDGE_DISABLE		(0x0 << 2)
++#define ISPCTRL_PAR_BRIDGE_LENDIAN		(0x2 << 2)
++#define ISPCTRL_PAR_BRIDGE_BENDIAN		(0x3 << 2)
++
++#define ISPCTRL_PAR_CLK_POL_SHIFT		4
++#define ISPCTRL_PAR_CLK_POL_INV			(1 << 4)
++#define ISPCTRL_PING_PONG_EN			(1 << 5)
++#define ISPCTRL_SHIFT_SHIFT			6
++#define ISPCTRL_SHIFT_0				(0x0 << 6)
++#define ISPCTRL_SHIFT_2				(0x1 << 6)
++#define ISPCTRL_SHIFT_4				(0x2 << 6)
++#define ISPCTRL_SHIFT_MASK			(~(0x3 << 6))
++
++#define ISPCTRL_CCDC_CLK_EN			(1 << 8)
++#define ISPCTRL_SCMP_CLK_EN			(1 << 9)
++#define ISPCTRL_H3A_CLK_EN			(1 << 10)
++#define ISPCTRL_HIST_CLK_EN			(1 << 11)
++#define ISPCTRL_PREV_CLK_EN			(1 << 12)
++#define ISPCTRL_RSZ_CLK_EN			(1 << 13)
++#define ISPCTRL_SYNC_DETECT_SHIFT		14
++#define ISPCTRL_SYNC_DETECT_HSFALL	(0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_HSRISE	(0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_VSFALL	(0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_VSRISE	(0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
++#define ISPCTRL_SYNC_DETECT_MASK	(0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
 +
 +#define ISPCTRL_CCDC_RAM_EN		(1 << 16)
 +#define ISPCTRL_PREV_RAM_EN		(1 << 17)
 +#define ISPCTRL_SBL_RD_RAM_EN		(1 << 18)
-+#define ISPCTRL_SBL_WR1_RAM_EN	(1 << 19)
-+#define ISPCTRL_SBL_WR0_RAM_EN	(1 << 20)
-+#define ISPCTRL_SBL_AutoIdle		(1 << 21)
++#define ISPCTRL_SBL_WR1_RAM_EN		(1 << 19)
++#define ISPCTRL_SBL_WR0_RAM_EN		(1 << 20)
++#define ISPCTRL_SBL_AUTOIDLE		(1 << 21)
 +#define ISPCTRL_SBL_SHARED_RPORTB	(1 << 28)
 +#define ISPCTRL_JPEG_FLUSH		(1 << 30)
 +#define ISPCTRL_CCDC_FLUSH		(1 << 31)
 +
-+#define ISPSECURE_SecureMode		0
++#define ISPSECURE_SECUREMODE		0
++
++#define ISPTCTRL_CTRL_DIV_LOW		0x0
++#define ISPTCTRL_CTRL_DIV_HIGH		0x1
++#define ISPTCTRL_CTRL_DIV_BYPASS	0x1F
 +
 +#define ISPTCTRL_CTRL_DIVA_SHIFT	0
 +#define ISPTCTRL_CTRL_DIVA_MASK		(0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
-+#define ISPTCTRL_CTRL_DIVA_Low		0x0
-+#define ISPTCTRL_CTRL_DIVA_High	 	0x1
-+#define ISPTCTRL_CTRL_DIVA_Bypass	0x1F
 +
 +#define ISPTCTRL_CTRL_DIVB_SHIFT	5
 +#define ISPTCTRL_CTRL_DIVB_MASK		(0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
-+#define ISPTCTRL_CTRL_DIVB_Low		(0x0 << 5)
-+#define ISPTCTRL_CTRL_DIVB_High		(0x1 << 5)
-+#define ISPTCTRL_CTRL_DIVB_Bypass	(0x1F << 5)
 +
 +#define ISPTCTRL_CTRL_DIVC_SHIFT	10
-+#define ISPTCTRL_CTRL_DIVC_NoClock	(0x0 << 10)
++#define ISPTCTRL_CTRL_DIVC_NOCLOCK	(0x0 << 10)
 +
 +#define ISPTCTRL_CTRL_SHUTEN		(1 << 21)
 +#define ISPTCTRL_CTRL_PSTRBEN		(1 << 22)

+
+		for (i = 0; i < H3A_MAX_BUFF; i++) {
+			afstat.af_buff[i].virt_addr =
+				(unsigned long)dma_alloc_coherent(NULL,
+						afstat.min_buf_size,
+						(dma_addr_t *)
+						 &afstat.af_buff[i].phy_addr,
+						GFP_KERNEL | GFP_DMA);
+			if (afstat.af_buff[i].virt_addr == 0) {
+				printk(KERN_ERR "Can't acquire memory for "
+					"buffer[%d]\n", i);
+				return -ENOMEM;
+			}
+			afstat.af_buff[i].addr_align =
+					afstat.af_buff[i].virt_addr;
+			while ((afstat.af_buff[i].addr_align & 0xFFFFFFC0) !=
+				       afstat.af_buff[i].addr_align)
+				afstat.af_buff[i].addr_align++;
+			afstat.af_buff[i].ispmmu_addr =
+				ispmmu_map(afstat.af_buff[i].phy_addr,
+					   afstat.min_buf_size);
+		}
+		isp_af_unlock_buffers();
+		isp_af_link_buffers();

+#ifndef OMAP_ISP_PREVIEW_H
+#define OMAP_ISP_PREVIEW_H
+
+#include <mach/isp_user.h>
+/* Isp query control structure */
+
+#define ISPPRV_BRIGHT_STEP		0x1
+#define ISPPRV_BRIGHT_DEF		0x0
+#define ISPPRV_BRIGHT_LOW		0x0
+#define ISPPRV_BRIGHT_HIGH		0xF
+#define ISPPRV_BRIGHT_UNITS		0x7
+
+#define ISPPRV_CONTRAST_STEP		0x1
+#define ISPPRV_CONTRAST_DEF		0x4
+#define ISPPRV_CONTRAST_LOW		0x0
+#define ISPPRV_CONTRAST_HIGH		0xF
+#define ISPPRV_CONTRAST_UNITS		0x4
+
+#define NO_AVE				0x0
+#define AVE_2_PIX			0x1
+#define AVE_4_PIX			0x2
+#define AVE_8_PIX			0x3
+#define AVE_ODD_PIXEL_DIST		(1 << 4) /* For Bayer Sensors */
+#define AVE_EVEN_PIXEL_DIST		(1 << 2)
+
+#define WB_GAIN_MAX			4
+
+/* Features list */
+#define PREV_AVERAGER			(1 << 0)
+#define PREV_INVERSE_ALAW 		(1 << 1)
+#define PREV_HORZ_MEDIAN_FILTER		(1 << 2)
+#define PREV_NOISE_FILTER 		(1 << 3)
+#define PREV_CFA			(1 << 4)
+#define PREV_GAMMA_BYPASS		(1 << 5)
+#define PREV_LUMA_ENHANCE		(1 << 6)
+#define PREV_CHROMA_SUPPRESS		(1 << 7)
+#define PREV_DARK_FRAME_SUBTRACT	(1 << 8)
+#define PREV_LENS_SHADING		(1 << 9)
+#define PREV_DARK_FRAME_CAPTURE		(1 << 10)
+#define PREV_DEFECT_COR			(1 << 11)
+
+
+#define ISP_NF_TABLE_SIZE 		(1 << 10)
+
+#define ISP_GAMMA_TABLE_SIZE 		(1 << 10)
+
+/* Table addresses */
+#define ISPPRV_TBL_ADDR_RED_G_START  0x00
+#define ISPPRV_TBL_ADDR_BLUE_G_START  0x800
+#define ISPPRV_TBL_ADDR_GREEN_G_START  0x400
+
+/*
+ *Enumeration Constants for input and output format
