 +}
 +
 +defm : VecStPat<store, V_ST32X8>;
++*/
++
++
++
++// Temporary
++def V_LD32X8 : Load_vri<0b111, "v.ld32x8", int_riscv_v_ld32x8>;
++def : Pat<(v32i8 (load GPR:$rs1)), (V_LD32X8 GPR:$rs1, 0)>;
++
++def V_ST32X8 : Store_vri<0b100, "v.st32x8", int_riscv_v_st32x8>;
++def : Pat<(store (v32i8 VPR:$rs2), GPR:$rs1), (V_ST32X8 VPR:$rs2, GPR:$rs1, 0)>;
 -- 
 1.7.9.msysgit.0
 

From 3a9de9c042789b75d28b068966d9b6a9b1bd01c5 Mon Sep 17 00:00:00 2001
From: Min Chen <chenm003@163.com>
Date: Fri, 20 Oct 2017 17:17:41 -0500
Subject: [PATCH] x266 RISC-V Vector Extension

---
 include/llvm/IR/Intrinsics.td                      |    1 +
 include/llvm/IR/IntrinsicsRISCV.td                 |   29 ++++++
 lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp      |    9 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp       |   26 +++++
 lib/Target/RISCV/RISCVISelLowering.cpp             |   84 ++++++++++++++++
 lib/Target/RISCV/RISCVInstrInfo.td                 |    2 +
 lib/Target/RISCV/RISCVInstrInfoV.td                |  102 ++++++++++++++++++++
 lib/Target/RISCV/RISCVIntrinsics.td                |   40 ++++++++
 8 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/llvm/IR/IntrinsicsRISCV.td
 create mode 100644 lib/Target/RISCV/RISCVInstrInfoV.td
 create mode 100644 lib/Target/RISCV/RISCVIntrinsics.td

+def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
+def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
+
+/*
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class Vec0_LDvri<bits<6> funct6, string opcodestr, Intrinsic IntOP> :
+      RVInstVI<funct6, OPC_CUSTOM0, (outs VPR:$rd), (ins GPR:$rs1, simm9:$imm9),
