 +  let Opcode = opcode.Value;
 +}
 +
++class RVInstI_Ext<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
++              string opcodestr, string argstr, list<dag> pattern>
++    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatI> {
++  bits<12> imm12;
++  bits<5> rs1;
++  bits<5> rd;
++
++  let Inst{31-20} = imm12;
++  let Inst{19-15} = rs1;
++  let Inst{14-12} = funct3;
++  let Inst{11-7} = rd;
++  let Opcode = opcode.Value;
++}
++
++class RVInstS_Ext<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
++              string opcodestr, string argstr, list<dag> pattern>
++    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatS> {
++  bits<12> imm12;
++  bits<5> rs2;
++  bits<5> rs1;
++
++  let Inst{31-25} = imm12{11-5};
++  let Inst{24-20} = rs2;
++  let Inst{19-15} = rs1;
++  let Inst{14-12} = funct3;
++  let Inst{11-7} = imm12{4-0};
++  let Opcode = opcode.Value;
++}
++
++
 +def simm9 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<9>(Imm);}]> {
 +  let ParserMatchClass = SImmAsmOperand<9>;
 +  let EncoderMethod = "getImmOpValue";

+}
+
+defm : VecStPat<store, V_ST32X8>;
-- 
1.7.9.msysgit.0


+}
+
+defm : VecLdPat<load, V_LD32X8>;
+*/
+
+//======
+// Store
+//======
+
+/*
+def V_ST32X8 : Vec0_STvri<0b000001, "v.st32x8", int_riscv_v_st32x8>, Requires<[IsRV32]>;
+
+multiclass VecStPat<PatFrag StoreOp, RVInst Inst> {
+  def : Pat<(StoreOp (v32i8 VPR:$rs2), GPR:$rs1), (Inst VPR:$rs2, GPR:$rs1, 0)>;
