 +      - const: CLKOUT5
 +      - const: CLKOUT6
 +
-+  litex,nclkout:
-+    description: |
-+      Number of desired clock outputs
-+
-+        min: 1
-+        max: 7
-+
 +  litex,lock-timeout:
 +    description: |
 +      Number of ms to wait for MMCM to assert LOCK signal

+        min: 1
+        max: 100
+
+    required:
+      - compatible
+      - "#clock-cells"
+      - clock-output-names
+      - reg
+      - litex,clock-frequency
+      - litex,clock-phase
+      - litex,clock-duty-num
+      - litex,clock-duty-den
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#address-cells"
+  - "#size-cells"
+  - clock-output-names
+  - litex,nclkout
+  - CLKOUTx
+
+examples:
+  - |
+    clk0: clk@f0003000 {
+            compatible = "litex,clk";
+            reg = <0x0 0xf0003000 0x0 0x100>;
+            #clock-cells =        <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            clock-output-names = "CLKOUT0",
+                                 "CLKOUT1",
+                                 "CLKOUT2",
+                                 "CLKOUT3",
+                                 "CLKOUT4",
+                                 "CLKOUT5",
+                                 "CLKOUT6";
+            litex,nclkout = <7>;
+
+            CLKOUT0: CLKOUT0 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT0";
+                    reg = <0>;
+                    litex,clock-frequency = <50000000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT1: CLKOUT1 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT1";
+                    reg = <1>;
+                    litex,clock-frequency = <50000000>;
+                    litex,clock-phase = <90>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT2: CLKOUT2 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT2";
+                    reg = <2>;
+                    litex,clock-frequency = <25000000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <25>;
+            };
+
+            CLKOUT3: CLKOUT3 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT3";
+                    reg = <3>;
+                    litex,clock-frequency = <12500000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <75>;
+            };
+
+            CLKOUT4: CLKOUT4 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT4";
+                    reg = <4>;
+                    litex,clock-frequency = <6250000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT5: CLKOUT5 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT5";
+                    reg = <5>;
+                    litex,clock-frequency = <3125000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT6: CLKOUT6 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT6";
+                    reg = <6>;
+                    litex,clock-frequency = <1562500>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <5>;
+            };
+    };
+...
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index d2f0bb5ba47e..0280f9b9bb1d 100644

+        description: |
+          default frequency in Hz for clock output
+
+      litex,clock-phase:
+        description: |
+          default phase offset given in degrees
