      }
    }
  
-+#if BX_SUPPORT_ICACHE
++#if BX_SUPPORT_TRACE_CACHE
 +  if (attr & BxTraceEnd) instruction->setStopTraceAttr();
 +#endif
 +
    imm_mode = attr & BxImmediate;
    if (imm_mode) {
      switch (imm_mode) {
-@@ -2937,8 +2942,16 @@
+@@ -2938,8 +2943,16 @@
    if (BX_NULL_SEG_REG(instruction->seg()))
       instruction->setSeg(BX_SEG_REG_DS);
  
-+#if BX_SUPPORT_ICACHE
++#if BX_SUPPORT_TRACE_CACHE
 +  // set stop-trace attribute for invalid instructions
 +  if(instruction->execute == &BX_CPU_C::BxError) {
 +     instruction->setStopTraceAttr();

   }
 };
 // <TAG-CLASS-INSTRUCTION-END>
@@ -2917,7 +2927,12 @@
 #if BX_SUPPORT_X86_64
   BX_SMF unsigned fetchDecode64(Bit8u *, bxInstruction_c *, unsigned);
 #endif
+#if BX_SUPPORT_ICACHE
+  BX_SMF bxICacheEntry_c* fetchInstructionTrace(bxInstruction_c *, bx_address);
+  BX_SMF bx_bool mergeTraces(bxICacheEntry_c *trace, bxInstruction_c *i, bx_phy_address pAddr);
+#else

   /* 0F B8 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8q },
-  /* 0F B9 /qm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
+  /* 0F B9 /qm */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
   /* 0F BA /qm */ { BxGroup8, NULL, BxOpcodeInfo64G8EqIbM },
   /* 0F BB /qm */ { BxLockable, &BX_CPU_C::BTC_EqGqM },
   /* 0F BC /qm */ { 0, &BX_CPU_C::BSF_GqEq },
@@ -3768,10 +3768,15 @@
     // mod == 0xc0 can't be BxLockable in fetchdecode tables
     if (/*(mod == 0xc0) ||*/ !(attr & BxLockable)) {
       BX_INFO(("LOCK prefix unallowed (op1=0x%x, mod=%u, nnn=%u)", b1, mod, nnn));
-      UndefinedOpcode(instruction);
+      // replace execution function with undefined-opcode
