  };
  
  #define AVA2_WRITE_SIZE (sizeof(struct avalon2_pkg))
-@@ -145,7 +155,8 @@ struct avalon2_info {
+@@ -145,7 +156,9 @@ struct avalon2_info {
  extern char *set_avalon2_fan(char *arg);
  extern char *set_avalon2_freq(char *arg);
  extern char *set_avalon2_voltage(char *arg);

 	char mm_version[AVA2_DEFAULT_MODULARS][16];
 
 	struct cgpu_info *avalon2;
@@ -558,24 +620,29 @@ static bool avalon2_detect_one(const char *devpath)
 	}
 	tcflush(fd, TCIOFLUSH);
 

 #define AVA2_DEFAULT_MODULARS	4
 
 #define AVA2_PWM_MAX	0x3FF
@@ -30,15 +28,24 @@
 #define AVA2_DEFAULT_FAN_MIN	0
 #define AVA2_DEFAULT_FAN_MAX	100
 
-#define AVA2_DEFAULT_VOLTAGE	10000 /* V * 10000 */
+#define AVALON2_TEMP_OVERHEAT	88
+#define AVALON2_DEFAULT_POLLING_DELAY	20 /* ms */
+
 #define AVA2_DEFAULT_VOLTAGE_MIN	6000
 #define AVA2_DEFAULT_VOLTAGE_MAX	11000
