RISCVEMU: 128 bit RISC-V emulator
I understand that designing processors is fun, but I hold several things against RISC-V:<p>- the assembler dst, src backward syntax (like intel);<p>- the fact that this processor design is being aggressively pushed here (featured several times already);<p>- the fact that the instruction set is non-orthogonal (32-bit fixed encoding makes the decoder simple, but creates the same load-store problem as on SPARC - hello non-existent, synthetic instructions!);<p>- the fact that they could have extended the open source UltraSPARC T-series design, but decided to just re-invent the wheel all over again. How does 128-bit support justify starting from scratch, and not re-using what is already there and open sourced?<p>The last point is their biggest sin, in my view. There is already an open source processor design, and a good, solid design, and they just went ahead and invented their own anyway. All the lessons about reuse went out of the window. We're the only industry that I know of that keeps nuking itself and starting from scratch, throwing away all the work which had been done before.<p>Oh, and I seriously dislike the instruction mnemonics. To the authors of RISC-V:<p>couldn't you have made the mnemonics MC68000 compatible, or at least make them similar?