FPGA Design for Software Engineers
The problem of FPGAs is their proprietary nature, and Verilog/VHDL are far from the best languages. Gladly there is a number of open-source projects aiming to close this gap - Yosys[1], SymbiFlow[2], Chisel3[3]/FIRRTL[4]. Some time ago I suggested[5] different open source projects should unite and reuse the common intermediate language, akin to LLVM in many software development and analysis tools. From my point of view, FIRRTL is the best designed one, there is a huge problem of being implemented in Scala though, especially for C/C++/etc written projects. Hopefully, there will be more collaboration one day. Either reimplementation from scratch, e.g. in Rust or C++, or using Scala Native.<p>[1] <a href="https://github.com/YosysHQ" rel="nofollow">https://github.com/YosysHQ</a><p>[2] <a href="https://symbiflow.github.io/" rel="nofollow">https://symbiflow.github.io/</a><p>[3] <a href="https://www.chisel-lang.org/" rel="nofollow">https://www.chisel-lang.org/</a><p>[4] <a href="https://www.chisel-lang.org/firrtl/" rel="nofollow">https://www.chisel-lang.org/firrtl/</a><p>[5] <a href="https://github.com/SymbiFlow/ideas/issues/19" rel="nofollow">https://github.com/SymbiFlow/ideas/issues/19</a>