ULX3S: Hackable FPGA that runs Linux on RISC-V
Is there any published rationale for the RISC-V instruction encoding?<p>A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables.<p>But the instruction encoding is much more irregular than I expected: <a href="https://github.com/ucb-bar/riscv-sodor/blob/master/src/common/instructions.scala" rel="nofollow">https://github.com/ucb-bar/riscv-sodor/blob/master/src/commo...</a><p>In particular:<p><pre><code>    - The bit patterns allocated to the simplest instructions
      (eg. rv32i) seem random. Why not allocate starting from zero
      to allow dense jump tables?
    - I can't make any sense of the groupings. A bunch of instructions
      have 0b1100011 in the lowest bits, do these instructions have
      something in common?
</code></pre>
I assume there is some rhyme and reason to all this?  Where is this explained?