Rules for new FPGA designers
> <i>Do not use an asynchronous reset within your design.</i><p>This is flat out wrong. Registers that drive output pins should <i>always</i> be reset asynchronously. If you're not careful with your board design, it can happen that your FPGA is powered and configured before your clock signal is available, especially if it is generated by a PLL. An asynchronous reset on the output IO registers ensures that you're not inadvertently driving external electronics with bogus signals.<p>For internal registers it usually doesn't matter whether they're reset synchronously or asynchronously. There are some cases where the synthesis software cannot move async. reset registers from flip-flops into built-in hard IP cores like DSP elements or block RAMs, so a sync. reset can make sense here for performance reasons.<p>There's one caveat, though: An async. reset signal <i>must</i> be released synchronously to the clock, or there <i>will</i> be timing errors. However, this is a tiny, simple construct easily written by any non-beginner.<p>(source: I design FPGAs for a living)