Cerebras’s giant chip will smash deep learning’s speed barrier
A chip that size, imagine the yield.  Equally, cooling - has to be water based as a heatsink that size would be on par to a small anvil and the weight factor would be some serious issues.  Though unsure as no pictures of it in-play alas and all they say is - "20 kilowatts being consumed by each blew out into the Silicon Valley streets through a hole cut into the wall", which does somewhat beg for a picture as just raises more questions.<p>Why would they make a chip this big with AMD showing a chiplet design approach is cheaper and more scalable on so many levels.  Let alone, yields.<p>Equally, arms approach to utilising the back of the chip as a power delivery :- <a href="https://spectrum.ieee.org/nanoclast/semiconductors/design/arm-shows-backside-power-delivery-as-path-to-further-moores-law" rel="nofollow">https://spectrum.ieee.org/nanoclast/semiconductors/design/ar...</a><p>Then a wafer scale chip like this, using that approach, would save so much power.  But again, yeilds will be a factor and can imagine this is not the cutting edge process node as you find as nodes mature, the yields improve.  So an older node size would have a better yield and be more suitable for such wafer scale chips.  But again, no mention of what is used.  I have read in the past that it would use Intel's 10nm, but this article mentions TSMC.  Another article I read that they used a 16nm node ( <a href="https://fuse.wikichip.org/news/3010/a-look-at-cerebras-wafer-scale-engine-half-square-foot-silicon-chip/" rel="nofollow">https://fuse.wikichip.org/news/3010/a-look-at-cerebras-wafer...</a> ), which as mentioned above about node maturity, understandable.