What do RISC and CISC mean in 2020?
The better explanation of RISC v CISC is this old discussion from comp.arch: <a href="https://yarchive.net/comp/risc_definition.html" rel="nofollow">https://yarchive.net/comp/risc_definition.html</a><p>In short, the term RISC comes from a new set of architecture designs in the late 80s/early 90s. CISC is not so much an architecture design as it is lacking many of the features. The major features that RISC adds are:<p>* Avoid complex operations, which may include things such as multiply and divide. (Although note that "modern" RISCs have these nowadays).<p>* More registers (32 registers instead of 8 or 16). (ARM has 16. So does x86-64.)<p>* Fixed-length instructions instead of variable-length.<p>* Avoid indirect memory references or a lot of memory accessing types (note that x86 also does this).<p>Functionally speaking, x86 itself is pretty close to RISC, especially in terms of how the operations themselves need to be implemented. The implementation benefits of RISC (especially in allowing pipelining) are largely applicable to x86 as well, since x86 really skips the problematic instructions that other CISCs have.<p>> One of the key ideas of RISC was to push a lot of heavy lifting over to the compiler. That is still the case. Micro-ops cannot be re-arranged by the compiler for optimal execution.<p>Modern compilers do use instruction scheduling to optimize execution, and instruction scheduling for microcoded execution is well-understood.<p>> Time is more critical when running micro-ops than when compiling. It is an obvious advantage in making it possible for advance compiler to rearrange code rather than relying on precious silicon to do it.<p>All modern high-performance chips are out-of-order execution, because some instructions (especially memory!) take longer than others to execute. The "precious silicon" is silicon that's already been used for that reason, whether RISC or CISC.