Is the x86 Architecture Sustainable?
Even ignoring CPU die size cost, there&#x27;s another cost to legacy features: some of those features have register state, and contexts switching it is expensive.  Simpler architectures can do crazy things like switching between threads in mere tens of cycles.  X86: not so much.  The OS needs to deal with DS, ES, FS, and GS, and the microcode needs to deal with CS, SS, and FLAGS.  The segment registers are almost useless these days, but saving and restoring them is very slow.<p>Even x86&#x27;s model of handling CPL (privilege level) isn&#x27;t ideal.  I&#x27;ve tried to push RISC-V toward a model where user and kernel code have entirely separate address spaces, which would let privilege handling move to the front end and potentially allow pipelining across privilege changes.  Amusingly, x86&#x27;s privilege mechanism is complicated enough that Intel implemented it wrong in a few CPUs with MPX, resulting in a bizarre erratum.<p>I would love to see x86 add a &quot;clean mode&quot; in which a lot of legacy features are inaccessible to user code.  Then kernels could try to run programs in clean mode and, if they don&#x27;t fault, context switching between clean mode threads would be much faster.