AVX-512: when and how to use these new instructions
This post cites sources that actively contradict the points it attempts to make. It provides a wealth of useful aggregation of information against the points it makes.<p>Let&#x27;s us begin<p><pre><code>    However, there are also deterministic frequency 
    reductions based specifically on which instructions you
    use and on how many cores are active (downclocking).
</code></pre>
As you are likely using AVX-512 in a cloud deployment you don&#x27;t have access to any of the information, and are likely sharing that hardware who may not respect the same engineering rigor.<p>Also, nobody setting there CPU affinity to ensure the down-clocking stays on a single core. You have to pray the scheduler doesn&#x27;t shuffle your workload around. This requires a lot of platform specific C and most people are writing Java&#x2F;Go&#x2F;Ruby&#x2F;Python where doing bit twidling NUMA management is impossible, furthermore the information you have access to in a cloud environment (which is where you&#x27;ll be using advanced AVX-512 unless you work for Amazon, Google, Intel, or Cloudflare) may just lie about core count, and NUMA architecture.<p>Also this is just false [1]. Running AVX-512 adjusts the BASE clock for the package. There are throttling attempts to ensure every other core on the package throttles back. This is a package wide effect, not a per-core effect.<p><pre><code>    Light instructions include integer operations other than
    multiplication, logical operations, data shuffling
    (such as vpermw and vpermd) and so forth.
</code></pre>
This is false according cloudflare [2] which you&#x27;ve linked. They test your &quot;light&quot; carry less adding, shifting, and xoring (these are the only operations in ChaCha20 [4]). It cost too much.<p><pre><code>    We have chosen to only include two columns.
</code></pre>
I&#x27;ll include the whole thing [3]. Wow yeah the entire package&#x27;s power curve is changing. The base clock, cores not effected, all their clocks are changing. Its almost like having 1 out of 24 cores still effects all 24 cores....<p><pre><code>    For example, the openssl project used heavy AVX-512
    instructions to bring down the cost of a particular
    hashing algorithm (poly1305) from 0.51 cycles per byte
    (when using 256-bit AVX instructions) to 0.35 cycles
    per byte, a 30% gain on a per-cycle basis. They have
    since disabled this optimization.
</code></pre>
The literal example to show AVX-512 is good at ends with statement that people using AVX-512 are now actively avoiding it.<p>This is less then content, do you have an agenda or are you just an idiot?<p>[1] <a href="https:&#x2F;&#x2F;en.wikichip.org&#x2F;wiki&#x2F;intel&#x2F;xeon_silver&#x2F;4116" rel="nofollow">https:&#x2F;&#x2F;en.wikichip.org&#x2F;wiki&#x2F;intel&#x2F;xeon_silver&#x2F;4116</a><p>[2] <a href="https:&#x2F;&#x2F;blog.cloudflare.com&#x2F;on-the-dangers-of-intels-frequency-scaling&#x2F;" rel="nofollow">https:&#x2F;&#x2F;blog.cloudflare.com&#x2F;on-the-dangers-of-intels-frequen...</a><p>[3] <a href="https:&#x2F;&#x2F;en.wikichip.org&#x2F;wiki&#x2F;intel&#x2F;xeon_gold&#x2F;5120" rel="nofollow">https:&#x2F;&#x2F;en.wikichip.org&#x2F;wiki&#x2F;intel&#x2F;xeon_gold&#x2F;5120</a><p>[4] <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Salsa20" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Salsa20</a>