Microcode Research Team
I would love to see an open-source x86 Microcode (or x86 subset Microcode) which would enable a separate open-source RISC CPU (i.e., <a href="https:&#x2F;&#x2F;opencores.org&#x2F;projects?expanded=Processor" rel="nofollow">https:&#x2F;&#x2F;opencores.org&#x2F;projects?expanded=Processor</a>) to run x86 instructions, or a subset of x86 instructions...<p>Perhaps the path to such an endeavor is simply taking an existing open-source FPGA RISC CPU (RISC-V would be a good choice) -- and then trying to implement a single x86 instruction in open-source Microcode, on it...<p>Success?<p>Well, then let&#x27;s try another x86 instruction!  Eventually we&#x27;ll have a few!<p>If this or other x86 microcodes are copyrighted and&#x2F;or patent-protected, what could occur is that a new microcode format (non-copyright or patent infringing) could be defined during this process...<p>Also, an x86 subset FPGA &quot;Soft&quot; CPU -- would never be as fast or as instruction-complete as current Intel or AMD CPU&#x27;s...<p>In other words, such devices would be for hobbyist and&#x2F;or educational use only -- they wouldn&#x27;t compete with current Intel or AMD CPU&#x27;s...