Why FPGA manufacturers keep their bitstream formats secret
Here&#x27;s my official prediction: there&#x27;s going to be a sea change in the FPGA market in the next five to ten years.  The reason FPGAs are so complex is that more than half of the die space is given over to the routing structures.  This means that to be even in the ballpark of ASIC performance they have to have a complicated mish-mash of logic tiles and all sorts of other special-purpose tiles (like arm cores etc.).<p>The die space issue is an artifact of using SRAM to store the configuration (likewise using flash is also too big and cumbersome), not to mention the power usage.  However, the new non-volatile memories coming up (like memristors or nano-ram) are absolutely minuscule and will have a dramatic effect on the competitiveness of FPGAs.  All the sudden you can have an extremely regular structure, with no specialized tiles, with performance comparable to ASICs.  In fact, there&#x27;s an argument that they will outperform ASICs because as we start getting into quantum effects because of die feature shrink, being able to function despite a relatively high degree of errors (which FPGAs can route around with minimal performance loss) will become a huge advantage.<p>Here&#x27;s a paper that talks about it:<p><a href="https:&#x2F;&#x2F;www.ece.ucsb.edu&#x2F;~strukov&#x2F;papers&#x2F;2006&#x2F;Worldcomp2006.pdf" rel="nofollow">https:&#x2F;&#x2F;www.ece.ucsb.edu&#x2F;~strukov&#x2F;papers&#x2F;2006&#x2F;Worldcomp2006....</a> [PDF]<p>The very regular structure of the iCE40 is quoted as a reason for its choice as a reverse-engineering target - this helps a great deal with the tooling issue.  If the above prediction is true, then FPGAs can potentially be: extremely regular, on par with ASIC performance, and potentially cheaper to produce because of economies of scale.  These factors will, I believe, change the dynamics of the market to a point where an open source FPGA is a viable option for crowd-sourcing.