Practice Problems for Hardware Engineers
Gone over sections 16..19 - Several questions are clearly nonsense, eg 17.11) &quot;MISR the BIST out of Z!Xussia&quot; or vague eg 16.4b) &quot;Explain at least 2 different types of data Perl&#x2F;Python can handle&quot;. Question 18.h) &quot;33-Dimensional Maze Router&quot; is more of a strange fever dream than an actual question<p>Section 17 is mostly testing for rote learning, I&#x27;m guessing these questions are taken from some university course?<p>My favourite quesiton is 18.a) &quot;Verilog Syntax&#x2F;compile errors&quot; which asks you to spot all the mistakes (while ignoring behaviour) and hint at a fix -- but since you&#x27;re allowed to ignore all behaviour a valid (and reasonable) fix is actually to delete it all.<p>Beyond these superficial issues I&#x27;m mostly interested because my company takes in a lot of EE graduates for beginner FPGA roles, and in our experience almost all undergraduate instructive material is 30 years out of date. Almost all graduates still seem to get taught that VLSI design is done by manually instantiating combinatorial gates and D type flip flops.<p>And in honesty, I think this document falls into the same trap, section 18 asks the learner to design a transparent latch as a single module. It&#x27;s very rare to want put a transparent latch in an FPGA, and you&#x27;d never dedicate an entire entity to describing one. It also asks for an 8-to-1 mux, a 4 bit shift register, and a 16 bit shift register.<p>However I think question 18.f) &quot;FSM – Verilog Design of a Crosswalk Controller&quot; is actually a very good example of the right sort of question (for, say midrange&#x2F;advanced beginner), which will focus the students&#x27; attention on &quot;normal&quot; RTL design. Specifically I like that is requires specific clock timings (assert X for 32 clock cycles, assert Y for 10 cycles), as I think off-by-one timing errors in FSMs are a very common problem for beginners.<p>A more difficult extension (perhaps a part of student&#x27;s first introduction to concurrency in an FPGA) would be to design a crosswalk controller with slightly more complexity.. maybe multiple buttons or multiple junctions or whatever.