Linus Torvalds: “Somebody is pushing complete garbage for unclear reasons.”
Haha, two mails down, David Woodhouse doesn&#x27;t disappoint and sends a message that&#x27;m copying here:<p><a href="http:&#x2F;&#x2F;lkml.iu.edu&#x2F;hypermail&#x2F;linux&#x2F;kernel&#x2F;1801.2&#x2F;05282.html" rel="nofollow">http:&#x2F;&#x2F;lkml.iu.edu&#x2F;hypermail&#x2F;linux&#x2F;kernel&#x2F;1801.2&#x2F;05282.html</a><p><pre><code>    I think we&#x27;ve covered the technical part of this now, not that you like
    it â not that any of us *like* it. But since the peanut gallery is
    paying lots of attention it&#x27;s probably worth explaining it a little
    more for their benefit.
    
    This is all about Spectre variant 2, where the CPU can be tricked into
    mispredicting the target of an indirect branch. And I&#x27;m specifically
    looking at what we can do on *current* hardware, where we&#x27;re limited to
    the hacks they can manage to add in the microcode.
    
    The new microcode from Intel and AMD adds three new features.
    
    One new feature (IBPB) is a complete barrier for branch prediction.
    After frobbing this, no branch targets learned earlier are going to be
    used. It&#x27;s kind of expensive (order of magnitude ~4000 cycles).
    
    The second (STIBP) protects a hyperthread sibling from following branch
    predictions which were learned on another sibling. You *might* want
    this when running unrelated processes in userspace, for example. Or
    different VM guests running on HT siblings.
    
    The third feature (IBRS) is more complicated. It&#x27;s designed to be
    set when you enter a more privileged execution mode (i.e. the kernel).
    It prevents branch targets learned in a less-privileged execution mode,
    BEFORE IT WAS MOST RECENTLY SET, from taking effect. But it&#x27;s not just
    a &#x27;set-and-forget&#x27; feature, it also has barrier-like semantics and
    needs to be set on *each* entry into the kernel (from userspace or a VM
    guest). It&#x27;s *also* expensive. And a vile hack, but for a while it was
    the only option we had.
    
    Even with IBRS, the CPU cannot tell the difference between different
    userspace processes, and between different VM guests. So in addition to
    IBRS to protect the kernel, we need the full IBPB barrier on context
    switch and vmexit. And maybe STIBP while they&#x27;re running.
    
    Then along came Paul with the cunning plan of &quot;oh, indirect branches
    can be exploited? Screw it, let&#x27;s not have any of *those* then&quot;, which
    is retpoline. And it&#x27;s a *lot* faster than frobbing IBRS on every entry
    into the kernel. It&#x27;s a massive performance win.
    
    So now we *mostly* don&#x27;t need IBRS. We build with retpoline, use IBPB
    on context switches&#x2F;vmexit (which is in the first part of this patch
    series before IBRS is added), and we&#x27;re safe. We even refactored the
    patch series to put retpoline first.
    
    But wait, why did I say &quot;mostly&quot;? Well, not everyone has a retpoline
    compiler yet... but OK, screw them; they need to update.
    
    Then there&#x27;s Skylake, and that generation of CPU cores. For complicated
    reasons they actually end up being vulnerable not just on indirect
    branches, but also on a &#x27;ret&#x27; in some circumstances (such as 16+ CALLs
    in a deep chain).
    
    The IBRS solution, ugly though it is, did address that. Retpoline
    doesn&#x27;t. There are patches being floated to detect and prevent deep
    stacks, and deal with some of the other special cases that bite on SKL,
    but those are icky too. And in fact IBRS performance isn&#x27;t anywhere
    near as bad on this generation of CPUs as it is on earlier CPUs
    *anyway*, which makes it not quite so insane to *contemplate* using it
    as Intel proposed.
    
    That&#x27;s why my initial idea, as implemented in this RFC patchset, was to
    stick with IBRS on Skylake, and use retpoline everywhere else. I&#x27;ll
    give you &quot;garbage patches&quot;, but they weren&#x27;t being &quot;just mindlessly
    sent around&quot;. If we&#x27;re going to drop IBRS support and accept the
    caveats, then let&#x27;s do it as a conscious decision having seen what it
    would look like, not just drop it quietly because poor Davey is too
    scared that Linus might shout at him again. :)
    
    I have seen *hand-wavy* analyses of the Skylake thing that mean I&#x27;m not
    actually lying awake at night fretting about it, but nothing concrete
    that really says it&#x27;s OK.
    
    If you view retpoline as a performance optimisation, which is how it
    first arrived, then it&#x27;s rather unconventional to say &quot;well, it only
    opens a *little* bit of a security hole but it does go nice and fast so
    let&#x27;s do it&quot;.
    
    But fine, I&#x27;m content with ditching the use of IBRS to protect the
    kernel, and I&#x27;m not even surprised. There&#x27;s a *reason* we put it last
    in the series, as both the most contentious and most dispensable part.
    I&#x27;d be *happier* with a coherent analysis showing Skylake is still OK,
    but hey-ho, screw Skylake.
    
    The early part of the series adds the new feature bits and detects when
    it can turn KPTI off on non-Meltdown-vulnerable Intel CPUs, and also
    supports the IBPB barrier that we need to make retpoline complete. That
    much I think we definitely *do* want. There have been a bunch of us
    working on this behind the scenes; one of us will probably post that
    bit in the next day or so.
    
    I think we also want to expose IBRS to VM guests, even if we don&#x27;t use
    it ourselves. Because Windows guests (and RHEL guests; yay!) do use it.
    
    If we can be done with the shouty part, I&#x27;d actually quite like to have
    a sensible discussion about when, if ever, we do IBPB on context switch
    (ptraceability and dumpable have both been suggested) and when, if
    ever, we set STIPB in userspace.</code></pre>