Moore's Law, AI, and the pace of progress
&gt;This is not merely a populist view by the <i>uninformed</i>.<p>Ok I will bite.<p>It is always easy to suggest Moore&#x27;s Law isn&#x27;t dead using Logarithmic scale. But if you only look at recent data. Let&#x27;s take TSMC 10nm, the moment which TSMC achieved its leading edge status from Intel, you then have 7nm, 5nm which we are currently on, the 3nm which <i>might</i> [0] ship in early 2023, and the expected 2nm in 2025. That is 2017 to 2025. There is nothing 2x &#x2F; 2 year within this period, even if you only use the best &#x2F; peak quoted [1] density matrices.<p>Let me just give this quoted density number using their node name [2]; in Million Transistors per mm2.<p>2015 - Intel 14nm - 44.67 [3]<p>2017 - TSMC 10nm - 52.51<p>2018 - TSMC 7nm -  91.20<p>2019 - 178.68 ( Hypothetical of Intel 14nm lineage at 2x &#x2F; 2 year )<p>2020 - TSMC 5nm - 171.30<p>2023 - TSMC 3nm - 292.21 ( EST )<p>2025 - IBM Research GAA 2nm - 333.33 ( EST ), TSMC GAA 2nm - ~500 ( EST ),<p>2025 - 1430 ( Hypothetical of Intel 14nm lineage at 2x &#x2F; 2 year  )<p>Notice where the trend starts to break? 2019 - 2020. [4]<p>And unless Intel or TSMC could adjust their 2025 - 2030 roadmap to somehow increase transistor density by <i>2.9x</i> every 2 years, they would not be back in the same trajectory as the original trend. So it either follows Power Law, or the next 5 - 10 years will be a beep &#x2F; outliner in Moore&#x27;s law history.<p>And it is not only Jensen, CEO of AMD Dr. Lisa Su made similar comments on Moore&#x27;s Law. And they are not wrong ( or <i>uninformed</i>, in fact they are too well informed ). In order to achieve 2x performance increase or 50% reduction in die size. Their Cost of Die, Cost of R&amp;D purely in terms of design and fabrication are increasing. Their total unit cost are increasing. GPU vendors are much more sensitive to this since their performance scales extremely well with transistor count. That is why chiplet and packaging has become important to solve this cost issues. ( They are not silver bullet )<p>There are also problems with 3D Stacking and layering. Which I have seen far too many people being completely dismissive of it, is thermal dynamics. You cant have a hundred layer of compute with each layer using 10W if not higher. It wasn&#x27;t until AMD made it absolutely clear with their V-Cache implementation, you cant have your SRAM layer on top of your compute layer due to heat issue did people start to realise their dream of a hundred layered GPU might not actually work. At least not between now and 2030.<p>Not only are DRAM not getting any price &#x2F; bit reduction in the past 10 years. NAND may see similar fate. We are getting faster, and lower power DRAM, but we are certainly not getting any cheaper DRAM [5]. And that is ignoring a majority of DRAM revenues comes from LPDDR and not normal DRAM. Which has a higher price per GB. NAND may have one or two generation to go in terms of cost reduction. ( Also worth looking at HDD Cost &#x2F; GB with similar trend. ) But those hundred layers of NAND are done by string stacking. Stacking up multiple of 60 &#x2F; 70 layers of stacks which has higher yield. Currently Samsung is the only one doing 128 layer single stack. Cell sizes hasn&#x27;t shrink much either due to error rate and cost until they moved to EUV. Moving from TLC to QLC and later PLC has diminishing returns. It may be worth pointing out the obvious, DRAM and NAND are commodities, and follows the rules of any commodity market.<p>It is not that we are not getting any more cost &#x2F; performance or IO or storage improvements. It&#x27;s just their rate are slowing.<p>[0] Originally scheduled for 2022 iPhone launch ( as usual ) but TSMC announced they had a three month ( one quarter ) delay. Assuming yield were good enough and no contractual obliteration for Apple to be the first using their 3nm you might see other vendor launch using 3nm in early 2023.<p>[1] Peak Quoted Transistor Densities -  Different Fabs may have different counting methodologies, they are estimated Logic Density. But give the best number from a marketing perspective.<p>[2] You should know these node number are marketing numbers, Every time we have a node discussion on HN there are people jumping over the node number are marketing number and how these numbers are wrong. And Samsung since 2020 ( again ) have their marketing spin on node numbers post 4nm.<p>[3] I already factor in Intel&#x27;s 14nm being 2.7x density increase over their 22nm. So the date started in 2015 instead of what should have been 2014. Intel&#x27;s marketing at one point were eager to push this narrative in 2019 during their 10nm fiasco.<p>[4] Which happens to be where the graph ends. In the past ~3 years there has been some sort of shift in the definition of Moore&#x27;s Law. Some people ( PR ) now use it to mean &quot;transistor improvements&quot;, whether you agree or disagree with that definition, no one is arguing we are not getting any more improvements.<p>[5] Until China joins the game and start dumping DRAM and NAND on to the market. Which is what they are already doing within China. They just haven&#x27;t succeeded in  catching up to the latest DRAM &#x2F; NAND quality yet.