Why does this code execute more slowly after strength-reducing multiplications?
Tldr: autovectorizer transforms the first code into SIMD instructions, but the second into 64 bit instructions.<p>SIMD is very powerful, and modern compilers can sometimes simd-ify your code automatically.<p>-------<p>The second code can probably become SIMD as well, but it&#x27;s beyond GCC&#x27;s ability to autovectorizer it in that form. I kinda want to give it a go myself but don&#x27;t have time today...<p>Autovectorizers are mysterious, often harder to see and use than explicitly SIMD code (like OpenCL or CUDA).