ZipCPU – A small, lightweight, RISC soft core in Verilog
Found some info in the repo&#x27;s issues about how much room ZipCPU takes on an FPGA:<p><a href="https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;issues&#x2F;8" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;issues&#x2F;8</a><p>PDFs:<p><a href="https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;blob&#x2F;master&#x2F;doc&#x2F;orconf.pdf" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;blob&#x2F;master&#x2F;doc&#x2F;orconf.pdf</a><p><a href="https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;blob&#x2F;master&#x2F;doc&#x2F;orconf2017.pdf" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;blob&#x2F;master&#x2F;doc&#x2F;orconf2017....</a><p><a href="https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;blob&#x2F;master&#x2F;doc&#x2F;orconf2018.pdf" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;ZipCPU&#x2F;zipcpu&#x2F;blob&#x2F;master&#x2F;doc&#x2F;orconf2018....</a><p>Also a list of FPGA dev boards as of 2018:<p><a href="https:&#x2F;&#x2F;www.reddit.com&#x2F;r&#x2F;FPGA&#x2F;comments&#x2F;9yutk8&#x2F;best_100300_fpga_development_board_in_2018&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.reddit.com&#x2F;r&#x2F;FPGA&#x2F;comments&#x2F;9yutk8&#x2F;best_100300_fp...</a><p>So looks like ZipCPU takes between 2400 and 7372 LUTs, depending on how optimized the routing is. An Ultra96 with 154k LUTs could hold between about 20 and 64 ZipCPUs, although busses would be an issue.<p>I&#x27;d like to see more of these projects start from a stance of connecting to other CPUs on the same chip rather than out to main memory. Or rather, a spec should only be considered complete when it has designs for both an in-mesh core to be placed beside its neighbors in a grid, and a bus-facing core for connecting out to main memory.<p>I think the future is going to be a series of basic blocks like CPUs, RAMs, maybe even GPUs that can be placed arbitrarily and run as clusters for tackling big data problems using techniques like map reduce. Or better yet, maybe FPGAs that look like multiple FPGAs (each with their own RAM) running on the same chip.