The Genius of RISC-V Microprocessors
I find it interesting that, in one aspect, ARM went into the opposite direction with its newer 64-bit ISA. Like with RISC-V, the designers of the 64-bit ARM ISA &quot;knew about instruction compression and macro-ops fusion when they began designing their ISA&quot; (32-bit ARM already had the alternative compressed ISAs Thumb&#x2F;Thumb2&#x2F;ThumbEE); however, they chose to use fixed-size 32-bit instructions without any compressed format. I suspect that they did it expecting that, once compatibility with the 32-bit ARM ISAs is removed on newer processors, the fixed-size instructions would allow for very wide decoders, like we&#x27;ve seen with Apple M1 (which can decode 8 instructions in parallel). It remains to be seen whether the RISC-V choice (the first two bits of every instruction are enough to determine the instruction length) will allow for a similarly wide decoder.