Implementing a GPU's programming model on a CPU
This so-called GPU programming model has existed many decades before the appearance of the first GPUs, but at that time the compilers were not so good like the CUDA compilers, so the burden for a programmer was greater.<p>As another poster has already mentioned, there exists a compiler for CPUs which has been inspired by CUDA and which has been available for many years: ISPC (Implicit SPMD Program Compiler), at <a href="https:&#x2F;&#x2F;github.com&#x2F;ispc&#x2F;ispc">https:&#x2F;&#x2F;github.com&#x2F;ispc&#x2F;ispc</a> .<p>NVIDIA has the very annoying habit of using a lot of terms that are different from those that have been previously used in computer science for decades. The worst is that NVIDIA has not invented new words, but they have frequently reused words that have been widely used with other meanings.<p>SIMT (Single-Instruction Multiple Thread) is not the worst term coined by NVIDIA, but there was no need for yet another acronym. For instance they could have used SPMD (Single Program, Multiple Data Stream), which dates from 1988, two decades before CUDA.<p>Moreover, SIMT is the same thing that was called &quot;array of processes&quot; by C.A.R. Hoare in August 1978 (in &quot;Communicating Sequential Processes&quot;), or &quot;replicated parallel&quot; by Occam in 1985 or &quot;PARALLEL DO&quot; by &quot;OpenMP Fortran&quot; in 1997-10 or &quot;parallel for&quot; by &quot;OpenMP C and C++&quot; in 1998-10.<p>Each so-called CUDA kernel is just the body of a &quot;parallel for&quot; (which is multi-dimensional, like in Fortran).<p>The only (but extremely important) innovation brought by CUDA is that the compiler is smart enough so that the programmer does not need to know the structure of the processor, i.e. how many cores it has and how many SIMD lanes each core has. The CUDA compiler distributes automatically the work over the available SIMD lanes and available cores and in most cases the programmer does not care whether two executions of the function that must be executed for each data item are done on two different cores or on two different SIMD lanes of the same core.<p>This distribution of the work over SIMD lanes and over cores is simple when the SIMD operations are maskable, like in GPUs or in AVX-512 a.k.a. AVX10 or in ARM SVE. When masking is not available, like in AVX2 or Armv8-A, the implementation of conditional statements and expressions is more complicated.