PCI-Sig Releases 256GBps PCIe 6.0 X16 Spec
Stupid question from me: how the hell do they prototype and debug this? It&#x27;s very far from my EE knowledge. Communication analysers will show the eye diagram and tell you a lot about stray capacitance and inductance, but I know that most 10GSa&#x2F;s+ devices cost more than a house and have a tendency to live in a lab for a long time. It seems to my mind like there are so many difficulties in driving pci-e fast, from timing to voltage drop and current limitations. All of this must be implemented, somehow, if the spec is finalised. Right? They wouldn&#x27;t write it up otherwise (right?!).<p>So -- how do you prove that your infrastructure can blow the socks off everything without building two of them and testing?