RISC-V Pushes into the Mainstream
Does anyone know of a good wiki for doing multicore RISC-V on FPGA? Something more substantial than:<p><a href="https:&#x2F;&#x2F;www.reddit.com&#x2F;r&#x2F;RISCV&#x2F;comments&#x2F;z6xzu0&#x2F;multi_core_implentation_of_risc_v&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.reddit.com&#x2F;r&#x2F;RISCV&#x2F;comments&#x2F;z6xzu0&#x2F;multi_core_im...</a><p>When I got my ECE degree in 1999, I was so excited to start an open source project for at least a 256+ core (MIPS?) processor in VHDL on an FPGA to compete with GPUs so I could mess with stuff like genetic algorithms. I felt at the time that too much emphasis was being placed on manual layout, when even then, tools like Mentor Graphics, Cadence and Synopsys could synthesize layouts that were 80% as dense as what humans could come up with (sorry if I&#x27;m mixing terms, I&#x27;m rusty).<p>Unfortunately the Dot Bomb, 9&#x2F;11 and outsourcing pretty much gutted R&amp;D and I felt discouraged from working on such things. But supply chain issues and GPU price hikes for crypto have revealed that it&#x27;s maybe not wise to rely on the status quo anymore. Here&#x27;s a figure that shows just how far behind CPUs have fallen since Dennard scaling ended when smartphones arrived in 2007 and cost&#x2F;power became the priority over performance:<p><a href="https:&#x2F;&#x2F;www.researchgate.net&#x2F;figure&#x2F;The-Dennard-scaling-failed-around-the-middle-of-the-2000s-24_fig1_330893452" rel="nofollow">https:&#x2F;&#x2F;www.researchgate.net&#x2F;figure&#x2F;The-Dennard-scaling-fail...</a><p>FPGA performance on embarrassingly parallel tasks scales linearly with the number of transistors, so more closely approaches the top line.<p>I did a quick search and found these intros:<p><a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=gJno9TloDj8">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=gJno9TloDj8</a><p><a href="https:&#x2F;&#x2F;www.hackster.io&#x2F;pablotrujillojuan&#x2F;creating-a-risc-v-system-with-an-fpga-80d726" rel="nofollow">https:&#x2F;&#x2F;www.hackster.io&#x2F;pablotrujillojuan&#x2F;creating-a-risc-v-...</a><p><a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Field-programmable_gate_array" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Field-programmable_gate_array</a><p><a href="https:&#x2F;&#x2F;www.napatech.com&#x2F;road-to-fpga-reconfigurable-computing&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.napatech.com&#x2F;road-to-fpga-reconfigurable-computi...</a><p>Looks like the timeline went:<p>2000: 100-500 million transistors<p>2010: 3-5 billion transistors<p>2020: 50-100 billion transistors<p><a href="https:&#x2F;&#x2F;www.umc.com&#x2F;en&#x2F;News&#x2F;press_release&#x2F;Content&#x2F;technology_related&#x2F;19991018" rel="nofollow">https:&#x2F;&#x2F;www.umc.com&#x2F;en&#x2F;News&#x2F;press_release&#x2F;Content&#x2F;technology...</a><p><a href="https:&#x2F;&#x2F;www.design-reuse.com&#x2F;news&#x2F;27611&#x2F;xilinx-virtex-7-2000t-fpga.html" rel="nofollow">https:&#x2F;&#x2F;www.design-reuse.com&#x2F;news&#x2F;27611&#x2F;xilinx-virtex-7-2000...</a><p><a href="https:&#x2F;&#x2F;www.hpcwire.com&#x2F;off-the-wire&#x2F;xilinx-announces-general-availability-of-vu19p-worlds-largest-fpga&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.hpcwire.com&#x2F;off-the-wire&#x2F;xilinx-announces-genera...</a><p>I did a quick search on Digi-Key, and it looks like FPGAs are overpriced by a factor of about 10-100 with prices as high as $10,000. Since most of the patents have probably run out by now, that would be a huge opportunity for someone like Micron to make use of Inflation Reduction Act money and introduce a 100+ billion transistor 1 GHz FPGA for a similar price as something like an Intel i9, say $500 or less.<p>Looks like about 75 transistors per gate, so I&#x27;m mainly interested in how many transistors it takes to make a 32 or 64 bit ALU, and for RAM or DRAM. I&#x27;m envisioning an 8x8 array of RISC-V cores, each with perhaps 64 MB of memory for 16 GB total. That would compete with Apple&#x27;s M1, but with no special heterogenous computing hardware, so we could get back to generic multicore desktop programming and not have to deal with proprietary GPU drivers and function coloring problems around CPU code vs shaders.