Show HN: The SC4-HSM, a fully open USB hardware secure module
Security assessment is a bottom-up process. Most security in a HSM is in the hardware. This is clearly not using secure IC&#x27;s as illustrated in the smartcard market. It&#x27;s already going to hit a ceiling there. Let&#x27;s look at the datasheet anyway to see what can be built on foundation of STM32F415. Keep in mind I rarely deal with MCU&#x27;s or embedded stuff. Some questions or concerns will come from my memory loss or lack of experience.<p><a href="http:&#x2F;&#x2F;www.st.com&#x2F;content&#x2F;ccc&#x2F;resource&#x2F;technical&#x2F;document&#x2F;datasheet&#x2F;98&#x2F;9f&#x2F;89&#x2F;73&#x2F;01&#x2F;b1&#x2F;48&#x2F;98&#x2F;DM00035129.pdf&#x2F;files&#x2F;DM00035129.pdf&#x2F;jcr:content&#x2F;translations&#x2F;en.DM00035129.pdf" rel="nofollow">http:&#x2F;&#x2F;www.st.com&#x2F;content&#x2F;ccc&#x2F;resource&#x2F;technical&#x2F;document&#x2F;da...</a><p>Embedded flash 512KB or 1MB for programs and data. Checked with a CRC unit. There&#x27;s some kind of accelerator between flash memory and main bus. Effects on security or robustness unknown. The flash might be writeable to attacker, esp since it&#x27;s flash not ROM. What protections are here to prevent that?<p>Embedded SRAM. Up to 192KB of system SRAM w&#x2F; up to 64KB of CCM data RAM. Has 4KB backup SRAM &quot;only accessible from CPU... content protected against unwanted write accesses, and retained in Standby or VBAT mode.&quot; First, what does &quot;protected against unwanted&quot; mean specifically? Second, does HSM software properly overwrite new memory, check pointers, do periods processing, and so on to prevent leaks via requests from host or compromise of subsystem?<p>Memory protection unit. Simplified MMU splits memory into 8 areas with 8 sub-areas ranging from 32 bytes to 4GB addressable memory. Access control typically managed by RTOS. Does HSM properly use MPU to isolate keys, cryptographic functions, kernel, and non-security critical software? What&#x27;s the TCB size and assurance activities that went into the component that manages this?<p>DMA controller. Two units do what DMA always does: bypass all checks for raw speed. Configured by software. Attacks on that code or anything that can reference it might lead to DMA attacks. Curious what effect attack on host, esp a driver, could have far as divulging the MCU&#x27;s secrets to a malicious program on the host.<p>Interrupts. Can compromised host flood the device for DDOS or use them selectively to extract keys via glitch in interrupt handling? Doing just the flooding while otherwise doing nothing could also be used to trick users into thinking device is unreliable. They might use less confidential method as backup.<p>&quot;The boot loader is located in system memory. It is used to reprogram the Flash memory by 
using USART1 (PA9&#x2F;PA10), USART3 (PC10&#x2F;PC11 or PB10&#x2F;PB11), CAN2 (PB5&#x2F;PB13), USB OTG FS in Device mode (PA11&#x2F;PA12) through DFU (device firmware upgrade).&quot; This is a pile of stuff embedded people probably recognize. All I know is it needs exploration to help determine exposure to boot- or flash-level attacks.<p>&quot;The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode.&quot; This could be useful for long-term, key storage. The flash filesystems are harder to overwrite since they put data all over the place to reduce wear on individual components. Overwriting this is... with my limited memory... more straight-forward. It also preserves availability. To prevent thieves extracting, the keys might be encrypted before storage using a function that combines onboard-software, something entered through the host, and&#x2F;or something done via buttons on drive. If host app deletes its secrest after use, then a simple snatch-and-grab won&#x27;t work.<p>Watchdog timers. These are useful in high-security to deal with HW- &amp; SW-level failures in the &quot;known unknowns&quot; and &quot;unknown unknowns&quot; categories. Maybe set a watchdog during important, cryptographic operations that should be done in certain timerange and&#x2F;or for system operation in general. If it activates, any secrets are cleared immediately then user must recover device. Basically, &quot;Fail Safe, Hard, and Noticeably&quot; principle in action given who knows what led to watchdog activating. Catch all.<p>&quot;Secure digital input&#x2F;output interface&quot; I got unnecessarily excited: it was just SDcard support. Oh well. :)<p>&quot;USB controller... Internal USB DMA.&quot; The USB section doesn&#x27;t tell me enough to know the risks it might have. Depends on what software directs it, what access it has to what memory, and so on. Then, we can at least see where the checks have to be put or what code has to be perfect. The DMA part was in &quot;high-speed&quot; section but not &quot;full-speed.&quot; So, add DMA concerns above to USB subsystem and code if HSM uses high-speed. Possibly if full-speed if DMA stays on and accessible anyway where designers just assume people wouldn&#x27;t try to use it rather than force that to be true.<p>&quot;embed a cryptographic accelerator&quot; This always concerns me as I have trust issues with these. Let&#x27;s say we trust them. I&#x27;d apply all the tests available for these. Past that, do security at interface design-by-contract style plus extra code review to make sure they&#x27;re used correctly. Guttman&#x27;s security kernel in cryptlib is a nice example. Also mentions it supports DMA request generation. If it&#x27;s always on, then add DMA considerations to the protocol engine that uses these.<p>&quot;delivers 32-bit random numbers generated by an integrated analog circuit&quot; Have at least one unit doing nothing but outputing analog noise all day for weeks. Run all randomness tests on the whole set plus subsets of it to see if statistical properties change significantly during specific periods of time. This is good practice in general to assess effectiveness. However, especially important with analog in case they chose shitty noise source that varies with environmental factors. I recall Bitbabbler lead says they keep a whole pile of them doing this since first prototypes to keep sample size statistically significant itself. That approach is even better if one has resources to do it.<p>JTAG and embedded trace macrocell. Well, these are always interesting from an attacker perspective. :) Maxim says there&#x27;s no security once it&#x27;s in their physical possession. Let&#x27;s not make it easy, though. A basic mitigation here is requiring user to activate it with their password, PIN or some button presses. Lacking that, anything the software sees indicating unauthorized access can lead to nuking the secrets. Should stop majority of attackers who are casual or script kiddies. Part of that backup 4K SRAM might be used to keep track of anomolies that otherwise disappear with power turned on and off due to attacker experimenting.<p>So, that&#x27;s the hardware. It has potential, as smartcards illustrate, to perform the job at hand with numerous risks that must be assessed and countered. Anything on host that configures, does requests through, or interrupts it is a security threat to be mitigated somehow. Protocol engines need sanity checks plus coded in a way to be amenable to any and all forms of static&#x2F;dynamic analysis. MPU should compartmentalize secrets &amp; kernel from the rest. Long-term keys can be stored in flash and&#x2F;or backup SRAM with SRAM having some advantages. Other SRAM overwritten after use, including memory for intermediate steps. Any onboard registers overwritten during context switch (periods processing) to untrusted code. Ops take fixed time with careful attention to shared memory&#x2F;resources to mitigate timing channels. Make damn sure they can&#x27;t corrupt the boot code. I still don&#x27;t know exactly how that&#x27;s installed or protected from software attack. Need help from MCU or embedded people here.<p>The system level I&#x27;m unclear on as lisper hasn&#x27;t given me full use-case list. The basic is to make sure keys are generated properly, used properly, never see host and trustworthy TRNG. These can be met with above methods if identified risks are knocked out or turn out not a concern. Security-oriented IC&#x27;s, as found in EAL5+ or EAL6+ smartcards, are <i>much</i> more suited to this stuff as they put in more effort into HW mitigations and assurance of TCB implementation. Ledger Blue wallet uses an EAL6+ IC as an example. Consider using one of them in future version of product. Additionally, pull up MCU errata page to look at any CPU errata in specific product causing crashes or weird execution. Especially on MPU. Malware &amp; smart pentesters used those in the past.<p>Emanation or HW-level attacks will still work on this device due to no mitigations. That means one use-case, using it on untrustworthy computers in public, cannot be performed with this device in event person&#x27;s secrets are high-value to Five Eyes, Israeli, or Russian intelligence services known to use those attacks plus any high-end contractors that can do the same. Security researchers are also publishing more over time, which means blackhats will eventually use them. An associate pointed out that one of the designs for card computer (Bitcoin?) used red-black separation in PCB itself to a degree to reduce cryptozone&#x27;s ability to electrically effect untrusted zone. Physical Red-Black was used by military for decades to reduce leaks. Cheaper solutions like those might be used to reduce impact a bit but users should be warned this risk remains for high-value targets.<p>So, that&#x27;s my brief review of this product at just the hardware and system levels. I haven&#x27;t looked at the app level to determine if how it&#x27;s used or implemented meets the criteria. There&#x27;s risks there, too. Might look into them. For now, I think lisper has plenty to think about on the hardware &amp; implementation side of things. He will be busy. :)