Unidentified PC DOS 1.1 Boot Sector Junk Identified
I will recount one mystery that I personally wondered about for decades, and that coincidentally the author of this article might have shed most light on:<p>The 386 was the first x86 processor to introduce four &quot;Control Registers&quot;, CR0-CR3. The first one, CR0, was technically already introduced with the 286, but then still named &quot;Machine Status Word&quot; and manipulated with its own set of different , explicit instructions (that still survive to this day).<p>Now, if you look at Intel&#x27;s documentation of the 386, or any later CPU in the line--including today&#x27;s Intel CPUs in Laptops, Desktops, and Servers--you will see that the second of those registers, CR1, is entirely &quot;reserved&quot;. No single bit in it can be accessed, neither reading or writing.<p>This is bizarre not only because CR1 was introduced by the 386 along with CR2 and CR3 (which are defined and common), but also because the successor, the 486, introduced a <i>new</i> Control Register, CR4, instead of starting to use reserved bits in CR1. This is despite CR4 sharing its characteristics with CR0 (and unlike e.g. CR2): It&#x27;s mostly a bit field for global processor state. So while you could have assumed that CR1 existed as planned &quot;overflow&quot; to add new control bits to once CR0 became full, the seemingly simple addition of CR4 in the immediate successor goes against that theory.<p>Decades ago, I even wrote to the 386&#x27;s chief architect to try to settle that question... he must have not understood my question, because he just replied that according to Intel documentation, that register is &quot;reserved&quot;.<p>But incidentally, a while ago I talked about that mystery with the author of this article, and received the most plausible theory so far: It turns out that an early pre-release document shows that the 386 was originally planned to contain an on-chip cache. Evidently, that part of the plan must have been scrapped, because the 386 shipped without an on-chip cache, which was only added with the 486 (maybe they ran into problems with implementing a cache controller, or maybe at the time so much on-chip SRAM would have made for a prohibitive price point).<p>It is therefore not unlikely that CR1 was once meant, and in prototypes maybe even did, control the cache. Once that cache was removed, CR1 was just made &quot;reserved&quot;, and not repurposed in the 486 and later CPUs out of an abundance of caution for compatibility: Accessing CR1 reliably causes an Undefined Opcode trap, and maybe some important software at the time relied on that in a bad way.