Ask HN: How does a CPU communicate with a GPU?
Woah there, my dude. Let&#x27;s try to understand a simple model first.<p>A CPU can access memory. When a CPU performs loads &amp; stores it initiates transactions containing the address of the memory. Therefore, it is a bus master--it initiates transactions. A slave accepts transactions and services them. The interconnect routes those transactions to the appropriate hardware, e.g. the DDR controller, based on the system address map.<p>Let&#x27;s add a CPU, interconnect, and 2GB of DRAM memory:<p><pre><code>  +-------+
  |  CPU  |
  +---m---+
      |
  +---s--------------------+
  |      Interconnect      |
  +-------m----------------+
          |
     +----s-----------+
     | DDR controller |
     +----------------+
  
  
  System Address Map:
  
    0x8000_0000 - 0x0000_0000  DDR controller
</code></pre>
So, a memory access to 0x0004_0000 is going to DRAM memory storage.<p>Let&#x27;s add a GPU.<p><pre><code>  +-------+    +-------+
  |  CPU  |    |  GPU  |
  +---m---+    +---s---+
      |            |
  +---s------------m-------+
  |      Interconnect      |
  +-------m----------------+
          |
     +----s-----------+
     | DDR controller |
     +----------------+
  
  
  System Address Map:
  
    0x9000_0000 - 0x8000_0000  GPU
    0x8000_0000 - 0x0000_0000  DDR controller
</code></pre>
Now the CPU can perform loads &amp; stores from&#x2F;to the GPU. The CPU can read&#x2F;write registers in the GPU. But that&#x27;s only one-way communication. Let&#x27;s make the GPU a bus master as well:<p><pre><code>  +-------+    +-------+
  |  CPU  |    |  GPU  |
  +---m---+    +--s-m--+
      |           | |
  +---s-----------m-s-----+
  |      Interconnect      |
  +-------m----------------+
          |
     +----s-----------+
     | DDR controller |
     +----------------+
  
  
  System Address Map:
  
    0x9000_0000 - 0x8000_0000  GPU
    0x8000_0000 - 0x0000_0000  DDR controller
</code></pre>
Now, the GPU can not only receive transactions, but it can also initiate transactions. Which also means it has access to DRAM memory too.<p>But this is still only one-way communication (CPU-&gt;GPU). How can the GPU communicate to the CPU? Well, both have access to DRAM memory. The CPU can store information in DRAM memory (0x8000_0000 - 0x0000_0000) and then write to a register in the GPU (0x9000_0000 - 0x8000_0000) to inform the GPU that the information is ready. The GPU then reads that information from DRAM memory. In the other direction, the GPU can store information in DRAM memory, and then send an interrupt to the CPU to inform the CPU that the information is ready. The CPU then reads that information from DRAM memory. An alternative to using interrupts is to have the CPU poll. The GPU stores information in DRAM memory and then sets some bit in DRAM memory. The CPU polls on this bit in DRAM memory, and when it changes, the CPU knows that it can read the information in DRAM memory that was previously written by the GPU.<p>Hope this helps. It&#x27;s very fun stuff!