Why hardware development is hard, part 1: Verilog is weird (2013)
Verilog seems &quot;hard&quot; because people often use it in a similar fashion to a programming language, and in most cases that does not make any sense. The proper way to use it is to design the hardware, then code it up using verilog (which is trivial compared to the actual design). 
In fact in terms of time spent on design, the actual coding part does not take much time at all.
In fact, this very article uses a motivating example that does not make any sense.