Lock-free programming for the masses
It&#x27;s time for better CPU support for atomic operations. &quot;Backoff, retry, blocking and signalling&quot; is a hack. What we really need is machine level support for short memory transactions.  This would be an extension of fence hardware.<p>What&#x27;s needed is a CPU instruction to fence a critical section and lock up two cache lines while you manipulate them from one CPU, with other CPUs locked out. Transactions should have a hardware instruction cycle limit, so you can&#x27;t lock up the other CPUs for very long.  Then you could do swaps, sets, appends to lists, and such with straightforward code.<p>This locking would be local to the two cache lines - unless two CPUs are trying to hit the same two cache lines, there&#x27;s no delay. Why two cache lines? That lets you do moves and swaps, and maybe some list and queue manipulation. Those can all be completed in a few instruction cycles.