Designing a MIPS CPU in Hardcaml
I&#x27;m enjoying this series.  I&#x27;ve got a few comments about inaccuracies:<p>&gt; Vivado, the dominant IDE for hardware design<p>I haven&#x27;t heard that one before.  I use it when I&#x27;m working with Xilinx parts, but I rarely open the GUI.  I use VSCode mainly, and nvim.<p>Xilinx has come a long way with Vivado from its roots, but I&#x27;d never actually do day to day work in it, for the same reasons I wouldn&#x27;t work in eclipse.<p>&gt; Want to write code in a different editor like VSCode? Alright, but you&#x27;ll need to manually register every new file you make in Vivado.<p>It is pretty straight forward to automate with a general script for this and you never deal with it again.<p>&gt; Oh, and there&#x27;s no syntax error highlighting in VSCode&#x27;s Verilog extensions either.<p>This is not true.<p><a href="https:&#x2F;&#x2F;marketplace.visualstudio.com&#x2F;items?itemName=mshr-h.VerilogHDL" rel="nofollow">https:&#x2F;&#x2F;marketplace.visualstudio.com&#x2F;items?itemName=mshr-h.V...</a><p><a href="https:&#x2F;&#x2F;marketplace.visualstudio.com&#x2F;items?itemName=eirikpre.systemverilog" rel="nofollow">https:&#x2F;&#x2F;marketplace.visualstudio.com&#x2F;items?itemName=eirikpre...</a><p>&gt; On the rare occasions you do get errors&#x2F;warnings<p>Synthesis is notorious for barfing out thousands of warnings even on simple designs.  I have never considered them rare, or heard someone else call them &quot;rare,&quot; until this blog series.<p>Quite the opposite.  We are inundated with <i>so many</i> warnings that people start to ignore them and that leads to problems.  Vivado even invented &quot;critical warnings&quot; to try help with the situation.<p>&gt;  a friend and I once spent over an hour debugging an issue, only to find out that I mispelled a wire name.<p>This one has me puzzled.  Did they misspell it such that it looked like another declared signal?<p>&gt; The synthesis process doesn&#x27;t throw error in cases where you would expect it to [...] You can have multiple modules &#x2F; circuits outputting to the same wire.<p>You might expect that to be an error, but it&#x27;s called a &quot;wired-OR.&quot;  It&#x27;s often a mistake so you will definitely get warnings about it, but it&#x27;s not wrong. Go back and look at transistor diagrams of gates.<p>&gt; You can pass wires into a module by name, but it won&#x27;t error if a wire is missing, misnamed, etc.<p>It&#x27;s true that it won&#x27;t error if one is missing, because it&#x27;s not strictly wrong to do that.  You will get warnings about undriven logic though.<p>It&#x27;s hard to envision a scenario where something misnamed doesn&#x27;t cause an error unless you typo it into another signal name.<p>You definitely will get errors trying to connect to a port that doesn&#x27;t exist.<p>&gt; You can pass a 1-bit wire to a 5-bit port on a module (or any other mismatched combination).<p>This is true.   And if you aren&#x27;t aware of it you can get into trouble.  I had a friend run into this issue last week, mainly because he came from VHDL which (like ADA) is very strongly typed.<p>&gt; Explicitly extending&#x2F;truncating signals is already possible by making a module to transform your input&#x2F;output, so I&#x27;m not sure why this implicit conversion should be allowed.<p>It&#x27;s a reaction to VHDL (based on ADA), which with its extreme typing made arithmetic difficult to do.  Verilog was intended to be more like C.<p>&gt; Hardcaml really interesting because OCaml is functional, compiled, and statically typed. Also (and somewhat more importantly), Hardcaml supports testing<p>Ok, I think it&#x27;s cool to try other languages and to branch out.  I&#x27;ve tinkered with an HDL based on Clojure.  But the post implies Verilog does not support those things..<p>Verilog supports testing trivially.  It is statically typed, albeit weakly in some cases.  It clearly is functional.<p>But the semantics get clunky.  I would think that is where OCaml or Chisel or others would be interesting.<p>&gt; On the rare occasions you do get errors&#x2F;warnings, they&#x27;re generally cryptic and require relatively deep understanding of Verilog. Not great for beginners.<p>This is true.  I find it annoying about most languages I work with, most recently python.<p>&gt; Tooling sucks. All the synthesis errors I complained about above could be identified through static analysis and surfaced as warnings&#x2F;errors in the editor. Emphasis on *could be.*<p>Yes, it does suck.  I&#x27;m hopeful for things like symbiflow and the tooling it&#x27;s based on.<p>But to be fair, static analysis is very much a part of digital design.  It&#x27;s often called Formal.<p>&gt; Tests also have to be Verilog modules, whereas usually in software it&#x27;s preferable to use functions&#x2F;methods for test cases.<p>I don&#x27;t really understand what this point is.  Your top level has to be a module (or a program) ... it&#x27;s a fundamental unit Verilog.  You can put all the functions&#x2F;tasks you want in that module.<p>It&#x27;s like complaining about classes in c++?<p>&gt; Partially as a consequence of the previous point, testing requires a lot of boilerplate<p>That really depends on what level of testing you are doing.  You can do the simple function&#x2F;task based testing, and that is nearly zero boiler plate.<p>&gt; There isn&#x27;t really an ecosystem for things like continuous integration. For that matter, many testing innovations from the software world (like mocks&#x2F;stubs) don&#x27;t seem to carry over well to hardware.<p>I don&#x27;t really get this either.  Mocking and Stubs are an incremental design technique.  They work fine.  And <i>all</i> of my development and that of my team happens through gitlab-CI.<p>&gt; A lot of automated testing seems to be based around printing assertions and generating waveforms in the Vivado console&#x2F;waveform viewer. That&#x27;s not very automatable.<p>I don&#x27;t really know what this is talking about.  I don&#x27;t do testing with vivado... it&#x27;s a compiler&#x2F;synthesizer for me.<p>I think the real problem here is that tools are expensive for digital design (hopefully symbiflow&#x2F;yosys et al get serious traction and change this).  If you are stuck in vivado, maybe you can&#x27;t do automated testing?  I find it hard to believe.<p>ok, now that I&#x27;m done complaining about the blog post&#x27;s complaints, on to the good stuff (I hope) re Hardcaml.