Addressing Criticism of RISC-V Microprocessors
I have difficulty following the points the author is trying to make.<p>- Even with instruction compression the type of code they present will take more space than, say, Aarch64.
- The entire section on conditional execution doesn&#x27;t make any sense. Conditional execution is bad, we know it, that&#x27;s why modern ARM does not have conditional execution. Overall, author&#x27;s insistence to compare RISC-V to practically obsolete ARMv7 when ARMv8 has been available for over a decade is... odd. 
- Regarding SIMD... it&#x27;s a very complex topic, but personally, I don&#x27;t see any fundamental problem with vector-style ISA. I think it&#x27;s a great way of allowing scalable software. But vector ISA does not replace basic SIMD as they solve different problems. Vector stuff is great for throughput, SIMD is great for latency. There are many tasks such as geometry processing, modern data structures etc. where fixed-size 128-bit SIMD is an excellent building block. That&#x27;s why ARM has both NEON and SVE2, the latter does not make obsolete the former. And that bit about GPUs and how they are not good for vector processing... not even sure how to comment on it. Also, at the end of the day, specialised devices will vastly outperform any general-purpose CPU solution. That&#x27;s why we see, say, Apple M1 matrix accelerators delivering matmul performance on par with workstation CPU solutions, despite using a fraction of power.<p>Overall, my impression is that the article is grasping at straws, ignores modern technology and ultimately fails to deliver. I aolso remain unconvinced by the initial premise that RISC-V follows the principle &quot;not painting yourself into a corner due to choices which have short term benefit&quot;. I do think that choices like  keeping instructions as simple as possible (even though it makes expression of common patterns verbose), avoiding flags registers, disregarding SIMD etc. could be characterised as &quot;painting oneself into a corner&quot;.<p>A usual disclaimer: I do think that RISC-V is a great architecture for many domains. Simple low-power&#x2F;low-cost controllers, specialised hardware, maybe even GPUs (with extensions) — the simplicity and openness of RISC-V makes it a great point of entry for basically anyone and invites experimentation. I just don&#x27;t see much merit of RISC-V in the general-purpose high-performance consumer computing (laptop&#x2F;desktop). In this space RISC-V does not have any notable advantages, it does have potential disadvantages (e.g. code density and lack of standard SIMD — yet). Most importantly, the CPU microarchitecture becomes the decisive factor, and designing a fast general-purpose CPU requires a lot of expertise and resources. It&#x27;s not something that a small group of motivated folk can realistically pull off. So all the great things about RISC-V simply do not apply here.