Power Complexity On The Rise
This came across twitter and I found it a really interesting read. Simulation tools make a bunch of assumptions, when the chip designer breaks those assumptions, the tools break in unexpected ways. The first time I saw this in action was the design of the SPARC 10 CPU which was, in places, an asynchronous design, meaning that the signals for controlling functions in various units happened when the previous unit finished, there wasn&#x27;t a common clock domain. That broke all of the simulation code and it took months to work around it. I got to hear this second hand as I was just doing system software, not chip design, but it stories were pretty amazing.