FPGA Interchange format to enable interoperable FPGA tooling
I&#x27;m really interested in this subject. What with it being my job. I&#x27;ve thought about this a lot, and the fundamental problem for me is that you have RTLs, but these don&#x27;t mean anything, they&#x27;re a cruel joke on engineering students &quot;Oh sure, you <i>can</i> do that in this language but does it <i>map</i>.&quot;<p>The problem is that really it&#x27;s only a tiny subset of RTL languages that are supported by FPGAs, and an even tinier subset that&#x27;s optimial. God alone can write 10 lines of RTL that&#x27;ll map to DSP blocks utilizing the carry chain. The problem isn&#x27;t that the languages don&#x27;t support multiple targets, it&#x27;s that the targets are so idiosyncratic that you have to know exactly how it maps.<p>Now, what this format promises to do encompasses describing the resources on a device, but there&#x27;s a few problems with this. Firstly, they&#x27;re incredibly complex in terms of trade-offs (you can do X Y Z but X only in A mode Y in all modes but B, Z but the timing of N is off). The likely result of this are a set of simplified rules that make it tractable, but not performant. Secondly, since the only way of getting optimal hardware is to design it for one target - an interchange format seems like nonsense. It&#x27;s exactly like RTL - it describes everything but doesn&#x27;t functionally help you translate between targets at all.<p>Fundamentally this just doesn&#x27;t seem like it solves anything, it&#x27;s seems to suggest &quot;Hey guys, adopt our standard for all your stuff!&quot;, but why? They don&#x27;t seem to be offering anything of value.<p>If I were being particularly glib, I&#x27;d wish a swift promotion to the guys at Google who authored this.