Xilinx Vitis and Vitis AI Software Development Platforms
Note that all of this is predicated on High Level Synthesis (HLS) becoming real, after many years of industry over-promises and under-deliveries.<p>A jaded RTL engineer may fairly ask, &quot;what&#x27;s different this time?&quot; I&#x27;m convinced it&#x27;s two things:<p>1. These chips have scaled to the point where the toolflow isn&#x27;t just annoying, it&#x27;s crippling. (I say that as an RTL designer who likes Vivado, believe it or not.) Making effective use of the largest FPGAs in traditional FPGA applications is difficult enough. Plus, the marginal cost of baking e.g. ARM cores onto an FPGA is now so low that these parts are quickly becoming heterogeneous SoCs and it requires extensive cross-domain knowledge to get a modern design off the ground. More importantly, though, Xilinx is trying to expand FPGAs beyond traditional FPGA markets, and it can&#x27;t do so without expanding the pool of available talent to program them. Finally, new FPGA applications (e.g. AI) come with their own technical arcana and finding FPGA designers who are proficient in all of these domains is only growing harder. It is necessary for the tools to help, and Xilinx is amply incentivized to pour money into the R&amp;D programs necessary, even if the new tools are simply bundled alongside the old ones.<p>2. This may be a surprise, but LLVM. Doing HLS correctly is a forced march through every conceivable corner of compiler, language, and RTL design, and to date, that&#x27;s been much too difficult for EDA companies. I believe that LLVM as an accessible compiler workshop has been instrumental to Xilinx&#x27;s success to date.<p>I hope Xilinx does genuinely open-source some of the pieces. (Not the synthesis flow, in this case, but all the stuff built on top of it.) The open-source EDA community is small but motivated and talented, but it&#x27;s crippled by balkanization caused by the commercial EDA market. This might be an interesting shot in the arm.