FPGAs Have the Wrong Abstraction for Computing
I have designed ASICs and FPGAs for nearly 30 years, and seen the evolution of this technology first hand. To say that FPGAs have the wrong abstraction is to not understand what an FPGA is and what is intended to accomplish.<p>Transistors are abstracted into logic gates. Logic gates are abstracted into higher-order digital functions like flip-flops, muxes, etc. It is the mapping of algorithms&#x2F;functions onto gates that is the essence of digital design. This is difficult work that would be impossible at today&#x27;s scales (5-billion+ transistors) without synthesis tools and HDLs. And, given that an ASIC mask set costs 1MM+ for a modern geometry, it needs to be done right the first time (or at least the 2nd). Furthermore, the mapping to gates needs to be efficient, throwing more gates at a problem increases area, heat, and power, all of which need to be minimized in most contexts.<p>My first job out of college was designing 386 motherboards. Back then we were still using discrete 74xx ICs for most digital functions. The boards were huge. PLDs allowed better intergration and were cost effective since a single device could implement many different functions, and reduced board area and power consumption. CPLDs moved this further along.<p>FPGAs grew out of PLD&#x2F;CPLDs and allowed a significantly higher level of integration and board area reduction. They offered a way to reduce the cost of a system without requiring the investment and expertise required for an ASIC. But, FPGAs themselves are an ASIC, implemented with the same technology as any other ASIC. So, FPGAs are a compromise; the LUTs, routing, etc are all a mechanism to make a programmable ASIC. Compared to an ASIC, however, FPGAs require more power and can implement less capability for a given die size. But, they allow a faster and lower cost development cycle. To bring this back around, the LUTs and routing mechanisms are functions that have been mapped to gates. To use an FPGA, algorithms still need to be mapped onto the LUTs and this is largely the same process as mapping to gates.<p>This article was pointless, even the author acknowledges: &quot;I don’t know what abstraction should replace RTL for computational FPGAs.&quot; And, &quot;Practically, replacing Verilog may be impossible as long as the FPGA vendors keep their lower-level abstractions secret and their sub-RTL toolchains proprietary.&quot; As I have argued above, knowing the FPGA vendors lower-level abstractions won&#x27;t make the problem any better. The hard work is mapping onto gates&#x2F;LUTs.  And that analogy is wrong: &quot;GPU : GPGPU :: FPGA : &quot; An FPGA is the most general purpose hardware available.<p>The best FPGA&#x2F;ASIC abstraction we have today is a CPU&#x2F;GPU.