<|start_filename|>rcs/m6502/instructions_test.go<|end_filename|>
package m6502

import "testing"

func flagError(t *testing.T, want uint8, have uint8) {
	t.Errorf("\n       nv-bdizc\n want: %08b \n have: %08b \n", want, have)
}

// ----------------------------------------------------------------------------
// adc
// ----------------------------------------------------------------------------
func TestAdcImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.A = 0x08
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcWithCarry(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.A = 0x08
	c.SR = FlagC
	testRunCPU(t, c)
	want := uint8(0x0b)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcCarryResult(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.A = 0xff
	testRunCPU(t, c)
	want := uint8(0x01)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.A = 0xfe
	testRunCPU(t, c)
	want := uint8(0x00)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcZeroSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.A = 0xf0
	testRunCPU(t, c)
	want := uint8(0xf2)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcOverflowSet(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.A = 0x7f
	testRunCPU(t, c)
	want := uint8(0x81)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagV | FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcOverflowClear(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0xff) // lda #$ff (-1)
	c.SR |= FlagV
	c.A = 0x81
	testRunCPU(t, c)
	want := uint8(0x80)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagC | FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcBcd(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda $#02
	c.SR |= FlagD
	c.A = 0x08
	testRunCPU(t, c)
	want := uint8(0x10)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcBcdWithCarry(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda $#02
	c.SR |= FlagD | FlagC
	c.A = 0x08
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcBcdCarryResult(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x69, 0x02) // lda #$02
	c.SR |= FlagD
	c.A = 0x99
	testRunCPU(t, c)
	want := uint8(0x01)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0x65, 0x34) // adc $34
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0x75, 0x30) // adc $30,X
	c.A = 0x02
	c.X = 0x04
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x08)              // .byte $08
	c.mem.WriteN(0x0200, 0x6d, 0xab, 0x02) // adc $02ab
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x08)              // .byte $08
	c.mem.WriteN(0x0200, 0x7d, 0xa0, 0x02) // adc $02a0,X
	c.A = 0x02
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x08)              // .byte $08
	c.mem.WriteN(0x0200, 0x79, 0xa0, 0x02) // adc $02a0,Y
	c.A = 0x02
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0x61, 0x40) // adc ($40,X)
	c.A = 0x02
	c.X = 0x0a
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAdcIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0x71, 0x4a) // adc ($4a),Y
	c.A = 0x02
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x0a)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// and
// ----------------------------------------------------------------------------
func TestAndImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x29, 0x0f) // and #$0f
	c.A = 0xcd
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAndZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x29, 0xf0) // and #$f0
	c.A = 0x0f
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAndSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x29, 0xf0) // and #$f0
	c.A = 0xff
	testRunCPU(t, c)

	want0 := uint8(0xf0)
	have0 := c.A
	if want0 != have0 {
		t.Errorf("\n want: %02x \n have: %02x \n", want0, have0)
	}

	want1 := FlagN | Flag5
	have1 := c.SR
	if want1 != have1 {
		flagError(t, want1, have1)
	}
}

func TestAndZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x0f)        // .byte $0f
	c.mem.WriteN(0x0200, 0x25, 0x34) // and $34
	c.A = 0xcd
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAndZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x0f)        // .byte $0f
	c.mem.WriteN(0x0200, 0x35, 0x30) // and $30,X
	c.A = 0xcd
	c.X = 0x04
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAndAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x0f)              // .byte $0f
	c.mem.WriteN(0x0200, 0x2d, 0xab, 0x02) // and $02ab
	c.A = 0xcd
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAndAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x0f)              // .byte $0f
	c.mem.WriteN(0x0200, 0x3d, 0xa0, 0x02) // and $02a0,X
	c.A = 0xcd
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAndAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x0f)              // .byte $0f
	c.mem.WriteN(0x0200, 0x39, 0xa0, 0x02) // and $02a0,Y
	c.A = 0xcd
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAndIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x0f)        // .byte $0f
	c.mem.WriteN(0x0200, 0x21, 0x40) // and ($40,X)
	c.A = 0xcd
	c.X = 0x0a
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAndIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x0f)        // .byte $0f
	c.mem.WriteN(0x0200, 0x31, 0x4a) // and ($4a),Y
	c.A = 0xcd
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x0d)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// asl
// ----------------------------------------------------------------------------
func TestAslAccumulator(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x0a) // asl a
	c.A = 4
	testRunCPU(t, c)
	want := uint8(8)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAslSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x0a) // asl a
	c.A = 1 << 6
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAslCarry(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x0a) // asl a
	c.A = 1 << 7
	testRunCPU(t, c)
	want := FlagC | FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAslZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 4)           // .byte 4
	c.mem.WriteN(0x0200, 0x06, 0xab) // asl $ab
	testRunCPU(t, c)
	want := uint8(8)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAslZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 4)           // .byte 4
	c.mem.WriteN(0x0200, 0x16, 0xa0) // asl $a0
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(8)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAslAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 4)                 // .byte 4
	c.mem.WriteN(0x0200, 0x0e, 0xab, 0x02) // asl $02ab
	testRunCPU(t, c)
	want := uint8(8)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestAslAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 4)                 // .byte 4
	c.mem.WriteN(0x0200, 0x1e, 0xa0, 0x02) // asl $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(8)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// bit
// ----------------------------------------------------------------------------
var bitTests = []struct {
	name          string
	a             uint8
	fetch         uint8
	expectedFlags uint8
}{
	{"zero", 0x00, 0x00, FlagZ | Flag5},
	{"non-zero", 0x01, 0x01, Flag5},
	{"and-zero", 0x01, 0x02, FlagZ | Flag5},
	{"bit6", 0x00, 1 << 6, FlagV | FlagZ | Flag5},
	{"bit7", 0x00, 1 << 7, FlagN | FlagZ | Flag5},
}

func TestBitAbsolute(t *testing.T) {
	for _, test := range bitTests {
		t.Run(test.name, func(t *testing.T) {
			c := newTestCPU()
			c.mem.Write(0x02ab, test.fetch)        // .byte test.fetch
			c.mem.WriteN(0x0200, 0x2c, 0xab, 0x02) // bit $02ab
			c.A = test.a
			testRunCPU(t, c)
			want := test.expectedFlags
			have := c.SR
			if want != have {
				flagError(t, want, have)
			}
		})
	}
}

func TestBitZeroPage(t *testing.T) {
	for _, test := range bitTests {
		t.Run(test.name, func(t *testing.T) {
			c := newTestCPU()
			c.mem.Write(0xab, test.fetch)    // .byte fetch
			c.mem.WriteN(0x0200, 0x24, 0xab) // bit $ab
			c.A = test.a
			testRunCPU(t, c)
			want := test.expectedFlags
			have := c.SR
			if want != have {
				flagError(t, want, have)
			}
		})
	}
}

// ----------------------------------------------------------------------------
// branches
// ----------------------------------------------------------------------------
var branchTests = []struct {
	name      string
	op        uint8
	flags     uint8
	expectedA uint8
}{
	{"bpl yea", 0x10, 0, 0x02},
	{"bpl nay", 0x10, FlagN, 0x01},
	{"bmi yea", 0x30, FlagN, 0x02},
	{"bmi nay", 0x30, 0, 0x01},
	{"bvc yea", 0x50, 0, 0x02},
	{"bvc nay", 0x50, FlagV, 0x01},
	{"bvs yea", 0x70, FlagV, 0x02},
	{"bvs nay", 0x70, 0, 0x01},
	{"bcc yea", 0x90, 0, 0x02},
	{"bcc nay", 0x90, FlagC, 0x01},
	{"bcs yea", 0xb0, FlagC, 0x02},
	{"bcs nay", 0xb0, 0, 0x01},
	{"bne yea", 0xd0, 0, 0x02},
	{"bne nay", 0xd0, FlagZ, 0x01},
	{"beq yea", 0xf0, FlagZ, 0x02},
	{"beq nay", 0xf0, 0, 0x01},
}

func TestBranches(t *testing.T) {
	for _, test := range branchTests {
		t.Run(test.name, func(t *testing.T) {
			c := newTestCPU()
			c.mem.WriteN(0x0200, test.op, 0x03) // branch to $0205
			c.mem.WriteN(0x0202, 0xa9, 0x01)    // lda #$01
			c.mem.WriteN(0x0204, 0x00)          // brk
			c.mem.WriteN(0x0205, 0xa9, 0x02)    // lda #$02
			c.SR = test.flags
			testRunCPU(t, c)
			want := test.expectedA
			have := c.A
			if want != have {
				t.Errorf("\n want: %02x \n have: %02x \n", want, have)
			}
		})
	}
}

func TestBranchBackwards(t *testing.T) {
	c := newTestCPU()
	c.SetPC(0x0202)
	c.mem.WriteN(0x0200, 0xa9, 0x01) // lda #$01
	c.mem.WriteN(0x0202, 0x00)       // brk
	c.mem.WriteN(0x0203, 0xd0, 0xfb) // bne $0200
	testRunCPU(t, c)
	want := uint8(0x01)
	have := c.A
	if want != have {
		t.Errorf("\n want: %04x \n have: %04x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// cmp
// ----------------------------------------------------------------------------
func TestCmpImmediateEqual(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.WriteN(0x0200, 0xc9, 0x12) // cmp #$12
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpImmediateLessThan(t *testing.T) {
	c := newTestCPU()
	c.A = 0x02
	c.mem.WriteN(0x0200, 0xc9, 0x12) // cmp #$12
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpImmediateGreaterThan(t *testing.T) {
	c := newTestCPU()
	c.A = 0x22
	c.mem.WriteN(0x0200, 0xc9, 0x12) // cmp #$12
	testRunCPU(t, c)
	want := FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpZeroPage(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xc5, 0x34) // cmp $34
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xd5, 0x30) // cmp $30,X
	c.X = 0x04
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpAbsolute(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xcd, 0xab, 0x02) // cmp $02ab
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xdd, 0xa0, 0x02) // cmp $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xd9, 0xa0, 0x02) // cmp $02a0,Y
	c.Y = 0x0b
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpIndirectX(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xc1, 0x40) // cmp ($40,X)
	c.X = 0x0a
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCmpIndirectY(t *testing.T) {
	c := newTestCPU()
	c.A = 0x12
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xd1, 0x4a) // cmp ($4a),Y
	c.Y = 0x0b
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// cpx
// ----------------------------------------------------------------------------
func TestCpxImmediateEqual(t *testing.T) {
	c := newTestCPU()
	c.X = 0x12
	c.mem.WriteN(0x0200, 0xe0, 0x12) // cpx #$12
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpxImmediateLessThan(t *testing.T) {
	c := newTestCPU()
	c.X = 0x02
	c.mem.WriteN(0x0200, 0xe0, 0x12) // cpx #$12
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpxImmediateGreaterThan(t *testing.T) {
	c := newTestCPU()
	c.X = 0x22
	c.mem.WriteN(0x0200, 0xe0, 0x12) // cpx #$12
	testRunCPU(t, c)
	want := FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpxZeroPage(t *testing.T) {
	c := newTestCPU()
	c.X = 0x12
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xe4, 0x34) // cpx $34
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpxAbsolute(t *testing.T) {
	c := newTestCPU()
	c.X = 0x12
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xec, 0xab, 0x02) // cpx $02ab
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// cpy
// ----------------------------------------------------------------------------
func TestCpyImmediateEqual(t *testing.T) {
	c := newTestCPU()
	c.Y = 0x12
	c.mem.WriteN(0x0200, 0xc0, 0x12) // cpy #$12
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpyImmediateLessThan(t *testing.T) {
	c := newTestCPU()
	c.Y = 0x02
	c.mem.WriteN(0x0200, 0xc0, 0x12) // cpy #$12
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpyImmediateGreaterThan(t *testing.T) {
	c := newTestCPU()
	c.Y = 0x22
	c.mem.WriteN(0x0200, 0xc0, 0x12) // cpy #$12
	testRunCPU(t, c)
	want := FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpyZeroPage(t *testing.T) {
	c := newTestCPU()
	c.Y = 0x12
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xc4, 0x34) // cpy $34
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCpyAbsolute(t *testing.T) {
	c := newTestCPU()
	c.Y = 0x12
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xcc, 0xab, 0x02) // cpy $02ab
	testRunCPU(t, c)
	want := FlagZ | FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// dec
// ----------------------------------------------------------------------------
func TestDecZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x12)          // .byte $12
	c.mem.WriteN(0x0200, 0xc6, 0xab) // dec $ab
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestDecZeroPageZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x01)          // .byte $01
	c.mem.WriteN(0x0200, 0xc6, 0xab) // dec $ab
	testRunCPU(t, c)
	want := uint8(0x00)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestDecZeroPageSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x00)          // .byte $00
	c.mem.WriteN(0x0200, 0xc6, 0xab) // dec $ab
	testRunCPU(t, c)
	want := uint8(0xff)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestDecZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x12)          // .byte $12
	c.mem.WriteN(0x0200, 0xd6, 0xa0) // dec $a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestDecAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xce, 0xab, 0x02) // dec $02ab
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestDecAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xde, 0xa0, 0x02) // dec $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// dex
// ----------------------------------------------------------------------------
func TestDex(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xca)
	c.X = 0x12
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestDexZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xca)
	c.X = 0x01
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestDexSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xca)
	c.X = 0x00
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// dey
// ----------------------------------------------------------------------------
func TestDey(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x88)
	c.Y = 0x12
	testRunCPU(t, c)
	want := uint8(0x11)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestDeyZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x88)
	c.Y = 0x01
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestDeySigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x88)
	c.Y = 0x00
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// eor
// ----------------------------------------------------------------------------
func TestEorImmdediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x200, 0x49, 0x01) // eor #$01
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestEorImmediateZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x200, 0x49, 0x01) // eor #$01
	c.A = 0x01
	testRunCPU(t, c)
	want := uint8(0x00)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestEorImmediateSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x200, 0x49, 0x0f) // eor #$0f
	c.A = 0xf0
	testRunCPU(t, c)
	want := uint8(0xff)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestEorZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x45, 0x34) // eor $34
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestEorZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x55, 0x30) // eor $30,X
	c.A = 0x02
	c.X = 0x04
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestEorAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x01)              // .byte $01
	c.mem.WriteN(0x0200, 0x4d, 0xab, 0x02) // eor $02ab
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestEorAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x01)              // .byte $01
	c.mem.WriteN(0x0200, 0x5d, 0xa0, 0x02) // eor $02a0,X
	c.A = 0x02
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestEorAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x01)              // .byte $01
	c.mem.WriteN(0x0200, 0x59, 0xa0, 0x02) // eor $02a0,Y
	c.A = 0x02
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestEorIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x41, 0x40) // eor ($40,X)
	c.A = 0x02
	c.X = 0x0a
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestEorIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x51, 0x4a) // lda ($4a),Y
	c.A = 0x02
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// flags
// ----------------------------------------------------------------------------
func TestClc(t *testing.T) {
	c := newTestCPU()
	c.SP |= FlagC
	c.mem.WriteN(0x0200, 0x18) // clc
	testRunCPU(t, c)
	want := Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSec(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x38) // sec
	testRunCPU(t, c)
	want := FlagC | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCli(t *testing.T) {
	c := newTestCPU()
	c.SR |= FlagI
	c.mem.WriteN(0x0200, 0x58) // cli
	testRunCPU(t, c)
	want := Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSei(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x78) // sei
	testRunCPU(t, c)
	want := FlagI | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestClv(t *testing.T) {
	c := newTestCPU()
	c.SR |= FlagV
	c.mem.WriteN(0x0200, 0xb8) // clv
	testRunCPU(t, c)
	want := Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestCld(t *testing.T) {
	c := newTestCPU()
	c.SR |= FlagD
	c.mem.WriteN(0x0200, 0xd8) // cld
	testRunCPU(t, c)
	want := Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSed(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xf8) // sed
	testRunCPU(t, c)
	want := FlagD | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// inc
// ----------------------------------------------------------------------------
func TestIncZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x12)          // .byte $12
	c.mem.WriteN(0x0200, 0xe6, 0xab) // inc $ab
	testRunCPU(t, c)
	want := uint8(0x13)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestIncZeroPageZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0xff)          // .byte $ff
	c.mem.WriteN(0x0200, 0xe6, 0xab) // inc $ab
	testRunCPU(t, c)
	want := uint8(0x00)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestIncZeroPageSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x7f)          // .byte $7f
	c.mem.WriteN(0x0200, 0xe6, 0xab) // inc $ab
	testRunCPU(t, c)
	want := uint8(0x80)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestIncZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0xab, 0x12)          // .byte $12
	c.mem.WriteN(0x0200, 0xf6, 0xa0) // inc $a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x13)
	have := c.mem.Read(0xab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestIncAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xee, 0xab, 0x02) // inc $02ab
	testRunCPU(t, c)
	want := uint8(0x13)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestIncAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xfe, 0xa0, 0x02) // inc $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x13)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// inx
// ----------------------------------------------------------------------------
func TestInx(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe8)
	c.X = 0x12
	testRunCPU(t, c)
	want := uint8(0x13)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestInxZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe8)
	c.X = 0xff
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestInxSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe8)
	c.X = 0x7f
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// iny
// ----------------------------------------------------------------------------
func TestIny(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xc8)
	c.Y = 0x12
	testRunCPU(t, c)
	want := uint8(0x13)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestInyZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xc8)
	c.Y = 0xff
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestInySigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xc8)
	c.Y = 0x7f
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// jmp
// ----------------------------------------------------------------------------
func TestJmpAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x4c, 0x30, 0x02) // jmp $0230
	c.Next()
	want := uint16(0x022f)
	have := c.pc
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestJmpIndirect(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x0230, 0x0240)
	c.mem.WriteN(0x0200, 0x6c, 0x30, 0x02) // jmp ($0230)
	c.Next()
	want := uint16(0x023f)
	have := c.pc
	if want != have {
		t.Errorf("\n want: %04x \n have: %04x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// jsr
// ----------------------------------------------------------------------------
func TestJsr(t *testing.T) {
	c := newTestCPU()
	c.pc = 0x02ff
	c.mem.WriteN(0x0300, 0x20, 0x30, 0x04) // jsr $0430
	c.Next()
	want0 := uint16(0x042f)
	have0 := c.pc
	if want0 != have0 {
		t.Errorf("\n want: %04x \n have: %04x \n", want0, have0)
	}
	want1 := 0x0302
	have1 := c.mem.ReadLE(addrStack + 0x100 - 2)
	if want1 != have1 {
		t.Errorf("\n want: %04x \n have: %04x \n", want1, have1)
	}
}

// ----------------------------------------------------------------------------
// lda
// ----------------------------------------------------------------------------
func TestLdaImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa9, 0x12) // lda #$12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdaZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa9, 0x00) // lda #$00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdaSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa9, 0xff) // lda #$ff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdaZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xa5, 0x34) // lda $34
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdaZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xb5, 0x30) // lda $30,X
	c.X = 0x4
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdaAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xad, 0xab, 0x02) // lda $02ab
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdaAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xbd, 0xa0, 0x02) // lda $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdaAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xb9, 0xa0, 0x02) // lda $02a0,Y
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdaIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xa1, 0x40) // lda ($40,X)
	c.X = 0x0a
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdaIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xb1, 0x4a) // lda ($4a),Y
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// ldx
// ----------------------------------------------------------------------------
func TestLdxImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa2, 0x12) // ldx #$12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdxZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa2, 0x00) // ldx #$00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdxSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa2, 0xff) // ldx #$ff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdxZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xa6, 0x34) // ldx $34
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdxZeroPageY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xb6, 0x30) // ldx $30,Y
	c.Y = 0x04
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdxAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xae, 0xab, 0x02) // ldx $02ab
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdxAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xbe, 0xa0, 0x02) // ldx $02a0,Y
	c.Y = 0xb
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// ldy
// ----------------------------------------------------------------------------
func TestLdyImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa0, 0x12) // ldy #$12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdyZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa0, 0x00) // ldy #$00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdySigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa0, 0xff) // ldy #$ff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLdyZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xa4, 0x34) // ldy $34
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdyZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x12)        // .byte $12
	c.mem.WriteN(0x0200, 0xb4, 0x30) // ldy $30,X
	c.X = 0x4
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdyAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xac, 0xab, 0x02) // ldy $02ab
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLdyAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x12)              // .byte $12
	c.mem.WriteN(0x0200, 0xbc, 0xa0, 0x02) // ldy $02a0,X
	c.X = 0xb
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// lsr
// ----------------------------------------------------------------------------
func TestLsrAccumulator(t *testing.T) {
	c := newTestCPU()
	c.A = 0x04
	c.mem.WriteN(0x0200, 0x04a) // lsr a
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLsrShiftOut(t *testing.T) {
	c := newTestCPU()
	c.A = 0x01
	c.mem.WriteN(0x0200, 0x04a) // lsr a
	testRunCPU(t, c)
	want := uint8(0x00)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestLsrZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 4)           // .byte 4
	c.mem.WriteN(0x0200, 0x46, 0xab) // lsr $ab
	testRunCPU(t, c)
	want := uint8(2)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLsrZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 4)           // .byte 4
	c.mem.WriteN(0x0200, 0x56, 0xa0) // lsr $a0
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(2)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLsrAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 4)                 // .byte 4
	c.mem.WriteN(0x0200, 0x4e, 0xab, 0x02) // lsr $02ab
	testRunCPU(t, c)
	want := uint8(2)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestLsrAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 4)                 // .byte 4
	c.mem.WriteN(0x0200, 0x5e, 0xa0, 0x02) // lsr $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(2)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// nop
// ----------------------------------------------------------------------------
func TestNop(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xea)
	c.Next()
	want := uint16(0x0200)
	have := c.pc
	if want != have {
		t.Errorf("\n want: %04x \n have: %04x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// ora
// ----------------------------------------------------------------------------
func TestOraImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x09, 0x01) // ora #$01
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestOraZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x09, 0x00) // ora #$00
	c.A = 0x00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestOraSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xa9, 0xf0) // and #$f0
	c.A = 0x0f
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestOraZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x05, 0x34) // ora $34
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestOraZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x15, 0x30) // ora $30,X
	c.A = 0x02
	c.X = 0x04
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestOraAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x01)              // .byte $01
	c.mem.WriteN(0x0200, 0x0d, 0xab, 0x02) // ora $02ab
	c.A = 0x02
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestOraAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x01)              // .byte $01
	c.mem.WriteN(0x0200, 0x1d, 0xa0, 0x02) // ora $02a0,X
	c.A = 0x02
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestOraAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x01)              // .byte $01
	c.mem.WriteN(0x0200, 0x19, 0xa0, 0x02) // ora $02a0,Y
	c.A = 0x02
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestOraIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x01, 0x40) // ora ($40,X)
	c.A = 0x02
	c.X = 0x0a
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestOraIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x01)        // .byte $01
	c.mem.WriteN(0x0200, 0x11, 0x4a) // ora ($4a),Y
	c.A = 0x02
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x03)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// pha
// ----------------------------------------------------------------------------
func TestPha(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x48)
	c.A = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(addrStack + 0xff)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// php
// ----------------------------------------------------------------------------
func TestPhp(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x08)
	c.SR |= FlagC
	testRunCPU(t, c)
	want := FlagC | Flag5 | FlagB
	have := c.mem.Read(addrStack + 0xff)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// pla
// ----------------------------------------------------------------------------
func TestPla(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x68)
	c.SP = 0xfe
	c.mem.Write(addrStack+0xff, 0x12)
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestPlaZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x68)
	c.SP = 0xfe
	c.mem.Write(addrStack+0xff, 0x00)
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestPlaSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x68)
	c.SP = 0xfe
	c.mem.Write(addrStack+0xff, 0xff)
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// plp
// ----------------------------------------------------------------------------
func TestPlp(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x28)
	c.SP = 0xfe
	c.mem.Write(addrStack+0xff, FlagC|FlagN)
	testRunCPU(t, c)
	want := FlagC | FlagN | Flag5
	have := c.SR
	if want != have {
		flagError(t, want, have)
	}
}

// ----------------------------------------------------------------------------
// rol
// ----------------------------------------------------------------------------
func TestRolAccumulator(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x2a) // rol a
	c.A = 4
	testRunCPU(t, c)
	want := uint8(0x08)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestRolRotateOut(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x2a) // rol a
	c.A = 1 << 7
	testRunCPU(t, c)
	want := uint8(0)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestRolRotateIn(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x2a) // rol a
	c.SR |= FlagC
	c.A = 0
	testRunCPU(t, c)
	want := uint8(0x01)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestRolSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x2a) // rol a
	c.A = 1 << 6
	testRunCPU(t, c)
	want := uint8(1 << 7)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestRolZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 0x04)        // .byte 0x04
	c.mem.WriteN(0x0200, 0x26, 0xab) // rol $ab
	testRunCPU(t, c)
	want := uint8(0x08)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}
func TestRolZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 0x04)        // .byte 0x04
	c.mem.WriteN(0x0200, 0x36, 0xa0) // rol $a0
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x08)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestRolAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x04)              // .byte 0x04
	c.mem.WriteN(0x0200, 0x2e, 0xab, 0x02) // rol $02ab
	testRunCPU(t, c)
	want := uint8(0x08)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestRolAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x04)              // .byte 0x04
	c.mem.WriteN(0x0200, 0x3e, 0xa0, 0x02) // rol $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x08)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// ror
// ----------------------------------------------------------------------------
func TestRorAccumulator(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x6a) // ror a
	c.A = 4
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}
func TestRorRotateOut(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x6a) // ror a
	c.A = 1
	testRunCPU(t, c)
	want := uint8(0)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestRorRotateIn(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x6a) // ror a
	c.SR |= FlagC
	c.A = 0
	testRunCPU(t, c)
	want := uint8(0x80)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestRorZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 0x04)        // .byte 0x04
	c.mem.WriteN(0x0200, 0x66, 0xab) // ror $ab
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestRorZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x00ab, 0x04)        // .byte 0x04
	c.mem.WriteN(0x0200, 0x76, 0xa0) // ror $a0
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.mem.Read(0x00ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestRorAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x04)              // .byte 0x04
	c.mem.WriteN(0x0200, 0x6e, 0xab, 0x02) // ror $02ab
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestRorAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x04)              // .byte 0x04
	c.mem.WriteN(0x0200, 0x7e, 0xa0, 0x02) // ror $02a0,X
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// rti
// ----------------------------------------------------------------------------
func TestRti(t *testing.T) {
	c := newTestCPU()
	c.push2(0x1234)
	c.push(FlagC)
	c.mem.Write(0x0200, 0x40) //rti
	testRunCPU(t, c)
	wantSR := FlagC | Flag5
	haveSR := c.SR
	if wantSR != haveSR {
		t.Errorf("\n want: %02x \n have: %02x \n", wantSR, haveSR)
	}
	wantPC := uint16(0x1234)
	havePC := c.pc
	if wantPC != havePC {
		t.Errorf("\n want: %04x \n have: %04x \n", wantPC, havePC)
	}
}

// ----------------------------------------------------------------------------
// rts
// ----------------------------------------------------------------------------
func TestRts(t *testing.T) {
	c := newTestCPU()
	c.push2(0x1234)
	c.mem.Write(0x0200, 0x60) // rts
	c.Next()
	want := uint16(0x1234)
	have := c.pc
	if want != have {
		t.Errorf("\n want: %04x \n have: %04x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// sbc
// ----------------------------------------------------------------------------
func TestSbcImmediate(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc #$02
	c.A = 0x08
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x06)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestAdcWithBorrow(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc #$02
	c.A = 0x08
	testRunCPU(t, c)
	want := uint8(0x05)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSbcCarryResult(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc #$02
	c.A = 0x01
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0xff)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSbcZero(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc #$02
	c.A = 0x02
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x00)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagZ | FlagC | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSbcOverflowSet(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc #$02
	c.A = 0x81
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x7f)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagV | Flag5 | FlagC
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSbcOverflowClear(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0xff) // sbc #$ff (-1)
	c.A = 0x82
	c.SR |= FlagC | FlagV
	testRunCPU(t, c)
	want := uint8(0x83)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
	want = FlagN | Flag5
	have = c.SR
	if want != have {
		flagError(t, want, have)
	}
}

func TestSbcBcd(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc $#02
	c.SR |= FlagD | FlagC
	c.A = 0x11
	testRunCPU(t, c)
	want := uint8(0x09)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcBcdWithBorrow(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // lda $#02
	c.SR |= FlagD
	c.A = 0x11
	testRunCPU(t, c)
	want := uint8(0x08)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcBcdBorrowResult(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0xe9, 0x02) // sbc #$02
	c.SR |= FlagD | FlagC
	c.A = 0x01
	testRunCPU(t, c)
	want := uint8(0x99)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0xe5, 0x34) // sbc $34
	c.A = 0x0a
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0034, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0xf5, 0x30) // sbc $30,X
	c.A = 0x0a
	c.X = 0x04
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x08)              // .byte $08
	c.mem.WriteN(0x0200, 0xed, 0xab, 0x02) // sbc $02ab
	c.A = 0x0a
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x08)              // .byte $08
	c.mem.WriteN(0x0200, 0xfd, 0xa0, 0x02) // sbc $02a0,X
	c.A = 0x0a
	c.X = 0x0b
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x02ab, 0x08)              // .byte $08
	c.mem.WriteN(0x0200, 0xf9, 0xa0, 0x02) // sbc $02a0,Y
	c.A = 0x0a
	c.Y = 0x0b
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.Write(0x02ab, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0xe1, 0x40) // sbc ($40,X)
	c.A = 0x0a
	c.X = 0x0a
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestSbcIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.Write(0x02ab, 0x08)        // .byte $08
	c.mem.WriteN(0x0200, 0xf1, 0x4a) // sbc ($4a),Y
	c.A = 0x0a
	c.Y = 0x0b
	c.SR |= FlagC
	testRunCPU(t, c)
	want := uint8(0x02)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// sta
// ----------------------------------------------------------------------------
func TestStaZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x85, 0x34) // sta $34
	c.A = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x34)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStaZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x95, 0x30) // sta $30,X
	c.A = 0x12
	c.X = 0x04
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x34)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStaAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x8d, 0xab, 0x02) // sta $02ab
	c.A = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStaAbsoluteX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x9d, 0xa0, 0x02) // sta $02a0,X
	c.A = 0x12
	c.X = 0x0b
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStaAbsoluteY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x99, 0xa0, 0x02) // sta $02a0,Y
	c.A = 0x12
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStaIndirectX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02ab)      // .word $02ab
	c.mem.WriteN(0x0200, 0x81, 0x40) // sta ($40,X)
	c.A = 0x12
	c.X = 0x0a
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStaIndirectY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteLE(0x4a, 0x02a0)      // .word $02a0
	c.mem.WriteN(0x0200, 0x91, 0x4a) // sta ($4a),Y
	c.A = 0x12
	c.Y = 0x0b
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// stx
// ----------------------------------------------------------------------------

func TestStxZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x86, 0x34) // stx $34
	c.X = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x34)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStxZeroPageY(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x96, 0x30) // stx $30,Y
	c.X = 0x12
	c.Y = 0x04
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x34)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStxAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x8e, 0xab, 0x02) // stx $02ab
	c.X = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// sty
// ----------------------------------------------------------------------------

func TestStyZeroPage(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x84, 0x34) // sty $34
	c.Y = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x34)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStyZeroPageX(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x94, 0x30) // sty $30,X
	c.Y = 0x12
	c.X = 0x04
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x34)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestStyAbsolute(t *testing.T) {
	c := newTestCPU()
	c.mem.WriteN(0x0200, 0x8c, 0xab, 0x02) // sty $02ab
	c.Y = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.mem.Read(0x02ab)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// tax
// ----------------------------------------------------------------------------
func TestTax(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xaa)
	c.A = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTaxZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xaa)
	c.A = 0x00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTaxSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xaa)
	c.A = 0xff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// tay
// ----------------------------------------------------------------------------
func TestTay(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xa8)
	c.A = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.Y
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTayZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xa8)
	c.A = 0x00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTaySigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xa8)
	c.A = 0xff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// tsx
// ----------------------------------------------------------------------------
func TestTsx(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xba)
	c.SP = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.X
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTsxZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xba)
	c.SP = 0x00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTsxSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0xba)
	c.SP = 0xff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// txa
// ----------------------------------------------------------------------------
func TestTxa(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x8a)
	c.X = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTxaZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x8a)
	c.X = 0x00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTxaSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x8a)
	c.X = 0xff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// txs
// ----------------------------------------------------------------------------
func TestTxs(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x9a)
	c.X = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.SP
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

// ----------------------------------------------------------------------------
// tya
// ----------------------------------------------------------------------------
func TestTya(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x98)
	c.Y = 0x12
	testRunCPU(t, c)
	want := uint8(0x12)
	have := c.A
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTyaZero(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x98)
	c.Y = 0x00
	testRunCPU(t, c)
	want := FlagZ | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}

func TestTyaSigned(t *testing.T) {
	c := newTestCPU()
	c.mem.Write(0x0200, 0x98)
	c.Y = 0xff
	testRunCPU(t, c)
	want := FlagN | Flag5
	have := c.SR
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x \n", want, have)
	}
}


<|start_filename|>rcs/z80/dasm_test.go<|end_filename|>
package z80

import (
	"fmt"
	"testing"

	"github.com/blackchip-org/retro-cs/mock"
	"github.com/blackchip-org/retro-cs/rcs"
)

type harstonTest struct {
	Name  string
	Op    string
	Bytes []uint8
}

func TestDasm(t *testing.T) {
	for _, test := range harstonTests {
		t.Run(test.Name, func(t *testing.T) {
			mock.ResetMemory()
			ptr := rcs.NewPointer(mock.TestMemory)
			dasm := NewDisassembler(mock.TestMemory)
			dasm.SetPC(0x10)
			ptr.SetAddr(0x10)
			ptr.PutN(test.Bytes...)
			ptr.SetAddr(0x10)
			s := dasm.NextStmt()
			if s.Op != test.Op {
				t.Errorf("\n have: %v \n want: %v", s.Op, test.Op)
			}
		})
	}
}

func TestInvalid(t *testing.T) {
	var tests = []struct {
		name   string
		prefix []uint8
	}{
		{"dd", []uint8{0xdd}},
		{"ed", []uint8{0xed}},
		{"fd", []uint8{0xfd}},
		{"ddcb", []uint8{0xdd, 0xcb}},
		{"fdcb", []uint8{0xfd, 0xcb}},
	}

	for _, test := range tests {
		for opcode := 0; opcode < 0x100; opcode++ {
			if test.name == "dd" || test.name == "fd" {
				switch opcode {
				case 0xdd, 0xed, 0xfd, 0xcb:
					continue
				}
			}
			mock.ResetMemory()
			ptr := rcs.NewPointer(mock.TestMemory)
			ptr.Put(test.prefix[0])
			if len(test.prefix) > 1 {
				ptr.Put(test.prefix[1])
				ptr.Put(0) // displacement byte
			}
			ptr.Put(uint8(opcode))
			dasm := NewDisassembler(mock.TestMemory)
			s := dasm.NextStmt()
			if s.Op[0] == '?' {
				name := fmt.Sprintf("%v%02x", test.name, opcode)
				t.Run(name, func(t *testing.T) {
					want := fmt.Sprintf("?%s%02x", test.name, opcode)
					if s.Op != want {
						t.Errorf("\n have: %v \n want: %v", s.Op, want)
					}
				})
			}
		}
	}
}

func TestInvalidDD(t *testing.T) {
	for i := 0; i <= 0xff; i++ {
		name := fmt.Sprintf("%02x", i)
		t.Run(name, func(t *testing.T) {
			mock.ResetMemory()
			mem := mock.TestMemory
			mem.Write(0, 0xdd)
			mem.Write(1, uint8(i))
			dasm := NewDisassembler(mem)
			s := dasm.NextStmt()
			if s.Op[0] == '?' && i != 0xdd && i != 0xed && i != 0xfd && i != 0xcb {
				want := fmt.Sprintf("?dd%02x", i)
				if s.Op != want {
					t.Errorf("\n have: %v \n want: %v", s.Op, want)
				}
			}
		})
	}
}

func TestInvalidFD(t *testing.T) {
	for i := 0; i <= 0xff; i++ {
		name := fmt.Sprintf("%02x", i)
		t.Run(name, func(t *testing.T) {
			mock.ResetMemory()
			mem := mock.TestMemory
			mem.Write(0, 0xfd)
			mem.Write(1, uint8(i))
			dasm := NewDisassembler(mem)
			s := dasm.NextStmt()
			if s.Op[0] == '?' && i != 0xdd && i != 0xed && i != 0xfd && i != 0xcb {
				want := fmt.Sprintf("?fd%02x", i)
				if s.Op != want {
					t.Errorf("\n have: %v \n want: %v", s.Op, want)
				}
			}
		})
	}
}

func TestInvalidFDCB(t *testing.T) {
	for i := 0; i <= 0xff; i++ {
		name := fmt.Sprintf("%02x", i)
		t.Run(name, func(t *testing.T) {
			mock.ResetMemory()
			mem := mock.TestMemory
			mem.Write(0, 0xfd)
			mem.Write(1, 0xcb)
			mem.Write(2, 0)
			mem.Write(3, uint8(i))
			dasm := NewDisassembler(mem)
			s := dasm.NextStmt()
			if s.Op[0] == '?' {
				want := fmt.Sprintf("?fdcb%02x", i)
				if s.Op != want {
					t.Errorf("\n have: %v \n want: %v", s.Op, want)
				}
			}
		})
	}
}


<|start_filename|>mock/memory.go<|end_filename|>
package mock

import (
	"github.com/blackchip-org/retro-cs/rcs"
)

// The FUSE tests want the full address space available. Creating memory
// is expensive and with the amount of tests to run it takes up to 12 seconds
// to complete. Instead, create memory once and zero out the backing
// slice each time.
var (
	TestMemory *rcs.Memory
	testRAM    []uint8
	testZero   []uint8
)

func init() {
	testRAM = make([]uint8, 0x10000, 0x10000)
	testZero = make([]uint8, 0x10000, 0x10000)
	TestMemory = rcs.NewMemory(1, 0x10000)
	TestMemory.MapRAM(0, testRAM)
}

// ResetMemory zeros out all memory values in TestMemory.
func ResetMemory() {
	copy(testRAM, testZero)
}

func MockRead(data []int) func() uint8 {
	pos := 0
	return func() uint8 {
		pos++
		return uint8(data[pos-1])
	}
}


<|start_filename|>system/c64/roms.go<|end_filename|>
package c64

import "github.com/blackchip-org/retro-cs/rcs"

var SystemROM = []rcs.ROM{
	rcs.NewROM("basic  ", "basic  ", "79015323128650c742a3694c9429aa91f355905e"),
	rcs.NewROM("chargen", "chargen", "adc7c31e18c7c7413d54802ef2f4193da14711aa"),
	rcs.NewROM("kernal ", "kernal ", "1d503e56df85a62fee696e7618dc5b4e781df1bb"),
}


<|start_filename|>tools/icmp/icmp-rcs/icmp-rcs.go<|end_filename|>
package main

import (
	"fmt"

	"github.com/blackchip-org/retro-cs/mock"
	"github.com/blackchip-org/retro-cs/rcs/z80"
)

func main() {
	af()
}

func cpd() {
	for a := 0; a <= 0xff; a++ {
		for _hl := 0; _hl <= 0xff; _hl++ {
			for f := 0; f <= 1; f++ {
				for c := 2; c <= 2; c++ {
					mock.ResetMemory()
					mem := mock.TestMemory
					cpu := z80.New(mem)
					mem.Write(0x1234, uint8(_hl))
					cpu.H, cpu.L = 0x12, 0x34
					cpu.C = uint8(c)
					cpu.A = uint8(a)
					cpu.F = uint8(f)
					mem.WriteN(0x00, 0xed, 0xb9)
					cpu.Next()
					fmt.Printf("a:%02x _hl:%02x c:%02x f:%02x => b:%02x c:%02x f:%02x\n", a, _hl, c, f, cpu.B, cpu.C, cpu.F)
				}
			}
		}
	}
}

func af() {
	for f := 0; f <= 0xff; f++ {
		for a := 0; a <= 0xff; a++ {
			mock.ResetMemory()
			mem := mock.TestMemory
			cpu := z80.New(mem)
			mem.Write(0x00, 0x17)
			cpu.A = uint8(a)
			cpu.F = uint8(f)
			cpu.Next()
			fmt.Printf("a:%02x f:%02x => a:%02x f:%02x\n", a, f, cpu.A, cpu.F)
		}
	}
}


<|start_filename|>rcs/video.go<|end_filename|>
package rcs

import (
	"fmt"
	"image/color"
	"math"

	"github.com/veandco/go-sdl2/sdl"
)

type TileSheet struct {
	TextureW int32
	TextureH int32
	TileW    int32
	TileH    int32
	Texture  *sdl.Texture
}

type Screen struct {
	W         int32
	H         int32
	X         int32
	Y         int32
	Scale     int32
	Texture   *sdl.Texture
	ScanLineH bool
	ScanLineV bool
	Draw      func(*sdl.Renderer) error
}

func NewColorSheet(r *sdl.Renderer, palettes [][]color.RGBA) (TileSheet, error) {
	tileW := int32(32)
	tileH := int32(32)

	colorN := len(palettes) * len(palettes[0])
	per := int32(math.Sqrt(float64(colorN)))

	texW := per * tileW
	texH := per * tileH

	t, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888,
		sdl.TEXTUREACCESS_TARGET, texW, texH)
	if err != nil {
		return TileSheet{}, fmt.Errorf("unable to create sheet: %v", err)
	}
	r.SetRenderTarget(t)

	x := int32(0)
	y := int32(0)
	for _, pal := range palettes {
		for _, c := range pal {
			r.SetDrawColor(c.R, c.G, c.B, c.A)
			r.FillRect(&sdl.Rect{
				X: x,
				Y: y,
				W: tileW,
				H: tileH,
			})
			x += tileW
			if x >= texW {
				x = 0
				y += tileH
			}
		}
	}
	r.SetRenderTarget(nil)
	return TileSheet{
		TextureW: texW,
		TextureH: texH,
		TileW:    tileW,
		TileH:    tileH,
		Texture:  t,
	}, nil
}

func NewScanLinesV(r *sdl.Renderer, w int32, h int32, size int32) (*sdl.Texture, error) {
	tex, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888,
		sdl.TEXTUREACCESS_TARGET, w, h)
	if err != nil {
		return nil, err
	}

	pixels := make([]uint32, w*h, w*h)
	for y := int32(0); y < h; y++ {
		for x := int32(0); x < w; x += 2 * size {
			ptr := (y * w) + x
			for i := int32(0); i < size; i++ {
				pixels[ptr] = 0x00000000
				ptr++
			}
			for i := int32(size); i < size*2; i++ {
				pixels[ptr] = 0x00000020
				ptr++
			}
		}
	}
	tex.SetBlendMode(sdl.BLENDMODE_BLEND)
	tex.UpdateRGBA(nil, pixels, int(w))
	return tex, nil
}

func NewScanLinesH(r *sdl.Renderer, w int32, h int32, size int32) (*sdl.Texture, error) {
	tex, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888,
		sdl.TEXTUREACCESS_TARGET, w, h)
	if err != nil {
		return nil, err
	}

	pixels := make([]uint32, w*h, w*h)
	for x := int32(0); x < w; x++ {
		for y := int32(0); y < h; y += 2 * size {
			ptr := (y * w) + x
			for i := int32(0); i < size; i++ {
				pixels[ptr] = 0x00000000
				ptr += w
			}
			for i := int32(size); i < size*2; i++ {
				pixels[ptr] = 0x00000020
				ptr += w
			}
		}
	}
	tex.SetBlendMode(sdl.BLENDMODE_BLEND)
	tex.UpdateRGBA(nil, pixels, int(w))
	return tex, nil
}

func FitInWindow(winW int32, winH int32, screen *Screen) {
	deltaW, deltaH := winW-screen.W, winH-screen.H
	scale := int32(1)
	if deltaW < deltaH {
		scale = winW / screen.W
	} else {
		scale = winH / screen.H
	}
	scaledW, scaledH := screen.W*scale, screen.H*scale
	screen.X = (winW - scaledW) / 2
	screen.Y = (winH - scaledH) / 2
	screen.Scale = scale
}


<|start_filename|>rcs/m6502/dasm.go<|end_filename|>
package m6502

type mode int

const (
	absolute mode = iota
	absoluteX
	absoluteY
	accumulator
	immediate
	implied
	indirect
	indirectX
	indirectY
	relative
	zeroPage
	zeroPageX
	zeroPageY
)

type op struct {
	inst string
	mode mode
}

var operandLengths = map[mode]int{
	absolute:    2,
	absoluteX:   2,
	absoluteY:   2,
	accumulator: 0,
	immediate:   1,
	implied:     0,
	indirect:    2,
	indirectX:   1,
	indirectY:   1,
	relative:    1,
	zeroPage:    1,
	zeroPageX:   1,
	zeroPageY:   1,
}

var operandFormats = map[mode]string{
	absolute:    "$%04x",
	absoluteX:   "$%04x,x",
	absoluteY:   "$%04x,y",
	accumulator: "a",
	immediate:   "#$%02x",
	indirect:    "($%04x)",
	indirectX:   "($%02x,x)",
	indirectY:   "($%02x),y",
	relative:    "$%04x",
	zeroPage:    "$%02x",
	zeroPageX:   "$%02x,x",
	zeroPageY:   "$%02x,y",
}

var dasmTable = map[uint8]op{
	0x00: op{"brk", implied},
	0x01: op{"ora", indirectX},
	0x05: op{"ora", zeroPage},
	0x06: op{"asl", zeroPage},
	0x08: op{"php", implied},
	0x09: op{"ora", immediate},
	0x0a: op{"asl", accumulator},
	0x0d: op{"ora", absolute},
	0x0e: op{"asl", absolute},

	0x10: op{"bpl", relative},
	0x11: op{"ora", indirectY},
	0x15: op{"ora", zeroPageX},
	0x16: op{"asl", zeroPageX},
	0x18: op{"clc", implied},
	0x19: op{"ora", absoluteY},
	0x1d: op{"ora", absoluteX},
	0x1e: op{"asl", absoluteX},

	0x20: op{"jsr", absolute},
	0x21: op{"and", indirectX},
	0x24: op{"bit", zeroPage},
	0x25: op{"and", zeroPage},
	0x26: op{"rol", zeroPage},
	0x28: op{"plp", implied},
	0x29: op{"and", immediate},
	0x2a: op{"rol", accumulator},
	0x2c: op{"bit", absolute},
	0x2d: op{"and", absolute},
	0x2e: op{"rol", absolute},

	0x30: op{"bmi", relative},
	0x31: op{"and", indirectY},
	0x35: op{"and", zeroPageX},
	0x36: op{"rol", zeroPageX},
	0x38: op{"sec", implied},
	0x39: op{"and", absoluteY},
	0x3d: op{"and", absoluteX},
	0x3e: op{"rol", absoluteX},

	0x40: op{"rti", implied},
	0x41: op{"eor", indirectX},
	0x45: op{"eor", zeroPage},
	0x46: op{"lsr", zeroPage},
	0x48: op{"pha", implied},
	0x49: op{"eor", immediate},
	0x4a: op{"lsr", accumulator},
	0x4c: op{"jmp", absolute},
	0x4d: op{"eor", absolute},
	0x4e: op{"lsr", absolute},

	0x50: op{"bvc", relative},
	0x51: op{"eor", indirectY},
	0x55: op{"eor", zeroPageX},
	0x56: op{"lsr", zeroPageX},
	0x58: op{"cli", implied},
	0x59: op{"eor", absoluteY},
	0x5d: op{"eor", absoluteX},
	0x5e: op{"lsr", absoluteX},

	0x60: op{"rts", implied},
	0x61: op{"adc", indirectX},
	0x65: op{"adc", zeroPage},
	0x66: op{"ror", zeroPage},
	0x68: op{"pla", implied},
	0x69: op{"adc", immediate},
	0x6a: op{"ror", accumulator},
	0x6c: op{"jmp", indirect},
	0x6d: op{"adc", absolute},
	0x6e: op{"ror", absolute},

	0x70: op{"bvs", relative},
	0x71: op{"adc", indirectY},
	0x75: op{"adc", zeroPageX},
	0x76: op{"ror", zeroPageX},
	0x78: op{"sei", implied},
	0x79: op{"adc", absoluteY},
	0x7d: op{"adc", absoluteX},
	0x7e: op{"ror", absoluteX},

	0x81: op{"sta", indirectX},
	0x84: op{"sty", zeroPage},
	0x85: op{"sta", zeroPage},
	0x86: op{"stx", zeroPage},
	0x88: op{"dey", implied},
	0x8a: op{"txa", implied},
	0x8c: op{"sty", absolute},
	0x8d: op{"sta", absolute},
	0x8e: op{"stx", absolute},

	0x90: op{"bcc", relative},
	0x91: op{"sta", indirectY},
	0x94: op{"sty", zeroPageX},
	0x95: op{"sta", zeroPageX},
	0x96: op{"stx", zeroPageY},
	0x98: op{"tya", implied},
	0x99: op{"sta", absoluteY},
	0x9a: op{"txs", implied},
	0x9d: op{"sta", absoluteX},

	0xa0: op{"ldy", immediate},
	0xa1: op{"lda", indirectX},
	0xa2: op{"ldx", immediate},
	0xa4: op{"ldy", zeroPage},
	0xa5: op{"lda", zeroPage},
	0xa6: op{"ldx", zeroPage},
	0xa8: op{"tay", implied},
	0xa9: op{"lda", immediate},
	0xaa: op{"tax", implied},
	0xac: op{"ldy", absolute},
	0xad: op{"lda", absolute},
	0xae: op{"ldx", absolute},

	0xb0: op{"bcs", relative},
	0xb1: op{"lda", indirectY},
	0xb4: op{"ldy", zeroPageX},
	0xb5: op{"lda", zeroPageX},
	0xb6: op{"ldx", zeroPageY},
	0xb8: op{"clv", implied},
	0xb9: op{"lda", absoluteY},
	0xba: op{"tsx", implied},
	0xbd: op{"lda", absoluteX},
	0xbc: op{"ldy", absoluteX},
	0xbe: op{"ldx", absoluteY},

	0xc0: op{"cpy", immediate},
	0xc1: op{"cmp", indirectX},
	0xc4: op{"cpy", zeroPage},
	0xc5: op{"cmp", zeroPage},
	0xc6: op{"dec", zeroPage},
	0xc8: op{"iny", implied},
	0xc9: op{"cmp", immediate},
	0xca: op{"dex", implied},
	0xcc: op{"cpy", absolute},
	0xcd: op{"cmp", absolute},
	0xce: op{"dec", absolute},

	0xd0: op{"bne", relative},
	0xd1: op{"cmp", indirectY},
	0xd5: op{"cmp", zeroPageX},
	0xd6: op{"dec", zeroPageX},
	0xd8: op{"cld", implied},
	0xd9: op{"cmp", absoluteY},
	0xdd: op{"cmp", absoluteX},
	0xde: op{"dec", absoluteX},

	0xe0: op{"cpx", immediate},
	0xe1: op{"sbc", indirectX},
	0xe4: op{"cpx", zeroPage},
	0xe5: op{"sbc", zeroPage},
	0xe6: op{"inc", zeroPage},
	0xe8: op{"inx", implied},
	0xe9: op{"sbc", immediate},
	0xea: op{"nop", implied},
	0xec: op{"cpx", absolute},
	0xed: op{"sbc", absolute},
	0xee: op{"inc", absolute},

	0xf0: op{"beq", relative},
	0xf1: op{"sbc", indirectY},
	0xf5: op{"sbc", zeroPageX},
	0xf6: op{"inc", zeroPageX},
	0xf8: op{"sed", implied},
	0xf9: op{"sbc", absoluteY},
	0xfd: op{"sbc", absoluteX},
	0xfe: op{"inc", absoluteX},
}


<|start_filename|>gen/cbm/petscii/petscii.go<|end_filename|>
package main

//go:generate go run .
//go:generate go fmt ../../../rcs/cbm/petscii_table.go

import (
	"bufio"
	"bytes"
	"fmt"
	"io/ioutil"
	"log"
	"os"
	"path/filepath"
	"regexp"
	"strconv"
	"strings"

	"github.com/blackchip-org/retro-cs/config"
)

var (
	root      = filepath.Join("..", "..", "..")
	targetDir = filepath.Join(root, "rcs", "cbm")
	sourceDir = filepath.Join(config.ResourceDir(), "ext", "petscii")
)

func main() {
	log.SetFlags(0)
	infile := filepath.Join(sourceDir, "table.txt")
	in, err := os.Open(infile)
	if err != nil {
		log.Fatal(err)
	}
	defer in.Close()

	var table [2][0x100]rune

	s := bufio.NewScanner(in)
	s.Split(bufio.ScanLines)
	for i := 0; i < 6; i++ {
		s.Scan()
	}
	for s.Scan() {
		line := strings.TrimSpace(s.Text())
		if line == "" {
			continue
		}
		if strings.Contains(line, "CHARACTER") {
			break
		}
		fields := strings.Split(line, "|")
		cp := strings.TrimSpace(fields[1])
		charCode, err := strconv.ParseUint(cp[1:], 16, 8)
		if err != nil {
			log.Fatalln(err)
		}
		ucp := strings.TrimSpace(fields[2])
		ucps := regexp.MustCompile("\\s+").Split(ucp, -1)
		if len(ucps) == 1 {
			ucps = append(ucps, ucps[0])
		}

		for tableN, uni := range ucps {
			if uni == "-" {
				table[tableN][charCode] = 0xfffd
			} else {
				value, err := strconv.ParseUint(uni[2:], 16, 16)
				if err != nil {
					log.Fatalln(err)
				}
				table[tableN][int(charCode)] = rune(value)
			}
		}
	}
	if s.Err() != nil {
		log.Fatalln(s.Err())
	}
	var out bytes.Buffer
	out.WriteString("package cbm\n")
	out.WriteString("var petsciiUnshifted = map[uint8]rune {\n")
	for i, val := range table[0] {
		ch := string(val)
		if val == '\'' {
			ch = "\\" + ch
		}
		if printable(i) {
			out.WriteString(fmt.Sprintf("0x%02x: '%s',\n", i, ch))
		}
	}
	out.WriteString("}\n")
	out.WriteString("var petsciiShifted = map[uint8]rune {\n")
	for i, val := range table[1] {
		ch := string(val)
		if val == '\'' {
			ch = "\\" + ch
		}
		if printable(i) {
			out.WriteString(fmt.Sprintf("0x%02x: '%s',\n", i, ch))
		}
	}
	out.WriteString("}\n")
	outfile := filepath.Join(targetDir, "petscii_table.go")
	err = ioutil.WriteFile(outfile, out.Bytes(), 0644)
	if err != nil {
		log.Fatalln(err)
	}
}

func printable(i int) bool {
	if i >= 0x20 && i <= 0x7f {
		return true
	}
	if i >= 0xa0 && i <= 0xbf {
		return true
	}
	return false
}


<|start_filename|>app/monitor/cpu.go<|end_filename|>
package monitor

import (
	"fmt"
	"log"
	"sort"
	"strings"

	"github.com/chzyer/readline"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/m6502"
	"github.com/blackchip-org/retro-cs/rcs/z80"
)

type modCPU struct {
	name   string
	mon    *Monitor
	out    *log.Logger
	cpu    rcs.CPU
	mem    *rcs.Memory
	dasm   *rcs.Disassembler
	brkpts map[int]struct{}
}

func newModCPU(mon *Monitor, comp rcs.Component) module {
	c := comp.C.(rcs.CPU)
	var dasm *rcs.Disassembler
	cpud, ok := c.(rcs.CPUDisassembler)
	if ok {
		dasm = cpud.NewDisassembler()
	}
	mod := &modCPU{
		name:   comp.Name,
		mon:    mon,
		out:    mon.out,
		cpu:    c,
		mem:    c.Memory(),
		dasm:   dasm,
		brkpts: mon.mach.Breakpoints[comp.Name],
	}
	return mod
}

func (m *modCPU) Command(args []string) error {
	if len(args) == 0 {
		return m.cmdInfo(args[0:])
	}
	switch args[0] {
	case "breakpoint", "bp":
		return m.cmdBreakpoint(args[1:])
	case "disassemble", "d":
		return m.cmdDisassemble(args[1:])
	case "info", "i":
		return m.cmdInfo(args[1:])
	case "next", "n":
		return m.cmdNext(args[1:])
	case "step", "s":
		return m.cmdStep(args[1:])
	case "select":
		return m.cmdSelect(args[1:])
	case "trace", "t":
		return m.cmdTrace(args[1:])
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modCPU) cmdBreakpoint(args []string) error {
	if len(args) == 0 {
		return m.cmdBreakpointList(args[0:])
	}
	switch args[0] {
	case "list":
		return m.cmdBreakpointList(args[1:])
	case "none":
		return m.cmdBreakpointNone(args[1:])
	case "address":
		return m.cmdBreakpointSwitch(args[1:])
	}
	return m.cmdBreakpointSwitch(args[0:])
}

func (m *modCPU) cmdBreakpointClear(args []string) error {
	if err := checkLen(args, 1, 1); err != nil {
		return err
	}
	addr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return err
	}
	delete(m.brkpts, addr)
	return nil
}

func (m *modCPU) cmdBreakpointList(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	if len(m.brkpts) == 0 {
		return nil
	}
	addrs := make([]string, 0, 0)
	for k := range m.brkpts {
		addrs = append(addrs, fmt.Sprintf("%v%v", m.prefix(), formatAddress(k)))
	}
	sort.Strings(addrs)
	m.mon.out.Printf(strings.Join(addrs, "\n"))
	return nil
}

func (m *modCPU) cmdBreakpointNone(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	for k := range m.brkpts {
		delete(m.brkpts, k)
	}
	return nil
}

func (m *modCPU) cmdBreakpointSwitch(args []string) error {
	if err := checkLen(args, 1, 2); err != nil {
		return err
	}
	addr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return fmt.Errorf("invalid address: %v", args[0])
	}
	if len(args) == 1 {
		if _, ok := m.brkpts[addr]; ok {
			m.out.Println("on")
		} else {
			m.out.Println("off")
		}
		return nil
	}
	switch args[1] {
	case "on":
		m.brkpts[addr] = struct{}{}
		return nil
	case "off":
		delete(m.brkpts, addr)
		return nil
	}
	return fmt.Errorf("invalid argument: %v", args[0])
}

func (m *modCPU) cmdDisassemble(args []string) error {
	if err := checkLen(args, 0, 2); err != nil {
		return err
	}
	if m.dasm == nil {
		return fmt.Errorf("cannot disassemble this processor")
	}
	if len(args) > 0 {
		addr, err := parseAddress(m.mem, args[0])
		if err != nil {
			return err
		}
		m.dasm.SetPC(addr)
	}
	if len(args) > 1 {
		// list until at ending address
		addrEnd, err := parseAddress(m.mem, args[1])
		if err != nil {
			return err
		}
		for m.dasm.PC() <= addrEnd {
			m.mon.out.Printf("%v%v\n", m.prefix(), m.dasm.Next())
		}
	} else {
		// list number of lines
		lines := m.mon.dasmLines
		if lines == 0 {
			_, h, err := readline.GetSize(0)
			if err != nil {
				return err
			}
			lines = h - 1
			if lines <= 0 {
				lines = 1
			}
		}
		for i := 0; i < lines; i++ {
			m.mon.out.Printf("%v%v\n", m.prefix(), m.dasm.Next())
		}
	}
	// m.lastCmd = m.cmdDasmList
	return nil
}

func (m *modCPU) cmdInfo(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	name := ""
	if m.name != "cpu" {
		name = m.name + ":"
	}
	m.mon.out.Printf("[%v%v]\n", name, m.mon.mach.Status)
	m.mon.out.Printf("%v", m.cpu)
	return nil
}

func (m *modCPU) cmdNext(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	ppc := m.dasm.PC()
	m.dasm.SetPC(m.cpu.PC() + m.cpu.Offset())
	m.mon.out.Println(m.dasm.Next())
	m.dasm.SetPC(ppc)
	return nil
}

func (m *modCPU) cmdSelect(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	m.mon.sc = m.name
	m.mon.rl.SetPrompt(m.mon.getPrompt())
	return nil
}

func (m *modCPU) cmdStep(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	m.cpu.Next()
	ppc := m.dasm.PC()
	m.dasm.SetPC(m.cpu.PC() + m.cpu.Offset())
	m.mon.out.Println(m.dasm.Next())
	m.dasm.SetPC(ppc)
	m.mon.defaultCmd = fmt.Sprintf("%v step", m.name)
	return nil
}

func (m *modCPU) cmdTrace(args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		m.mon.mach.Command(rcs.MachTrace, m.name)
		return nil
	}
	v, err := parseBool(args[0])
	if err != nil {
		return err
	}
	m.mon.mach.Command(rcs.MachTrace, m.name, v)
	return nil
}

func (m *modCPU) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("breakpoint",
			readline.PcItem("list"),
			readline.PcItem("none"),
			readline.PcItem("address"),
		),
		readline.PcItem("disassemble"),
		readline.PcItem("info"),
		readline.PcItem("next"),
		readline.PcItem("step"),
		readline.PcItem("select"),
		readline.PcItem("trace"),
	}
}

func (m *modCPU) Silence() error {
	m.cmdTrace([]string{"off"})
	return nil
}

func (m *modCPU) prefix() string {
	if m.name == "cpu" {
		return ""
	}
	return m.name + "  "
}

type modM6502 struct {
	parent module
	mon    *Monitor
	out    *log.Logger
	cpu    *m6502.CPU
}

func newModM6502(mon *Monitor, comp rcs.Component) module {
	cpu := comp.C.(*m6502.CPU)
	return &modM6502{
		parent: newModCPU(mon, comp),
		mon:    mon,
		out:    mon.out,
		cpu:    cpu,
	}
}

func (m *modM6502) Command(args []string) error {
	if len(args) == 0 {
		return m.parent.Command(args)
	}

	switch args[0] {
	case "r.pc":
		return valueIntF(m.out, m.cpu.PC, m.cpu.SetPC, args[1:])
	case "r.a":
		return valueUint8(m.out, &m.cpu.A, args[1:])
	case "r.x":
		return valueUint8(m.out, &m.cpu.X, args[1:])
	case "r.y":
		return valueUint8(m.out, &m.cpu.Y, args[1:])
	case "r.sp":
		return valueUint8(m.out, &m.cpu.SP, args[1:])
	case "r.sr":
		return valueUint8(m.out, &m.cpu.SR, args[1:])
	case "f.c":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagC, args[1:])
	case "f.z":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagZ, args[1:])
	case "f.i":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagI, args[1:])
	case "f.d":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagD, args[1:])
	case "f.b":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagB, args[1:])
	case "f.v":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagV, args[1:])
	case "f.n":
		return valueBit(m.out, &m.cpu.SR, m6502.FlagN, args[1:])

	case "watch-brk":
		return valueBool(m.out, &m.cpu.WatchBRK, args[1:])
	case "watch-irq":
		return valueBool(m.out, &m.cpu.WatchIRQ, args[1:])
	case "watch-stack":
		return valueBool(m.out, &m.cpu.WatchStack, args[1:])
	}
	return m.parent.Command(args)
}

func (m *modM6502) AutoComplete() []readline.PrefixCompleterInterface {
	cmd := m.parent.AutoComplete()
	cmd = append(cmd, []readline.PrefixCompleterInterface{
		readline.PcItem("r.a"),
		readline.PcItem("r.x"),
		readline.PcItem("r.y"),
		readline.PcItem("r.sp"),
		readline.PcItem("r.sr"),
		readline.PcItem("f.c"),
		readline.PcItem("f.z"),
		readline.PcItem("f.i"),
		readline.PcItem("f.d"),
		readline.PcItem("f.b"),
		readline.PcItem("f.v"),
		readline.PcItem("f.n"),

		readline.PcItem("watch-brk"),
		readline.PcItem("watch-irq"),
	}...)
	sort.Sort(byName(cmd))
	return cmd
}

func (m *modM6502) Silence() error {
	m.parent.Silence()
	m.cpu.WatchBRK = false
	m.cpu.WatchIRQ = false
	m.cpu.WatchStack = false
	return nil
}

type modZ80 struct {
	parent module
	mon    *Monitor
	out    *log.Logger
	cpu    *z80.CPU
}

func newModZ80(mon *Monitor, comp rcs.Component) module {
	cpu := comp.C.(*z80.CPU)
	return &modZ80{
		parent: newModCPU(mon, comp),
		mon:    mon,
		out:    mon.out,
		cpu:    cpu,
	}
}

func (m *modZ80) Command(args []string) error {
	if len(args) == 0 {
		return m.parent.Command(args)
	}

	switch args[0] {
	case "f.c":
		return valueBit(m.out, &m.cpu.F, z80.FlagC, args[1:])
	case "f.n":
		return valueBit(m.out, &m.cpu.F, z80.FlagN, args[1:])
	case "f.v":
		return valueBit(m.out, &m.cpu.F, z80.FlagV, args[1:])
	case "f.p":
		return valueBit(m.out, &m.cpu.F, z80.FlagP, args[1:])
	case "f.3":
		return valueBit(m.out, &m.cpu.F, z80.Flag3, args[1:])
	case "f.h":
		return valueBit(m.out, &m.cpu.F, z80.FlagH, args[1:])
	case "f.5":
		return valueBit(m.out, &m.cpu.F, z80.Flag5, args[1:])
	case "f.z":
		return valueBit(m.out, &m.cpu.F, z80.FlagZ, args[1:])
	case "f.s":
		return valueBit(m.out, &m.cpu.F, z80.FlagS, args[1:])

	case "r.pc":
		return valueIntF(m.out, m.cpu.PC, m.cpu.SetPC, args[1:])
	case "r.a":
		return valueUint8(m.out, &m.cpu.A, args[1:])
	case "r.f":
		return valueUint8(m.out, &m.cpu.F, args[1:])
	case "r.b":
		return valueUint8(m.out, &m.cpu.B, args[1:])
	case "r.c":
		return valueUint8(m.out, &m.cpu.C, args[1:])
	case "r.d":
		return valueUint8(m.out, &m.cpu.D, args[1:])
	case "r.e":
		return valueUint8(m.out, &m.cpu.E, args[1:])
	case "r.h":
		return valueUint8(m.out, &m.cpu.H, args[1:])
	case "r.l":
		return valueUint8(m.out, &m.cpu.L, args[1:])

	case "r.a1":
		return valueUint8(m.out, &m.cpu.A1, args[1:])
	case "r.f1":
		return valueUint8(m.out, &m.cpu.F1, args[1:])
	case "r.b1":
		return valueUint8(m.out, &m.cpu.B1, args[1:])
	case "r.c1":
		return valueUint8(m.out, &m.cpu.C1, args[1:])
	case "r.d1":
		return valueUint8(m.out, &m.cpu.D1, args[1:])
	case "r.e1":
		return valueUint8(m.out, &m.cpu.E1, args[1:])
	case "r.h1":
		return valueUint8(m.out, &m.cpu.H1, args[1:])
	case "r.l1":
		return valueUint8(m.out, &m.cpu.L1, args[1:])

	case "r.af":
		return valueUint16HL(m.out, &m.cpu.A, &m.cpu.F, args[1:])
	case "r.bc":
		return valueUint16HL(m.out, &m.cpu.B, &m.cpu.C, args[1:])
	case "r.de":
		return valueUint16HL(m.out, &m.cpu.D, &m.cpu.E, args[1:])
	case "r.hl":
		return valueUint16HL(m.out, &m.cpu.H, &m.cpu.L, args[1:])

	case "r.af1":
		return valueUint16HL(m.out, &m.cpu.A1, &m.cpu.F1, args[1:])
	case "r.bc1":
		return valueUint16HL(m.out, &m.cpu.B1, &m.cpu.C1, args[1:])
	case "r.de1":
		return valueUint16HL(m.out, &m.cpu.D1, &m.cpu.E1, args[1:])
	case "r.hl1":
		return valueUint16HL(m.out, &m.cpu.H1, &m.cpu.L1, args[1:])

	case "r.i":
		return valueUint8(m.out, &m.cpu.I, args[1:])
	case "r.r":
		return valueUint8(m.out, &m.cpu.R, args[1:])
	case "r.ixh":
		return valueUint8(m.out, &m.cpu.IXH, args[1:])
	case "r.ixl":
		return valueUint8(m.out, &m.cpu.IXL, args[1:])
	case "r.iyh":
		return valueUint8(m.out, &m.cpu.IYH, args[1:])
	case "r.iyl":
		return valueUint8(m.out, &m.cpu.IYL, args[1:])
	case "r.sp":
		return valueUint16(m.out, &m.cpu.SP, args[1:])

	case "r.ix":
		return valueUint16HL(m.out, &m.cpu.IXH, &m.cpu.IXL, args[1:])
	case "r.iy":
		return valueUint16HL(m.out, &m.cpu.IYH, &m.cpu.IYL, args[1:])

	case "r.iff1":
		return valueBool(m.out, &m.cpu.IFF1, args[1:])
	case "r.iff2":
		return valueBool(m.out, &m.cpu.IFF2, args[1:])
	case "r.im":
		return valueUint8(m.out, &m.cpu.IM, args[1:])

	case "watch-irq":
		return valueBool(m.out, &m.cpu.WatchIRQ, args[1:])

	}
	return m.parent.Command(args)
}

func (m *modZ80) AutoComplete() []readline.PrefixCompleterInterface {
	cmd := m.parent.AutoComplete()
	cmd = append(cmd, []readline.PrefixCompleterInterface{
		readline.PcItem("r.pc"),
		readline.PcItem("r.a"),
		readline.PcItem("r.f"),
		readline.PcItem("r.b"),
		readline.PcItem("r.c"),
		readline.PcItem("r.d"),
		readline.PcItem("r.e"),
		readline.PcItem("r.h"),
		readline.PcItem("r.l"),

		readline.PcItem("r.a1"),
		readline.PcItem("r.f1"),
		readline.PcItem("r.b1"),
		readline.PcItem("r.c1"),
		readline.PcItem("r.d1"),
		readline.PcItem("r.e1"),
		readline.PcItem("r.h1"),
		readline.PcItem("r.l1"),

		readline.PcItem("r.af"),
		readline.PcItem("r.bc"),
		readline.PcItem("r.de"),
		readline.PcItem("r.hl"),

		readline.PcItem("r.af1"),
		readline.PcItem("r.bc1"),
		readline.PcItem("r.de1"),
		readline.PcItem("r.hl1"),

		readline.PcItem("r.i"),
		readline.PcItem("r.r"),
		readline.PcItem("r.ixh"),
		readline.PcItem("r.ixl"),
		readline.PcItem("r.iyh"),
		readline.PcItem("r.iyl"),
		readline.PcItem("r.sp"),

		readline.PcItem("r.ix"),
		readline.PcItem("r.iy"),

		readline.PcItem("r.iff1"),
		readline.PcItem("r.iff2"),
		readline.PcItem("r.im"),

		readline.PcItem("f.c"),
		readline.PcItem("f.n"),
		readline.PcItem("f.v"),
		readline.PcItem("f.p"),
		readline.PcItem("f.3"),
		readline.PcItem("f.h"),
		readline.PcItem("f.5"),
		readline.PcItem("f.z"),
		readline.PcItem("f.s"),

		readline.PcItem("watch-irq"),
	}...)
	sort.Sort(byName(cmd))
	return cmd
}

func (m *modZ80) Silence() error {
	m.parent.Silence()
	m.cpu.WatchIRQ = false
	return nil
}


<|start_filename|>cmd/rcs-viewer/main.go<|end_filename|>
package main

import (
	"flag"
	"fmt"
	"log"
	"os"
	"path/filepath"
	"sort"
	"strings"
	"unsafe"

	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/veandco/go-sdl2/img"
	"github.com/veandco/go-sdl2/sdl"
)

var (
	scale    int
	hscan    bool
	vscan    bool
	filename string
)

func init() {
	flag.IntVar(&scale, "scale", 1, "image `scale`")
	flag.StringVar(&config.RCSDir, "home", "", "set the RCS `home` directory")
	flag.BoolVar(&hscan, "hscan", false, "add horizontal scan lines")
	flag.BoolVar(&vscan, "vscan", false, "add vertical scan lines")
	flag.StringVar(&filename, "out", "", "output to `filename`")

	flag.Usage = func() {
		o := flag.CommandLine.Output()
		fmt.Fprintf(o, "Usage: rcs-viewer [options] <view>\n\n")
		flag.PrintDefaults()
		fmt.Fprintf(o, "\nAvailable values for <view>:\n\n")
		list := []string{}
		for key := range views {
			list = append(list, key)
		}
		sort.Strings(list)
		fmt.Fprintln(o, strings.Join(list, "\n"))
		fmt.Fprintln(o)
	}
}

type view struct {
	system string
	roms   []rcs.ROM
	render func(*sdl.Renderer, map[string][]byte) (rcs.TileSheet, error)
}

func main() {
	log.SetFlags(0)

	flag.Parse()
	if flag.NArg() != 1 {
		flag.Usage()
		os.Exit(1)
	}

	v, ok := views[flag.Arg(0)]
	if !ok {
		log.Fatalln("no such view")
	}

	var roms map[string][]byte
	if v.roms != nil {
		dir := filepath.Join(config.ResourceDir(), "data", v.system)
		r, err := rcs.LoadROMs(dir, v.roms)
		if err != nil {
			log.Fatalf("unable to load roms:\n%v\n", err)
		}
		roms = r
	}

	if err := sdl.Init(sdl.INIT_EVERYTHING); err != nil {
		fmt.Fprintf(os.Stderr, "unable to initialize sdl: %v\n", err)
		os.Exit(1)
	}
	defer sdl.Quit()

	window, err := sdl.CreateWindow(
		flag.Arg(0),
		sdl.WINDOWPOS_UNDEFINED, sdl.WINDOWPOS_UNDEFINED,
		100, 100,
		sdl.WINDOW_HIDDEN,
	)
	if err != nil {
		fmt.Fprintf(os.Stderr, "unable to initialize window: %v", err)
		os.Exit(1)
	}

	r, err := sdl.CreateRenderer(window, -1, sdl.RENDERER_ACCELERATED)
	if err != nil {
		log.Fatalf("unable to initialize renderer: %v", err)
	}

	sheet, err := v.render(r, roms)
	if err != nil {
		log.Fatalf("unable to create sheet: %v", err)
	}
	winX, winY := sheet.TextureW*int32(scale), sheet.TextureH*int32(scale)
	window.SetSize(winX, winY)
	window.SetPosition(sdl.WINDOWPOS_CENTERED, sdl.WINDOWPOS_CENTERED)
	window.Show()

	// err = sdl.GLSetSwapInterval(1)
	// if err != nil {
	// 	fmt.Printf("unable to set swap interval: %v\n", err)
	// }

	var scanlines *sdl.Texture
	// Now that the window has been shown, the texture needs to be rerendered.
	sheet, _ = v.render(r, roms)
	slwidth := int32(scale / 2)
	if slwidth == 0 {
		slwidth = 1
	}
	if hscan {
		scanlines, err = rcs.NewScanLinesH(r, winX, winY, slwidth)
		if err != nil {
			log.Fatal(err)
		}
	}
	if vscan {
		scanlines, err = rcs.NewScanLinesV(r, winX, winY, slwidth)
		if err != nil {
			log.Fatal(err)
		}
	}

	if filename != "" {
		surf, err := sdl.CreateRGBSurface(0, winX, winY, 32, 0, 0, 0, 0)
		if err != nil {
			log.Fatal(err)
		}
		r.SetRenderTarget(nil)
		r.SetDrawColor(0, 0, 0, 0)
		r.Clear()
		r.Copy(sheet.Texture, nil, nil)

		pixels := surf.Pixels()
		ptr := unsafe.Pointer(&pixels[0])
		r.ReadPixels(nil, surf.Format.Format, ptr, int(surf.Pitch))

		if err := img.SavePNG(surf, filename); err != nil {
			log.Fatal(err)
		}
		return
	}

	for {
		for event := sdl.PollEvent(); event != nil; event = sdl.PollEvent() {
			if _, ok := event.(*sdl.QuitEvent); ok {
				os.Exit(0)
			}
		}

		r.SetRenderTarget(nil)
		r.SetDrawColor(0, 0, 0, 0)
		r.Clear()
		r.Copy(sheet.Texture, nil, nil)
		if scanlines != nil {
			r.Copy(scanlines, nil, nil)
		}
		sdl.Delay(250)
		r.Present()
	}

}


<|start_filename|>system/c64/memory_test.go<|end_filename|>
package c64

import (
	"fmt"
	"testing"
)

func TestMemoryLoad(t *testing.T) {
	const (
		page00 = 0x0000
		page10 = 0x1000
		page80 = 0x8000
		pagea0 = 0xa000
		pagec0 = 0xc000
		paged0 = 0xd000
		pagee0 = 0xe000
	)

	const (
		vram    = 0xf0
		vbasic  = 0xba
		vkernal = 0xea
		vchar   = 0xca
		vcartlo = 0x0c
		vcarthi = 0xc0
		vio     = 0x10
	)

	cart := make([]byte, 16*1024, 16*1024)
	cart[0x0000] = vcartlo
	cart[0x2000] = vcarthi

	roms := map[string][]byte{
		"basic":   []byte{vbasic},
		"kernal":  []byte{vkernal},
		"chargen": []byte{vchar},
		"cart":    cart,
	}

	ram := make([]uint8, 0x10000, 0x10000)
	io := make([]uint8, 0x1000, 0x1000)
	mem := newMemory(ram, io, roms)
	mem.SetBank(31)
	mem.Write(paged0, vio)

	mem.SetBank(0)
	mem.Write(page00, vram)
	mem.Write(page10, vram)
	mem.Write(page80, vram)
	mem.Write(pagea0, vram)
	mem.Write(pagec0, vram)
	mem.Write(paged0, vram)
	mem.Write(pagee0, vram)

	var tests = []struct {
		mode int
		addr int
		want uint8
	}{
		{0, page00, vram},
		{0, page10, vram},
		{0, page80, vram},
		{0, pagea0, vram},
		{0, pagec0, vram},
		{0, paged0, vram},
		{0, pagee0, vram},

		{1, page00, vram},
		{1, page10, vram},
		{1, page80, vram},
		{1, pagea0, vram},
		{1, pagec0, vram},
		{1, paged0, vram},
		{1, pagee0, vram},

		{2, page00, vram},
		{2, page10, vram},
		{2, page80, vram},
		{2, pagea0, vcarthi},
		{2, pagec0, vram},
		{2, paged0, vchar},
		{2, pagee0, vkernal},

		{3, page00, vram},
		{3, page10, vram},
		{3, page80, vcartlo},
		{3, pagea0, vcarthi},
		{3, pagec0, vram},
		{3, paged0, vchar},
		{3, pagee0, vkernal},

		{4, page00, vram},
		{4, page10, vram},
		{4, page80, vram},
		{4, pagea0, vram},
		{4, pagec0, vram},
		{4, paged0, vram},
		{4, pagee0, vram},

		{5, page00, vram},
		{5, page10, vram},
		{5, page80, vram},
		{5, pagea0, vram},
		{5, pagec0, vram},
		{5, paged0, vio},
		{5, pagee0, vram},

		{6, page00, vram},
		{6, page10, vram},
		{6, page80, vram},
		{6, pagea0, vcarthi},
		{6, pagec0, vram},
		{6, paged0, vio},
		{6, pagee0, vkernal},

		{7, page00, vram},
		{7, page10, vram},
		{7, page80, vcartlo},
		{7, pagea0, vcarthi},
		{7, pagec0, vram},
		{7, paged0, vio},
		{7, pagee0, vkernal},

		{8, page00, vram},
		{8, page10, vram},
		{8, page80, vram},
		{8, pagea0, vram},
		{8, pagec0, vram},
		{8, paged0, vram},
		{8, pagee0, vram},

		{9, page00, vram},
		{9, page10, vram},
		{9, page80, vram},
		{9, pagea0, vram},
		{9, pagec0, vram},
		{9, paged0, vchar},
		{9, pagee0, vram},

		{10, page00, vram},
		{10, page10, vram},
		{10, page80, vram},
		{10, pagea0, vram},
		{10, pagec0, vram},
		{10, paged0, vchar},
		{10, pagee0, vkernal},

		{11, page00, vram},
		{11, page10, vram},
		{11, page80, vcartlo},
		{11, pagea0, vbasic},
		{11, pagec0, vram},
		{11, paged0, vchar},
		{11, pagee0, vkernal},

		{12, page00, vram},
		{12, page10, vram},
		{12, page80, vram},
		{12, pagea0, vram},
		{12, pagec0, vram},
		{12, paged0, vram},
		{12, pagee0, vram},

		{13, page00, vram},
		{13, page10, vram},
		{13, page80, vram},
		{13, pagea0, vram},
		{13, pagec0, vram},
		{13, paged0, vio},
		{13, pagee0, vram},

		{14, page00, vram},
		{14, page10, vram},
		{14, page80, vram},
		{14, pagea0, vram},
		{14, pagec0, vram},
		{14, paged0, vio},
		{14, pagee0, vkernal},

		{15, page00, vram},
		{15, page10, vram},
		{15, page80, vcartlo},
		{15, pagea0, vbasic},
		{15, pagec0, vram},
		{15, paged0, vio},
		{15, pagee0, vkernal},

		{16, page00, vram},
		{16, page10, 0},
		{16, page80, vcartlo},
		{16, pagea0, 0},
		{16, pagec0, 0},
		{16, paged0, vio},
		{16, pagee0, vcarthi},

		{17, page00, vram},
		{17, page10, 0},
		{17, page80, vcartlo},
		{17, pagea0, 0},
		{17, pagec0, 0},
		{17, paged0, vio},
		{17, pagee0, vcarthi},

		{18, page00, vram},
		{18, page10, 0},
		{18, page80, vcartlo},
		{18, pagea0, 0},
		{18, pagec0, 0},
		{18, paged0, vio},
		{18, pagee0, vcarthi},

		{19, page00, vram},
		{19, page10, 0},
		{19, page80, vcartlo},
		{19, pagea0, 0},
		{19, pagec0, 0},
		{19, paged0, vio},
		{19, pagee0, vcarthi},

		{20, page00, vram},
		{20, page10, 0},
		{20, page80, vcartlo},
		{20, pagea0, 0},
		{20, pagec0, 0},
		{20, paged0, vio},
		{20, pagee0, vcarthi},

		{21, page00, vram},
		{21, page10, 0},
		{21, page80, vcartlo},
		{21, pagea0, 0},
		{21, pagec0, 0},
		{21, paged0, vio},
		{21, pagee0, vcarthi},

		{22, page00, vram},
		{22, page10, 0},
		{22, page80, vcartlo},
		{22, pagea0, 0},
		{22, pagec0, 0},
		{22, paged0, vio},
		{22, pagee0, vcarthi},

		{23, page00, vram},
		{23, page10, 0},
		{23, page80, vcartlo},
		{23, pagea0, 0},
		{23, pagec0, 0},
		{23, paged0, vio},
		{23, pagee0, vcarthi},

		{24, page00, vram},
		{24, page10, vram},
		{24, page80, vram},
		{24, pagea0, vram},
		{24, pagec0, vram},
		{24, paged0, vram},
		{24, pagee0, vram},

		{25, page00, vram},
		{25, page10, vram},
		{25, page80, vram},
		{25, pagea0, vram},
		{25, pagec0, vram},
		{25, paged0, vchar},
		{25, pagee0, vram},

		{26, page00, vram},
		{26, page10, vram},
		{26, page80, vram},
		{26, pagea0, vram},
		{26, pagec0, vram},
		{26, paged0, vchar},
		{26, pagee0, vkernal},

		{27, page00, vram},
		{27, page10, vram},
		{27, page80, vram},
		{27, pagea0, vbasic},
		{27, pagec0, vram},
		{27, paged0, vchar},
		{27, pagee0, vkernal},

		{28, page00, vram},
		{28, page10, vram},
		{28, page80, vram},
		{28, pagea0, vram},
		{28, pagec0, vram},
		{28, paged0, vram},
		{28, pagee0, vram},

		{29, page00, vram},
		{29, page10, vram},
		{29, page80, vram},
		{29, pagea0, vram},
		{29, pagec0, vram},
		{29, paged0, vio},
		{29, pagee0, vram},

		{30, page00, vram},
		{30, page10, vram},
		{30, page80, vram},
		{30, pagea0, vram},
		{30, pagec0, vram},
		{30, paged0, vio},
		{30, pagee0, vkernal},

		{31, page00, vram},
		{31, page10, vram},
		{31, page80, vram},
		{31, pagea0, vbasic},
		{31, pagec0, vram},
		{31, paged0, vio},
		{31, pagee0, vkernal},
	}

	for _, test := range tests {
		label := fmt.Sprintf("mode %02d addr %04x", test.mode, test.addr)
		t.Run(label, func(t *testing.T) {
			mem.SetBank(test.mode)
			have := mem.Read(test.addr)
			if test.want != have {
				t.Errorf("\n want: %02x \n have: %02x", test.want, have)
			}
		})
	}
}


<|start_filename|>system/pacman/audio.go<|end_filename|>
package pacman

import (
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/veandco/go-sdl2/sdl"
)

type audioData struct {
	waveforms []uint8
}

type voice struct {
	acc      []uint8
	waveform uint8
	freq     []uint8
	vol      uint8
}

type audio struct {
	voices    []voice
	waveforms [16][]float64
	synth     *rcs.Synth
}

func newAudio(spec sdl.AudioSpec, data audioData) (*audio, error) {
	synth, err := rcs.NewSynth(spec, 3)
	if err != nil {
		return nil, err
	}
	a := &audio{
		voices: make([]voice, 3, 3),
		synth:  synth,
	}
	a.voices[0].acc = make([]uint8, 5, 5)
	a.voices[0].freq = make([]uint8, 5, 5)
	a.voices[1].acc = make([]uint8, 4, 4)
	a.voices[1].freq = make([]uint8, 4, 4)
	a.voices[2].acc = make([]uint8, 4, 4)
	a.voices[2].freq = make([]uint8, 4, 4)

	for i := 0; i < 16; i++ {
		addr := uint16(i * 32)
		a.waveforms[i] = rescale(data.waveforms, addr)
	}

	return a, nil
}

func (a *audio) queue() error {
	for i := 0; i < 3; i++ {
		v := a.voices[i]
		wf := rcs.SliceBits(v.waveform, 0, 2)

		// Voice 0 has 5 bytes but Voice 1 and 2 only have 4 bytes with
		// the missing lower byte being zero.
		nFreq := 4
		if i == 0 {
			nFreq = 5
		}
		a.synth.V[i].Freq = freq(v.freq, nFreq)
		a.synth.V[i].Vol = float64(v.vol&0xf) / 15
		a.synth.V[i].Waveform = a.waveforms[wf]
	}
	return a.synth.Queue()
}

func rescale(d []uint8, addr uint16) []float64 {
	out := make([]float64, 32, 32)
	for i := uint16(0); i < 32; i++ {
		v := d[addr+i]
		out[i] = (float64(v) - 7.5) / 8
	}
	return out
}

func freq(f []uint8, n int) int {
	val := uint32(0)
	shift := uint(0)
	if n == 4 {
		shift = 4
	}
	for i := 0; i < n; i++ {
		val += uint32(f[i]&0x0f) << shift
		shift += 4
	}
	freq := (375.0 / 4096.0) * float32(val)
	return int(freq)
}


<|start_filename|>mock/mock_test.go<|end_filename|>
package mock

import (
	"log"
	"os"
	"strings"
	"testing"
)

func TestPanicWriter(t *testing.T) {
	log.SetOutput(&PanicWriter{})
	defer func() {
		log.SetOutput(os.Stderr)
		if r := recover(); r != nil {
			msg := r.(string)
			if !strings.HasSuffix(msg, "This is a panic\n") {
				t.Errorf("panic message is: %v", msg)
			}
		}
	}()
	log.Printf("This is a panic")
	t.Fail()
}


<|start_filename|>rcs/m6502/addressing.go<|end_filename|>
package m6502

func (c *CPU) loadAbsolute() uint8 {
	c.addrLoad = c.fetch2()
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) loadAbsoluteX() uint8 {
	arg := c.fetch2()
	c.addrLoad = arg + int(c.X)
	if c.addrLoad&0xff00 != arg&0xff00 {
		c.pageCross = true
	}
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) loadAbsoluteY() uint8 {
	arg := c.fetch2()
	c.addrLoad = arg + int(c.Y)
	if c.addrLoad&0xff00 != arg&0xff00 {
		c.pageCross = true
	}
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) loadA() uint8 {
	return c.A
}

func (c *CPU) loadX() uint8 {
	return c.X
}

func (c *CPU) loadY() uint8 {
	return c.Y
}

func (c *CPU) loadSP() uint8 {
	return c.SP
}

func (c *CPU) loadSR() uint8 {
	return c.SR | (1 << 5)
}

func (c *CPU) loadImmediate() uint8 {
	return c.fetch()
}

func (c *CPU) loadIndirectX() uint8 {
	zpaddr := int(c.fetch() + c.X)
	c.addrLoad = c.mem.ReadLE(zpaddr)
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) loadIndirectY() uint8 {
	c.addrLoad = c.mem.ReadLE(int(c.fetch()))
	indexed := c.addrLoad + int(c.Y)
	if c.addrLoad&0xff00 != indexed&0xff00 {
		c.pageCross = true
	}
	return c.mem.Read(indexed)
}

func (c *CPU) loadZeroPage() uint8 {
	c.addrLoad = int(c.fetch())
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) loadZeroPageX() uint8 {
	c.addrLoad = int(c.fetch() + c.X)
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) loadZeroPageY() uint8 {
	c.addrLoad = int(c.fetch() + c.Y)
	return c.mem.Read(c.addrLoad)
}

func (c *CPU) storeAbsolute(value uint8) {
	c.mem.Write(c.fetch2(), value)
}

func (c *CPU) storeAbsoluteX(value uint8) {
	c.mem.Write(c.fetch2()+int(c.X), value)
}

func (c *CPU) storeAbsoluteY(v uint8) {
	c.mem.Write(c.fetch2()+int(c.Y), v)
}

func (c *CPU) storeIndirectX(v uint8) {
	zpaddr := int(c.fetch() + c.X)
	c.mem.Write(c.mem.ReadLE(zpaddr), v)
}

func (c *CPU) storeIndirectY(v uint8) {
	addr := c.mem.ReadLE(int(c.fetch())) + int(c.Y)
	c.mem.Write(addr, v)
}

func (c *CPU) storeZeroPage(v uint8) {
	c.mem.Write(int(c.fetch()), v)
}

func (c *CPU) storeZeroPageX(v uint8) {
	c.mem.Write(int(c.fetch()+c.X), v)
}

func (c *CPU) storeZeroPageY(v uint8) {
	c.mem.Write(int(c.fetch()+c.Y), v)
}

func (c *CPU) storeA(v uint8) {
	c.A = v
}

func (c *CPU) storeX(v uint8) {
	c.X = v
}

func (c *CPU) storeY(v uint8) {
	c.Y = v
}

func (c *CPU) storeSP(v uint8) {
	c.SP = v
}

func (c *CPU) storeSR(v uint8) {
	c.SR = v
}

func (c *CPU) storeBack(v uint8) {
	c.mem.Write(c.addrLoad, v)
}


<|start_filename|>tools/icmp/Makefile<|end_filename|>
Z80EMU_HOME=$(HOME)/z80emu

all: z80emu/icmp-z80emu
	z80emu/icmp-z80emu > z80emu.txt
	go run icmp-rcs/icmp-rcs.go > rcs.txt
	diff z80emu.txt rcs.txt

z80emu/icmp-z80emu: z80emu/icmp-z80emu.c
	gcc -o z80emu/icmp-z80emu \
		-I$(Z80EMU_HOME) \
		$(Z80EMU_HOME)/z80emu.c \
		z80emu/icmp-z80emu.c

clean:
	rm *.txt
	rm z80emu/icmp-z80emu



<|start_filename|>rcs/rcs_test.go<|end_filename|>
package rcs

import (
	"fmt"
	"testing"
)

func TestFormats(t *testing.T) {
	tests := []struct {
		in  int
		out string
		fn  func(int) string
	}{
		{15, "$f", func(v int) string { return X(v) }},
		{15, "$0f", func(v int) string { return X8(uint8(v)) }},
		{15, "$000f", func(v int) string { return X16(uint16(v)) }},
		{15, "%1111", func(v int) string { return B(v) }},
		{15, "%0000.1111", func(v int) string { return B8(uint8(v)) }},
		{15, "%0000.0000:0000.1111", func(v int) string { return B16(uint16(v)) }},
	}
	for i, test := range tests {
		name := fmt.Sprintf("%v", i)
		t.Run(name, func(t *testing.T) {
			have := test.fn(test.in)
			want := test.out
			if have != want {
				t.Errorf("\n have: %v \n want: %v\n", have, want)
			}
		})
	}
}

func ExampleFromBCD() {
	v := FromBCD(0x42)
	fmt.Println(v)
	// Output: 42
}

func ExampleToBCD() {
	v := ToBCD(42)
	fmt.Printf("%02x", v)
	// Output: 42
}

func TestToBCDOverflow(t *testing.T) {
	want := uint8(0x12)
	have := ToBCD(112)
	if want != have {
		t.Errorf("\n want: %02x \n have: %02x\n", want, have)
	}
}

func TestSliceBits(t *testing.T) {
	b := ParseBits
	tests := []struct {
		lo   int
		hi   int
		in   uint8
		out  uint8
		name string
	}{
		{6, 7, b("11000000"), b("011"), "high one"},
		{6, 7, b("00111111"), b("000"), "high zero"},
		{3, 5, b("00111000"), b("111"), "middle one"},
		{3, 5, b("11000111"), b("000"), "middle zero"},
		{0, 2, b("00000111"), b("111"), "low one"},
		{0, 2, b("11111000"), b("000"), "low zero"},
	}

	for _, test := range tests {
		t.Run(test.name, func(t *testing.T) {
			slice := SliceBits(test.in, test.lo, test.hi)
			if slice != test.out {
				t.Errorf("\n have: %08b \n want: %08b", slice, test.out)
			}
		})
	}
}

func ExampleSliceBits() {
	value := ParseBits("00111000")
	fmt.Printf("%03b", SliceBits(value, 3, 5))
	// Output: 111
}

func TestBitPlane(t *testing.T) {
	b := ParseBits
	tests := []struct {
		offset int
		in     uint8
		out    uint8
	}{
		{0, b("00010001"), b("11")},
		{1, b("00100010"), b("11")},
		{2, b("01000100"), b("11")},
		{3, b("10001000"), b("11")},
	}
	for _, test := range tests {
		out := BitPlane4(test.in, test.offset)
		if out != test.out {
			t.Errorf("\n have: %08b \n want: %08b", out, test.out)
		}
	}
}


<|start_filename|>rcs/cbm/vic.go<|end_filename|>
package cbm

import (
	"image/color"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/veandco/go-sdl2/sdl"
)

const (
	width      = 320
	height     = 200
	screenW    = 404 // actually 403?
	screenH    = 284
	borderW    = (screenW - width) / 2
	borderH    = (screenH - height) / 2
	charSheetW = 32
	charSheetH = 16
)

type VIC struct {
	W       int32
	H       int32
	Texture *sdl.Texture

	BorderColor uint8
	BgColor     uint8

	charSheet rcs.TileSheet
	mem       *rcs.Memory
}

func NewVIC(r *sdl.Renderer, mem *rcs.Memory, charData []uint8) (*VIC, error) {
	v := &VIC{W: screenW, H: screenH, mem: mem}
	if r == nil {
		return v, nil
	}
	t, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888, sdl.TEXTUREACCESS_TARGET,
		screenW, screenH)
	if err != nil {
		return nil, err
	}
	v.Texture = t
	charSheet, err := CharGen(r, charData)
	if err != nil {
		return nil, err
	}
	v.charSheet = charSheet
	return v, nil
}

func (v *VIC) Draw(r *sdl.Renderer) error {
	v.mem.Write(0xd012, 00) // HACK: set raster line to zero
	r.SetRenderTarget(v.Texture)
	r.SetDrawBlendMode(sdl.BLENDMODE_BLEND)
	v.drawBorder(r)
	v.drawBackground(r)
	v.drawCharacters(r)
	r.SetRenderTarget(nil)
	return nil
}

func (v *VIC) drawBorder(r *sdl.Renderer) {
	c := Palette[v.BorderColor&0x0f]
	r.SetDrawColor(c.R, c.G, c.B, c.A)
	topBorder := sdl.Rect{
		X: 0,
		Y: 0,
		W: screenW,
		H: borderH,
	}
	r.FillRect(&topBorder)
	bottomBorder := sdl.Rect{
		X: 0,
		Y: borderH + height,
		W: screenW,
		H: borderH,
	}
	r.FillRect(&bottomBorder)
	leftBorder := sdl.Rect{
		X: 0,
		Y: borderH,
		W: borderW,
		H: height,
	}
	r.FillRect(&leftBorder)
	rightBorder := sdl.Rect{
		X: borderW + width,
		Y: borderH,
		W: borderW,
		H: height,
	}
	r.FillRect(&rightBorder)
}

func (v *VIC) drawBackground(r *sdl.Renderer) {
	c := Palette[v.BgColor&0x0f]
	r.SetDrawColor(c.R, c.G, c.B, c.A)
	background := sdl.Rect{
		X: borderW,
		Y: borderH,
		W: width,
		H: height,
	}
	r.FillRect(&background)
}

func (v *VIC) drawCharacters(r *sdl.Renderer) {
	addrScreenMem := 0x0400
	addrColorMem := 0xd800
	baseX := 0
	baseY := 0
	for baseY < height {
		ch := v.mem.Read(addrScreenMem)
		clr := Palette[v.mem.Read(addrColorMem)&0x0f]
		v.charSheet.Texture.SetColorMod(clr.R, clr.G, clr.B)
		chx := int32(ch) % charSheetW * 8
		chy := int32(ch) / charSheetW * 8
		src := sdl.Rect{X: chx, Y: chy, W: 8, H: 8}
		dest := sdl.Rect{
			X: int32(baseX + borderW),
			Y: int32(baseY + borderH),
			W: 8,
			H: 8,
		}
		r.Copy(v.charSheet.Texture, &src, &dest)
		addrScreenMem++
		addrColorMem++
		baseX += 8
		if baseX >= width {
			baseX = 0
			baseY += 8
		}
	}
}

var (
	Palette = []color.RGBA{
		color.RGBA{0x00, 0x00, 0x00, 0xff}, // black
		color.RGBA{0xff, 0xff, 0xff, 0xff}, // white
		color.RGBA{0x88, 0x00, 0x00, 0xff}, // red
		color.RGBA{0xaa, 0xff, 0xee, 0xff}, // cyan
		color.RGBA{0xcc, 0x44, 0xcc, 0xff}, // purple
		color.RGBA{0x00, 0xcc, 0x55, 0xff}, // green
		color.RGBA{0x00, 0x00, 0xaa, 0xff}, // blue
		color.RGBA{0xee, 0xee, 0x77, 0xff}, // yellow
		color.RGBA{0xdd, 0x88, 0x55, 0xff}, // orange
		color.RGBA{0x66, 0x44, 0x00, 0xff}, // brown
		color.RGBA{0xff, 0x77, 0x77, 0xff}, // light red
		color.RGBA{0x33, 0x33, 0x33, 0xff}, // dark gray
		color.RGBA{0x77, 0x77, 0x77, 0xff}, // gray
		color.RGBA{0xaa, 0xff, 0x66, 0xff}, // light green
		color.RGBA{0x00, 0x88, 0xff, 0xff}, // light blue
		color.RGBA{0xbb, 0xbb, 0xbb, 0xff}, // light gray
	}
)

func CharGen(r *sdl.Renderer, data []uint8) (rcs.TileSheet, error) {
	tileW, tileH := int32(8), int32(8)
	texW := tileW * 32
	texH := tileH * 16
	t, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888,
		sdl.TEXTUREACCESS_TARGET, texW, texH)
	if err != nil {
		return rcs.TileSheet{}, err
	}
	r.SetRenderTarget(t)
	r.SetDrawColor(0, 0, 0, 0)
	r.FillRect(nil)
	r.SetDrawColor(0xff, 0xff, 0xff, 0xff)
	baseX := int32(0)
	baseY := int32(0)
	addr := 0
	for baseY < texH {
		for y := baseY; y < baseY+8; y++ {
			line := data[addr]
			addr++
			for x := baseX; x < baseX+8; x++ {
				bit := line & 0x80
				line = line << 1
				if bit != 0 {
					r.DrawPoint(x, y)
				}
			}
		}
		baseX += 8
		if baseX >= texW {
			baseX = 0
			baseY += 8
		}
	}
	t.SetBlendMode(sdl.BLENDMODE_BLEND)
	r.SetRenderTarget(nil)
	return rcs.TileSheet{
		TextureW: texW,
		TextureH: texH,
		TileW:    tileW,
		TileH:    tileH,
		Texture:  t,
	}, nil
}


<|start_filename|>rcs/m6502/cpu_test.go<|end_filename|>
package m6502

import (
	"testing"

	"github.com/blackchip-org/retro-cs/mock"
)

func newTestCPU() *CPU {
	mock.ResetMemory()
	cpu := New(mock.TestMemory)
	cpu.SP = 0xff
	cpu.SetPC(0x1ff)
	return cpu
}

func testRunCPU(t *testing.T, cpu *CPU) error {
	cycles := 0
	run := true
	cpu.BreakFunc = func() {
		run = false
	}
	for run {
		cycles++
		if cycles > 100 {
			t.Fatalf("max cycles exceeded")
		}
		cpu.Next()
	}
	return nil
}

func TestCPUString(t *testing.T) {

	var tests = []struct {
		setup func(*CPU)
		want  string
	}{
		{func(cpu *CPU) { cpu.SetPC(0x1234) },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"1234 20 00 00 00 ff  . . * . . . . ."},
		{func(cpu *CPU) { cpu.A = 0x56 },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 20 56 00 00 ff  . . * . . . . ."},
		{func(cpu *CPU) { cpu.X = 0x78 },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 20 00 78 00 ff  . . * . . . . ."},
		{func(cpu *CPU) { cpu.Y = 0x9a },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 20 00 00 9a ff  . . * . . . . ."},
		{func(cpu *CPU) { cpu.SP = 0xbc },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 20 00 00 00 bc  . . * . . . . ."},
		{func(cpu *CPU) { cpu.SR = FlagC },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 21 00 00 00 ff  . . * . . . . *"},
		{func(cpu *CPU) { cpu.SR = FlagZ },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 22 00 00 00 ff  . . * . . . * ."},
		{func(cpu *CPU) { cpu.SR = FlagI },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 24 00 00 00 ff  . . * . . * . ."},
		{func(cpu *CPU) { cpu.SR = FlagD },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 28 00 00 00 ff  . . * . * . . ."},
		{func(cpu *CPU) { cpu.SR = FlagB },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 30 00 00 00 ff  . . * . . . . ."},
		{func(cpu *CPU) { cpu.SR = FlagV },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff 60 00 00 00 ff  . * * . . . . ."},
		{func(cpu *CPU) { cpu.SR = FlagN },
			"" +
				" pc  sr ac xr yr sp  n v - - d i z c\n" +
				"01ff a0 00 00 00 ff  * . * . . . . ."},
	}

	for _, test := range tests {
		cpu := newTestCPU()
		test.setup(cpu)
		have := cpu.String()
		if test.want != have {
			t.Errorf("\n want: \n%v \n have: \n%v\n", test.want, have)
		}
	}
}


<|start_filename|>app/monitor/galaga.go<|end_filename|>
package monitor

import (
	"fmt"
	"log"

	"github.com/chzyer/readline"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/system/galaga"
)

type modGalaga struct {
	mon    *Monitor
	out    *log.Logger
	galaga *galaga.System
}

func newModGalaga(mon *Monitor, comp rcs.Component) module {
	return &modGalaga{
		mon:    mon,
		out:    mon.out,
		galaga: comp.C.(*galaga.System),
	}
}

func (m *modGalaga) Command(args []string) error {
	if err := checkLen(args, 1, maxArgs); err != nil {
		return err
	}
	switch args[0] {
	case "interrupt-enable1":
		return valueBit(m.out, &m.galaga.InterruptEnable0, (1 << 0), args[1:])
	case "interrupt-enable2":
		return valueBit(m.out, &m.galaga.InterruptEnable1, (1 << 0), args[1:])
	case "interrupt-enable3":
		return valueBit(m.out, &m.galaga.InterruptEnable2, (1 << 0), args[1:])
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modGalaga) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("interrupt-enable1"),
		readline.PcItem("interrupt-enable2"),
		readline.PcItem("interrupt-enable3"),
	}
}

func (m *modGalaga) Silence() error {
	return nil
}


<|start_filename|>app/monitor/monitor_test.go<|end_filename|>
package monitor

import (
	"bytes"
	"log"
	"strings"
	"testing"

	"github.com/blackchip-org/retro-cs/mock"
	"github.com/blackchip-org/retro-cs/rcs"
)

type monitorFixture struct {
	cpu *mock.CPU
	out bytes.Buffer
	mon *Monitor
}

func newMonitorFixture() *monitorFixture {
	mach := mock.NewMach()
	mach.Init()
	cpu := mach.CPU["cpu"].(*mock.CPU)
	mon, err := New(mach)
	if err != nil {
		panic(err)
	}
	f := &monitorFixture{
		mon: mon,
		cpu: cpu,
	}
	f.mon.out = log.New(&f.out, "", 0)
	return f
}

func TestMonitor(t *testing.T) {
	for _, test := range monitorTests {
		t.Run(test.name, func(t *testing.T) {
			f := newMonitorFixture()
			go f.mon.mach.Run()
			defer func() {
				f.mon.mach.Command(rcs.MachQuit)
			}()
			f.mon.Eval(strings.Join(test.in, "\n"))
			have := strings.TrimSpace(f.out.String())
			want := strings.TrimSpace(test.want)
			if have != want {
				t.Errorf("\n have: \n%v \n want: \n%v", have, want)
			}
		})
	}
}

var monitorTests = []struct {
	name string
	in   []string
	want string
}{
	{
		"conversions",
		[]string{"42", "$2a", "%101010"},
		`
+ 42
42 $2a %10.1010
+ $2a
42 $2a %10.1010
+ %101010
42 $2a %10.1010
		`,
	}, {
		"break",
		[]string{
			"bp $3456 on",
			"bp $2345 on",
			"bp $1234 on",
			"bp",
			"bp $2345 off",
			"bp",
			"bp none",
			"bp",
			"bp $123456 on",
		},
		`
+ bp $3456 on
+ bp $2345 on
+ bp $1234 on
+ bp
$1234
$2345
$3456
+ bp $2345 off
+ bp
$1234
$3456
+ bp none
+ bp
+ bp $123456 on
invalid address: $123456
		`,
	}, {
		"dasm",
		[]string{
			"config lines-disassembly 4",
			"poke $10 $09",
			"poke $11 $19 $ab",
			"poke $13 $29 $cd $ab",
			"poke $16 $27 $cd $ab",
			"d $10",
		},
		`
+ config lines-disassembly 4
+ poke $10 $09
+ poke $11 $19 $ab
+ poke $13 $29 $cd $ab
+ poke $16 $27 $cd $ab
+ d $10
$0010:  09        i09
$0011:  19 ab     i19 $ab
$0013:  29 cd ab  i29 $abcd
$0016:  27 cd ab  i27 $abcd
`,
	}, {
		"dasm continue",
		[]string{
			"config lines-disassembly 1",
			"poke $0 $09",
			"poke $1 $19 $ab",
			"poke $3 $29 $cd $ab",
			"poke $6 $27 $cd $ab",
			"d",
			"d",
		},
		`
+ config lines-disassembly 1
+ poke $0 $09
+ poke $1 $19 $ab
+ poke $3 $29 $cd $ab
+ poke $6 $27 $cd $ab
+ d
$0000:  09        i09
+ d
$0001:  19 ab     i19 $ab
		`,
	}, {
		"dasm range",
		[]string{
			"config lines-disassembly 4",
			"poke $10 $09",
			"poke $11 $19 $ab",
			"poke $13 $29 $cd $ab",
			"poke $16 $27 $cd $ab",
			"d $11 $14",
		},
		`
+ config lines-disassembly 4
+ poke $10 $09
+ poke $11 $19 $ab
+ poke $13 $29 $cd $ab
+ poke $16 $27 $cd $ab
+ d $11 $14
$0011:  19 ab     i19 $ab
$0013:  29 cd ab  i29 $abcd
		`,
	}, {
		"go",
		[]string{"bp $10 on", "g", "sleep 100"},
		`
+ bp $10 on
+ g
+ sleep 100

[break]
pc:0010 a:00 b:00 q:false z:false
		`,
	}, {
		"memory",
		[]string{"config lines-memory 2", "m"},
		`
+ config lines-memory 2
+ m
$0000  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
	`,
	}, {
		"memory page 1",
		[]string{"config lines-memory 2", "m $100"},
		`
+ config lines-memory 2
+ m $100
$0100  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0110  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
	`,
	}, {
		"memory next page",
		[]string{"config lines-memory 2", "m $100", "m"},
		`
+ config lines-memory 2
+ m $100
$0100  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0110  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
+ m
$0120  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0130  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
`,
	}, {
		"memory range",
		[]string{"m $140 $15f"},
		`
+ m $140 $15f
$0140  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0150  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
`,
	}, {
		"memory lines",
		[]string{"config lines-memory 3", "config lines-memory", "m"},
		`
+ config lines-memory 3
+ config lines-memory
3 $3 %11
+ m
$0000  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
$0020  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
`,
	}, {
		"memory encoding",
		[]string{
			"encoding",
			"poke $0 1 2 3 $41 $42 $43",
			"m 00 $0f",
			"encoding az26",
			"m 00 $0f",
			"encoding ebcdic",
		},
		`
+ encoding
ascii
+ poke $0 1 2 3 $41 $42 $43
+ m 00 $0f
$0000  01 02 03 41 42 43 00 00  00 00 00 00 00 00 00 00  ...ABC..........
+ encoding az26
+ m 00 $0f
$0000  01 02 03 41 42 43 00 00  00 00 00 00 00 00 00 00  ABC.............
+ encoding ebcdic
invalid value: ebcdic
		`,
	}, {
		"memory fill",
		[]string{
			"config lines-memory 1",
			"mem fill 0004 $000b $ff",
			"m 0",
			"mem fill $000b 0004 $aa",
			"m 0",
		},
		`
+ config lines-memory 1
+ mem fill 0004 $000b $ff
+ m 0
$0000  00 00 00 00 ff ff ff ff  ff ff ff ff 00 00 00 00  ................
+ mem fill $000b 0004 $aa
+ m 0
$0000  00 00 00 00 ff ff ff ff  ff ff ff ff 00 00 00 00  ................
		`,
	}, {
		"next",
		[]string{"n"},
		`
+ n
$0000:  00        i00
		`,
	}, {
		"peek",
		[]string{"poke $1234 $ab", "peek $1234"},
		`
+ poke $1234 $ab
+ peek $1234
171 $ab %1010.1011
		`,
	}, {
		"step",
		[]string{"s", "i", "s", "s", "i"},
		`
+ s
$0001:  00        i00
+ i
[pause]
pc:0001 a:00 b:00 q:false z:false
+ s
$0002:  00        i00
+ s
$0003:  00        i00
+ i
[pause]
pc:0003 a:00 b:00 q:false z:false
		`,
	}, {
		"trace",
		[]string{
			"poke 0 $a $b $c",
			"trace",
			"bp 1 on",
			"bp 2 on",
			"go",
			"sleep 100",
			"trace",
			"go",
		},
		`
+ poke 0 $a $b $c
+ trace
+ bp 1 on
+ bp 2 on
+ go
+ sleep 100
$0000:  0a        i0a

[break]
pc:0001 a:00 b:00 q:false z:false

+ trace
+ go
		`,
	}, {
		"watch",
		[]string{
			"w $10 rw",
			"w",
			"poke $10 $22",
			"peek $10",
			"w $10 off",
			"w $10 r",
			"w",
			"poke $10 $22",
			"peek $10",
			"w $10 off",
			"w $10 w",
			"w",
			"poke $10 $22",
			"peek $10",
			"w none",
			"w",
		},
		`
+ w $10 rw
+ w
$0010 rw
+ poke $10 $22
mem[$0010] <= $22
+ peek $10
$22 <= mem[$0010]
34 $22 %10.0010
+ w $10 off
+ w $10 r
+ w
$0010 r
+ poke $10 $22
+ peek $10
$22 <= mem[$0010]
34 $22 %10.0010
+ w $10 off
+ w $10 w
+ w
$0010 w
+ poke $10 $22
mem[$0010] <= $22
+ peek $10
34 $22 %10.0010
+ w none
+ w
		`,
	},
}

func TestBreakpointOffset(t *testing.T) {
	t.Skip("FIXME")
	f := newMonitorFixture()
	f.cpu.OffsetPC = 1
	cmds := `
bp $10 on
g
sleep 1000
	`
	go f.mon.mach.Run()
	defer func() {
		f.mon.mach.Command(rcs.MachQuit)
	}()
	f.mon.Eval(cmds)
	f.mon.Close()
	have := strings.TrimSpace(f.out.String())
	want := strings.TrimSpace(`
+ bp $10 on
+ g
+ sleep 100

[break]
pc:000f a:00 b:00 q:false z:false
`)
	if have != want {
		t.Errorf("\n have: \n%v \n want: \n%v", have, want)
	}
}

func TestDump(t *testing.T) {
	var dumpTests = []struct {
		name     string
		start    int
		data     func() []int
		showFrom int
		showTo   int
		want     string
	}{
		{
			"one line", 0x10,
			func() []int { return []int{} },
			0x10, 0x20, "" +
				"$0010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................",
		}, {
			"two lines", 0x10,
			func() []int { return []int{} },
			0x10, 0x30, "" +
				"$0010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................\n" +
				"$0020  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................",
		}, {
			"jagged top", 0x10,
			func() []int { return []int{} },
			0x14, 0x30, "" +
				"$0010              00 00 00 00  00 00 00 00 00 00 00 00      ............\n" +
				"$0020  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................",
		}, {
			"jagged bottom", 0x10,
			func() []int { return []int{} },
			0x10, 0x2b, "" +
				"$0010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................\n" +
				"$0020  00 00 00 00 00 00 00 00  00 00 00 00              ............",
		},
		{
			"single value", 0x10,
			func() []int { return []int{0, 0x41} },
			0x11, 0x11, "" +
				"$0010     41                                              A",
		},
		{
			"$40-$5f", 0x10,
			func() []int {
				data := make([]int, 0)
				for i := 0x40; i < 0x60; i++ {
					data = append(data, i)
				}
				return data
			},
			0x10, 0x30, "" +
				"$0010  40 41 42 43 44 45 46 47  48 49 4a 4b 4c 4d 4e 4f  @ABCDEFGHIJKLMNO\n" +
				"$0020  50 51 52 53 54 55 56 57  58 59 5a 5b 5c 5d 5e 5f  PQRSTUVWXYZ[\\]^_",
		},
	}

	mock.ResetMemory()
	m := mock.TestMemory
	for _, test := range dumpTests {
		t.Run(test.name, func(t *testing.T) {
			for i, value := range test.data() {
				m.Write(test.start+i, uint8(value))
			}
			have := dump(m, test.showFrom, test.showTo, rcs.ASCIIDecoder, "")
			have = strings.TrimSpace(have)
			if have != test.want {
				t.Errorf("\n have: \n%v \n want: \n%v \n", have, test.want)
			}
		})
	}
}

func TestRepeatWriter(t *testing.T) {
	tests := []struct {
		in  []string
		out []string
	}{
		{
			[]string{"a", "b", "c"},
			[]string{"a", "b", "c"},
		},
		{
			[]string{"a", "b", "b", "c"},
			[]string{"a", "b", "... repeats 1 time", "c"},
		},
		{
			[]string{"a", "b", "b", "b", "b", "b", "c"},
			[]string{"a", "b", "... repeats 4 times", "c"},
		},
		{
			[]string{"a", "b", "b", "b", "b", "b", "c", "c", "d"},
			[]string{"a", "b", "... repeats 4 times", "c", "... repeats 1 time", "d"},
		},
	}

	for _, test := range tests {
		var buf bytes.Buffer
		rw := newRepeatWriter(&buf)
		rw.ansi = false
		str := strings.Join(test.in, "\n")
		rw.Write([]byte(str))
		rw.Close()
		have := buf.String()
		want := strings.Join(test.out, "\n") + "\n"
		if have != want {
			t.Errorf("\n have: \n[%v] \n want: \n[%v]", have, want)
		}
	}
}

func TestFormatBits(t *testing.T) {
	tests := []struct {
		in  int
		out string
	}{
		{0x0f, "1111"},
		{0x1f, "1.1111"},
		{0xff, "1111.1111"},
		{0x1ff, "1:1111.1111"},
	}

	for _, test := range tests {
		have := formatBits(test.in)
		if have != test.out {
			t.Errorf("\n have: %v \n want: %v", have, test.out)
		}
	}
}


<|start_filename|>mock/cpu.go<|end_filename|>
package mock

import (
	"fmt"

	"github.com/blackchip-org/retro-cs/rcs"
)

type CPU struct {
	mem *rcs.Memory
	pc  uint16
	A   uint8 // sample register
	B   uint8 // sample register
	Q   bool  // sample flag
	Z   bool  // sample flag

	// Offset to be added to the program counter to get the address of the
	// next instruction.
	OffsetPC int
}

func NewCPU(mem *rcs.Memory) *CPU {
	return &CPU{mem: mem}
}

func (c *CPU) PC() int {
	return int(c.pc)
}

func (c *CPU) SetPC(addr int) {
	c.pc = uint16(addr)
}

func (c *CPU) Offset() int {
	return c.OffsetPC
}

func (c *CPU) Memory() *rcs.Memory {
	return c.mem
}

// Next reads the next byte at the program counter as the "opcode". The high
// nibble is the number of "arguments" it will fetch (max two).
func (c *CPU) Next() {
	if c.OffsetPC == 1 {
		c.pc++
	}
	opcode := c.mem.Read(int(c.pc))
	if c.OffsetPC == 0 {
		c.pc++
	}
	narg := int(opcode) >> 4
	if narg > 2 {
		narg = 2
	}
	c.pc += uint16(narg)
	return
}

func (c *CPU) String() string {
	return fmt.Sprintf("pc:%04x a:%02x b:%02x q:%v z:%v", c.pc, c.A, c.B, c.Q, c.Z)
}

func reader(e rcs.StmtEval) {
	e.Stmt.Addr = e.Ptr.Addr()
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	argN := opcode >> 4
	switch argN {
	case 0:
		e.Stmt.Op = fmt.Sprintf("i%02x", opcode)
	case 1:
		value := e.Ptr.Fetch()
		e.Stmt.Bytes = append(e.Stmt.Bytes, value)
		e.Stmt.Op = fmt.Sprintf("i%02x $%02x", opcode, value)
	case 2:
		value := e.Ptr.FetchLE()
		e.Stmt.Bytes = append(e.Stmt.Bytes, uint8(value&0xff))
		e.Stmt.Bytes = append(e.Stmt.Bytes, uint8(value>>8))
		e.Stmt.Op = fmt.Sprintf("i%02x $%04x", opcode, value)
	default:
		e.Stmt.Op = fmt.Sprintf("?%02x", opcode)
	}
}

func formatter() rcs.CodeFormatter {
	options := rcs.FormatOptions{
		BytesFormat: "%-8s",
	}
	return func(s rcs.Stmt) string {
		return rcs.FormatStmt(s, options)
	}
}

func (c *CPU) NewDisassembler() *rcs.Disassembler {
	return rcs.NewDisassembler(c.mem, reader, formatter())
}


<|start_filename|>cmd/retro-cs/main.go<|end_filename|>
package main

import (
	"bufio"
	"flag"
	"io/ioutil"
	"log"
	"os"
	"path/filepath"
	"runtime"
	"runtime/pprof"
	"strings"

	"github.com/blackchip-org/retro-cs/app/monitor"
	"github.com/blackchip-org/retro-cs/mock"

	"github.com/veandco/go-sdl2/sdl"

	"github.com/blackchip-org/retro-cs/app"
	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
)

const (
	defaultWidth  = 1024
	defaultHeight = 786
)

var (
	optFullStart bool
	optProfC     bool
	optPanic     bool
	optSystem    string
	optMonitor   bool
	optImport    string
	optNoAudio   bool
	optNoVideo   bool
	optTrace     bool
	optWait      bool
)

func init() {
	flag.BoolVar(&optFullStart, "f", false, "full start -- do not bypass POST")
	flag.StringVar(&optImport, "i", "", "import state from `filename`")
	flag.BoolVar(&optProfC, "profc", false, "enable cpu profiling")
	flag.BoolVar(&optNoAudio, "no-audio", false, "disable audio")
	flag.BoolVar(&optNoVideo, "no-video", false, "disable video")
	flag.BoolVar(&optMonitor, "m", false, "enable monitor")
	flag.BoolVar(&optPanic, "panic", false, "install panic log writer")
	flag.StringVar(&optSystem, "s", "c64", "start this `system`")
	flag.BoolVar(&optTrace, "t", false, "enable tracing")
	flag.BoolVar(&optWait, "w", false, "wait for go command")
}

func main() {
	runtime.LockOSThread()
	log.SetFlags(0)
	flag.Parse()

	if optProfC {
		f, err := os.Create("./cpu.prof")
		if err != nil {
			log.Fatal("could not create CPU profile: ", err)
		}
		if err := pprof.StartCPUProfile(f); err != nil {
			log.Fatal("could not start CPU profile: ", err)
		}
		log.Println("starting profile")
		defer func() {
			pprof.StopCPUProfile()
			log.Println("profile saved")
		}()
	}
	if optNoVideo || optTrace || optWait {
		optMonitor = true
	}

	newMachine, ok := app.Systems[optSystem]
	if !ok {
		log.Fatalf("no such system: %v", optSystem)
	}
	config.System = optSystem
	config.UserDir = filepath.Join(config.UserHome, ".retro-cs")
	config.DataDir = filepath.Join(config.ResourceDir(), "data", optSystem)
	config.VarDir = filepath.Join(config.ResourceDir(), "var", optSystem)

	if err := os.MkdirAll(config.UserDir, 0755); err != nil {
		log.Fatalf("unable to create directory %v: %v", config.UserDir, err)
	}
	if err := os.MkdirAll(config.VarDir, 0755); err != nil {
		log.Fatalf("unable to create directory %v: %v", config.VarDir, err)
	}

	ctx := rcs.SDLContext{}
	if !optNoVideo {
		if err := sdl.Init(sdl.INIT_VIDEO); err != nil {
			log.Fatalf("unable to initialize video: %v", err)
		}
		fullScreen := uint32(0)
		if !optMonitor {
			fullScreen = sdl.WINDOW_FULLSCREEN_DESKTOP
		}
		window, err := sdl.CreateWindow(
			"retro-cs",
			sdl.WINDOWPOS_UNDEFINED, sdl.WINDOWPOS_UNDEFINED,
			defaultWidth, defaultHeight,
			sdl.WINDOW_SHOWN|fullScreen,
		)
		if err != nil {
			log.Fatalf("unable to initialize window: %v", err)
		}
		r, err := sdl.CreateRenderer(window, -1, sdl.RENDERER_ACCELERATED)
		if err != nil {
			log.Fatalf("unable to initialize renderer: %v", err)
		}
		info, err := r.GetInfo()
		if err != nil {
			log.Fatalf("unable to get renderer info: %v", err)
		}
		// FIXME: Change this to check for OpenGL
		if info.Name != "direct3d" {
			if _, err := window.GLCreateContext(); err != nil {
				log.Printf("unable to createl GL context: %v", err)
			}
			if err = sdl.GLSetSwapInterval(1); err != nil {
				log.Printf("unable to set swap interval: %v", err)
			}
		}
		ctx.Window = window
		ctx.Renderer = r
	}

	if !optNoAudio {
		requestSpec := sdl.AudioSpec{
			Freq:     22050,
			Format:   sdl.AUDIO_S16LSB,
			Channels: 2,
			Samples:  367,
		}
		if err := sdl.OpenAudio(&requestSpec, &ctx.AudioSpec); err != nil {
			log.Fatalf("unable to initialize audio: %v", err)
		}
		sdl.PauseAudio(false)
	}

	err := sdl.Init(sdl.INIT_JOYSTICK | sdl.INIT_GAMECONTROLLER)
	if err != nil {
		log.Fatalf("unable to initialize game controllers: %v", err)
	}
	mappingsDir := filepath.Join(config.ResourceDir(), "data", "game_controllers")
	mappings, err := ioutil.ReadDir(mappingsDir)
	if err != nil {
		log.Printf("(!) unable to load game controller mappings: %v", err)
	}
	for _, f := range mappings {
		if strings.HasSuffix(f.Name(), ".txt") {
			in, err := os.Open(filepath.Join(mappingsDir, f.Name()))
			if err != nil {
				log.Printf("(!) unable to open controller mapping: %v", err)
				continue
			}
			defer in.Close()
			s := bufio.NewScanner(in)
			for s.Scan() {
				line := strings.TrimSpace(s.Text())
				if line == "" {
					continue
				}
				if line[0] == '#' {
					continue
				}
				sdl.GameControllerAddMapping(line)
			}
		}
	}

	mach, err := newMachine(ctx)
	if err != nil {
		log.Fatalf("unable to create machine: \n%v", err)
	}

	var mon *monitor.Monitor
	mon, err = monitor.New(mach)
	if err != nil {
		log.Fatalf("unable to create monitor: %v\n", err)
	}
	defer func() {
		mon.Close()
	}()

	if optMonitor {
		go func() {
			err := mon.Run()
			if err != nil {
				log.Fatalf("monitor error: %v", err)
			}
		}()
	}

	mach.Status = rcs.Run
	if optWait {
		mach.Status = rcs.Pause
	}
	if optTrace {
		mach.Command(rcs.MachTraceAll, true)
	}
	if optImport != "" {
		filename := filepath.Join(config.VarDir, optImport)
		mach.Command(rcs.MachImport, filename)
	} else if !optFullStart {
		filename := filepath.Join(config.DataDir, "init.state")
		if _, err := os.Stat(filename); !os.IsNotExist(err) {
			mach.Command(rcs.MachImport, filename)
		}
	}

	if optPanic {
		log.SetOutput(&mock.PanicWriter{})
	}

	startFile := filepath.Join(config.UserDir, "startup")
	cmds, err := ioutil.ReadFile(startFile)
	if err == nil {
		mon.Eval(string(cmds))
	}

	mach.Run()
}


<|start_filename|>system/c64/inputs.go<|end_filename|>
package c64

import (
	"github.com/blackchip-org/retro-cs/rcs/cbm/petscii"
	"github.com/veandco/go-sdl2/sdl"
)

const kbBufLen = 10 // length of keyboard buffer

type keyboard struct {
	buf   []uint8
	ndx   uint8 // Number of characters in keyboard buffer
	stkey uint8 // Was STOP Key Pressed?
	joy2  uint8 // HACK: joystick 2, move elsewhere
}

func newKeyboard() *keyboard {
	return &keyboard{
		buf:  make([]uint8, kbBufLen, kbBufLen),
		joy2: 0xff,
	}
}

func (k *keyboard) handle(e *sdl.KeyboardEvent) error {
	ch, ok := k.lookup(e)
	if !ok {
		return nil
	}
	if k.ndx >= kbBufLen {
		return nil
	}
	k.buf[k.ndx] = ch
	k.ndx++
	return nil
}

const (
	keyCursorDown  = uint8(0x11)
	keyCursorLeft  = uint8(0x9d)
	keyCursorRight = uint8(0x1d)
	keyCursorUp    = uint8(0x91)
)

// https://wiki.libsdl.org/SDLKeycodeLookup
type keymap map[sdl.Keycode]uint8

var keys = keymap{
	sdl.K_BACKSPACE:    0x14,
	sdl.K_RETURN:       0x0d,
	sdl.K_SPACE:        0x20,
	sdl.K_QUOTE:        0x27,
	sdl.K_PERIOD:       0x2e,
	sdl.K_COMMA:        0x2c,
	sdl.K_SLASH:        0x2f,
	sdl.K_0:            0x30,
	sdl.K_1:            0x31,
	sdl.K_2:            0x32,
	sdl.K_3:            0x33,
	sdl.K_4:            0x34,
	sdl.K_5:            0x35,
	sdl.K_6:            0x36,
	sdl.K_7:            0x37,
	sdl.K_8:            0x38,
	sdl.K_9:            0x39,
	sdl.K_SEMICOLON:    0x3b,
	sdl.K_EQUALS:       0x3d,
	sdl.K_LEFTBRACKET:  0x5b,
	sdl.K_BACKSLASH:    0x5c, // british pound
	sdl.K_RIGHTBRACKET: 0x5d,
	sdl.K_a:            0x41,
	sdl.K_b:            0x42,
	sdl.K_c:            0x43,
	sdl.K_d:            0x44,
	sdl.K_e:            0x45,
	sdl.K_f:            0x46,
	sdl.K_g:            0x47,
	sdl.K_h:            0x48,
	sdl.K_i:            0x49,
	sdl.K_j:            0x4a,
	sdl.K_k:            0x4b,
	sdl.K_l:            0x4c,
	sdl.K_m:            0x4d,
	sdl.K_n:            0x4e,
	sdl.K_o:            0x4f,
	sdl.K_p:            0x50,
	sdl.K_q:            0x51,
	sdl.K_r:            0x52,
	sdl.K_s:            0x53,
	sdl.K_t:            0x54,
	sdl.K_u:            0x55,
	sdl.K_v:            0x56,
	sdl.K_w:            0x57,
	sdl.K_x:            0x58,
	sdl.K_y:            0x59,
	sdl.K_z:            0x5a,
	sdl.K_DOWN:         keyCursorDown,
	sdl.K_LEFT:         keyCursorLeft,
	sdl.K_RIGHT:        keyCursorRight,
	sdl.K_UP:           keyCursorUp,
}

var keysShift = keymap{
	sdl.K_QUOTE:     0x22,
	sdl.K_PERIOD:    0x3e,
	sdl.K_COMMA:     0x3c,
	sdl.K_SLASH:     0x3f,
	sdl.K_0:         0x29,
	sdl.K_1:         0x21,
	sdl.K_2:         0x40,
	sdl.K_3:         0x23,
	sdl.K_4:         0x24,
	sdl.K_5:         0x25,
	sdl.K_6:         0x5e,
	sdl.K_7:         0x26,
	sdl.K_8:         0x2a,
	sdl.K_9:         0x28,
	sdl.K_SEMICOLON: 0x3a,
	sdl.K_EQUALS:    0x2b,
	sdl.K_a:         0xc1,
	sdl.K_b:         0xc2,
	sdl.K_c:         0xc3,
	sdl.K_d:         0xc4,
	sdl.K_e:         0xc5,
	sdl.K_f:         0xc6,
	sdl.K_g:         0xc7,
	sdl.K_h:         0xc8,
	sdl.K_i:         0xc9,
	sdl.K_j:         0xca,
	sdl.K_k:         0xcb,
	sdl.K_l:         0xcc,
	sdl.K_m:         0xcd,
	sdl.K_n:         0xce,
	sdl.K_o:         0xcf,
	sdl.K_p:         0xd0,
	sdl.K_q:         0xd1,
	sdl.K_r:         0xd2,
	sdl.K_s:         0xd3,
	sdl.K_t:         0xd4,
	sdl.K_u:         0xd5,
	sdl.K_v:         0xd6,
	sdl.K_w:         0xd7,
	sdl.K_x:         0xd8,
	sdl.K_y:         0xd9,
	sdl.K_z:         0xda,
}

var keysControl = keymap{
	sdl.K_1: petscii.Black,
	sdl.K_2: petscii.White,
	sdl.K_3: petscii.Red,
	sdl.K_4: petscii.Cyan,
	sdl.K_5: petscii.Purple,
	sdl.K_6: petscii.Green,
	sdl.K_7: petscii.Blue,
	sdl.K_8: petscii.Yellow,
}

var keysCommodore = keymap{
	sdl.K_1: petscii.Orange,
	sdl.K_2: petscii.Brown,
	sdl.K_3: petscii.LightRed,
	sdl.K_4: petscii.DarkGray,
	sdl.K_5: petscii.MediumGray,
	sdl.K_6: petscii.LightGreen,
	sdl.K_7: petscii.LightBlue,
	sdl.K_8: petscii.LightGray,
}

var keymaps = map[sdl.Keymod]keymap{
	sdl.KMOD_NONE:   keys,
	sdl.KMOD_LSHIFT: keysShift,
	sdl.KMOD_RSHIFT: keysShift,
	sdl.KMOD_LCTRL:  keysControl,
	sdl.KMOD_RCTRL:  keysControl,
	sdl.KMOD_LGUI:   keysCommodore,
	sdl.KMOD_RGUI:   keysCommodore,
}

func (k *keyboard) lookup(e *sdl.KeyboardEvent) (uint8, bool) {
	keysym := e.Keysym
	switch {
	/*
		case keysym.Mod&sdl.KMOD_CTRL > 0 && keysym.Sym == sdl.K_ESCAPE:
				if e.Type == sdl.KEYUP {
					k.mach.Reset()
					return 0, false
				}
	*/
	case keysym.Mod&sdl.KMOD_CTRL > 0 && keysym.Sym == sdl.K_c:
		if e.Type == sdl.KEYDOWN {
			k.stkey = 0x7f
		}
	case keysym.Sym == sdl.K_c && e.Type == sdl.KEYUP:
		k.stkey = 0xff

	case keysym.Sym == sdl.K_UP && e.Type == sdl.KEYDOWN:
		k.joy2 &^= (1 << 0)
	case keysym.Sym == sdl.K_DOWN && e.Type == sdl.KEYDOWN:
		k.joy2 &^= (1 << 1)
	case keysym.Sym == sdl.K_LEFT && e.Type == sdl.KEYDOWN:
		k.joy2 &^= (1 << 2)
	case keysym.Sym == sdl.K_RIGHT && e.Type == sdl.KEYDOWN:
		k.joy2 &^= (1 << 3)
	case keysym.Sym == sdl.K_SPACE && e.Type == sdl.KEYDOWN:
		k.joy2 &^= (1 << 4)

	case keysym.Sym == sdl.K_UP && e.Type == sdl.KEYUP:
		k.joy2 |= (1 << 0)
	case keysym.Sym == sdl.K_DOWN && e.Type == sdl.KEYUP:
		k.joy2 |= (1 << 1)
	case keysym.Sym == sdl.K_LEFT && e.Type == sdl.KEYUP:
		k.joy2 |= (1 << 2)
	case keysym.Sym == sdl.K_RIGHT && e.Type == sdl.KEYUP:
		k.joy2 |= (1 << 3)
	case keysym.Sym == sdl.K_SPACE && e.Type == sdl.KEYUP:
		k.joy2 |= (1 << 4)
	}

	if e.Type != sdl.KEYDOWN {
		return 0, false
	}
	keymap0 := keymaps[sdl.KMOD_NONE]
	//mod := sdl.Keymod(keysym.Mod & 0x03) // Just take the lower two bits (why?)
	mod := sdl.Keymod(keysym.Mod)
	keymap, ok := keymaps[mod]
	if !ok {
		keymap = keymap0
	}
	ch, ok := keymap[keysym.Sym]
	if !ok {
		ch, ok = keymap0[keysym.Sym]
	}
	if !ok {
		return 0, false
	}
	return ch, true
}

func (k *keyboard) special(keysym sdl.Keysym) bool {
	return false
}


<|start_filename|>mock/mock.go<|end_filename|>
// Package mock contains testing mocks and other various utilities
// for testing code.
package mock

import "bytes"

// PanicWriter is a write that panics after the first newline has been
// written. Useful for tracking down where warnings are being emitted
// in the logger.
type PanicWriter struct {
	buf bytes.Buffer
}

// Write appends the output to an internal buffer and then panics with
// the written text once a newline is found.
func (p *PanicWriter) Write(out []byte) (int, error) {
	p.buf.Write(out)
	for _, b := range out {
		if b == '\n' {
			panic(p.buf.String())
		}
	}
	return len(out), nil
}


<|start_filename|>mock/memory_test.go<|end_filename|>
package mock

import (
	"fmt"
)

func ExampleMockRead() {
	data := []int{1, 2, 3}
	read := MockRead(data)
	fmt.Println(read())
	fmt.Println(read())
	fmt.Println(read())
	// Output:
	// 1
	// 2
	// 3
}


<|start_filename|>config/config.go<|end_filename|>
package config

import (
	"log"
	"os"
	"os/user"
	"path/filepath"
)

var (
	UserHome string // the user's home directory
	RCSDir   string // use this as the home directory
	UserDir  string
	DataDir  string // data directory
	VarDir   string // Directory where runtime variable data is stored
	System   string
)

func init() {
	usr, err := user.Current()
	if err != nil {
		log.Printf("unable to get home directory: %v", err)
	}
	UserHome = usr.HomeDir
}

// ResourceDir returns the root directory where RCS data can be found. Locations
// for the root directory are checked in this order: 1) The value of the
// Home variable in the configuration, 2) The value of the RCS_HOME
// environmental variable, 3) The "retro-cs" directory in the user's home
// directory.
func ResourceDir() string {
	userHome := "."
	u, err := user.Current()
	if err != nil {
		log.Printf("unable to find home directory: %v", err)
	} else {
		userHome = u.HomeDir
	}

	root := RCSDir
	if root == "" {
		root = os.Getenv("RCS_HOME")
	}
	if root == "" {
		root = filepath.Join(userHome, "rcs")
	}
	return root
}


<|start_filename|>rcs/rcs.go<|end_filename|>
// Package rcs contains the common components used to create retro-computing
// systems.
package rcs

import (
	"encoding/gob"
	"fmt"
	"io"
	"math/bits"
	"strconv"

	"github.com/veandco/go-sdl2/sdl"
)

func X(v int) string {
	return fmt.Sprintf("$%x", v)
}

func X8(v uint8) string {
	return fmt.Sprintf("$%02x", v)
}

func X16(v uint16) string {
	return fmt.Sprintf("$%04x", v)
}

func B(v int) string {
	return "%" + formatBits("%b", v)
}

func B8(v uint8) string {
	return "%" + formatBits("%08b", int(v))
}

func B16(v uint16) string {
	return "%" + formatBits("%016b", int(v))
}

func formatBits(f string, v int) string {
	in := fmt.Sprintf(f, v)
	out := ""
	bit := 0
	for i := len(in) - 1; i >= 0; i-- {
		if bit != 0 {
			switch {
			case bit%8 == 0:
				out = string(":") + out
			case bit%4 == 0:
				out = string('.') + out
			}
		}
		out = string(in[i]) + out
		bit++
	}
	return out
}

// Load8 is a function which loads an unsigned 8-bit value
type Load8 func() uint8

// Store8 is a function which stores an unsiged 8-bit value
type Store8 func(uint8)

// Load is a function which loads an integer value
type Load func() int

// Store is a function which stores an integer value
type Store func(int)

// FromBCD converts a binary-coded decimal to an integer value.
func FromBCD(v uint8) uint8 {
	low := v & 0x0f
	high := v >> 4
	return high*10 + low
}

// ToBCD converts an integer value to a binary-coded decimal.
func ToBCD(v uint8) uint8 {
	low := v % 10
	high := (v / 10) % 10
	return high<<4 | low
}

// ParseBits parses the base-2 string value s to a uint8. Panics if s is not
// a valid number. Use strconv.ParseUint for input which may be malformed.
func ParseBits(s string) uint8 {
	value, err := strconv.ParseUint(s, 2, 8)
	if err != nil {
		panic(err)
	}
	return uint8(value)
}

// SliceBits extracts a sequence of bits in value from bit lo to bit hi,
// inclusive.
func SliceBits(value uint8, lo int, hi int) uint8 {
	value = value >> uint(lo)
	bits := uint(hi - lo + 1)
	mask := uint8(1)<<bits - 1
	return value & mask
}

// Add performs addition on in0 and in1 with a carry and returns the result
// along with the new values for the carry, half-carry, and overflow
// flags.
func Add(in0, in1 uint8, carry bool) (out uint8, c, h, v bool) {
	// https://stackoverflow.com/questions/8034566/overflow-and-carry-flags-on-z80/8037485#8037485
	var carryOut uint8

	if carry {
		if in0 >= 0xff-in1 {
			carryOut = 1
		}
		out = in0 + in1 + 1
	} else {
		if in0 > 0xff-in1 {
			carryOut = 1
		}
		out = in0 + in1
	}
	carryIns := out ^ in0 ^ in1

	c = carryOut != 0
	h = carryIns&(1<<4) != 0
	v = (carryIns>>7)^carryOut != 0
	return
}

// Sub performs subtraction of in1 from in0 with a borrow and returns the result
// along with the new values for the borrow, half-borrow, and overflow
// flags.
func Sub(in0, in1 uint8, borrow bool) (out uint8, fc, fh, fv bool) {
	fc = !borrow
	out, fc, fh, fv = Add(in0, ^in1, fc)
	fc = !fc
	fh = !fh
	return
}

// Parity returns true if there are an even number of bits set in the
// given value.
func Parity(v uint8) bool {
	p := bits.OnesCount8(v)
	return p == 0 || p == 2 || p == 4 || p == 6 || p == 8
}

// BitPlane4 returns the nth 2-bit value stored in 4-bit planes found in v.
// If n is 0, returns bits 0 and 4. If n is 1, returns bits 1 and 5, etc.
func BitPlane4(v uint8, n int) uint8 {
	result := 0
	for i, start := range []int{0, 4} {
		checkBit := uint8(1) << uint(start+n)
		if v&checkBit != 0 {
			result += 1 << uint(i)
		}
	}
	return uint8(result)
}

// CharDecoder converts a byte value to a unicode character and indicates
// if this character is considered to be printable.
type CharDecoder func(uint8) (ch rune, printable bool)

// ASCIIDecoder is a pass through of byte values to unicode characters.
// Values 32 to 128 are considered printable.
var ASCIIDecoder = func(code uint8) (rune, bool) {
	printable := code >= 32 && code < 128
	return rune(code), printable
}

const MaxGameControllers = 4

// SDLContext contains the window for rendering and the audio specs
// available for use.
type SDLContext struct {
	Window          *sdl.Window
	Renderer        *sdl.Renderer
	AudioSpec       sdl.AudioSpec
	GameControllers [MaxGameControllers]*sdl.GameController
}

type Encoder struct {
	Err error
	enc *gob.Encoder
}

func NewEncoder(w io.Writer) *Encoder {
	return &Encoder{
		enc: gob.NewEncoder(w),
	}
}

func (e *Encoder) Encode(v interface{}) {
	if e.Err != nil {
		return
	}
	e.Err = e.enc.Encode(v)
}

type Decoder struct {
	Err error
	dec *gob.Decoder
}

func NewDecoder(r io.Reader) *Decoder {
	return &Decoder{
		dec: gob.NewDecoder(r),
	}
}

func (d *Decoder) Decode(v interface{}) {
	if d.Err != nil {
		return
	}
	d.Err = d.dec.Decode(v)
}

type Saver interface {
	Save(*Encoder)
}

type Loader interface {
	Load(*Decoder)
}

type Component struct {
	Name   string
	Module string
	Parent string
	C      interface{}
}

func NewComponent(name string, mod string, parent string, c interface{}) Component {
	return Component{Name: name, Module: mod, Parent: parent, C: c}
}

type FlagRW struct {
	R bool // Read
	W bool // Write
}


<|start_filename|>app/monitor/monitor.go<|end_filename|>
package monitor

import (
	"bytes"
	"errors"
	"fmt"
	"io"
	"io/ioutil"
	"log"
	"os"
	"path/filepath"
	"regexp"
	"runtime"
	"sort"
	"strconv"
	"strings"
	"sync"
	"time"

	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/chzyer/readline"
)

const (
	maxArgs = 0x100
)

type module interface {
	Command([]string) error
	Silence() error
	AutoComplete() []readline.PrefixCompleterInterface
}

var modules = map[string]func(m *Monitor, comp rcs.Component) module{
	"c64":      newModC64,
	"c128/mmu": newModC128MMU,
	"c128/vdc": newModC128VDC,
	"cpu":      newModCPU,
	"galaga":   newModGalaga,
	"m6502":    newModM6502,
	"mem":      newModMemory,
	"n06xx":    newModN06XX,
	"n51xx":    newModN51XX,
	"n54xx":    newModN54XX,
	"z80":      newModZ80,
}

type Monitor struct {
	mach       *rcs.Mach
	comps      map[string]rcs.Component
	mods       map[string]module
	cpu        map[string]rcs.CPU
	tracers    map[string]*rcs.Disassembler
	sc         string // selected CPU core
	in         io.ReadCloser
	out        *log.Logger
	rl         *readline.Instance
	encoding   string
	defaultCmd string
	memLines   int
	dasmLines  int
	cw         *consoleWriter
}

var silencers = make([]func(), 0, 0)

func New(mach *rcs.Mach) (*Monitor, error) {
	mach.Init()
	cw := newConsoleWriter(os.Stdout)
	// rw := newRepeatWriter(cw)
	log.SetOutput(cw)
	// log.SetOutput(os.Stdout)

	m := &Monitor{
		mach:    mach,
		comps:   make(map[string]rcs.Component),
		mods:    make(map[string]module),
		cpu:     make(map[string]rcs.CPU),
		tracers: make(map[string]*rcs.Disassembler),
		in:      readline.NewCancelableStdin(os.Stdin),
		out:     log.New(cw, "", 0),
		//out:      log.New(os.Stdout, "", 0),
		memLines: 16, // show a full page on "m" command
		cw:       cw,
	}

	mach.Callback = m.cpuCallback
	if mach.DefaultEncoding != "" {
		m.encoding = mach.DefaultEncoding
	} else {
		for name := range mach.CharDecoders {
			m.encoding = name
			break
		}
	}

	for _, comp := range mach.Comps {
		if comp.Name != "" {
			m.comps[comp.Name] = comp
			m.mods[comp.Name] = modules[comp.Module](m, comp)
		}
		if cpu, ok := comp.C.(rcs.CPU); ok {
			m.cpu[comp.Name] = cpu
			// select the first CPU seen
			if m.sc == "" {
				m.sc = comp.Name
			}

			var tracer *rcs.Disassembler
			cpud, ok := cpu.(rcs.CPUDisassembler)
			if ok {
				tracer = cpud.NewDisassembler()
			}
			m.tracers[comp.Name] = tracer
		}
	}

	historyFile := ""
	if config.UserDir != "" {
		historyFile = filepath.Join(config.UserDir, "history")
	}
	rl, err := readline.NewEx(&readline.Config{
		Prompt:       m.getPrompt(),
		Stdin:        m.in,
		HistoryFile:  historyFile,
		AutoComplete: newCompleter(m),
	})
	if err != nil {
		return nil, err
	}
	m.rl = rl
	cw.RefreshFunc = func() { m.rl.Refresh() }
	m.rl.SetPrompt(m.getPrompt())
	return m, nil
}

func (m *Monitor) Run() error {
	for {
		line, err := m.rl.Readline()
		if err == io.EOF {
			return nil
		}
		if err != nil {
			return err
		}
		m.parse(line)
	}
}

func (m *Monitor) Eval(str string) error {
	lines := strings.Split(str, "\n")
	for _, line := range lines {
		args := splitArgs(line)
		if len(args) > 0 {
			m.out.Printf("+ %v\n", line)
			err := m.dispatch(args)
			if err != nil {
				m.out.Printf("%v", err)
			}
		}
	}
	return nil
}

func (m *Monitor) Close() {
	m.in.Close()
	m.rl.Close()
	m.cw.Flush()
}

func (m *Monitor) parse(line string) {
	line = strings.TrimSpace(line)
	if line == "" && m.defaultCmd != "" {
		line = m.defaultCmd
		m.defaultCmd = ""
	}
	if line == "" {
		return
	}
	args := splitArgs(line)
	err := m.dispatch(args)
	if err != nil {
		m.out.Printf("%v", err)
		return
	}
}

func (m *Monitor) dispatch(args []string) error {
	switch args[0] {
	case
		"breakpoint", "bp",
		"disassemble", "d",
		"info", "i",
		"next", "n",
		"step", "s",
		"trace", "t":
		return m.mods[m.sc].Command(args)
	case "m":
		parent := m.comps[m.sc].Parent
		return m.mods[parent].Command(args[1:])
	case
		"peek",
		"poke",
		"watch", "w":
		parent := m.comps[m.sc].Parent
		return m.mods[parent].Command(args)
	case "config":
		return m.cmdConfig(args[1:])
	case "encoding", "e":
		return m.cmdEncoding(args[1:])
	case "export":
		return m.cmdExport(args[1:])
	case "go", "g":
		return m.cmdGo(args[1:])
	case "import":
		return m.cmdImport(args[1:])
	case "pause", "p":
		return m.cmdPause(args[1:])
	case "sleep":
		return m.cmdSleep(args[1:])
	case "snapshot", "snap":
		return m.cmdSnapshot(args[1:])
	case "q", "quit":
		return m.cmdQuit(args[1:])
	case "x":
		return m.cmdSilence()
	}

	if mod, ok := m.mods[args[0]]; ok {
		return mod.Command(args[1:])
	}

	val, err := parseValue(args[0])
	if err == nil {
		m.out.Print(formatValue(val))
		return nil
	}

	return fmt.Errorf("no such command: %v", args[0])
}

// ============================================================================
// base commands

func (m *Monitor) cmdConfig(args []string) error {
	if err := checkLen(args, 1, maxArgs); err != nil {
		return err
	}
	switch args[0] {
	case "lines-memory":
		return valueInt(m.out, &m.memLines, args[1:])
	case "lines-disassembly":
		return valueInt(m.out, &m.dasmLines, args[1:])
	}
	return fmt.Errorf("no such configuration: %v", args[0])
}

func (m *Monitor) cmdExport(args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	filename := "state"
	if len(args) > 0 {
		filename = args[0]
	}
	file := filepath.Join(config.VarDir, filename)
	m.mach.Command(rcs.MachExport, file)
	return nil
}

func (m *Monitor) cmdEncoding(args []string) error {
	list := make([]string, 0, 0)
	for k := range m.mach.CharDecoders {
		list = append(list, k)
	}
	return valueList(m.out, &m.encoding, list, args)
}

func (m *Monitor) cmdImport(args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	filename := "state"
	if len(args) > 0 {
		filename = args[0]
	}
	file := filepath.Join(config.VarDir, filename)
	m.mach.Command(rcs.MachImport, file)
	return nil
}

func (m *Monitor) cmdGo(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	m.mach.Command(rcs.MachStart)
	m.defaultCmd = "g"
	return nil
}

func (m *Monitor) cmdPause(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	m.mach.Command(rcs.MachPause)
	return nil
}

func (m *Monitor) cmdQuit(args []string) error {
	m.rl.Close()
	m.mach.Command(rcs.MachQuit)
	runtime.Goexit()
	return nil
}

func (m *Monitor) cmdSilence() error {
	for _, mod := range m.mods {
		mod.Silence()
	}
	return nil
}

func (m *Monitor) cmdSleep(args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	duration := 1 * time.Second
	if len(args) > 0 {
		v, err := parseValue(args[0])
		if err != nil {
			return err
		}
		duration = time.Duration(v) * time.Millisecond
	}
	runtime.Gosched()
	time.Sleep(duration)
	return nil
}

func (m *Monitor) cmdSnapshot(args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	filename := filepath.Join(config.VarDir, "snapshot")
	if len(args) == 1 {
		filename = args[0]
	}
	m.mach.Command(rcs.MachSnapshot, filename)
	return nil
}

// ============================================================================
// autocomplete

type byName []readline.PrefixCompleterInterface

func (n byName) Len() int      { return len(n) }
func (n byName) Swap(i, j int) { n[i], n[j] = n[j], n[i] }
func (n byName) Less(i, j int) bool {
	return string(n[i].GetName()) < string(n[j].GetName())
}

func newCompleter(m *Monitor) *readline.PrefixCompleter {
	cmds := []readline.PrefixCompleterInterface{
		readline.PcItem("breakpoint"),
		readline.PcItem("config",
			readline.PcItem("lines-memory"),
			readline.PcItem("lines-disassembly"),
		),
		readline.PcItem("encoding",
			readline.PcItemDynamic(acEncodings(m)),
		),
		readline.PcItem("export"),
		readline.PcItem("disassemble"),
		readline.PcItem("import"),
		readline.PcItem("info"),
		readline.PcItem("next"),
		readline.PcItem("quit"),
		readline.PcItem("step"),
		readline.PcItem("sleep"),
		readline.PcItem("snapshot"),
		readline.PcItem("watch"),
	}
	for key, mod := range m.mods {
		cmds = append(cmds, []readline.PrefixCompleterInterface{
			readline.PcItem(key, mod.AutoComplete()...),
		}...)
	}
	sort.Sort(byName(cmds))
	return readline.NewPrefixCompleter(cmds...)
}

func acDataFiles(m *Monitor, suffix string) func(string) []string {
	return func(line string) []string {
		results := make([]string, 0, 0)
		arg := ""
		i := strings.LastIndex(line, " ")
		if i >= 0 {
			arg = line[i:]
		}
		var dir, prefix string
		if filepath.IsAbs(arg) {
			dir = filepath.Dir(arg)
			prefix = filepath.Base(arg)
		} else {
			dir = config.DataDir
			prefix = arg
		}
		prefix = strings.TrimSpace(prefix)
		files, err := ioutil.ReadDir(dir)
		if err != nil {
			m.out.Println(err)
			return []string{}
		}
		for _, f := range files {
			name := f.Name()
			if strings.HasPrefix(name, prefix) && strings.HasSuffix(name, suffix) {
				results = append(results, name)
			}
		}
		return results
	}
}

func acEncodings(m *Monitor) func(string) []string {
	return func(line string) []string {
		names := make([]string, 0)
		for k := range m.mach.CharDecoders {
			names = append(names, k)
		}
		sort.Strings(names)
		return names
	}
}

var acRW = []readline.PrefixCompleterInterface{
	readline.PcItem("r"),
	readline.PcItem("w"),
	readline.PcItem("rw"),
	readline.PcItem("on"),
	readline.PcItem("off"),
}

// ============================================================================
// aux

func (m *Monitor) cpuCallback(evt rcs.MachEvent, args ...interface{}) {
	switch evt {
	case rcs.TraceEvent:
		name := args[0].(string)
		pc := args[1].(int)
		prefix := ""
		if name != "cpu" {
			prefix = name + "  "
		}
		m.tracers[name].SetPC(pc + m.cpu[m.sc].Offset())
		m.out.Printf("%v%v", prefix, m.tracers[name].Next())
	case rcs.ErrorEvent:
		m.out.Println(args[0])
	case rcs.StatusEvent:
		status := args[0].(rcs.Status)
		if status == rcs.Break {
			m.out.Println()
			m.dispatch([]string{"i"})
			m.out.Println()
			m.rl.Refresh()
		}
	}
}

func checkLen(args []string, min int, max int) error {
	if len(args) < min {
		return errors.New("not enough arguments")
	}
	if len(args) > max {
		return errors.New("too many arguments")
	}
	return nil
}

func parseUint(str string, bitSize int) (uint64, error) {
	base := 10
	switch {
	case strings.HasPrefix(str, "$"), strings.HasPrefix(str, "0x"):
		str = str[1:]
		base = 16
	case strings.HasPrefix(str, "%"), strings.HasPrefix(str, "0b"):
		str = str[1:]
		str = strings.Replace(str, ":", "", -1)
		str = strings.Replace(str, ".", "", -1)
		base = 2
	}
	return strconv.ParseUint(str, base, bitSize)
}

func loadPath(name string) string {
	if filepath.IsAbs(name) {
		return name
	}
	return filepath.Join(config.DataDir, name)
}

var whitespaceRegex = regexp.MustCompile("\\s+")

func splitArgs(line string) []string {
	line = strings.TrimSpace(line)
	if line == "" || line[0] == '#' {
		return []string{}
	}
	return whitespaceRegex.Split(line, -1)
}

func parseValue(str string) (int, error) {
	value, err := parseUint(str, 64)
	if err != nil {
		return 0, fmt.Errorf("invalid value: %v", str)
	}
	return int(value), nil
}

func parseValue8(str string) (uint8, error) {
	value, err := parseUint(str, 8)
	if err != nil {
		return 0, fmt.Errorf("invalid value: %v", str)
	}
	return uint8(value), nil
}

func parseValue16(str string) (uint16, error) {
	value, err := parseUint(str, 16)
	if err != nil {
		return 0, fmt.Errorf("invalid value: %v", str)
	}
	return uint16(value), nil
}

func parseBool(str string) (bool, error) {
	switch str {
	case "true", "1", "yes", "on":
		return true, nil
	case "false", "0", "no", "off":
		return false, nil
	}
	return false, fmt.Errorf("invalid value: %v", str)
}

func formatBits(v int) string {
	in := fmt.Sprintf("%b", v)
	out := ""
	bit := 0
	for i := len(in) - 1; i >= 0; i-- {
		if bit != 0 {
			switch {
			case bit%8 == 0:
				out = string(":") + out
			case bit%4 == 0:
				out = string('.') + out
			}
		}
		out = string(in[i]) + out
		bit++
	}
	return out
}

func formatValue(v int) string {
	return fmt.Sprintf("%d $%x %%%s", v, v, formatBits(v))
}

// assumes 16-bit address for now, may be more flexable later
func formatAddress(v int) string {
	return fmt.Sprintf("%v", rcs.X16(uint16(v)))
}

func valueBool(out *log.Logger, val *bool, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(*val)
		return nil
	}
	sval := strings.ToLower(args[0])
	switch sval {
	case "true", "yes", "on", "t", "1":
		*val = true
	case "false", "no", "off", "f", "0":
		*val = false
	default:
		return fmt.Errorf("invalid value: %v", args[0])
	}
	return nil
}

func valueInt(out *log.Logger, val *int, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(formatValue(int(*val)))
		return nil
	}
	v, err := parseValue(args[0])
	if err != nil {
		return err
	}
	*val = v
	return nil
}

func valueUint8(out *log.Logger, val *uint8, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(formatValue(int(*val)))
		return nil
	}
	v, err := parseValue8(args[0])
	if err != nil {
		return err
	}
	*val = v
	return nil
}

func valueUint16(out *log.Logger, val *uint16, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(formatValue(int(*val)))
		return nil
	}
	v, err := parseValue16(args[0])
	if err != nil {
		return err
	}
	*val = v
	return nil
}

func valueUint16HL(out *log.Logger, hi *uint8, lo *uint8, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		val := int(*hi)<<8 | int(*lo)
		out.Println(formatValue(val))
		return nil
	}
	v, err := parseValue16(args[0])
	if err != nil {
		return err
	}
	*hi = uint8(v >> 8)
	*lo = uint8(v)
	return nil
}

func valueIntF(out *log.Logger, load rcs.Load, store rcs.Store, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(formatValue(load()))
		return nil
	}
	v, err := parseValue(args[0])
	if err != nil {
		return err
	}
	store(v)
	return nil
}

func valueList(out *log.Logger, val *string, list []string, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(*val)
		return nil
	}
	for _, i := range list {
		if i == args[0] {
			*val = i
			return nil
		}
	}
	return fmt.Errorf("invalid value: %v", args[0])
}

func valueBit(out *log.Logger, val *uint8, mask uint8, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(*val&mask != 0)
		return nil
	}
	switch args[0] {
	case "true", "yes", "on", "t", "1":
		*val |= mask
	case "false", "no", "off", "f", "0":
		*val &^= mask
	default:
		return fmt.Errorf("invalid value: %v", args[0])
	}
	return nil
}

func valueFunc8(out *log.Logger, load rcs.Load8, store rcs.Store8, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		out.Println(formatValue(int(load())))
		return nil
	}
	val, err := parseValue8(args[0])
	if err != nil {
		return err
	}
	store(val)
	return nil
}

func valueRW(out *log.Logger, f *rcs.FlagRW, args []string) error {
	if err := checkLen(args, 0, 1); err != nil {
		return err
	}
	if len(args) == 0 {
		switch {
		case f.R && f.W:
			out.Println("rw")
		case f.R:
			out.Println("r")
		case f.W:
			out.Println("w")
		default:
			out.Println("off")
		}
		return nil
	}
	switch args[0] {
	case "r":
		f.R = true
		f.W = false
	case "w":
		f.R = false
		f.W = true
	case "rw", "on":
		f.R = true
		f.W = true
	case "off":
		f.R = false
		f.W = false
	default:
		return fmt.Errorf("invalid argument: %v", args[0])
	}
	return nil
}

func terminal(args []string, fn func() error) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	return fn()
}

func parseAddress(mem *rcs.Memory, str string) (int, error) {
	value, err := parseUint(str, 64)
	if err != nil || int(value) > mem.MaxAddr {
		return 0, fmt.Errorf("invalid address: %v", str)
	}
	return int(value), nil
}

// =========================================================================
// console

const (
	// carriage return to go to the beginning of the line
	// then ansi escape sequence to clear the line
	ansiClearLine  = "\r\033[2K"
	ansiReset      = "\033[0m"
	ansiLightBlue  = "\033[1;34m"
	ansiLightGreen = "\033[1;32m"
)

func (m *Monitor) getPrompt() string {
	c := ""
	if len(m.mach.CPU) > 1 {
		c = fmt.Sprintf(":%v%v%v", ansiLightBlue, m.sc, ansiReset)
	}
	return fmt.Sprintf("%vmonitor%v%v> ", ansiLightGreen, ansiReset, c)
}

type consoleWriter struct {
	RefreshFunc     func()
	rl              *readline.Instance
	w               io.Writer
	line            bytes.Buffer
	backlog         bytes.Buffer
	timer           *time.Timer
	mutex           sync.Mutex
	firstInterval   time.Duration // wait this long before emitting the first line
	backlogInterval time.Duration // wait this long between backlog processing
	maxUpdate       int           // maximum number of charaters per update
}

func newConsoleWriter(w io.Writer) *consoleWriter {
	cw := &consoleWriter{
		w:               w,
		firstInterval:   time.Millisecond * 10,
		backlogInterval: time.Millisecond * 100,
		maxUpdate:       2000,
	}
	return cw
}

func (c *consoleWriter) Write(p []byte) (int, error) {
	for _, b := range p {
		c.line.WriteByte(b)
		if b == '\n' {
			c.backlog.Write(c.line.Bytes())
			if c.timer == nil {
				c.timer = time.AfterFunc(c.firstInterval, c.emit)
			}
			c.line.Reset()
		}
	}
	return len(p), nil
}

func (c *consoleWriter) Flush() {
	c.emit()
}

func (c *consoleWriter) emit() {
	c.mutex.Lock()
	defer func() {
		c.mutex.Unlock()
	}()

	if c.backlog.Len() == 0 {
		c.timer = nil
		return
	}
	update := c.backlog.String()
	lines := strings.Count(update, "\n")
	omission := false
	if lines > c.maxUpdate {
		// Count backwards to find start of the first line in the
		// maximum lines allowed per update
		omission = true
		seen := 0
		for i := len(update) - 1; i >= 0; i-- {
			if update[i] == '\n' {
				seen++
				if seen == c.maxUpdate {
					update = update[i+1 : len(update)-1]
					break
				}
			}
		}
	}
	// carriage return to go to the begnning of the line
	// then ansi escape sequence to clear the line
	io.WriteString(c.w, ansiClearLine)
	if omission {
		text := fmt.Sprintf("... omitted %v lines\n", lines-c.maxUpdate)
		io.WriteString(c.w, text)
	}
	io.WriteString(c.w, update)
	c.RefreshFunc()
	c.backlog.Reset()
	c.timer = time.AfterFunc(c.backlogInterval, c.emit)
}

type repeatWriter struct {
	w       io.Writer
	buf     strings.Builder
	prev    string
	repeats int
	ansi    bool
}

func newRepeatWriter(w io.Writer) *repeatWriter {
	return &repeatWriter{w: w, ansi: true}
}

func (r *repeatWriter) Write(p []byte) (int, error) {
	for _, b := range p {
		r.buf.WriteByte(b)
		if b == '\n' {
			r.eoln()
		}
	}
	return len(p), nil
}

func (r *repeatWriter) Close() error {
	if !strings.HasSuffix(r.buf.String(), "\n") {
		r.buf.WriteString("\n")
	}
	r.eoln()
	return nil
}

func (r *repeatWriter) eoln() {
	str := r.buf.String()
	if str != r.prev {
		if r.repeats > 0 {
			if r.ansi {
				io.WriteString(r.w, ansiClearLine)
				io.WriteString(r.w, "... repeats ")
			}
			if r.repeats == 1 {
				io.WriteString(r.w, "1 time\n")
			} else if r.repeats > 1 {
				io.WriteString(r.w, fmt.Sprintf("%d times\n", r.repeats))
			}
		}
		r.repeats = 0
		io.WriteString(r.w, str)
	} else {
		if r.repeats == 0 {
			io.WriteString(r.w, "... repeats ")
		}
		r.repeats++
	}
	r.buf.Reset()
	r.prev = str
}


<|start_filename|>system/c64/c64.go<|end_filename|>
// Package c64 is the Commodore 64.
package c64

import (
	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/cbm"
	"github.com/blackchip-org/retro-cs/rcs/cbm/petscii"
	"github.com/blackchip-org/retro-cs/rcs/m6502"
)

type system struct {
	cpu    *m6502.CPU
	mem    *rcs.Memory
	screen rcs.Screen
	vic    *cbm.VIC
	ram    []uint8
	io     []uint8
	bank   uint8
}

func New(ctx rcs.SDLContext) (*rcs.Mach, error) {
	s := &system{}
	roms, err := rcs.LoadROMs(config.DataDir, SystemROM)
	if err != nil {
		return nil, err
	}
	s.ram = make([]uint8, 0x10000, 0x10000)
	s.io = make([]uint8, 0x1000, 0x1000)

	s.mem = newMemory(s.ram, s.io, roms)
	kb := newKeyboard()

	v, err := cbm.NewVIC(ctx.Renderer, s.mem, roms["chargen"])
	if err != nil {
		return nil, err
	}
	s.vic = v
	s.screen = rcs.Screen{
		W:         v.W,
		H:         v.H,
		Texture:   v.Texture,
		ScanLineH: true,
		Draw:      v.Draw,
	}

	for b := 0; b < 32; b++ {
		s.mem.SetBank(b)
		// setup IO port on the 6510, map address 1 to "PLA"s
		s.mem.MapLoad(0x01, s.ioPortLoad)
		s.mem.MapStore(0x01, s.ioPortStore)

		s.mem.MapRW(0xd020, &s.vic.BorderColor)
		s.mem.MapRW(0xd021, &s.vic.BgColor)

		s.mem.MapRW(0x0091, &kb.stkey) // stop key
		s.mem.MapRW(0x00c6, &kb.ndx)   // buffer index
		s.mem.MapRAM(0x0277, kb.buf)

		s.mem.MapRW(0xdc00, &kb.joy2)
	}
	// Initialize to bank 31
	s.mem.SetBank(31)
	// GAME and EXROM on to start
	s.bank = 0x18
	// HIMEM, LOMEM, CHAREN on to start
	s.mem.Write(1, 0x7)

	// CPU should be created after memory is completely setup to obtain
	// the correct reset vector
	s.cpu = m6502.New(s.mem)

	mach := &rcs.Mach{
		Sys: s,
		Comps: []rcs.Component{
			rcs.NewComponent("c64", "c64", "", s),
			rcs.NewComponent("cpu", "m6502", "mem", s.cpu),
			rcs.NewComponent("mem", "mem", "", s.mem),
		},
		CharDecoders: map[string]rcs.CharDecoder{
			"petscii":         petscii.Decoder,
			"petscii-shifted": petscii.ShiftedDecoder,
			"screen":          cbm.ScreenDecoder,
			"screen-shifted":  cbm.ScreenShiftedDecoder,
		},
		DefaultEncoding: "petscii",
		Ctx:             ctx,
		VBlankFunc: func() {
			s.cpu.IRQ = true
		},
		Screen:   s.screen,
		Keyboard: kb.handle,
	}

	return mach, nil
}

func (s *system) ioPortStore(v uint8) {
	// PLA information is in the bottom 3 bits
	s.bank &^= 0x7
	s.bank |= v & 0x7
	s.mem.SetBank(int(s.bank))
}

func (s *system) ioPortLoad() uint8 {
	// Only return the bottom 3 bits for now
	return s.bank & 0x7
}

func (s *system) Save(enc *rcs.Encoder) {
	s.cpu.Save(enc)
	enc.Encode(s.ram)
	enc.Encode(s.io)
}

func (s *system) Load(dec *rcs.Decoder) {
	s.cpu.Load(dec)
	dec.Decode(&s.ram)
	dec.Decode(&s.io)
}


<|start_filename|>app/monitor/namco.go<|end_filename|>
package monitor

import (
	"fmt"
	"log"

	"github.com/chzyer/readline"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/namco"
)

type modN06XX struct {
	mon   *Monitor
	out   *log.Logger
	n06xx *namco.N06XX
}

func newModN06XX(mon *Monitor, comp rcs.Component) module {
	return &modN06XX{
		mon:   mon,
		out:   mon.out,
		n06xx: comp.C.(*namco.N06XX),
	}
}

func (m *modN06XX) Command(args []string) error {
	if err := checkLen(args, 1, maxArgs); err != nil {
		return err
	}
	switch args[0] {
	case "watch-data-write":
		return valueBool(m.out, &m.n06xx.WatchDataW, args[1:])
	case "watch-data-read":
		return valueBool(m.out, &m.n06xx.WatchDataR, args[1:])
	case "watch-control-write":
		return valueBool(m.out, &m.n06xx.WatchCtrlW, args[1:])
	case "watch-control-read":
		return valueBool(m.out, &m.n06xx.WatchCtrlR, args[1:])
	case "watch-nmi":
		return valueBool(m.out, &m.n06xx.WatchNMI, args[1:])
	case "watch-all":
		return terminal(args[1:], func() error {
			m.n06xx.WatchDataW = true
			m.n06xx.WatchDataR = true
			m.n06xx.WatchCtrlW = true
			m.n06xx.WatchCtrlR = true
			m.n06xx.WatchNMI = true
			return nil
		})
	case "watch-none":
		return terminal(args[1:], m.Silence)
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modN06XX) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("watch-data-write"),
		readline.PcItem("watch-data-read"),
		readline.PcItem("watch-control-write"),
		readline.PcItem("watch-control-read"),
		readline.PcItem("watch-nmi"),
		readline.PcItem("watch-all"),
		readline.PcItem("watch-none"),
	}
}

func (m *modN06XX) Silence() error {
	m.n06xx.WatchDataW = false
	m.n06xx.WatchDataR = false
	m.n06xx.WatchCtrlW = false
	m.n06xx.WatchCtrlR = false
	m.n06xx.WatchNMI = false
	return nil
}

type modN51XX struct {
	mon   *Monitor
	out   *log.Logger
	n51xx *namco.N51XX
}

func newModN51XX(mon *Monitor, comp rcs.Component) module {
	return &modN51XX{
		mon:   mon,
		out:   mon.out,
		n51xx: comp.C.(*namco.N51XX),
	}
}

func (m *modN51XX) Command(args []string) error {
	if err := checkLen(args, 1, maxArgs); err != nil {
		return err
	}
	switch args[0] {
	case "watch-write":
		return valueBool(m.out, &m.n51xx.WatchW, args[1:])
	case "watch-read":
		return valueBool(m.out, &m.n51xx.WatchR, args[1:])
	case "watch-all":
		return terminal(args[1:], func() error {
			m.n51xx.WatchW = true
			m.n51xx.WatchR = true
			return nil
		})
	case "watch-none":
		return terminal(args[1:], m.Silence)
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modN51XX) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("watch-write"),
		readline.PcItem("watch-read"),
		readline.PcItem("watch-all"),
		readline.PcItem("watch-none"),
	}
}

func (m *modN51XX) Silence() error {
	m.n51xx.WatchW = false
	m.n51xx.WatchR = false
	return nil
}

type modN54XX struct {
	mon   *Monitor
	out   *log.Logger
	n54xx *namco.N54XX
}

func newModN54XX(mon *Monitor, comp rcs.Component) module {
	return &modN54XX{
		mon:   mon,
		out:   mon.out,
		n54xx: comp.C.(*namco.N54XX),
	}
}

func (m *modN54XX) Command(args []string) error {
	if err := checkLen(args, 1, maxArgs); err != nil {
		return err
	}
	switch args[0] {
	case "watch-write":
		return valueBool(m.out, &m.n54xx.WatchW, args[1:])
	case "watch-read":
		return valueBool(m.out, &m.n54xx.WatchR, args[1:])
	case "watch-all":
		return terminal(args[1:], func() error {
			m.n54xx.WatchW = true
			m.n54xx.WatchR = true
			return nil
		})
	case "watch-none":
		return terminal(args[1:], m.Silence)
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modN54XX) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("watch-write"),
		readline.PcItem("watch-read"),
		readline.PcItem("watch-all"),
		readline.PcItem("watch-none"),
	}
}

func (m *modN54XX) Silence() error {
	m.n54xx.WatchW = false
	m.n54xx.WatchR = false
	return nil
}


<|start_filename|>rcs/z80/addressing.go<|end_filename|>
package z80

func (c *CPU) storeNil(v uint8) {}

func (c *CPU) storeIndImm(v uint8) { c.mem.Write(c.fetch2(), v) }
func (c *CPU) store16IndImm(v int) { c.mem.WriteLE(c.fetch2(), v) }

func (c *CPU) storeA(v uint8)   { c.A = v }
func (c *CPU) storeF(v uint8)   { c.F = v }
func (c *CPU) storeB(v uint8)   { c.B = v }
func (c *CPU) storeC(v uint8)   { c.C = v }
func (c *CPU) storeD(v uint8)   { c.D = v }
func (c *CPU) storeE(v uint8)   { c.E = v }
func (c *CPU) storeH(v uint8)   { c.H = v }
func (c *CPU) storeL(v uint8)   { c.L = v }
func (c *CPU) storeI(v uint8)   { c.I = v }
func (c *CPU) storeR(v uint8)   { c.R = v }
func (c *CPU) storeIXH(v uint8) { c.IXH = v }
func (c *CPU) storeIXL(v uint8) { c.IXL = v }
func (c *CPU) storeIYH(v uint8) { c.IYH = v }
func (c *CPU) storeIYL(v uint8) { c.IYL = v }

func (c *CPU) storeA1(v uint8) { c.A1 = v }
func (c *CPU) storeF1(v uint8) { c.F1 = v }
func (c *CPU) storeB1(v uint8) { c.B1 = v }
func (c *CPU) storeC1(v uint8) { c.C1 = v }
func (c *CPU) storeD1(v uint8) { c.D1 = v }
func (c *CPU) storeE1(v uint8) { c.E1 = v }
func (c *CPU) storeH1(v uint8) { c.H1 = v }
func (c *CPU) storeL1(v uint8) { c.L1 = v }

func (c *CPU) storeAF(v int) { c.A, c.F = uint8(v>>8), uint8(v) }
func (c *CPU) storeBC(v int) { c.B, c.C = uint8(v>>8), uint8(v) }
func (c *CPU) storeDE(v int) { c.D, c.E = uint8(v>>8), uint8(v) }
func (c *CPU) storeHL(v int) { c.H, c.L = uint8(v>>8), uint8(v) }
func (c *CPU) storeSP(v int) { c.SP = uint16(v) }
func (c *CPU) storeIX(v int) { c.IXH, c.IXL = uint8(v>>8), uint8(v) }
func (c *CPU) storeIY(v int) { c.IYH, c.IYL = uint8(v>>8), uint8(v) }

func (c *CPU) store16IndSP(v int) { c.mem.WriteLE(int(c.SP), v) }

func (c *CPU) storeAF1(v int) { c.A1, c.F1 = uint8(v>>8), uint8(v) }
func (c *CPU) storeBC1(v int) { c.B1, c.C1 = uint8(v>>8), uint8(v) }
func (c *CPU) storeDE1(v int) { c.D1, c.E1 = uint8(v>>8), uint8(v) }
func (c *CPU) storeHL1(v int) { c.H1, c.L1 = uint8(v>>8), uint8(v) }

func (c *CPU) storeIndHL(v uint8) { c.mem.Write(int(c.H)<<8|int(c.L), v) }

func (c *CPU) storeIndBC(v uint8) { c.mem.Write(int(c.B)<<8|int(c.C), v) }
func (c *CPU) storeIndDE(v uint8) { c.mem.Write(int(c.D)<<8|int(c.E), v) }

func (c *CPU) loadZero() uint8   { return 0 }
func (c *CPU) loadImm() uint8    { return c.fetch() }
func (c *CPU) loadImm16() int    { return c.fetch2() }
func (c *CPU) loadIndImm() uint8 { return c.mem.Read(c.fetch2()) }
func (c *CPU) load16IndImm() int { return c.mem.ReadLE(c.fetch2()) }

func (c *CPU) loadA() uint8    { return c.A }
func (c *CPU) loadF() uint8    { return c.F }
func (c *CPU) loadB() uint8    { return c.B }
func (c *CPU) loadC() uint8    { return c.C }
func (c *CPU) loadD() uint8    { return c.D }
func (c *CPU) loadE() uint8    { return c.E }
func (c *CPU) loadH() uint8    { return c.H }
func (c *CPU) loadL() uint8    { return c.L }
func (c *CPU) loadI() uint8    { return c.I }
func (c *CPU) loadR() uint8    { return c.R }
func (c *CPU) loadIXL() uint8  { return c.IXL }
func (c *CPU) loadIXH() uint8  { return c.IXH }
func (c *CPU) loadIYL() uint8  { return c.IYL }
func (c *CPU) loadIYH() uint8  { return c.IYH }
func (c *CPU) loadIndC() uint8 { return c.Ports.Read(int(c.C)) }

func (c *CPU) loadA1() uint8 { return c.A1 }
func (c *CPU) loadF1() uint8 { return c.F1 }
func (c *CPU) loadB1() uint8 { return c.B1 }
func (c *CPU) loadC1() uint8 { return c.C1 }
func (c *CPU) loadD1() uint8 { return c.D1 }
func (c *CPU) loadE1() uint8 { return c.E1 }
func (c *CPU) loadH1() uint8 { return c.H1 }
func (c *CPU) loadL1() uint8 { return c.L1 }

func (c *CPU) loadAF() int      { return int(c.A)<<8 | int(c.F) }
func (c *CPU) loadBC() int      { return int(c.B)<<8 | int(c.C) }
func (c *CPU) loadDE() int      { return int(c.D)<<8 | int(c.E) }
func (c *CPU) loadHL() int      { return int(c.H)<<8 | int(c.L) }
func (c *CPU) loadSP() int      { return int(c.SP) }
func (c *CPU) loadIX() int      { return int(c.IXH)<<8 | int(c.IXL) }
func (c *CPU) loadIY() int      { return int(c.IYH)<<8 | int(c.IYL) }
func (c *CPU) load16IndSP() int { return c.mem.ReadLE(int(c.SP)) }

func (c *CPU) loadAF1() int { return int(c.A1)<<8 | int(c.F1) }
func (c *CPU) loadBC1() int { return int(c.B1)<<8 | int(c.C1) }
func (c *CPU) loadDE1() int { return int(c.D1)<<8 | int(c.E1) }
func (c *CPU) loadHL1() int { return int(c.H1)<<8 | int(c.L1) }

func (c *CPU) loadIndHL() uint8 { return c.mem.Read(int(c.H)<<8 | int(c.L)) }

func (c *CPU) loadIndBC() uint8 { return c.mem.Read(int(c.B)<<8 | int(c.C)) }
func (c *CPU) loadIndDE() uint8 { return c.mem.Read(int(c.D)<<8 | int(c.E)) }

func (c *CPU) loadIndIX() uint8 {
	ix := int(c.IXH)<<8 | int(c.IXL)
	c.iaddr = ix + int(int8(c.delta))
	return c.mem.Read(c.iaddr)
}

func (c *CPU) loadIndIY() uint8 {
	iy := int(c.IYH)<<8 | int(c.IYL)
	c.iaddr = iy + int(int8(c.delta))
	return c.mem.Read(c.iaddr)
}

func (c *CPU) storeIndIX(v uint8) {
	ix := int(c.IXH)<<8 | int(c.IXL)
	addr := ix + int(int8(c.delta))
	c.mem.Write(addr, v)
}

func (c *CPU) storeIndIY(v uint8) {
	iy := int(c.IYH)<<8 | int(c.IYL)
	addr := iy + int(int8(c.delta))
	c.mem.Write(addr, v)
}

func (c *CPU) storeLastInd(v uint8) {
	c.mem.Write(c.iaddr, v)
}

func (c *CPU) outIndImm(v uint8) {
	addr := int(c.fetch())
	c.Ports.Write(addr, v)
}

func (c *CPU) inIndImm() uint8 {
	addr := int(c.fetch())
	return c.Ports.Read(addr)
}

func (c *CPU) outIndC(v uint8) {
	c.Ports.Write(int(c.C), v)
}

func (c *CPU) inIndC() uint8 {
	return c.Ports.Read(int(c.C))
}


<|start_filename|>system/pacman/inputs.go<|end_filename|>
package pacman

import (
	"github.com/veandco/go-sdl2/sdl"
)

type keyboard struct {
	s *system
}

func newKeyboard(s *system) *keyboard {
	return &keyboard{s: s}
}

func (k *keyboard) handle(e *sdl.KeyboardEvent) error {
	s := k.s
	if e.Type == sdl.KEYDOWN {
		switch e.Keysym.Sym {
		case sdl.K_1:
			s.in1 |= 1 << 5
		case sdl.K_2:
			s.in1 |= 1 << 6
		case sdl.K_c:
			s.in0 |= 1 << 5
		case sdl.K_r:
			s.in0 |= 1 << 4
		case sdl.K_UP:
			s.in0 &^= 1 << 0
		case sdl.K_LEFT:
			s.in0 &^= 1 << 1
		case sdl.K_RIGHT:
			s.in0 &^= 1 << 2
		case sdl.K_DOWN:
			s.in0 &^= 1 << 3
		}
	} else if e.Type == sdl.KEYUP {
		switch e.Keysym.Sym {
		case sdl.K_1:
			s.in1 &^= 1 << 5
		case sdl.K_2:
			s.in1 &^= 1 << 6
		case sdl.K_c:
			s.in0 &^= 1 << 5
		case sdl.K_r:
			s.in0 &^= 1 << 4
		case sdl.K_UP:
			s.in0 |= 1 << 0
		case sdl.K_LEFT:
			s.in0 |= 1 << 1
		case sdl.K_RIGHT:
			s.in0 |= 1 << 2
		case sdl.K_DOWN:
			s.in0 |= 1 << 3
		}
	}
	return nil
}

type joyPos int

const (
	joyNone joyPos = iota
	joyUp
	joyLeft
	joyRight
	joyDown
)

type joystick struct {
	s   *system
	pos joyPos
}

func newJoystick(s *system) *joystick {
	return &joystick{s: s}
}

func (j *joystick) buttonHandler(e *sdl.ControllerButtonEvent) error {
	s := j.s
	if e.Type == sdl.CONTROLLERBUTTONDOWN {
		switch e.Button {
		case sdl.CONTROLLER_BUTTON_BACK:
			s.in0 |= 1 << 5
		case sdl.CONTROLLER_BUTTON_START:
			s.in1 |= 1 << 5
		case sdl.CONTROLLER_BUTTON_DPAD_UP:
			if j.pos == joyNone {
				j.pos = joyUp
				s.in0 &^= 1 << 0
			}
		case sdl.CONTROLLER_BUTTON_DPAD_LEFT:
			if j.pos == joyNone {
				j.pos = joyLeft
				s.in0 &^= 1 << 1
			}
		case sdl.CONTROLLER_BUTTON_DPAD_RIGHT:
			if j.pos == joyNone {
				j.pos = joyRight
				s.in0 &^= 1 << 2
			}
		case sdl.CONTROLLER_BUTTON_DPAD_DOWN:
			if j.pos == joyNone {
				j.pos = joyDown
				s.in0 &^= 1 << 3
			}
		}
	} else if e.Type == sdl.CONTROLLERBUTTONUP {
		switch e.Button {
		case sdl.CONTROLLER_BUTTON_BACK:
			s.in0 &^= 1 << 5
		case sdl.CONTROLLER_BUTTON_START:
			s.in1 &^= 1 << 5
		case sdl.CONTROLLER_BUTTON_DPAD_UP:
			if j.pos == joyUp {
				j.pos = joyNone
				s.in0 |= 1 << 0
			}
		case sdl.CONTROLLER_BUTTON_DPAD_LEFT:
			if j.pos == joyLeft {
				j.pos = joyNone
				s.in0 |= 1 << 1
			}
		case sdl.CONTROLLER_BUTTON_DPAD_RIGHT:
			if j.pos == joyRight {
				j.pos = joyNone
				s.in0 |= 1 << 2
			}
		case sdl.CONTROLLER_BUTTON_DPAD_DOWN:
			if j.pos == joyDown {
				j.pos = joyNone
				s.in0 |= 1 << 3
			}
		}
	}
	return nil
}


<|start_filename|>rcs/z80/fuse_expected_test.go<|end_filename|>
// Code generated by gen/z80/fuse/fuse.go. DO NOT EDIT.

package z80

var fuseExpected = map[string]fuseTest{
	"00": fuseTest{
		name:       "00",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"01": fuseTest{
		name:       "01",
		af:         0x0000,
		bc:         0x3412,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"02": fuseTest{
		name:    "02",
		af:      0x5600,
		bc:      0x0001,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0x0001, 0x56},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"03": fuseTest{
		name:       "03",
		af:         0x0000,
		bc:         0x789b,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"04": fuseTest{
		name:       "04",
		af:         0x0050,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"05": fuseTest{
		name:       "05",
		af:         0x00ba,
		bc:         0xff00,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"06": fuseTest{
		name:       "06",
		af:         0x0000,
		bc:         0xbc00,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"07": fuseTest{
		name:       "07",
		af:         0x1101,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"08": fuseTest{
		name:       "08",
		af:         0x1234,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0xdef0,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"09": fuseTest{
		name:       "09",
		af:         0x0030,
		bc:         0x5678,
		de:         0x0000,
		hl:         0xf134,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"0a": fuseTest{
		name:       "0a",
		af:         0xde00,
		bc:         0x0001,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"0b": fuseTest{
		name:       "0b",
		af:         0x0000,
		bc:         0xffff,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"0c": fuseTest{
		name:       "0c",
		af:         0x0094,
		bc:         0x0080,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"0d": fuseTest{
		name:       "0d",
		af:         0x003e,
		bc:         0x007f,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"0e": fuseTest{
		name:       "0e",
		af:         0x0000,
		bc:         0x00f0,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"0f": fuseTest{
		name:       "0f",
		af:         0xa021,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"10": fuseTest{
		name:       "10",
		af:         0x0000,
		bc:         0x0001,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x11,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    135,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"11": fuseTest{
		name:       "11",
		af:         0x0000,
		bc:         0x0000,
		de:         0xbc9a,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"12": fuseTest{
		name:    "12",
		af:      0x5600,
		bc:      0x0000,
		de:      0x8000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0x8000, 0x56},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"13": fuseTest{
		name:       "13",
		af:         0x0000,
		bc:         0x0000,
		de:         0xdef1,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"14": fuseTest{
		name:       "14",
		af:         0x0028,
		bc:         0x0000,
		de:         0x2800,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"15": fuseTest{
		name:       "15",
		af:         0x001a,
		bc:         0x0000,
		de:         0x0f00,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"16": fuseTest{
		name:       "16",
		af:         0x0000,
		bc:         0x0000,
		de:         0x1200,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"17": fuseTest{
		name:       "17",
		af:         0x1100,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"18": fuseTest{
		name:       "18",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0042,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"19": fuseTest{
		name:       "19",
		af:         0x0028,
		bc:         0x0000,
		de:         0x3456,
		hl:         0xacf0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"1a": fuseTest{
		name:       "1a",
		af:         0x1300,
		bc:         0x0000,
		de:         0x8000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"1b": fuseTest{
		name:       "1b",
		af:         0x0000,
		bc:         0x0000,
		de:         0xe5d3,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"1c": fuseTest{
		name:       "1c",
		af:         0x00a8,
		bc:         0x0000,
		de:         0x00ab,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"1d": fuseTest{
		name:       "1d",
		af:         0x00aa,
		bc:         0x0000,
		de:         0x00a9,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"1e": fuseTest{
		name:       "1e",
		af:         0x0000,
		bc:         0x0000,
		de:         0x00ef,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"1f": fuseTest{
		name:       "1f",
		af:         0x00c5,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"20_1": fuseTest{
		name:       "20_1",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0042,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"20_2": fuseTest{
		name:       "20_2",
		af:         0x0040,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"21": fuseTest{
		name:       "21",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0xed28,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"22": fuseTest{
		name:    "22",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0xc64c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0xc3b0, 0x4c},
			[]int{0xc3b1, 0xc6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"23": fuseTest{
		name:       "23",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x9c4f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"24": fuseTest{
		name:       "24",
		af:         0x0020,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x7300,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"25": fuseTest{
		name:       "25",
		af:         0x00a2,
		bc:         0x0000,
		de:         0x0000,
		hl:         0xa400,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"26": fuseTest{
		name:       "26",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x3a00,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"27_1": fuseTest{
		name:       "27_1",
		af:         0x3423,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"27": fuseTest{
		name:       "27",
		af:         0x2530,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"28_1": fuseTest{
		name:       "28_1",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"28_2": fuseTest{
		name:       "28_2",
		af:         0x0040,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xff90,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"29": fuseTest{
		name:       "29",
		af:         0x0019,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x9bf4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"2a": fuseTest{
		name:       "2a",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0xdec4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    16,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"2b": fuseTest{
		name:       "2b",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x9e65,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"2c": fuseTest{
		name:       "2c",
		af:         0x0020,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0027,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"2d": fuseTest{
		name:       "2d",
		af:         0x0022,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0031,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"2e": fuseTest{
		name:       "2e",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0018,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"2f": fuseTest{
		name:       "2f",
		af:         0x7632,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"30_1": fuseTest{
		name:       "30_1",
		af:         0x0036,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0052,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"30_2": fuseTest{
		name:       "30_2",
		af:         0x0037,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"31": fuseTest{
		name:       "31",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x61d4,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"32": fuseTest{
		name:    "32",
		af:      0x0e00,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 13,
		memory: [][]int{
			[]int{0xadac, 0x0e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"33": fuseTest{
		name:       "33",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xa55b,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"34": fuseTest{
		name:    "34",
		af:      0x00a8,
		bc:      0x0000,
		de:      0x0000,
		hl:      0xfe1d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0xfe1d, 0xfe},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"35": fuseTest{
		name:    "35",
		af:      0x0082,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x470c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x470c, 0x81},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"36": fuseTest{
		name:    "36",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x7d29,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 10,
		memory: [][]int{
			[]int{0x7d29, 0x7c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"37_1": fuseTest{
		name:       "37_1",
		af:         0x00c5,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"37_2": fuseTest{
		name:       "37_2",
		af:         0xff29,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"37_3": fuseTest{
		name:       "37_3",
		af:         0xffed,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"37": fuseTest{
		name:       "37",
		af:         0x0001,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"38_1": fuseTest{
		name:       "38_1",
		af:         0x00b2,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"38_2": fuseTest{
		name:       "38_2",
		af:         0x00b3,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0068,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"39": fuseTest{
		name:       "39",
		af:         0x0030,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x35de,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xc534,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"3a": fuseTest{
		name:       "3a",
		af:         0x2800,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    13,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"3b": fuseTest{
		name:       "3b",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x9d35,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"3c": fuseTest{
		name:       "3c",
		af:         0xd090,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"3d": fuseTest{
		name:       "3d",
		af:         0xe9aa,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"3e": fuseTest{
		name:       "3e",
		af:         0xd600,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"3f": fuseTest{
		name:       "3f",
		af:         0x0050,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"40": fuseTest{
		name:       "40",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"41": fuseTest{
		name:       "41",
		af:         0x0200,
		bc:         0x9898,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"42": fuseTest{
		name:       "42",
		af:         0x0200,
		bc:         0x9098,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"43": fuseTest{
		name:       "43",
		af:         0x0200,
		bc:         0xd898,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"44": fuseTest{
		name:       "44",
		af:         0x0200,
		bc:         0xa198,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"45": fuseTest{
		name:       "45",
		af:         0x0200,
		bc:         0x6998,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"46": fuseTest{
		name:       "46",
		af:         0x0200,
		bc:         0x5098,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"47": fuseTest{
		name:       "47",
		af:         0x0200,
		bc:         0x0298,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"48": fuseTest{
		name:       "48",
		af:         0x0200,
		bc:         0xcfcf,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"49": fuseTest{
		name:       "49",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"4a": fuseTest{
		name:       "4a",
		af:         0x0200,
		bc:         0xcf90,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"4b": fuseTest{
		name:       "4b",
		af:         0x0200,
		bc:         0xcfd8,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"4c": fuseTest{
		name:       "4c",
		af:         0x0200,
		bc:         0xcfa1,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"4d": fuseTest{
		name:       "4d",
		af:         0x0200,
		bc:         0xcf69,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"4e": fuseTest{
		name:       "4e",
		af:         0x0200,
		bc:         0xcf50,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"4f": fuseTest{
		name:       "4f",
		af:         0x0200,
		bc:         0xcf02,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"50": fuseTest{
		name:       "50",
		af:         0x0200,
		bc:         0xcf98,
		de:         0xcfd8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"51": fuseTest{
		name:       "51",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x98d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"52": fuseTest{
		name:       "52",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"53": fuseTest{
		name:       "53",
		af:         0x0200,
		bc:         0xcf98,
		de:         0xd8d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"54": fuseTest{
		name:       "54",
		af:         0x0200,
		bc:         0xcf98,
		de:         0xa1d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"55": fuseTest{
		name:       "55",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x69d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"56": fuseTest{
		name:       "56",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x50d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"57": fuseTest{
		name:       "57",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x02d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"58": fuseTest{
		name:       "58",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90cf,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"59": fuseTest{
		name:       "59",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x9098,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"5a": fuseTest{
		name:       "5a",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x9090,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"5b": fuseTest{
		name:       "5b",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"5c": fuseTest{
		name:       "5c",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90a1,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"5d": fuseTest{
		name:       "5d",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x9069,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"5e": fuseTest{
		name:       "5e",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x9050,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"5f": fuseTest{
		name:       "5f",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x9002,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"60": fuseTest{
		name:       "60",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xcf69,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"61": fuseTest{
		name:       "61",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0x9869,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"62": fuseTest{
		name:       "62",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0x9069,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"63": fuseTest{
		name:       "63",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xd869,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"64": fuseTest{
		name:       "64",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"65": fuseTest{
		name:       "65",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0x6969,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"66": fuseTest{
		name:       "66",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0x5069,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"67": fuseTest{
		name:       "67",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0x0269,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"68": fuseTest{
		name:       "68",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa1cf,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"69": fuseTest{
		name:       "69",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa198,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"6a": fuseTest{
		name:       "6a",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa190,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"6b": fuseTest{
		name:       "6b",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa1d8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"6c": fuseTest{
		name:       "6c",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa1a1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"6d": fuseTest{
		name:       "6d",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"6e": fuseTest{
		name:       "6e",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa150,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"6f": fuseTest{
		name:       "6f",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa102,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"70": fuseTest{
		name:    "70",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0xcf},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"71": fuseTest{
		name:    "71",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0x98},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"72": fuseTest{
		name:    "72",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0x90},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"73": fuseTest{
		name:    "73",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0xd8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"74": fuseTest{
		name:    "74",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0xa1},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"75": fuseTest{
		name:    "75",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0x69},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"76": fuseTest{
		name:       "76",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       1,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"77": fuseTest{
		name:    "77",
		af:      0x0200,
		bc:      0xcf98,
		de:      0x90d8,
		hl:      0xa169,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 7,
		memory: [][]int{
			[]int{0xa169, 0x02},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"78": fuseTest{
		name:       "78",
		af:         0xcf00,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"79": fuseTest{
		name:       "79",
		af:         0x9800,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"7a": fuseTest{
		name:       "7a",
		af:         0x9000,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"7b": fuseTest{
		name:       "7b",
		af:         0xd800,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"7c": fuseTest{
		name:       "7c",
		af:         0xa100,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"7d": fuseTest{
		name:       "7d",
		af:         0x6900,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"7e": fuseTest{
		name:       "7e",
		af:         0x5000,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"7f": fuseTest{
		name:       "7f",
		af:         0x0200,
		bc:         0xcf98,
		de:         0x90d8,
		hl:         0xa169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"80": fuseTest{
		name:       "80",
		af:         0x0411,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"81": fuseTest{
		name:       "81",
		af:         0x3031,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"82": fuseTest{
		name:       "82",
		af:         0x1501,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"83": fuseTest{
		name:       "83",
		af:         0x0211,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"84": fuseTest{
		name:       "84",
		af:         0xd191,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"85": fuseTest{
		name:       "85",
		af:         0x9b89,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"86": fuseTest{
		name:       "86",
		af:         0x3e29,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"87": fuseTest{
		name:       "87",
		af:         0xeaa9,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"88": fuseTest{
		name:       "88",
		af:         0x0411,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"89": fuseTest{
		name:       "89",
		af:         0x3031,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"8a": fuseTest{
		name:       "8a",
		af:         0x1501,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"8b": fuseTest{
		name:       "8b",
		af:         0x0211,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"8c": fuseTest{
		name:       "8c",
		af:         0xd191,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"8d": fuseTest{
		name:       "8d",
		af:         0x9b89,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"8e": fuseTest{
		name:       "8e",
		af:         0x3e29,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"8f": fuseTest{
		name:       "8f",
		af:         0xeaa9,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"90": fuseTest{
		name:       "90",
		af:         0xe6b2,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"91": fuseTest{
		name:       "91",
		af:         0xbaba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"92": fuseTest{
		name:       "92",
		af:         0xd582,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"93": fuseTest{
		name:       "93",
		af:         0xe8ba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"94": fuseTest{
		name:       "94",
		af:         0x191a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"95": fuseTest{
		name:       "95",
		af:         0x4f1a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"96": fuseTest{
		name:       "96",
		af:         0xacba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"97": fuseTest{
		name:       "97",
		af:         0x0042,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"98": fuseTest{
		name:       "98",
		af:         0xe6b2,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"99": fuseTest{
		name:       "99",
		af:         0xbaba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"9a": fuseTest{
		name:       "9a",
		af:         0xd582,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"9b": fuseTest{
		name:       "9b",
		af:         0xe8ba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"9c": fuseTest{
		name:       "9c",
		af:         0x191a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"9d": fuseTest{
		name:       "9d",
		af:         0x4f1a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"9e": fuseTest{
		name:       "9e",
		af:         0xacba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"9f": fuseTest{
		name:       "9f",
		af:         0x0042,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a0": fuseTest{
		name:       "a0",
		af:         0x0514,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a1": fuseTest{
		name:       "a1",
		af:         0x3130,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a2": fuseTest{
		name:       "a2",
		af:         0x2030,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a3": fuseTest{
		name:       "a3",
		af:         0x0514,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a4": fuseTest{
		name:       "a4",
		af:         0xd494,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a5": fuseTest{
		name:       "a5",
		af:         0xa4b0,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a6": fuseTest{
		name:       "a6",
		af:         0x4114,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a7": fuseTest{
		name:       "a7",
		af:         0xf5b4,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a8": fuseTest{
		name:       "a8",
		af:         0xfaac,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"a9": fuseTest{
		name:       "a9",
		af:         0xce88,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"aa": fuseTest{
		name:       "aa",
		af:         0xd580,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ab": fuseTest{
		name:       "ab",
		af:         0xf8a8,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ac": fuseTest{
		name:       "ac",
		af:         0x2928,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ad": fuseTest{
		name:       "ad",
		af:         0x5304,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ae": fuseTest{
		name:       "ae",
		af:         0xbca8,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"af": fuseTest{
		name:       "af",
		af:         0x0044,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b0": fuseTest{
		name:       "b0",
		af:         0xffac,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b1": fuseTest{
		name:       "b1",
		af:         0xffac,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b2": fuseTest{
		name:       "b2",
		af:         0xf5a4,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b3": fuseTest{
		name:       "b3",
		af:         0xfda8,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b4": fuseTest{
		name:       "b4",
		af:         0xfda8,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b5": fuseTest{
		name:       "b5",
		af:         0xf7a0,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b6": fuseTest{
		name:       "b6",
		af:         0xfda8,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b7": fuseTest{
		name:       "b7",
		af:         0xf5a4,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b8": fuseTest{
		name:       "b8",
		af:         0xf59a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"b9": fuseTest{
		name:       "b9",
		af:         0xf5ba,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ba": fuseTest{
		name:       "ba",
		af:         0xf5a2,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"bb": fuseTest{
		name:       "bb",
		af:         0xf59a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"bc": fuseTest{
		name:       "bc",
		af:         0xf51a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"bd": fuseTest{
		name:       "bd",
		af:         0xf532,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"be": fuseTest{
		name:       "be",
		af:         0xf59a,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"bf": fuseTest{
		name:       "bf",
		af:         0xf562,
		bc:         0x0f3b,
		de:         0x200d,
		hl:         0xdca6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c0_1": fuseTest{
		name:       "c0_1",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c0_2": fuseTest{
		name:       "c0_2",
		af:         0x00d8,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c1": fuseTest{
		name:       "c1",
		af:         0x0000,
		bc:         0xe8ce,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x4145,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c2_1": fuseTest{
		name:       "c2_1",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c2_2": fuseTest{
		name:       "c2_2",
		af:         0x00c7,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c3": fuseTest{
		name:       "c3",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x7ced,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c4_1": fuseTest{
		name:    "c4_1",
		af:      0x000e,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c4_2": fuseTest{
		name:       "c4_2",
		af:         0x004e,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c5": fuseTest{
		name:    "c5",
		af:      0x53e3,
		bc:      0x1459,
		de:      0x775f,
		hl:      0x1a2f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xec10,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0xec10, 0x59},
			[]int{0xec11, 0x14},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c6": fuseTest{
		name:       "c6",
		af:         0x3939,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c7": fuseTest{
		name:    "c7",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0000,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c8_1": fuseTest{
		name:       "c8_1",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c8_2": fuseTest{
		name:       "c8_2",
		af:         0x00d8,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"c9": fuseTest{
		name:       "c9",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x8880,
		pc:         0x1136,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ca_1": fuseTest{
		name:       "ca_1",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ca_2": fuseTest{
		name:       "ca_2",
		af:         0x00c7,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb00": fuseTest{
		name:       "cb00",
		af:         0xda8d,
		bc:         0xc979,
		de:         0x552e,
		hl:         0xa806,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb01": fuseTest{
		name:       "cb01",
		af:         0x10a0,
		bc:         0xb3f2,
		de:         0xb480,
		hl:         0xef65,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb02": fuseTest{
		name:       "cb02",
		af:         0x2e09,
		bc:         0x9adf,
		de:         0x5d6e,
		hl:         0xa7f2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb03": fuseTest{
		name:       "cb03",
		af:         0x682c,
		bc:         0x9995,
		de:         0xde7e,
		hl:         0xca71,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb04": fuseTest{
		name:       "cb04",
		af:         0x8c88,
		bc:         0xbeea,
		de:         0x0ce4,
		hl:         0xceb0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb05": fuseTest{
		name:       "cb05",
		af:         0x3620,
		bc:         0xe19f,
		de:         0x78c9,
		hl:         0xcb64,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb06": fuseTest{
		name:    "cb06",
		af:      0x8aad,
		bc:      0xdb02,
		de:      0x8fb1,
		hl:      0x5b04,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x5b04, 0xa9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb07": fuseTest{
		name:       "cb07",
		af:         0xda88,
		bc:         0x19cf,
		de:         0x7259,
		hl:         0xdcaa,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb08": fuseTest{
		name:       "cb08",
		af:         0x80a1,
		bc:         0xe6b5,
		de:         0x818e,
		hl:         0x2ee2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb09": fuseTest{
		name:       "cb09",
		af:         0x182c,
		bc:         0x122e,
		de:         0xdd97,
		hl:         0x59c6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb0a": fuseTest{
		name:       "cb0a",
		af:         0x12ad,
		bc:         0x3ba1,
		de:         0xbb24,
		hl:         0x63ad,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb0b": fuseTest{
		name:       "cb0b",
		af:         0x7600,
		bc:         0x2abf,
		de:         0xb613,
		hl:         0x0289,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb0c": fuseTest{
		name:       "cb0c",
		af:         0x0e08,
		bc:         0x6fc5,
		de:         0x2f12,
		hl:         0x1ad9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb0d": fuseTest{
		name:       "cb0d",
		af:         0x630c,
		bc:         0x95a3,
		de:         0xfcd2,
		hl:         0x514d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb0e": fuseTest{
		name:    "cb0e",
		af:      0xfc2c,
		bc:      0xadf9,
		de:      0x4925,
		hl:      0x543e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x543e, 0x69},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb0f": fuseTest{
		name:       "cb0f",
		af:         0xe1a5,
		bc:         0x18f3,
		de:         0x41b8,
		hl:         0x070b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb10": fuseTest{
		name:       "cb10",
		af:         0xf8ad,
		bc:         0xb825,
		de:         0x33b3,
		hl:         0x0d74,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb11": fuseTest{
		name:       "cb11",
		af:         0x65ac,
		bc:         0xe2b8,
		de:         0x4b8a,
		hl:         0xed42,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb12": fuseTest{
		name:       "cb12",
		af:         0x770c,
		bc:         0x1384,
		de:         0x1e50,
		hl:         0x29c6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb13": fuseTest{
		name:       "cb13",
		af:         0xce04,
		bc:         0x9f17,
		de:         0xe150,
		hl:         0x3ed7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb14": fuseTest{
		name:       "cb14",
		af:         0xb2a8,
		bc:         0x541a,
		de:         0x60c7,
		hl:         0xf89a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb15": fuseTest{
		name:       "cb15",
		af:         0x2d81,
		bc:         0xc1df,
		de:         0x6eab,
		hl:         0x03c4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb16": fuseTest{
		name:    "cb16",
		af:      0x3681,
		bc:      0x3b53,
		de:      0x1a4a,
		hl:      0x684e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x684e, 0x86},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb17": fuseTest{
		name:       "cb17",
		af:         0xa8a8,
		bc:         0xd090,
		de:         0xf60d,
		hl:         0x0fa2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb18": fuseTest{
		name:       "cb18",
		af:         0x8624,
		bc:         0x6358,
		de:         0x755f,
		hl:         0x9596,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb19": fuseTest{
		name:       "cb19",
		af:         0x960d,
		bc:         0xbe59,
		de:         0x7c22,
		hl:         0x71c8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb1a": fuseTest{
		name:       "cb1a",
		af:         0x3928,
		bc:         0x882f,
		de:         0x2a3b,
		hl:         0x5279,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb1b": fuseTest{
		name:       "cb1b",
		af:         0x9e24,
		bc:         0xb338,
		de:         0x8736,
		hl:         0xe8b4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb1c": fuseTest{
		name:       "cb1c",
		af:         0x4b0d,
		bc:         0xb555,
		de:         0x238f,
		hl:         0x181d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb1d": fuseTest{
		name:       "cb1d",
		af:         0x212d,
		bc:         0x3d7e,
		de:         0x5e39,
		hl:         0xe428,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb1e": fuseTest{
		name:    "cb1e",
		af:      0x5e0d,
		bc:      0x66b9,
		de:      0x80dc,
		hl:      0x00ef,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x00ef, 0x48},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb1f": fuseTest{
		name:       "cb1f",
		af:         0x7621,
		bc:         0xb838,
		de:         0x8e18,
		hl:         0xace7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb20": fuseTest{
		name:       "cb20",
		af:         0xc708,
		bc:         0x0897,
		de:         0xd72b,
		hl:         0xccb6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb21": fuseTest{
		name:       "cb21",
		af:         0x22ad,
		bc:         0x5ce8,
		de:         0x938e,
		hl:         0x37a8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb22": fuseTest{
		name:       "cb22",
		af:         0x8589,
		bc:         0x0950,
		de:         0xcee8,
		hl:         0x0641,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb23": fuseTest{
		name:       "cb23",
		af:         0x21a5,
		bc:         0x2a7c,
		de:         0x37a0,
		hl:         0xaa59,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb24": fuseTest{
		name:       "cb24",
		af:         0xfb09,
		bc:         0xb9de,
		de:         0x7014,
		hl:         0x08b6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb25": fuseTest{
		name:       "cb25",
		af:         0x152d,
		bc:         0x6bbc,
		de:         0x894e,
		hl:         0x8578,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb26": fuseTest{
		name:    "cb26",
		af:      0x0a89,
		bc:      0x372e,
		de:      0xe315,
		hl:      0x283a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x283a, 0xdc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb27": fuseTest{
		name:       "cb27",
		af:         0x7e2d,
		bc:         0xbdba,
		de:         0x67ab,
		hl:         0x5ea2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb28": fuseTest{
		name:       "cb28",
		af:         0xc000,
		bc:         0x0235,
		de:         0x3e0f,
		hl:         0x021b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb29": fuseTest{
		name:       "cb29",
		af:         0x0624,
		bc:         0xf121,
		de:         0x6ada,
		hl:         0xc306,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb2a": fuseTest{
		name:       "cb2a",
		af:         0x302d,
		bc:         0xec3a,
		de:         0x3f7d,
		hl:         0x3473,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb2b": fuseTest{
		name:       "cb2b",
		af:         0xe0ac,
		bc:         0xccf0,
		de:         0xbbed,
		hl:         0xb78a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb2c": fuseTest{
		name:       "cb2c",
		af:         0x5b0c,
		bc:         0x25c0,
		de:         0x996d,
		hl:         0x0f7b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb2d": fuseTest{
		name:       "cb2d",
		af:         0x5ea4,
		bc:         0xc51b,
		de:         0x58e3,
		hl:         0x78f5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb2e": fuseTest{
		name:    "cb2e",
		af:      0x3989,
		bc:      0xa2cd,
		de:      0x0629,
		hl:      0x24bf,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x24bf, 0xda},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb2f": fuseTest{
		name:       "cb2f",
		af:         0xd580,
		bc:         0xa194,
		de:         0xd0e3,
		hl:         0x5c65,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb30": fuseTest{
		name:       "cb30",
		af:         0xcda4,
		bc:         0xf581,
		de:         0xd67b,
		hl:         0x656b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb31": fuseTest{
		name:       "cb31",
		af:         0x28a5,
		bc:         0xe7f5,
		de:         0x6d8c,
		hl:         0x75a4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb32": fuseTest{
		name:       "cb32",
		af:         0x13ad,
		bc:         0x3f36,
		de:         0xed08,
		hl:         0x5e56,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb33": fuseTest{
		name:       "cb33",
		af:         0xd588,
		bc:         0x9720,
		de:         0x7689,
		hl:         0x038f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb34": fuseTest{
		name:       "cb34",
		af:         0x12a1,
		bc:         0x77f6,
		de:         0x0206,
		hl:         0xf738,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb35": fuseTest{
		name:       "cb35",
		af:         0x3c84,
		bc:         0xfd68,
		de:         0xea91,
		hl:         0x78c3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb36": fuseTest{
		name:    "cb36",
		af:      0x8aa1,
		bc:      0x1185,
		de:      0x1dde,
		hl:      0x6d38,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x6d38, 0xe3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb37": fuseTest{
		name:       "cb37",
		af:         0x8784,
		bc:         0xd7bc,
		de:         0x9133,
		hl:         0x6e56,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb38": fuseTest{
		name:       "cb38",
		af:         0xdf28,
		bc:         0x3e1b,
		de:         0x9f9f,
		hl:         0x4ff2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb39": fuseTest{
		name:       "cb39",
		af:         0x6600,
		bc:         0xb701,
		de:         0x14f5,
		hl:         0x3c17,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb3a": fuseTest{
		name:       "cb3a",
		af:         0xd124,
		bc:         0x5c5f,
		de:         0x722e,
		hl:         0xf1b1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb3b": fuseTest{
		name:       "cb3b",
		af:         0xb224,
		bc:         0x38c8,
		de:         0xa530,
		hl:         0x7419,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb3c": fuseTest{
		name:       "cb3c",
		af:         0x7800,
		bc:         0xcfae,
		de:         0x66d8,
		hl:         0x15d8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb3d": fuseTest{
		name:       "cb3d",
		af:         0xe625,
		bc:         0xdcda,
		de:         0x06aa,
		hl:         0x4666,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb3e": fuseTest{
		name:    "cb3e",
		af:      0xa904,
		bc:      0x6a34,
		de:      0xe8d0,
		hl:      0xa96c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0xa96c, 0x50},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb3f": fuseTest{
		name:       "cb3f",
		af:         0x782d,
		bc:         0xceea,
		de:         0x721e,
		hl:         0x77f0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb40": fuseTest{
		name:       "cb40",
		af:         0x9e7c,
		bc:         0xbcb2,
		de:         0xefaa,
		hl:         0x505f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb41": fuseTest{
		name:       "cb41",
		af:         0x9e10,
		bc:         0x1b43,
		de:         0x954e,
		hl:         0x7be9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb42": fuseTest{
		name:       "cb42",
		af:         0xf238,
		bc:         0xdd12,
		de:         0x7d4f,
		hl:         0x551f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb43": fuseTest{
		name:       "cb43",
		af:         0xad54,
		bc:         0xc3b3,
		de:         0xf1d0,
		hl:         0xbab4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb44": fuseTest{
		name:       "cb44",
		af:         0xb718,
		bc:         0xc829,
		de:         0x27e3,
		hl:         0x5b92,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb45": fuseTest{
		name:       "cb45",
		af:         0x7718,
		bc:         0x68ee,
		de:         0x0c77,
		hl:         0x409b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb46": fuseTest{
		name:       "cb46",
		af:         0x7210,
		bc:         0x7ae3,
		de:         0xa11e,
		hl:         0x6131,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb47_1": fuseTest{
		name:       "cb47_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb47": fuseTest{
		name:       "cb47",
		af:         0x1054,
		bc:         0xd8ca,
		de:         0xe2c4,
		hl:         0x8a8c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb48": fuseTest{
		name:       "cb48",
		af:         0xa930,
		bc:         0x6264,
		de:         0xe833,
		hl:         0x6de0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb49": fuseTest{
		name:       "cb49",
		af:         0x6c30,
		bc:         0xd0f7,
		de:         0x1db7,
		hl:         0xa040,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4a": fuseTest{
		name:       "cb4a",
		af:         0x4f18,
		bc:         0xf04c,
		de:         0x5b29,
		hl:         0x77a4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4b": fuseTest{
		name:       "cb4b",
		af:         0x5518,
		bc:         0x9848,
		de:         0x095f,
		hl:         0x40ca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4c": fuseTest{
		name:       "cb4c",
		af:         0x887c,
		bc:         0x0521,
		de:         0xbf31,
		hl:         0x6d5d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4d": fuseTest{
		name:       "cb4d",
		af:         0xf95c,
		bc:         0x27d0,
		de:         0x0f7e,
		hl:         0x158d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4e": fuseTest{
		name:       "cb4e",
		af:         0x2618,
		bc:         0x9207,
		de:         0x459a,
		hl:         0xada3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4f_1": fuseTest{
		name:       "cb4f_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb4f": fuseTest{
		name:       "cb4f",
		af:         0x1710,
		bc:         0x2dc1,
		de:         0xaca2,
		hl:         0x0bcc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb50": fuseTest{
		name:       "cb50",
		af:         0x2330,
		bc:         0x2749,
		de:         0x1012,
		hl:         0x84d2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb51": fuseTest{
		name:       "cb51",
		af:         0x225c,
		bc:         0xb7db,
		de:         0xe19d,
		hl:         0xaafc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb52": fuseTest{
		name:       "cb52",
		af:         0x8b74,
		bc:         0xff7a,
		de:         0xb0ff,
		hl:         0xac44,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb53": fuseTest{
		name:       "cb53",
		af:         0x6030,
		bc:         0x31a1,
		de:         0xa4f4,
		hl:         0x7c75,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb54": fuseTest{
		name:       "cb54",
		af:         0x385c,
		bc:         0x7ccc,
		de:         0x89cc,
		hl:         0x1999,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb55": fuseTest{
		name:       "cb55",
		af:         0xf95c,
		bc:         0x1f79,
		de:         0x19cd,
		hl:         0xfb4b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb56": fuseTest{
		name:       "cb56",
		af:         0x1554,
		bc:         0x2bfe,
		de:         0xe3b5,
		hl:         0xbbf9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb57_1": fuseTest{
		name:       "cb57_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb57": fuseTest{
		name:       "cb57",
		af:         0x6630,
		bc:         0xaf32,
		de:         0x532a,
		hl:         0xda50,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb58": fuseTest{
		name:       "cb58",
		af:         0x5018,
		bc:         0x1aee,
		de:         0x2e47,
		hl:         0x1479,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb59": fuseTest{
		name:       "cb59",
		af:         0x7238,
		bc:         0x5e68,
		de:         0xff28,
		hl:         0x2075,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5a": fuseTest{
		name:       "cb5a",
		af:         0xeb54,
		bc:         0xfea7,
		de:         0x17d1,
		hl:         0xd99b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5b": fuseTest{
		name:       "cb5b",
		af:         0x6b74,
		bc:         0x6f2c,
		de:         0x3fe3,
		hl:         0x1691,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5c": fuseTest{
		name:       "cb5c",
		af:         0x3354,
		bc:         0xa7e7,
		de:         0x2077,
		hl:         0x13e9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5d": fuseTest{
		name:       "cb5d",
		af:         0xc118,
		bc:         0xafcc,
		de:         0xc8b1,
		hl:         0xee49,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5e": fuseTest{
		name:       "cb5e",
		af:         0x3038,
		bc:         0xad43,
		de:         0x16c1,
		hl:         0x349a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5f_1": fuseTest{
		name:       "cb5f_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb5f": fuseTest{
		name:       "cb5f",
		af:         0x8c18,
		bc:         0x1b67,
		de:         0x2314,
		hl:         0x6133,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb60": fuseTest{
		name:       "cb60",
		af:         0x9930,
		bc:         0x34b5,
		de:         0x0fd8,
		hl:         0x5273,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb61": fuseTest{
		name:       "cb61",
		af:         0xd118,
		bc:         0x219f,
		de:         0x3bb4,
		hl:         0x7c44,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb62": fuseTest{
		name:       "cb62",
		af:         0xaf54,
		bc:         0xbdf8,
		de:         0xc536,
		hl:         0x8cc5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb63": fuseTest{
		name:       "cb63",
		af:         0x2a74,
		bc:         0x5e16,
		de:         0xf627,
		hl:         0x84ca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb64": fuseTest{
		name:       "cb64",
		af:         0xa97c,
		bc:         0xa365,
		de:         0xc00b,
		hl:         0xea94,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb65": fuseTest{
		name:       "cb65",
		af:         0x1838,
		bc:         0x8d58,
		de:         0x4256,
		hl:         0x427a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb66": fuseTest{
		name:       "cb66",
		af:         0x4c10,
		bc:         0x3ef7,
		de:         0xe544,
		hl:         0xa44f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb67_1": fuseTest{
		name:       "cb67_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb67": fuseTest{
		name:       "cb67",
		af:         0x8654,
		bc:         0x5e92,
		de:         0x2986,
		hl:         0x394d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb68": fuseTest{
		name:       "cb68",
		af:         0xd75c,
		bc:         0x0f6a,
		de:         0x18a6,
		hl:         0xddd2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb69": fuseTest{
		name:       "cb69",
		af:         0xda5c,
		bc:         0x691b,
		de:         0x7c79,
		hl:         0x1dba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6a": fuseTest{
		name:       "cb6a",
		af:         0x2254,
		bc:         0x13e8,
		de:         0x86d4,
		hl:         0x4e09,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6b": fuseTest{
		name:       "cb6b",
		af:         0xaf30,
		bc:         0x5123,
		de:         0x7635,
		hl:         0x1ca9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6c": fuseTest{
		name:       "cb6c",
		af:         0x4354,
		bc:         0xfaa6,
		de:         0xabc2,
		hl:         0x5605,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6d": fuseTest{
		name:       "cb6d",
		af:         0x7f38,
		bc:         0xf099,
		de:         0xd435,
		hl:         0xd9ad,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6e": fuseTest{
		name:       "cb6e",
		af:         0x4a30,
		bc:         0x08c9,
		de:         0x8177,
		hl:         0xd8ba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6f_1": fuseTest{
		name:       "cb6f_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb6f": fuseTest{
		name:       "cb6f",
		af:         0xa130,
		bc:         0x8c80,
		de:         0x4678,
		hl:         0x4d34,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb70": fuseTest{
		name:       "cb70",
		af:         0x1954,
		bc:         0x958a,
		de:         0x5dab,
		hl:         0xf913,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb71": fuseTest{
		name:       "cb71",
		af:         0x3d18,
		bc:         0x095e,
		de:         0xd6df,
		hl:         0x42fe,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb72": fuseTest{
		name:       "cb72",
		af:         0xa518,
		bc:         0xc0bf,
		de:         0x4c8d,
		hl:         0xad11,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb73": fuseTest{
		name:       "cb73",
		af:         0xf238,
		bc:         0x49a6,
		de:         0xb279,
		hl:         0x2ecc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb74": fuseTest{
		name:       "cb74",
		af:         0x055c,
		bc:         0x445e,
		de:         0x05e9,
		hl:         0x983d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb75": fuseTest{
		name:       "cb75",
		af:         0x6b5c,
		bc:         0x83c6,
		de:         0x635a,
		hl:         0xd18d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb76": fuseTest{
		name:       "cb76",
		af:         0xf85c,
		bc:         0x3057,
		de:         0x3629,
		hl:         0xbc71,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb77_1": fuseTest{
		name:       "cb77_1",
		af:         0xff38,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb77": fuseTest{
		name:       "cb77",
		af:         0x9254,
		bc:         0xd6f8,
		de:         0x5100,
		hl:         0x736d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb78": fuseTest{
		name:       "cb78",
		af:         0x725c,
		bc:         0x1cf8,
		de:         0x8d2b,
		hl:         0xc76a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb79": fuseTest{
		name:       "cb79",
		af:         0xa898,
		bc:         0x809e,
		de:         0x1124,
		hl:         0x39e8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7a": fuseTest{
		name:       "cb7a",
		af:         0x5874,
		bc:         0x7d24,
		de:         0x63e1,
		hl:         0xd9af,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7b": fuseTest{
		name:       "cb7b",
		af:         0x03b8,
		bc:         0x50ab,
		de:         0x05bd,
		hl:         0x6bd0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7c": fuseTest{
		name:       "cb7c",
		af:         0xad54,
		bc:         0xf77b,
		de:         0x55ae,
		hl:         0x063b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7d": fuseTest{
		name:       "cb7d",
		af:         0x8298,
		bc:         0xb792,
		de:         0x38cb,
		hl:         0x5f9b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7e": fuseTest{
		name:       "cb7e",
		af:         0x4290,
		bc:         0x3b91,
		de:         0xf59c,
		hl:         0xa25e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7f_1": fuseTest{
		name:       "cb7f_1",
		af:         0xffb8,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb7f": fuseTest{
		name:       "cb7f",
		af:         0x6a7c,
		bc:         0x84ec,
		de:         0xcf4e,
		hl:         0x185b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb80": fuseTest{
		name:       "cb80",
		af:         0x8f00,
		bc:         0x702f,
		de:         0x17bd,
		hl:         0xa706,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb81": fuseTest{
		name:       "cb81",
		af:         0xae00,
		bc:         0x947e,
		de:         0x7153,
		hl:         0x6616,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb82": fuseTest{
		name:       "cb82",
		af:         0x8100,
		bc:         0xbed2,
		de:         0xc619,
		hl:         0x4572,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb83": fuseTest{
		name:       "cb83",
		af:         0xe600,
		bc:         0x63a2,
		de:         0xccf6,
		hl:         0xae9a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb84": fuseTest{
		name:       "cb84",
		af:         0xce00,
		bc:         0xe0cc,
		de:         0xd305,
		hl:         0xd6c0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb85": fuseTest{
		name:       "cb85",
		af:         0xf300,
		bc:         0xed79,
		de:         0x9db7,
		hl:         0xdda0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb86": fuseTest{
		name:       "cb86",
		af:         0x2a00,
		bc:         0xb0b9,
		de:         0x9426,
		hl:         0x1b48,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb87": fuseTest{
		name:       "cb87",
		af:         0x1000,
		bc:         0x86dc,
		de:         0x1798,
		hl:         0xdfc5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb88": fuseTest{
		name:       "cb88",
		af:         0xe300,
		bc:         0x8821,
		de:         0xe33e,
		hl:         0x674d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb89": fuseTest{
		name:       "cb89",
		af:         0x6000,
		bc:         0xd184,
		de:         0xc5b6,
		hl:         0x1bd7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb8a": fuseTest{
		name:       "cb8a",
		af:         0x3e00,
		bc:         0x5fcd,
		de:         0x0938,
		hl:         0xb98e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb8b": fuseTest{
		name:       "cb8b",
		af:         0x6500,
		bc:         0x040e,
		de:         0x103d,
		hl:         0x4a07,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb8c": fuseTest{
		name:       "cb8c",
		af:         0xf800,
		bc:         0x6d27,
		de:         0x9bdf,
		hl:         0xd8ef,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb8d": fuseTest{
		name:       "cb8d",
		af:         0x3e00,
		bc:         0x5469,
		de:         0x2c28,
		hl:         0xbd70,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb8e": fuseTest{
		name:       "cb8e",
		af:         0x1f00,
		bc:         0x140b,
		de:         0xb492,
		hl:         0x63a7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb8f": fuseTest{
		name:       "cb8f",
		af:         0x2500,
		bc:         0xc522,
		de:         0xca46,
		hl:         0x1c1a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb90": fuseTest{
		name:       "cb90",
		af:         0x5700,
		bc:         0x595c,
		de:         0x4f0a,
		hl:         0xc73c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb91": fuseTest{
		name:       "cb91",
		af:         0x5e00,
		bc:         0x8f22,
		de:         0xa735,
		hl:         0x97e0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb92": fuseTest{
		name:       "cb92",
		af:         0x3300,
		bc:         0x7d9f,
		de:         0x83d0,
		hl:         0x83d0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb93": fuseTest{
		name:       "cb93",
		af:         0xc200,
		bc:         0x4e05,
		de:         0xb3f8,
		hl:         0x2234,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb94": fuseTest{
		name:       "cb94",
		af:         0xee00,
		bc:         0x8f4b,
		de:         0x2831,
		hl:         0xd2a6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb95": fuseTest{
		name:       "cb95",
		af:         0x3c00,
		bc:         0x6af2,
		de:         0xb25d,
		hl:         0x36fb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb96": fuseTest{
		name:       "cb96",
		af:         0x7600,
		bc:         0xb027,
		de:         0xd0a5,
		hl:         0x3324,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb97": fuseTest{
		name:       "cb97",
		af:         0x1200,
		bc:         0xad09,
		de:         0x7902,
		hl:         0x97bc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb98": fuseTest{
		name:       "cb98",
		af:         0x3400,
		bc:         0xb61c,
		de:         0x771d,
		hl:         0x5d5e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb99": fuseTest{
		name:       "cb99",
		af:         0x5100,
		bc:         0x65b6,
		de:         0x1359,
		hl:         0x8bec,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb9a": fuseTest{
		name:       "cb9a",
		af:         0x6400,
		bc:         0x976d,
		de:         0x4425,
		hl:         0xdcb2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb9b": fuseTest{
		name:       "cb9b",
		af:         0xa100,
		bc:         0xb58a,
		de:         0xd264,
		hl:         0x2bd6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb9c": fuseTest{
		name:       "cb9c",
		af:         0xd800,
		bc:         0x63d6,
		de:         0xac7b,
		hl:         0xc7a0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb9d": fuseTest{
		name:       "cb9d",
		af:         0x0d00,
		bc:         0xd840,
		de:         0x0810,
		hl:         0x0800,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb9e": fuseTest{
		name:    "cb9e",
		af:      0x3b00,
		bc:      0xebbf,
		de:      0x9434,
		hl:      0x3a65,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x3a65, 0x22},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cb9f": fuseTest{
		name:       "cb9f",
		af:         0xb200,
		bc:         0xd1de,
		de:         0xf991,
		hl:         0x72f6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba0": fuseTest{
		name:       "cba0",
		af:         0xfa00,
		bc:         0xc669,
		de:         0x71e1,
		hl:         0xc80d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba1": fuseTest{
		name:       "cba1",
		af:         0x8200,
		bc:         0x75e4,
		de:         0xa0de,
		hl:         0xd0ba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba2": fuseTest{
		name:       "cba2",
		af:         0xdd00,
		bc:         0x2b0d,
		de:         0x4554,
		hl:         0x6fc0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba3": fuseTest{
		name:       "cba3",
		af:         0x2200,
		bc:         0x2f0d,
		de:         0x4d2c,
		hl:         0x6666,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba4": fuseTest{
		name:       "cba4",
		af:         0xd600,
		bc:         0xd8ed,
		de:         0x9cd4,
		hl:         0x8bb1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba5": fuseTest{
		name:       "cba5",
		af:         0xb400,
		bc:         0xb393,
		de:         0x3e42,
		hl:         0x88ca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba6": fuseTest{
		name:       "cba6",
		af:         0x0a00,
		bc:         0x4c34,
		de:         0xf5a7,
		hl:         0xe70d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba7": fuseTest{
		name:       "cba7",
		af:         0x4500,
		bc:         0xaf61,
		de:         0x569a,
		hl:         0xc77b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba8": fuseTest{
		name:       "cba8",
		af:         0x6400,
		bc:         0xd269,
		de:         0xbae4,
		hl:         0xc9e7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cba9": fuseTest{
		name:       "cba9",
		af:         0xe400,
		bc:         0x7ad4,
		de:         0xbf0a,
		hl:         0xce0b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbaa": fuseTest{
		name:       "cbaa",
		af:         0xcd00,
		bc:         0xd249,
		de:         0x4159,
		hl:         0xfed5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbab": fuseTest{
		name:       "cbab",
		af:         0xac00,
		bc:         0x939a,
		de:         0x5d9b,
		hl:         0x0812,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbac": fuseTest{
		name:       "cbac",
		af:         0x2400,
		bc:         0x8a7d,
		de:         0x2cac,
		hl:         0xdfaa,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbad": fuseTest{
		name:       "cbad",
		af:         0x6f00,
		bc:         0x5ffb,
		de:         0x2360,
		hl:         0xae15,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbae": fuseTest{
		name:    "cbae",
		af:      0x5a00,
		bc:      0xaa17,
		de:      0x12f3,
		hl:      0x190e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x190e, 0x46},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbaf": fuseTest{
		name:       "cbaf",
		af:         0xdc00,
		bc:         0xbb3f,
		de:         0x8bb6,
		hl:         0x5877,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb0": fuseTest{
		name:       "cbb0",
		af:         0xb900,
		bc:         0x3a79,
		de:         0x1aaa,
		hl:         0xc3ba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb1": fuseTest{
		name:       "cbb1",
		af:         0x4900,
		bc:         0x63a4,
		de:         0xa544,
		hl:         0x1190,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb2": fuseTest{
		name:       "cbb2",
		af:         0x4d00,
		bc:         0x2b03,
		de:         0x2b23,
		hl:         0x6ff5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb3": fuseTest{
		name:       "cbb3",
		af:         0x8700,
		bc:         0x857a,
		de:         0xe98b,
		hl:         0x5cb1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb4": fuseTest{
		name:       "cbb4",
		af:         0x2b00,
		bc:         0xb73e,
		de:         0x79c9,
		hl:         0xa1bb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb5": fuseTest{
		name:       "cbb5",
		af:         0x9b00,
		bc:         0xd879,
		de:         0x2ec9,
		hl:         0x4bba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb6": fuseTest{
		name:       "cbb6",
		af:         0x8600,
		bc:         0x89bf,
		de:         0xde4a,
		hl:         0x4fab,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb7": fuseTest{
		name:       "cbb7",
		af:         0x2200,
		bc:         0xfb8a,
		de:         0x3d6e,
		hl:         0xd4a2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb8": fuseTest{
		name:       "cbb8",
		af:         0xd000,
		bc:         0x37c6,
		de:         0x225a,
		hl:         0xd249,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbb9": fuseTest{
		name:       "cbb9",
		af:         0xa500,
		bc:         0x1b4a,
		de:         0xd584,
		hl:         0x5dee,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbba": fuseTest{
		name:       "cbba",
		af:         0x6300,
		bc:         0xa5fe,
		de:         0x742b,
		hl:         0x34c9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbbb": fuseTest{
		name:       "cbbb",
		af:         0x1200,
		bc:         0xf661,
		de:         0xaa4f,
		hl:         0xcb30,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbbc": fuseTest{
		name:       "cbbc",
		af:         0x9800,
		bc:         0xadc3,
		de:         0x0b29,
		hl:         0x7b6e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbbd": fuseTest{
		name:       "cbbd",
		af:         0xd600,
		bc:         0xa6e1,
		de:         0x8813,
		hl:         0x1038,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbbe": fuseTest{
		name:    "cbbe",
		af:      0xca00,
		bc:      0xff64,
		de:      0x1218,
		hl:      0x77d5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x77d5, 0x6a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbbf": fuseTest{
		name:       "cbbf",
		af:         0x6800,
		bc:         0x4845,
		de:         0x690a,
		hl:         0x15de,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc0": fuseTest{
		name:       "cbc0",
		af:         0xe300,
		bc:         0xef71,
		de:         0xbffb,
		hl:         0xb3a1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc1": fuseTest{
		name:       "cbc1",
		af:         0x3200,
		bc:         0x32a1,
		de:         0x59ab,
		hl:         0x3343,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc2": fuseTest{
		name:       "cbc2",
		af:         0xc700,
		bc:         0xb159,
		de:         0xc123,
		hl:         0xe1f3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc3": fuseTest{
		name:       "cbc3",
		af:         0x0400,
		bc:         0xb463,
		de:         0xc211,
		hl:         0x8f3a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc4": fuseTest{
		name:       "cbc4",
		af:         0x7e00,
		bc:         0x545a,
		de:         0x6ecf,
		hl:         0x5976,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc5": fuseTest{
		name:       "cbc5",
		af:         0x4000,
		bc:         0xc617,
		de:         0x079c,
		hl:         0x4107,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc6": fuseTest{
		name:    "cbc6",
		af:      0xb800,
		bc:      0x0373,
		de:      0xb807,
		hl:      0xf0be,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0xf0be, 0x9d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc7": fuseTest{
		name:       "cbc7",
		af:         0x7700,
		bc:         0x3681,
		de:         0x9b55,
		hl:         0x583f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc8": fuseTest{
		name:       "cbc8",
		af:         0x7d00,
		bc:         0xa772,
		de:         0x8682,
		hl:         0x7cf3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbc9": fuseTest{
		name:       "cbc9",
		af:         0x0b00,
		bc:         0x67ee,
		de:         0x30e0,
		hl:         0x72db,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbca": fuseTest{
		name:       "cbca",
		af:         0x9c00,
		bc:         0x9517,
		de:         0xcfbb,
		hl:         0xfbc7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbcb": fuseTest{
		name:       "cbcb",
		af:         0xe800,
		bc:         0x0f3d,
		de:         0x336f,
		hl:         0xf70d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbcc": fuseTest{
		name:       "cbcc",
		af:         0xfb00,
		bc:         0x7981,
		de:         0x0bbb,
		hl:         0x1afd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbcd": fuseTest{
		name:       "cbcd",
		af:         0x5500,
		bc:         0x5e78,
		de:         0xbf34,
		hl:         0x2602,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbce": fuseTest{
		name:       "cbce",
		af:         0xd500,
		bc:         0xa111,
		de:         0xcb2a,
		hl:         0x8ec6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbcf": fuseTest{
		name:       "cbcf",
		af:         0xa200,
		bc:         0x6baf,
		de:         0x98b2,
		hl:         0x98a0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd0": fuseTest{
		name:       "cbd0",
		af:         0x2300,
		bc:         0x7fcb,
		de:         0x02e7,
		hl:         0x1724,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd1": fuseTest{
		name:       "cbd1",
		af:         0x5300,
		bc:         0x581f,
		de:         0xb775,
		hl:         0x47f4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd2": fuseTest{
		name:       "cbd2",
		af:         0x6900,
		bc:         0xc147,
		de:         0xb79c,
		hl:         0x7528,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd3": fuseTest{
		name:       "cbd3",
		af:         0xae00,
		bc:         0xbbc4,
		de:         0xce56,
		hl:         0x5fba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd4": fuseTest{
		name:       "cbd4",
		af:         0xd800,
		bc:         0x6e1e,
		de:         0xaf6f,
		hl:         0xbf2e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd5": fuseTest{
		name:       "cbd5",
		af:         0x8400,
		bc:         0xa19a,
		de:         0xd2fd,
		hl:         0x8a77,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd6": fuseTest{
		name:       "cbd6",
		af:         0xa900,
		bc:         0xf5f3,
		de:         0x2180,
		hl:         0x6029,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd7": fuseTest{
		name:       "cbd7",
		af:         0xb500,
		bc:         0xc008,
		de:         0x8425,
		hl:         0x290a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd8": fuseTest{
		name:       "cbd8",
		af:         0x8b00,
		bc:         0x09c4,
		de:         0xddf3,
		hl:         0x6d7e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbd9": fuseTest{
		name:       "cbd9",
		af:         0x3e00,
		bc:         0x3e3e,
		de:         0x30ec,
		hl:         0xefc6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbda": fuseTest{
		name:       "cbda",
		af:         0xd000,
		bc:         0x3e8f,
		de:         0x28fe,
		hl:         0x1c87,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbdb": fuseTest{
		name:       "cbdb",
		af:         0x1200,
		bc:         0x977a,
		de:         0x8c49,
		hl:         0xbc48,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbdc": fuseTest{
		name:       "cbdc",
		af:         0x8d00,
		bc:         0x05de,
		de:         0xf8d3,
		hl:         0xb925,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbdd": fuseTest{
		name:       "cbdd",
		af:         0xc300,
		bc:         0x08a9,
		de:         0x2bc8,
		hl:         0x5b9f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbde": fuseTest{
		name:    "cbde",
		af:      0x1900,
		bc:      0x900f,
		de:      0xd572,
		hl:      0xba03,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0xba03, 0x9b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbdf": fuseTest{
		name:       "cbdf",
		af:         0x6f00,
		bc:         0x2745,
		de:         0x7e3d,
		hl:         0x0fa1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe0": fuseTest{
		name:       "cbe0",
		af:         0x3e00,
		bc:         0xd633,
		de:         0x9897,
		hl:         0x3744,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe1": fuseTest{
		name:       "cbe1",
		af:         0x7d00,
		bc:         0x50b6,
		de:         0x0136,
		hl:         0x5334,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe2": fuseTest{
		name:       "cbe2",
		af:         0xd400,
		bc:         0x6b45,
		de:         0xb192,
		hl:         0x3a4c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe3": fuseTest{
		name:       "cbe3",
		af:         0x3b00,
		bc:         0xd29c,
		de:         0x05f0,
		hl:         0x2e78,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe4": fuseTest{
		name:       "cbe4",
		af:         0x1e00,
		bc:         0x7d5e,
		de:         0x846d,
		hl:         0x1978,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe5": fuseTest{
		name:       "cbe5",
		af:         0xca00,
		bc:         0xdf0d,
		de:         0xd588,
		hl:         0xb49f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe6": fuseTest{
		name:       "cbe6",
		af:         0xb300,
		bc:         0x52c2,
		de:         0xdbfe,
		hl:         0x9f9b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe7": fuseTest{
		name:       "cbe7",
		af:         0x9e00,
		bc:         0xcf02,
		de:         0x67ef,
		hl:         0xf2e0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe8": fuseTest{
		name:       "cbe8",
		af:         0x7100,
		bc:         0xbb18,
		de:         0x66ec,
		hl:         0x4a05,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbe9": fuseTest{
		name:       "cbe9",
		af:         0x5700,
		bc:         0x28b7,
		de:         0x8f2f,
		hl:         0xa4d0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbea": fuseTest{
		name:       "cbea",
		af:         0xec00,
		bc:         0x304a,
		de:         0x60a1,
		hl:         0xf32a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbeb": fuseTest{
		name:       "cbeb",
		af:         0xf000,
		bc:         0x532b,
		de:         0xa1be,
		hl:         0x1a1a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbec": fuseTest{
		name:       "cbec",
		af:         0xf200,
		bc:         0xf0f3,
		de:         0xa816,
		hl:         0xba08,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbed": fuseTest{
		name:       "cbed",
		af:         0x1300,
		bc:         0x5127,
		de:         0xadab,
		hl:         0x2dec,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbee": fuseTest{
		name:       "cbee",
		af:         0x9000,
		bc:         0xb273,
		de:         0x50ae,
		hl:         0xe90d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbef": fuseTest{
		name:       "cbef",
		af:         0x2500,
		bc:         0x4281,
		de:         0xf0d4,
		hl:         0x2c39,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf0": fuseTest{
		name:       "cbf0",
		af:         0xfb00,
		bc:         0x5802,
		de:         0x0c27,
		hl:         0x6ff5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf1": fuseTest{
		name:       "cbf1",
		af:         0x5500,
		bc:         0xa143,
		de:         0x3ff5,
		hl:         0x5e1c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf2": fuseTest{
		name:       "cbf2",
		af:         0xf000,
		bc:         0x625a,
		de:         0xef82,
		hl:         0x9819,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf3": fuseTest{
		name:       "cbf3",
		af:         0x8600,
		bc:         0xd7bd,
		de:         0x5dc6,
		hl:         0x263f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf4": fuseTest{
		name:       "cbf4",
		af:         0x9400,
		bc:         0x0243,
		de:         0x9ec1,
		hl:         0x75d9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf5": fuseTest{
		name:       "cbf5",
		af:         0xce00,
		bc:         0x2d42,
		de:         0x5e6a,
		hl:         0x47e6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf6": fuseTest{
		name:    "cbf6",
		af:      0x7b00,
		bc:      0xc2d7,
		de:      0x4492,
		hl:      0xa9bc,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0xa9bc, 0xf1},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf7": fuseTest{
		name:       "cbf7",
		af:         0x6d00,
		bc:         0xabaf,
		de:         0x5b5d,
		hl:         0x188c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf8": fuseTest{
		name:       "cbf8",
		af:         0xc600,
		bc:         0xb812,
		de:         0xa037,
		hl:         0xd2b0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbf9": fuseTest{
		name:       "cbf9",
		af:         0xef00,
		bc:         0xc5f2,
		de:         0x77a8,
		hl:         0x0730,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbfa": fuseTest{
		name:       "cbfa",
		af:         0x8700,
		bc:         0x1581,
		de:         0xe3e3,
		hl:         0xed03,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbfb": fuseTest{
		name:       "cbfb",
		af:         0xa300,
		bc:         0x7d27,
		de:         0x97c3,
		hl:         0xd1ae,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbfc": fuseTest{
		name:       "cbfc",
		af:         0xec00,
		bc:         0x060a,
		de:         0x3ef6,
		hl:         0xd00f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbfd": fuseTest{
		name:       "cbfd",
		af:         0x1100,
		bc:         0x231a,
		de:         0x8563,
		hl:         0x28c5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbfe": fuseTest{
		name:       "cbfe",
		af:         0x5300,
		bc:         0x4948,
		de:         0x89dd,
		hl:         0x3a24,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cbff": fuseTest{
		name:       "cbff",
		af:         0xf900,
		bc:         0x799b,
		de:         0x6cf7,
		hl:         0xe3f2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cc_1": fuseTest{
		name:    "cc_1",
		af:      0x004e,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cc_2": fuseTest{
		name:       "cc_2",
		af:         0x000e,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cd": fuseTest{
		name:    "cd",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xb07b,
		pc:      0x3a5d,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0xb07b, 0x03},
			[]int{0xb07c, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ce": fuseTest{
		name:       "ce",
		af:         0x1301,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"cf": fuseTest{
		name:    "cf",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0008,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d0_1": fuseTest{
		name:       "d0_1",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d0_2": fuseTest{
		name:       "d0_2",
		af:         0x0099,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d1": fuseTest{
		name:       "d1",
		af:         0x0000,
		bc:         0x0000,
		de:         0xe8ce,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x4145,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d2_1": fuseTest{
		name:       "d2_1",
		af:         0x0086,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d2_2": fuseTest{
		name:       "d2_2",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d3_1": fuseTest{
		name:      "d3_1",
		af:        0xa200,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0000,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x01,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   11,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xed, 0xa2},
		},
	},
	"d3_2": fuseTest{
		name:      "d3_2",
		af:        0x4200,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0000,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x01,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   11,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xec, 0x42},
		},
	},
	"d3_3": fuseTest{
		name:      "d3_3",
		af:        0x4200,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0000,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x01,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   11,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xed, 0x42},
		},
	},
	"d3": fuseTest{
		name:      "d3",
		af:        0xa200,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0000,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x01,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   11,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xec, 0xa2},
		},
	},
	"d4_1": fuseTest{
		name:    "d4_1",
		af:      0x000e,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d4_2": fuseTest{
		name:       "d4_2",
		af:         0x000f,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d5": fuseTest{
		name:    "d5",
		af:      0x53e3,
		bc:      0x1459,
		de:      0x775f,
		hl:      0x1a2f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xec10,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0xec10, 0x5f},
			[]int{0xec11, 0x77},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d6": fuseTest{
		name:       "d6",
		af:         0x5a1b,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d7": fuseTest{
		name:    "d7",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0010,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d8_1": fuseTest{
		name:       "d8_1",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d8_2": fuseTest{
		name:       "d8_2",
		af:         0x0099,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"d9": fuseTest{
		name:       "d9",
		af:         0x4d94,
		bc:         0xc930,
		de:         0x3d01,
		hl:         0x7d02,
		af1:        0x1a64,
		bc1:        0xe07a,
		de1:        0xe35b,
		hl1:        0x9d64,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"da_1": fuseTest{
		name:       "da_1",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"da_2": fuseTest{
		name:       "da_2",
		af:         0x0086,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"db_1": fuseTest{
		name:    "db_1",
		af:      0xc100,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xe3, 0xc1},
		},
		portWrites: [][]int{},
	},
	"db_2": fuseTest{
		name:    "db_2",
		af:      0x7100,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xe2, 0x71},
		},
		portWrites: [][]int{},
	},
	"db_3": fuseTest{
		name:    "db_3",
		af:      0x7100,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xe3, 0x71},
		},
		portWrites: [][]int{},
	},
	"db": fuseTest{
		name:    "db",
		af:      0xc100,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xe2, 0xc1},
		},
		portWrites: [][]int{},
	},
	"dc_1": fuseTest{
		name:    "dc_1",
		af:      0x000f,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dc_2": fuseTest{
		name:       "dc_2",
		af:         0x000e,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd00": fuseTest{
		name:       "dd00",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x03,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    12,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd09": fuseTest{
		name:       "dd09",
		af:         0x0d34,
		bc:         0x1426,
		de:         0x53ce,
		hl:         0x41e3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb2e6,
		iy:         0x5c89,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd19": fuseTest{
		name:       "dd19",
		af:         0x1928,
		bc:         0x0e0b,
		de:         0x2724,
		hl:         0xbe62,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa973,
		iy:         0x760b,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd21": fuseTest{
		name:       "dd21",
		af:         0xc935,
		bc:         0x4353,
		de:         0xbd22,
		hl:         0x94d5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7cf2,
		iy:         0xaad6,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd22": fuseTest{
		name:    "dd22",
		af:      0x5b1d,
		bc:      0x45a1,
		de:      0x6de8,
		hl:      0x39d3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xebe7,
		iy:      0x05b0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 20,
		memory: [][]int{
			[]int{0xad4f, 0xe7},
			[]int{0xad50, 0xeb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd23": fuseTest{
		name:       "dd23",
		af:         0x9095,
		bc:         0xac3c,
		de:         0x4d90,
		hl:         0x379b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd50c,
		iy:         0xa157,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd24": fuseTest{
		name:       "dd24",
		af:         0x0688,
		bc:         0xdcd0,
		de:         0xa31b,
		hl:         0xd527,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8dda,
		iy:         0xb096,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd25": fuseTest{
		name:       "dd25",
		af:         0x5aaa,
		bc:         0x206b,
		de:         0xed10,
		hl:         0x6eab,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xba3c,
		iy:         0x5ebd,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd26": fuseTest{
		name:       "dd26",
		af:         0x9522,
		bc:         0xede0,
		de:         0xa352,
		hl:         0xadea,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xad40,
		iy:         0x82e1,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd29": fuseTest{
		name:       "dd29",
		af:         0xaca0,
		bc:         0x0f0e,
		de:         0x72c8,
		hl:         0x1f2a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa32a,
		iy:         0x7d8a,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd2a": fuseTest{
		name:       "dd2a",
		af:         0x3d36,
		bc:         0xb24e,
		de:         0xbdbc,
		hl:         0xca4e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x30b5,
		iy:         0xe7ce,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd2b": fuseTest{
		name:       "dd2b",
		af:         0xad4b,
		bc:         0xd5e6,
		de:         0x9377,
		hl:         0xf132,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7a16,
		iy:         0x2188,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd2c": fuseTest{
		name:       "dd2c",
		af:         0x8830,
		bc:         0xf2f3,
		de:         0xd277,
		hl:         0x9153,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc630,
		iy:         0xb002,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd2d": fuseTest{
		name:       "dd2d",
		af:         0x3922,
		bc:         0xb23c,
		de:         0x6e11,
		hl:         0x5a49,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0266,
		iy:         0xab03,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd2e": fuseTest{
		name:       "dd2e",
		af:         0x9aca,
		bc:         0xa04a,
		de:         0xb49f,
		hl:         0xa4a6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbd1c,
		iy:         0x38a1,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd34": fuseTest{
		name:    "dd34",
		af:      0x8308,
		bc:      0xd1fc,
		de:      0xb80b,
		hl:      0x8082,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xdea9,
		iy:      0x6fd8,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xde8f, 0x58},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd35": fuseTest{
		name:    "dd35",
		af:      0x86a3,
		bc:      0x4641,
		de:      0x1ef6,
		hl:      0x10ab,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc733,
		iy:      0x8ec4,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc793, 0xf6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd36": fuseTest{
		name:    "dd36",
		af:      0x76dc,
		bc:      0x2530,
		de:      0x5158,
		hl:      0x877d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb5c6,
		iy:      0x8d3c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0xb5fb, 0xb5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd39": fuseTest{
		name:       "dd39",
		af:         0x8769,
		bc:         0xa334,
		de:         0xd79d,
		hl:         0x59e4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xab64,
		iy:         0x4c88,
		sp:         0xfa4a,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd44": fuseTest{
		name:       "dd44",
		af:         0xb37e,
		bc:         0x27b0,
		de:         0x36e8,
		hl:         0x3f45,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2702,
		iy:         0xb3b9,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd45": fuseTest{
		name:       "dd45",
		af:         0x4e10,
		bc:         0x986d,
		de:         0xd11d,
		hl:         0x1736,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7298,
		iy:         0x2d10,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd46": fuseTest{
		name:       "dd46",
		af:         0xc758,
		bc:         0x8d29,
		de:         0x66f2,
		hl:         0x29ef,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5cc7,
		iy:         0x407d,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd4c": fuseTest{
		name:       "dd4c",
		af:         0xe15c,
		bc:         0x753e,
		de:         0x7531,
		hl:         0xae9e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3ed8,
		iy:         0x03b7,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd4d": fuseTest{
		name:       "dd4d",
		af:         0x469e,
		bc:         0x78aa,
		de:         0x6a5a,
		hl:         0x00e2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa1aa,
		iy:         0x0d6f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd4e": fuseTest{
		name:       "dd4e",
		af:         0x7bf7,
		bc:         0x6676,
		de:         0x8d55,
		hl:         0xdef2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd94b,
		iy:         0x17fb,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd54": fuseTest{
		name:       "dd54",
		af:         0x8376,
		bc:         0x0d13,
		de:         0x4b67,
		hl:         0x3119,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4b6d,
		iy:         0x030b,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd55": fuseTest{
		name:       "dd55",
		af:         0xff78,
		bc:         0x85e3,
		de:         0xd76b,
		hl:         0x8f3a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd7d7,
		iy:         0x4e0b,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd56": fuseTest{
		name:       "dd56",
		af:         0x97b3,
		bc:         0xb617,
		de:         0xde50,
		hl:         0x81d1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa306,
		iy:         0x7a49,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd5c": fuseTest{
		name:       "dd5c",
		af:         0xaf82,
		bc:         0x24bf,
		de:         0x27f9,
		hl:         0xf925,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf9a3,
		iy:         0x0b82,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd5d": fuseTest{
		name:       "dd5d",
		af:         0x36cb,
		bc:         0x97a9,
		de:         0x4040,
		hl:         0x30fe,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3340,
		iy:         0xb3ed,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd5e": fuseTest{
		name:       "dd5e",
		af:         0xa220,
		bc:         0x389d,
		de:         0x2fce,
		hl:         0x368c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8d32,
		iy:         0x3512,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd60": fuseTest{
		name:       "dd60",
		af:         0x2392,
		bc:         0x7f6a,
		de:         0x3dc0,
		hl:         0xcefb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7fa0,
		iy:         0xc424,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd61": fuseTest{
		name:       "dd61",
		af:         0x76ed,
		bc:         0x268c,
		de:         0xd5c8,
		hl:         0xbab0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8c50,
		iy:         0x0a93,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd62": fuseTest{
		name:       "dd62",
		af:         0x4c6f,
		bc:         0xb482,
		de:         0xfef4,
		hl:         0x62e7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfe25,
		iy:         0x9655,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd63": fuseTest{
		name:       "dd63",
		af:         0x6e9a,
		bc:         0x5499,
		de:         0x3c8f,
		hl:         0x1f64,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8f35,
		iy:         0x0df7,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd64": fuseTest{
		name:       "dd64",
		af:         0x47f6,
		bc:         0x1b7a,
		de:         0xa55e,
		hl:         0x2fc2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xefc7,
		iy:         0xaca0,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd65": fuseTest{
		name:       "dd65",
		af:         0xd786,
		bc:         0x7d1d,
		de:         0xb659,
		hl:         0x77e8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfafa,
		iy:         0x006d,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd66": fuseTest{
		name:       "dd66",
		af:         0x84c2,
		bc:         0x79b1,
		de:         0xca4a,
		hl:         0x03a0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xce5d,
		iy:         0xdd2d,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd67": fuseTest{
		name:       "dd67",
		af:         0x967c,
		bc:         0x511e,
		de:         0x336d,
		hl:         0x40f6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x96e7,
		iy:         0x5be2,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd68": fuseTest{
		name:       "dd68",
		af:         0x4a9d,
		bc:         0xefa8,
		de:         0xfebd,
		hl:         0x07e4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5fef,
		iy:         0xb23f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd69": fuseTest{
		name:       "dd69",
		af:         0x6466,
		bc:         0x2142,
		de:         0x2523,
		hl:         0x82b3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6442,
		iy:         0x04a7,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd6a": fuseTest{
		name:       "dd6a",
		af:         0x401f,
		bc:         0x61f1,
		de:         0x4b08,
		hl:         0xfa88,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc34b,
		iy:         0xd8f6,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd6b": fuseTest{
		name:       "dd6b",
		af:         0x6dc7,
		bc:         0xe2ae,
		de:         0x40bd,
		hl:         0xf3c0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x22bd,
		iy:         0x2749,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd6c": fuseTest{
		name:       "dd6c",
		af:         0x3939,
		bc:         0x90da,
		de:         0x62dc,
		hl:         0x7c31,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4141,
		iy:         0x7211,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd6d": fuseTest{
		name:       "dd6d",
		af:         0x3964,
		bc:         0xff3f,
		de:         0x23d4,
		hl:         0xc7c7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9b70,
		iy:         0x20c6,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd6e": fuseTest{
		name:       "dd6e",
		af:         0x223f,
		bc:         0xf661,
		de:         0xb61c,
		hl:         0x0f6b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc648,
		iy:         0xfae8,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd6f": fuseTest{
		name:       "dd6f",
		af:         0x6e84,
		bc:         0x9cd4,
		de:         0xa293,
		hl:         0x647d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0d6e,
		iy:         0x4a56,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd70": fuseTest{
		name:    "dd70",
		af:      0xd09f,
		bc:      0xfe00,
		de:      0x231e,
		hl:      0x31ec,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x05fa,
		iy:      0xea92,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x05f0, 0xfe},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd71": fuseTest{
		name:    "dd71",
		af:      0xebee,
		bc:      0x151c,
		de:      0x05c7,
		hl:      0xee08,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3722,
		iy:      0x2ec6,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x3745, 0x1c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd72": fuseTest{
		name:    "dd72",
		af:      0x80c9,
		bc:      0xac1e,
		de:      0x63bd,
		hl:      0x828b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8dff,
		iy:      0x94ef,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x8d92, 0x63},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd73": fuseTest{
		name:    "dd73",
		af:      0x8f3e,
		bc:      0xb5a3,
		de:      0x07de,
		hl:      0x0b0c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x79c6,
		iy:      0xae79,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x7a1d, 0xde},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd74": fuseTest{
		name:    "dd74",
		af:      0x4ae0,
		bc:      0x49c5,
		de:      0x3deb,
		hl:      0x0125,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5910,
		iy:      0x429a,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x58c9, 0x01},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd75": fuseTest{
		name:    "dd75",
		af:      0x5772,
		bc:      0xe833,
		de:      0xb63e,
		hl:      0x734f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xae4c,
		iy:      0xe8c2,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0xae7c, 0x4f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd77": fuseTest{
		name:    "dd77",
		af:      0xdc56,
		bc:      0xd893,
		de:      0x4116,
		hl:      0xf2d2,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa181,
		iy:      0x3157,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0xa10d, 0xdc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd7c": fuseTest{
		name:       "dd7c",
		af:         0x8c58,
		bc:         0x7705,
		de:         0xac92,
		hl:         0xa6a1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8cde,
		iy:         0x7507,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd7d": fuseTest{
		name:       "dd7d",
		af:         0xcb18,
		bc:         0x93fb,
		de:         0x6bdd,
		hl:         0x3a10,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd7cb,
		iy:         0xc0f6,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd7e": fuseTest{
		name:       "dd7e",
		af:         0x5766,
		bc:         0x1f77,
		de:         0x6220,
		hl:         0x0c40,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1cf4,
		iy:         0x1a1f,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd84": fuseTest{
		name:       "dd84",
		af:         0xcd98,
		bc:         0x1de8,
		de:         0xb8b9,
		hl:         0x78a6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9f1d,
		iy:         0xb11f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd85": fuseTest{
		name:       "dd85",
		af:         0xc580,
		bc:         0xb1ff,
		de:         0x8d7b,
		hl:         0x40c0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb513,
		iy:         0x0688,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd86": fuseTest{
		name:       "dd86",
		af:         0xa9bc,
		bc:         0xd085,
		de:         0x5bac,
		hl:         0xe364,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb5b5,
		iy:         0xfe3a,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd8c": fuseTest{
		name:       "dd8c",
		af:         0xcb98,
		bc:         0x8fdc,
		de:         0xea8f,
		hl:         0x9734,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0eb3,
		iy:         0x1b54,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd8d": fuseTest{
		name:       "dd8d",
		af:         0x7535,
		bc:         0x1c81,
		de:         0xb6fb,
		hl:         0xd6e5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x09be,
		iy:         0xa736,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd8e": fuseTest{
		name:       "dd8e",
		af:         0x8094,
		bc:         0x182d,
		de:         0xab17,
		hl:         0x94ae,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbb97,
		iy:         0x87da,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd94": fuseTest{
		name:       "dd94",
		af:         0x7422,
		bc:         0x9efe,
		de:         0x6ea1,
		hl:         0xfc55,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0a09,
		iy:         0x89c5,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd95": fuseTest{
		name:       "dd95",
		af:         0x2c3b,
		bc:         0x59ab,
		de:         0x428c,
		hl:         0x3a94,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x44fd,
		iy:         0xf243,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd96": fuseTest{
		name:       "dd96",
		af:         0x5206,
		bc:         0x461f,
		de:         0xced7,
		hl:         0xdb3f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2c66,
		iy:         0x9dbf,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd9c": fuseTest{
		name:       "dd9c",
		af:         0xd282,
		bc:         0x670e,
		de:         0xafcc,
		hl:         0x8b34,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x285f,
		iy:         0x1caa,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd9d": fuseTest{
		name:       "dd9d",
		af:         0xe5a2,
		bc:         0x0cdb,
		de:         0xdf32,
		hl:         0xd0e4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9b12,
		iy:         0x7d07,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dd9e": fuseTest{
		name:       "dd9e",
		af:         0xde9b,
		bc:         0xf9c5,
		de:         0xcbc4,
		hl:         0xca21,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb4cc,
		iy:         0x46fa,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dda4": fuseTest{
		name:       "dda4",
		af:         0x0210,
		bc:         0xba53,
		de:         0xacfc,
		hl:         0x9481,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2f8b,
		iy:         0xedf6,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dda5": fuseTest{
		name:       "dda5",
		af:         0xaabc,
		bc:         0xa675,
		de:         0xd757,
		hl:         0xf1db,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfdef,
		iy:         0xd8ce,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dda6": fuseTest{
		name:       "dda6",
		af:         0x0514,
		bc:         0x20c4,
		de:         0xebc3,
		hl:         0xda8d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7e95,
		iy:         0x5e8a,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddac": fuseTest{
		name:       "ddac",
		af:         0x4000,
		bc:         0x2a7c,
		de:         0x17e5,
		hl:         0x3f6e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xaffa,
		iy:         0xa0b5,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddad": fuseTest{
		name:       "ddad",
		af:         0x8284,
		bc:         0x6ba1,
		de:         0xef1b,
		hl:         0x5713,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xba38,
		iy:         0xa708,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddae": fuseTest{
		name:       "ddae",
		af:         0x4300,
		bc:         0x3ad6,
		de:         0xa721,
		hl:         0x2100,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe909,
		iy:         0x87b4,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddb4": fuseTest{
		name:       "ddb4",
		af:         0x9c8c,
		bc:         0x29aa,
		de:         0x2e82,
		hl:         0x4dc8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9c04,
		iy:         0x8be3,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddb5": fuseTest{
		name:       "ddb5",
		af:         0xc780,
		bc:         0xfc93,
		de:         0x7a06,
		hl:         0x0518,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0ac5,
		iy:         0x4150,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddb6": fuseTest{
		name:       "ddb6",
		af:         0x5c0c,
		bc:         0xab81,
		de:         0x4287,
		hl:         0x5ee1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc66f,
		iy:         0xd6cc,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddbc": fuseTest{
		name:       "ddbc",
		af:         0x53bf,
		bc:         0xaa98,
		de:         0xf7d7,
		hl:         0xfa0c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbe7a,
		iy:         0xa41f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddbd": fuseTest{
		name:       "ddbd",
		af:         0xdc82,
		bc:         0x80ce,
		de:         0x5d2f,
		hl:         0xe999,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbb41,
		iy:         0xa24f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddbe": fuseTest{
		name:       "ddbe",
		af:         0x981e,
		bc:         0xbfd5,
		de:         0xa299,
		hl:         0xd34b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9332,
		iy:         0xb1d5,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb00": fuseTest{
		name:    "ddcb00",
		af:      0x3c01,
		bc:      0x43e4,
		de:      0x09d1,
		hl:      0x646b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1da1,
		iy:      0xf08f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1dae, 0x43},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb01": fuseTest{
		name:    "ddcb01",
		af:      0xf681,
		bc:      0xe3c7,
		de:      0x2d4a,
		hl:      0x7725,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x28fd,
		iy:      0xf31b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x28b4, 0xc7},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb02": fuseTest{
		name:    "ddcb02",
		af:      0xe20d,
		bc:      0x836e,
		de:      0x1b3a,
		hl:      0xf840,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc796,
		iy:      0xae9b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc727, 0x1b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb03": fuseTest{
		name:    "ddcb03",
		af:      0x62a4,
		bc:      0x3571,
		de:      0xc5f0,
		hl:      0x48dc,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x041e,
		iy:      0xc07b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0466, 0xf0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb04": fuseTest{
		name:    "ddcb04",
		af:      0xb380,
		bc:      0xbfc4,
		de:      0x64af,
		hl:      0xd022,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5949,
		iy:      0xa989,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5991, 0xd0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb05": fuseTest{
		name:    "ddcb05",
		af:      0x492d,
		bc:      0xbb04,
		de:      0x56ec,
		hl:      0x9d2b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0077,
		iy:      0x1349,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0076, 0x2b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb06": fuseTest{
		name:    "ddcb06",
		af:      0x0c29,
		bc:      0xf636,
		de:      0x90a6,
		hl:      0x6117,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5421,
		iy:      0x90ee,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5428, 0x2f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb07": fuseTest{
		name:    "ddcb07",
		af:      0x5d09,
		bc:      0x9ca3,
		de:      0xbdf6,
		hl:      0xed50,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9803,
		iy:      0x55f9,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9845, 0x5d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb08": fuseTest{
		name:    "ddcb08",
		af:      0x0228,
		bc:      0x6d66,
		de:      0x6023,
		hl:      0xae06,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xef40,
		iy:      0xb006,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xef4a, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb09": fuseTest{
		name:    "ddcb09",
		af:      0x98a5,
		bc:      0x92b7,
		de:      0x54d5,
		hl:      0x5e1e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9d0b,
		iy:      0x6e58,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9d46, 0xb7},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb0a": fuseTest{
		name:    "ddcb0a",
		af:      0xd22c,
		bc:      0x6aac,
		de:      0x3c89,
		hl:      0x9293,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1fb4,
		iy:      0x2498,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1f37, 0x3c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb0b": fuseTest{
		name:    "ddcb0b",
		af:      0xb808,
		bc:      0xb284,
		de:      0x2349,
		hl:      0x7e7d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xcd09,
		iy:      0x6a03,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xcd03, 0x49},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb0c": fuseTest{
		name:    "ddcb0c",
		af:      0xdf81,
		bc:      0xb6cc,
		de:      0xee8d,
		hl:      0x865a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbf6b,
		iy:      0x9b7d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbfe4, 0x86},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb0d": fuseTest{
		name:    "ddcb0d",
		af:      0xba89,
		bc:      0xceec,
		de:      0xbbaa,
		hl:      0xb68f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x88bd,
		iy:      0x503e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x88a1, 0x8f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb0e": fuseTest{
		name:    "ddcb0e",
		af:      0x1c81,
		bc:      0x890b,
		de:      0x7830,
		hl:      0x060c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfd49,
		iy:      0x5d07,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xfd0f, 0xd6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb0f": fuseTest{
		name:    "ddcb0f",
		af:      0x7c28,
		bc:      0xfad4,
		de:      0xfa4b,
		hl:      0x9c53,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7447,
		iy:      0x2267,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x749e, 0x7c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb10": fuseTest{
		name:    "ddcb10",
		af:      0xf38c,
		bc:      0x8b1f,
		de:      0x5387,
		hl:      0x926e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbba2,
		iy:      0xca47,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbbf1, 0x8b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb11": fuseTest{
		name:    "ddcb11",
		af:      0x2aa1,
		bc:      0xd6b3,
		de:      0xa9aa,
		hl:      0x5b52,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1809,
		iy:      0xd275,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x17f4, 0xb3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb12": fuseTest{
		name:    "ddcb12",
		af:      0x9285,
		bc:      0xc479,
		de:      0xc5d1,
		hl:      0x10ce,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc0fb,
		iy:      0x2777,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc0a1, 0xc5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb13": fuseTest{
		name:    "ddcb13",
		af:      0xa509,
		bc:      0x580a,
		de:      0xa44f,
		hl:      0x11cd,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5ac4,
		iy:      0xccc7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5ac3, 0x4f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb14": fuseTest{
		name:    "ddcb14",
		af:      0x2909,
		bc:      0x5b89,
		de:      0x8467,
		hl:      0x0b30,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0977,
		iy:      0xc4e8,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0954, 0x0b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb15": fuseTest{
		name:    "ddcb15",
		af:      0x1f0c,
		bc:      0x6d53,
		de:      0x5b7c,
		hl:      0xa11d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xede9,
		iy:      0xa85c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xedf0, 0x1d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb16": fuseTest{
		name:    "ddcb16",
		af:      0xdaa0,
		bc:      0xa1e4,
		de:      0x00b0,
		hl:      0x92c8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x16be,
		iy:      0x2c95,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1703, 0xb6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb17": fuseTest{
		name:    "ddcb17",
		af:      0xfcac,
		bc:      0xcbd1,
		de:      0x4e1a,
		hl:      0xcd27,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb8c9,
		iy:      0xe6d4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb8e5, 0xfc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb18": fuseTest{
		name:    "ddcb18",
		af:      0xd90c,
		bc:      0x48b5,
		de:      0x9cf9,
		hl:      0xb9f1,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa189,
		iy:      0xbd7c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa197, 0x48},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb19": fuseTest{
		name:    "ddcb19",
		af:      0x2389,
		bc:      0x599b,
		de:      0xa756,
		hl:      0xcf2e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf0e7,
		iy:      0x26e4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf08a, 0x9b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb1a": fuseTest{
		name:    "ddcb1a",
		af:      0x8b24,
		bc:      0x7e45,
		de:      0x660f,
		hl:      0x37a6,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xde61,
		iy:      0x9cd9,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xde0d, 0x66},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb1b": fuseTest{
		name:    "ddcb1b",
		af:      0x5c89,
		bc:      0x1414,
		de:      0x81c8,
		hl:      0x5881,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb7c3,
		iy:      0xd14f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb7c8, 0xc8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb1c": fuseTest{
		name:    "ddcb1c",
		af:      0xfa25,
		bc:      0x6277,
		de:      0x8b67,
		hl:      0x3023,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfef9,
		iy:      0x4a66,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xfef8, 0x30},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb1d": fuseTest{
		name:    "ddcb1d",
		af:      0x76ad,
		bc:      0x324e,
		de:      0xe641,
		hl:      0x58f9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5b63,
		iy:      0xe18b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5b9d, 0xf9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb1e": fuseTest{
		name:    "ddcb1e",
		af:      0xc589,
		bc:      0xcd58,
		de:      0x8967,
		hl:      0xf074,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x75b4,
		iy:      0x693a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7582, 0xc8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb1f": fuseTest{
		name:    "ddcb1f",
		af:      0xda88,
		bc:      0x7f6d,
		de:      0x2058,
		hl:      0x63e3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1d9b,
		iy:      0xbaba,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1d43, 0xda},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb20": fuseTest{
		name:    "ddcb20",
		af:      0x4c08,
		bc:      0x1c9e,
		de:      0xdc6c,
		hl:      0x18f4,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xdc39,
		iy:      0x8b0c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdc21, 0x1c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb21": fuseTest{
		name:    "ddcb21",
		af:      0xd2ad,
		bc:      0x66ee,
		de:      0x23ef,
		hl:      0x9096,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3494,
		iy:      0xb6c3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3432, 0xee},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb22": fuseTest{
		name:    "ddcb22",
		af:      0xfb29,
		bc:      0xe0d0,
		de:      0x3e02,
		hl:      0xb4b7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbd3f,
		iy:      0x385b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbd82, 0x3e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb23": fuseTest{
		name:    "ddcb23",
		af:      0xc385,
		bc:      0x68b6,
		de:      0xdac0,
		hl:      0xb990,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x22dd,
		iy:      0xbd27,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x229e, 0xc0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb24": fuseTest{
		name:    "ddcb24",
		af:      0xba81,
		bc:      0x7b0b,
		de:      0x560b,
		hl:      0x8633,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x31f1,
		iy:      0xddbd,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x31d9, 0x86},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb25": fuseTest{
		name:    "ddcb25",
		af:      0x4381,
		bc:      0xa21b,
		de:      0x2347,
		hl:      0xaed6,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xcc63,
		iy:      0xfc94,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xcc24, 0xd6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb26": fuseTest{
		name:    "ddcb26",
		af:      0x2005,
		bc:      0xff37,
		de:      0xe41f,
		hl:      0x70e7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6528,
		iy:      0xa0d5,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x651f, 0x12},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb27": fuseTest{
		name:    "ddcb27",
		af:      0x5809,
		bc:      0x5669,
		de:      0x1bee,
		hl:      0xf62c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1f69,
		iy:      0x3418,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1f2c, 0x58},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb28": fuseTest{
		name:    "ddcb28",
		af:      0x7a04,
		bc:      0x12b8,
		de:      0x51f7,
		hl:      0x7164,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x999b,
		iy:      0x8857,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9951, 0x12},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb29": fuseTest{
		name:    "ddcb29",
		af:      0x0480,
		bc:      0xb7c1,
		de:      0x323f,
		hl:      0xfd34,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x20e7,
		iy:      0xc753,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2083, 0xc1},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb2a": fuseTest{
		name:    "ddcb2a",
		af:      0x4528,
		bc:      0xafde,
		de:      0x3e08,
		hl:      0x75d7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9505,
		iy:      0xb624,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x94dd, 0x3e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb2b": fuseTest{
		name:    "ddcb2b",
		af:      0x8324,
		bc:      0xe290,
		de:      0x2622,
		hl:      0x7ddd,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb484,
		iy:      0x571c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb441, 0x22},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb2c": fuseTest{
		name:    "ddcb2c",
		af:      0xc685,
		bc:      0x0c94,
		de:      0x6e4b,
		hl:      0xc0c7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfe28,
		iy:      0xdc80,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xfe54, 0xc0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb2d": fuseTest{
		name:    "ddcb2d",
		af:      0xce24,
		bc:      0xd2ae,
		de:      0xc9be,
		hl:      0x4222,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb4ed,
		iy:      0x6de3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb488, 0x22},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb2e": fuseTest{
		name:    "ddcb2e",
		af:      0x5001,
		bc:      0xde74,
		de:      0xeca8,
		hl:      0x83ff,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x69d8,
		iy:      0x75c7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x6a15, 0x02},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb2f": fuseTest{
		name:    "ddcb2f",
		af:      0xf9ac,
		bc:      0x759b,
		de:      0x3059,
		hl:      0x01b9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7a30,
		iy:      0xdd56,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7a03, 0xf9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb30": fuseTest{
		name:    "ddcb30",
		af:      0x3c24,
		bc:      0x65ad,
		de:      0x9cc7,
		hl:      0xa68c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xeee8,
		iy:      0x5a80,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xeec7, 0x65},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb31": fuseTest{
		name:    "ddcb31",
		af:      0xeb89,
		bc:      0x419b,
		de:      0x929b,
		hl:      0x7d47,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf22d,
		iy:      0x8943,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf276, 0x9b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb32": fuseTest{
		name:    "ddcb32",
		af:      0x9a85,
		bc:      0xaa64,
		de:      0xc509,
		hl:      0x01ad,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x579f,
		iy:      0xec4c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x577f, 0xc5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb33": fuseTest{
		name:    "ddcb33",
		af:      0xb804,
		bc:      0xb854,
		de:      0x5217,
		hl:      0x9599,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xefac,
		iy:      0xd9ec,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xef75, 0x17},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb34": fuseTest{
		name:    "ddcb34",
		af:      0xcd89,
		bc:      0x4432,
		de:      0x20d4,
		hl:      0xdf3e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xab48,
		iy:      0xc95f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xab91, 0xdf},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb35": fuseTest{
		name:    "ddcb35",
		af:      0xde09,
		bc:      0xc6fc,
		de:      0x696d,
		hl:      0x151f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xeb1a,
		iy:      0x4a12,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xead3, 0x1f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb36": fuseTest{
		name:    "ddcb36",
		af:      0x3d04,
		bc:      0x443b,
		de:      0xff21,
		hl:      0x63e3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x132e,
		iy:      0xfb39,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x12e2, 0x05},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb37": fuseTest{
		name:    "ddcb37",
		af:      0x7b2c,
		bc:      0xbfc9,
		de:      0xa69a,
		hl:      0xec0b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5077,
		iy:      0x4e3e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x503d, 0x7b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb38": fuseTest{
		name:    "ddcb38",
		af:      0x3c28,
		bc:      0x2fee,
		de:      0x38e1,
		hl:      0xae9f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf695,
		iy:      0x44b3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf623, 0x2f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb39": fuseTest{
		name:    "ddcb39",
		af:      0x0505,
		bc:      0x9a41,
		de:      0xa2db,
		hl:      0xdf75,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa895,
		iy:      0xe243,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa871, 0x41},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb3a": fuseTest{
		name:    "ddcb3a",
		af:      0x0e05,
		bc:      0x0b9f,
		de:      0x443b,
		hl:      0xc01d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2591,
		iy:      0x49c3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x259e, 0x44},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb3b": fuseTest{
		name:    "ddcb3b",
		af:      0x1b01,
		bc:      0xc795,
		de:      0xd854,
		hl:      0x7ccf,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6fed,
		iy:      0x09dc,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x700d, 0x54},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb3c": fuseTest{
		name:    "ddcb3c",
		af:      0xb628,
		bc:      0xbdf7,
		de:      0xfca3,
		hl:      0x6829,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf53b,
		iy:      0x018b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf51c, 0x68},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb3d": fuseTest{
		name:    "ddcb3d",
		af:      0x2a28,
		bc:      0x6e6e,
		de:      0xcfbd,
		hl:      0x1d2c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0320,
		iy:      0x6ab0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x02de, 0x2c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb3e": fuseTest{
		name:    "ddcb3e",
		af:      0x392d,
		bc:      0xb26e,
		de:      0xb670,
		hl:      0xb8a2,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x784a,
		iy:      0x7840,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7854, 0x2e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb3f": fuseTest{
		name:    "ddcb3f",
		af:      0x0200,
		bc:      0x429d,
		de:      0xd8c0,
		hl:      0xe069,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3488,
		iy:      0x7150,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x34b9, 0x02},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb40": fuseTest{
		name:       "ddcb40",
		af:         0x1119,
		bc:         0xf6ba,
		de:         0x079e,
		hl:         0x0e41,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8c01,
		iy:         0xcd21,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb41": fuseTest{
		name:       "ddcb41",
		af:         0x2219,
		bc:         0xc4b0,
		de:         0x575b,
		hl:         0x66b4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xcdcf,
		iy:         0xa25c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb42": fuseTest{
		name:       "ddcb42",
		af:         0xaf74,
		bc:         0x7720,
		de:         0xaa95,
		hl:         0x3b0a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf03a,
		iy:         0x856a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb43": fuseTest{
		name:       "ddcb43",
		af:         0x7f38,
		bc:         0xb699,
		de:         0x5e71,
		hl:         0x1827,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe8b6,
		iy:         0x96a8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb44": fuseTest{
		name:       "ddcb44",
		af:         0x5f7c,
		bc:         0xde05,
		de:         0x12fd,
		hl:         0xf73b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xee0a,
		iy:         0x6634,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb45": fuseTest{
		name:       "ddcb45",
		af:         0xea31,
		bc:         0x699c,
		de:         0x47d3,
		hl:         0x89c3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa2be,
		iy:         0xd81e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb46": fuseTest{
		name:       "ddcb46",
		af:         0x6030,
		bc:         0xac1d,
		de:         0x4173,
		hl:         0xf92a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa39f,
		iy:         0x12e5,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb47": fuseTest{
		name:       "ddcb47",
		af:         0x1b54,
		bc:         0xf7c0,
		de:         0x22f6,
		hl:         0x5253,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5227,
		iy:         0x919d,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb48": fuseTest{
		name:       "ddcb48",
		af:         0x7274,
		bc:         0x4509,
		de:         0xd68f,
		hl:         0x3b3d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2746,
		iy:         0x7f97,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb49": fuseTest{
		name:       "ddcb49",
		af:         0x7f11,
		bc:         0xda22,
		de:         0xea9c,
		hl:         0xf480,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x41c6,
		iy:         0x75a9,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb4a": fuseTest{
		name:       "ddcb4a",
		af:         0xf155,
		bc:         0xe6c3,
		de:         0x5a42,
		hl:         0x8b21,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbfeb,
		iy:         0xe383,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb4b": fuseTest{
		name:       "ddcb4b",
		af:         0x1054,
		bc:         0x880a,
		de:         0x52b2,
		hl:         0xfb1b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc239,
		iy:         0x6b40,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb4c": fuseTest{
		name:       "ddcb4c",
		af:         0x0510,
		bc:         0xbc63,
		de:         0xf081,
		hl:         0x0a55,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x874c,
		iy:         0x80a3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb4d": fuseTest{
		name:       "ddcb4d",
		af:         0x7f7c,
		bc:         0x32b4,
		de:         0x03d5,
		hl:         0xef66,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7d2a,
		iy:         0x03bc,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb4e": fuseTest{
		name:       "ddcb4e",
		af:         0x7c39,
		bc:         0xfa92,
		de:         0xb4d0,
		hl:         0x9f23,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xeade,
		iy:         0x1785,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb4f": fuseTest{
		name:       "ddcb4f",
		af:         0x725c,
		bc:         0x257b,
		de:         0xdb73,
		hl:         0x2478,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x88c0,
		iy:         0xf151,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb50": fuseTest{
		name:       "ddcb50",
		af:         0x355c,
		bc:         0x8e51,
		de:         0x406c,
		hl:         0x2e3c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xdaf2,
		iy:         0x413c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb51": fuseTest{
		name:       "ddcb51",
		af:         0xa610,
		bc:         0xba85,
		de:         0xc88c,
		hl:         0xe86c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x84b2,
		iy:         0xcd8e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb52": fuseTest{
		name:       "ddcb52",
		af:         0xcb74,
		bc:         0x1220,
		de:         0x1103,
		hl:         0xa868,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6156,
		iy:         0xcfac,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb53": fuseTest{
		name:       "ddcb53",
		af:         0x5e39,
		bc:         0x569e,
		de:         0xf76d,
		hl:         0x88c6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xae45,
		iy:         0x623e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb54": fuseTest{
		name:       "ddcb54",
		af:         0xc331,
		bc:         0x76fe,
		de:         0xf1ff,
		hl:         0x416e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xefd5,
		iy:         0x7576,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb55": fuseTest{
		name:       "ddcb55",
		af:         0x7074,
		bc:         0xdcd0,
		de:         0x8345,
		hl:         0xd498,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf352,
		iy:         0xa88b,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb56": fuseTest{
		name:       "ddcb56",
		af:         0x917c,
		bc:         0x2cb8,
		de:         0x571c,
		hl:         0xf4fd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6d30,
		iy:         0xaec2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb57": fuseTest{
		name:       "ddcb57",
		af:         0x3c19,
		bc:         0x541a,
		de:         0x027c,
		hl:         0xc0b4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5833,
		iy:         0x160a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb58": fuseTest{
		name:       "ddcb58",
		af:         0xc638,
		bc:         0xe1a8,
		de:         0x9d6c,
		hl:         0xbec3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6a46,
		iy:         0xb66c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb59": fuseTest{
		name:       "ddcb59",
		af:         0xad55,
		bc:         0x9bda,
		de:         0xb7ee,
		hl:         0x63c4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9195,
		iy:         0x9703,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb5a": fuseTest{
		name:       "ddcb5a",
		af:         0x8018,
		bc:         0x5105,
		de:         0x36b0,
		hl:         0xa37c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0de0,
		iy:         0xce7f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb5b": fuseTest{
		name:       "ddcb5b",
		af:         0x2a75,
		bc:         0x083d,
		de:         0x1409,
		hl:         0x06ba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x62ad,
		iy:         0xbaff,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb5c": fuseTest{
		name:       "ddcb5c",
		af:         0x4c18,
		bc:         0xe502,
		de:         0xd23c,
		hl:         0x6da8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9dc6,
		iy:         0x6f04,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb5d": fuseTest{
		name:       "ddcb5d",
		af:         0x7e11,
		bc:         0x511b,
		de:         0x3cfa,
		hl:         0x60d3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd193,
		iy:         0x3fe9,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb5e": fuseTest{
		name:       "ddcb5e",
		af:         0xce7d,
		bc:         0x0235,
		de:         0xe2b1,
		hl:         0x7a4c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xed14,
		iy:         0xd0d6,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb5f": fuseTest{
		name:       "ddcb5f",
		af:         0x0919,
		bc:         0x20a8,
		de:         0x52e1,
		hl:         0xd783,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xdf46,
		iy:         0xda41,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb60": fuseTest{
		name:       "ddcb60",
		af:         0x4274,
		bc:         0x0713,
		de:         0xdc90,
		hl:         0x2c89,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x32a2,
		iy:         0xc4d4,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb61": fuseTest{
		name:       "ddcb61",
		af:         0x1b30,
		bc:         0x1403,
		de:         0x8b9b,
		hl:         0xc221,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x36cb,
		iy:         0x93d4,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb62": fuseTest{
		name:       "ddcb62",
		af:         0x365d,
		bc:         0x4055,
		de:         0x650a,
		hl:         0x3f98,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0acc,
		iy:         0xa102,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb63": fuseTest{
		name:       "ddcb63",
		af:         0x6574,
		bc:         0x08df,
		de:         0x3ceb,
		hl:         0x6d24,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe679,
		iy:         0xf98e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb64": fuseTest{
		name:       "ddcb64",
		af:         0x3c38,
		bc:         0xe2a7,
		de:         0x6da9,
		hl:         0xc346,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xecfb,
		iy:         0x85b6,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb65": fuseTest{
		name:       "ddcb65",
		af:         0x0931,
		bc:         0x0abb,
		de:         0x3afa,
		hl:         0x91f5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7779,
		iy:         0xaef5,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb66": fuseTest{
		name:       "ddcb66",
		af:         0xcc38,
		bc:         0xd301,
		de:         0x9b66,
		hl:         0x40fb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xee15,
		iy:         0x0d23,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb67": fuseTest{
		name:       "ddcb67",
		af:         0xec7d,
		bc:         0x342f,
		de:         0xbe3e,
		hl:         0xa79b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xeea1,
		iy:         0xdfae,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb68": fuseTest{
		name:       "ddcb68",
		af:         0x8e39,
		bc:         0x0063,
		de:         0x49ad,
		hl:         0xb7d4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe968,
		iy:         0x864e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb69": fuseTest{
		name:       "ddcb69",
		af:         0x9f75,
		bc:         0x42b5,
		de:         0x74fe,
		hl:         0x1116,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x33f4,
		iy:         0x46c2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb6a": fuseTest{
		name:       "ddcb6a",
		af:         0x4654,
		bc:         0x0bd8,
		de:         0x0018,
		hl:         0x1ac3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x86b6,
		iy:         0x1dd2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb6b": fuseTest{
		name:       "ddcb6b",
		af:         0x7a18,
		bc:         0xf79f,
		de:         0xa78e,
		hl:         0xf867,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x187b,
		iy:         0x0023,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb6c": fuseTest{
		name:       "ddcb6c",
		af:         0xdd39,
		bc:         0x1f1e,
		de:         0xc1e1,
		hl:         0x0ea7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3e21,
		iy:         0xf544,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb6d": fuseTest{
		name:       "ddcb6d",
		af:         0xde75,
		bc:         0x9ae4,
		de:         0xfd24,
		hl:         0xb3c2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe314,
		iy:         0xad84,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb6e": fuseTest{
		name:       "ddcb6e",
		af:         0xca31,
		bc:         0x9f16,
		de:         0xc700,
		hl:         0x1dce,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3086,
		iy:         0xd68e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb6f": fuseTest{
		name:       "ddcb6f",
		af:         0xd47d,
		bc:         0x0b39,
		de:         0x3e2e,
		hl:         0xc06e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfc1b,
		iy:         0xd592,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb70": fuseTest{
		name:       "ddcb70",
		af:         0xf911,
		bc:         0x09b8,
		de:         0x43f8,
		hl:         0x2a76,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x042c,
		iy:         0x7f2d,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb71": fuseTest{
		name:       "ddcb71",
		af:         0xac5c,
		bc:         0x36ad,
		de:         0x34cb,
		hl:         0xf950,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1b33,
		iy:         0xaa23,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb72": fuseTest{
		name:       "ddcb72",
		af:         0xb15d,
		bc:         0xf1e4,
		de:         0x9984,
		hl:         0xc7fb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xce25,
		iy:         0xc5b6,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb73": fuseTest{
		name:       "ddcb73",
		af:         0x2174,
		bc:         0x592d,
		de:         0xf406,
		hl:         0xe21f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6442,
		iy:         0xcf58,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb74": fuseTest{
		name:       "ddcb74",
		af:         0x667c,
		bc:         0x64c1,
		de:         0xdbe5,
		hl:         0xeb48,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7dc1,
		iy:         0xc1fb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb75": fuseTest{
		name:       "ddcb75",
		af:         0x8730,
		bc:         0x580e,
		de:         0x00dd,
		hl:         0xf4c6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x60ad,
		iy:         0x9b60,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb76": fuseTest{
		name:       "ddcb76",
		af:         0x657c,
		bc:         0x5cc2,
		de:         0x3058,
		hl:         0xe258,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7e8a,
		iy:         0xb296,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb77": fuseTest{
		name:       "ddcb77",
		af:         0xe354,
		bc:         0x47a0,
		de:         0xc510,
		hl:         0xcf0a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0537,
		iy:         0xb242,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb78": fuseTest{
		name:       "ddcb78",
		af:         0x4255,
		bc:         0x24f6,
		de:         0x1632,
		hl:         0x8a4f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9397,
		iy:         0x846c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb79": fuseTest{
		name:       "ddcb79",
		af:         0xe690,
		bc:         0xeeaa,
		de:         0x41f7,
		hl:         0x5da2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x41de,
		iy:         0x4189,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb7a": fuseTest{
		name:       "ddcb7a",
		af:         0xca99,
		bc:         0x56aa,
		de:         0x6a06,
		hl:         0x6cd7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0aa9,
		iy:         0x9812,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb7b": fuseTest{
		name:       "ddcb7b",
		af:         0xae5d,
		bc:         0x0227,
		de:         0x721f,
		hl:         0x52a1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5040,
		iy:         0xb98a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb7c": fuseTest{
		name:       "ddcb7c",
		af:         0x8a7c,
		bc:         0xa2f1,
		de:         0x239a,
		hl:         0xd5cc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6883,
		iy:         0xb050,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb7d": fuseTest{
		name:       "ddcb7d",
		af:         0xc375,
		bc:         0xcf33,
		de:         0x1010,
		hl:         0x98e6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb021,
		iy:         0x0356,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb7e": fuseTest{
		name:       "ddcb7e",
		af:         0x9a99,
		bc:         0x2f6e,
		de:         0x0d0d,
		hl:         0xa83f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xcef0,
		iy:         0x8c15,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb7f": fuseTest{
		name:       "ddcb7f",
		af:         0x5399,
		bc:         0x1f4e,
		de:         0x4837,
		hl:         0x21b6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5ec2,
		iy:         0x80c3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb80": fuseTest{
		name:       "ddcb80",
		af:         0x6319,
		bc:         0x30f9,
		de:         0xc84b,
		hl:         0xbcf2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xacc5,
		iy:         0xa4ed,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb81": fuseTest{
		name:       "ddcb81",
		af:         0xfae1,
		bc:         0x5a24,
		de:         0x9502,
		hl:         0xdc9b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbdd3,
		iy:         0x1a52,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb82": fuseTest{
		name:    "ddcb82",
		af:      0xdaf6,
		bc:      0x3260,
		de:      0x50ac,
		hl:      0x1d47,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5e74,
		iy:      0x35e2,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5e0e, 0x50},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb83": fuseTest{
		name:    "ddcb83",
		af:      0x8e7c,
		bc:      0x5586,
		de:      0x8c00,
		hl:      0xfb00,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3441,
		iy:      0xd365,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x344f, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb84": fuseTest{
		name:       "ddcb84",
		af:         0xc1b3,
		bc:         0x4874,
		de:         0xc535,
		hl:         0xb01c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0123,
		iy:         0xdd28,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb85": fuseTest{
		name:       "ddcb85",
		af:         0x0928,
		bc:         0xb0db,
		de:         0x4e07,
		hl:         0xa7de,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0ba3,
		iy:         0xc61c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb86": fuseTest{
		name:       "ddcb86",
		af:         0x4515,
		bc:         0xde09,
		de:         0x3ce7,
		hl:         0x1fde,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x10c5,
		iy:         0x33ed,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb87": fuseTest{
		name:       "ddcb87",
		af:         0xc45e,
		bc:         0xa733,
		de:         0xd1dd,
		hl:         0x1603,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xede6,
		iy:         0xe5fb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb88": fuseTest{
		name:       "ddcb88",
		af:         0xe4fa,
		bc:         0x7c25,
		de:         0xc266,
		hl:         0x1b13,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x878e,
		iy:         0xe695,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb89": fuseTest{
		name:    "ddcb89",
		af:      0x933b,
		bc:      0x6fcd,
		de:      0xa3a8,
		hl:      0x2634,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8f3e,
		iy:      0x7727,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8f69, 0xcd},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb8a": fuseTest{
		name:    "ddcb8a",
		af:      0x6759,
		bc:      0xad1e,
		de:      0xe871,
		hl:      0xce52,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x39a9,
		iy:      0x38a0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x39b3, 0xe8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb8b": fuseTest{
		name:    "ddcb8b",
		af:      0x3da2,
		bc:      0x1833,
		de:      0x0388,
		hl:      0x07e9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1685,
		iy:      0xd790,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x16e7, 0x88},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb8c": fuseTest{
		name:    "ddcb8c",
		af:      0xa625,
		bc:      0xed31,
		de:      0x3946,
		hl:      0x3cdc,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc6a2,
		iy:      0x7ad6,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc68a, 0x3c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb8d": fuseTest{
		name:    "ddcb8d",
		af:      0x016b,
		bc:      0x5802,
		de:      0xa683,
		hl:      0x259c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x22e6,
		iy:      0x33bb,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x22b2, 0x9c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb8e": fuseTest{
		name:    "ddcb8e",
		af:      0xf4f4,
		bc:      0xf3a8,
		de:      0x2843,
		hl:      0x82cb,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd2e8,
		iy:      0xd367,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd2f2, 0x01},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb8f": fuseTest{
		name:    "ddcb8f",
		af:      0x941a,
		bc:      0x8ae2,
		de:      0x269b,
		hl:      0xcb2f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3ffe,
		iy:      0x75dd,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4079, 0x94},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb90": fuseTest{
		name:    "ddcb90",
		af:      0xc167,
		bc:      0x42fc,
		de:      0x42e7,
		hl:      0x9e14,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb501,
		iy:      0x84fe,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb505, 0x42},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb91": fuseTest{
		name:       "ddcb91",
		af:         0xe85e,
		bc:         0xcc83,
		de:         0xd249,
		hl:         0xea3b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc987,
		iy:         0xc4d1,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb92": fuseTest{
		name:       "ddcb92",
		af:         0x28a3,
		bc:         0x85ff,
		de:         0xaa28,
		hl:         0x47a5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9166,
		iy:         0xe755,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb93": fuseTest{
		name:       "ddcb93",
		af:         0x58ac,
		bc:         0xc88b,
		de:         0x6d93,
		hl:         0xdbdd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xac2e,
		iy:         0x5199,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb94": fuseTest{
		name:    "ddcb94",
		af:      0xe38d,
		bc:      0x35a5,
		de:      0x8d07,
		hl:      0xb3b8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5e84,
		iy:      0x5f24,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5e95, 0xb3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb95": fuseTest{
		name:    "ddcb95",
		af:      0x41f4,
		bc:      0x9536,
		de:      0xdd7d,
		hl:      0x49c2,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfb74,
		iy:      0xf17d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xfb5a, 0xc2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb96": fuseTest{
		name:    "ddcb96",
		af:      0x4a9e,
		bc:      0x42ef,
		de:      0x32d7,
		hl:      0x18cf,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7a81,
		iy:      0xbb1d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7a56, 0xaa},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb97": fuseTest{
		name:       "ddcb97",
		af:         0x23d3,
		bc:         0x89f0,
		de:         0x73c7,
		hl:         0x0b1a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x847c,
		iy:         0x4b86,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb98": fuseTest{
		name:    "ddcb98",
		af:      0x6e22,
		bc:      0x50fd,
		de:      0x9fdc,
		hl:      0x3aed,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x041e,
		iy:      0xfd79,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x03fa, 0x50},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb99": fuseTest{
		name:    "ddcb99",
		af:      0xa132,
		bc:      0x38c6,
		de:      0x1515,
		hl:      0x2830,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x09fd,
		iy:      0x0473,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0a6a, 0xc6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb9a": fuseTest{
		name:    "ddcb9a",
		af:      0x783d,
		bc:      0x8f69,
		de:      0xa0c4,
		hl:      0xe38f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x68a8,
		iy:      0x391d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x6832, 0xa0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb9b": fuseTest{
		name:       "ddcb9b",
		af:         0x955a,
		bc:         0xc7b0,
		de:         0x5362,
		hl:         0xaec6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x06ef,
		iy:         0xe991,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb9c": fuseTest{
		name:    "ddcb9c",
		af:      0xaf69,
		bc:      0xf896,
		de:      0xe791,
		hl:      0x13ee,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x847b,
		iy:      0x59ed,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x84cf, 0x13},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb9d": fuseTest{
		name:    "ddcb9d",
		af:      0x7d1e,
		bc:      0x5009,
		de:      0x1248,
		hl:      0x38e0,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe920,
		iy:      0x4fe6,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe92f, 0xe0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb9e": fuseTest{
		name:    "ddcb9e",
		af:      0xc207,
		bc:      0xb47c,
		de:      0x0e16,
		hl:      0xe17f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd8bb,
		iy:      0xbb99,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd870, 0xe6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcb9f": fuseTest{
		name:       "ddcb9f",
		af:         0xa66b,
		bc:         0x7537,
		de:         0x46bb,
		hl:         0x13c0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe63c,
		iy:         0x1d98,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba0": fuseTest{
		name:    "ddcba0",
		af:      0x0bbe,
		bc:      0x2900,
		de:      0x8609,
		hl:      0x5352,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa2f0,
		iy:      0xda02,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa2f2, 0x29},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba1": fuseTest{
		name:    "ddcba1",
		af:      0xad0a,
		bc:      0xaac2,
		de:      0x0f2d,
		hl:      0x832c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x45bb,
		iy:      0xa22d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x45b0, 0xc2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba2": fuseTest{
		name:       "ddcba2",
		af:         0xf586,
		bc:         0x4a7d,
		de:         0xa1ab,
		hl:         0x26fc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x628b,
		iy:         0x6c4d,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba3": fuseTest{
		name:       "ddcba3",
		af:         0xde5b,
		bc:         0xa284,
		de:         0xd404,
		hl:         0xc92d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x040d,
		iy:         0x12c0,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba4": fuseTest{
		name:       "ddcba4",
		af:         0xdfaa,
		bc:         0xae40,
		de:         0x02c3,
		hl:         0x27b5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfe4d,
		iy:         0xfaa3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba5": fuseTest{
		name:       "ddcba5",
		af:         0x1a15,
		bc:         0x04cb,
		de:         0x4352,
		hl:         0xee6b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7b27,
		iy:         0x38a0,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba6": fuseTest{
		name:       "ddcba6",
		af:         0x5e46,
		bc:         0xb98a,
		de:         0xb822,
		hl:         0x04ca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xae1b,
		iy:         0x8730,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba7": fuseTest{
		name:       "ddcba7",
		af:         0x87ed,
		bc:         0x7b11,
		de:         0x8cb0,
		hl:         0xeb3d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5ec8,
		iy:         0x97cf,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba8": fuseTest{
		name:    "ddcba8",
		af:      0x5173,
		bc:      0x5e89,
		de:      0x070d,
		hl:      0xe8f9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe84f,
		iy:      0x55f0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe81f, 0x5e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcba9": fuseTest{
		name:       "ddcba9",
		af:         0x4fb8,
		bc:         0xcc1f,
		de:         0x3e9a,
		hl:         0x2673,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0fdd,
		iy:         0xaef2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbaa": fuseTest{
		name:       "ddcbaa",
		af:         0xfe76,
		bc:         0x6f96,
		de:         0x50eb,
		hl:         0x0b21,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6747,
		iy:         0x07ba,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbab": fuseTest{
		name:    "ddcbab",
		af:      0x2eb4,
		bc:      0x36f1,
		de:      0x8fcb,
		hl:      0x36af,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6682,
		iy:      0x9d60,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x6698, 0xcb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbac": fuseTest{
		name:       "ddcbac",
		af:         0xaf32,
		bc:         0x8ca8,
		de:         0x6558,
		hl:         0x44d9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa4dd,
		iy:         0xcd1f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbad": fuseTest{
		name:    "ddcbad",
		af:      0xfcc9,
		bc:      0x69a7,
		de:      0x0eed,
		hl:      0xea56,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xeef5,
		iy:      0x3ed2,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xef3e, 0x56},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbae": fuseTest{
		name:       "ddcbae",
		af:         0x5f7a,
		bc:         0x9c20,
		de:         0xf013,
		hl:         0xc4b7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb306,
		iy:         0x15dd,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbaf": fuseTest{
		name:       "ddcbaf",
		af:         0x151e,
		bc:         0x2583,
		de:         0x51fa,
		hl:         0xd427,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3619,
		iy:         0x9cef,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb0": fuseTest{
		name:       "ddcbb0",
		af:         0xf43e,
		bc:         0x1e57,
		de:         0x3bf3,
		hl:         0x0933,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x58d7,
		iy:         0xd89f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb1": fuseTest{
		name:    "ddcbb1",
		af:      0x35ef,
		bc:      0xbb06,
		de:      0xdb46,
		hl:      0x046c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xadd2,
		iy:      0x2b6e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xad58, 0x06},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb2": fuseTest{
		name:    "ddcbb2",
		af:      0xc26c,
		bc:      0xfd32,
		de:      0x087f,
		hl:      0xab6c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe7d0,
		iy:      0x501f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe840, 0x08},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb3": fuseTest{
		name:       "ddcbb3",
		af:         0x36ca,
		bc:         0xb434,
		de:         0xe206,
		hl:         0xf805,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x53fb,
		iy:         0xb191,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb4": fuseTest{
		name:    "ddcbb4",
		af:      0x0a1c,
		bc:      0xab67,
		de:      0x9ca1,
		hl:      0x9d98,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5066,
		iy:      0x320c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x50d1, 0x9d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb5": fuseTest{
		name:    "ddcbb5",
		af:      0xfd6d,
		bc:      0x51c9,
		de:      0x16d6,
		hl:      0x1396,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x146e,
		iy:      0x2148,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x145a, 0x96},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb6": fuseTest{
		name:       "ddcbb6",
		af:         0x1d0b,
		bc:         0x04e8,
		de:         0x109e,
		hl:         0x1dde,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8772,
		iy:         0x8661,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb7": fuseTest{
		name:    "ddcbb7",
		af:      0x1412,
		bc:      0xb87e,
		de:      0x65ba,
		hl:      0xa5c8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6120,
		iy:      0x789d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x60f3, 0x14},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb8": fuseTest{
		name:    "ddcbb8",
		af:      0x8eae,
		bc:      0x0753,
		de:      0xbfa1,
		hl:      0x5e7e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0bf6,
		iy:      0x1e35,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0c09, 0x07},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbb9": fuseTest{
		name:    "ddcbb9",
		af:      0x5fb7,
		bc:      0xa848,
		de:      0xe2d2,
		hl:      0x4117,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0564,
		iy:      0x48a1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x05ba, 0x48},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbba": fuseTest{
		name:       "ddcbba",
		af:         0x7f6a,
		bc:         0x47fe,
		de:         0x3045,
		hl:         0x75de,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf5e0,
		iy:         0x032c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbbb": fuseTest{
		name:    "ddcbbb",
		af:      0xc7e3,
		bc:      0xe49e,
		de:      0x9e49,
		hl:      0x07e7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbd31,
		iy:      0x9d5f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbd20, 0x49},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbbc": fuseTest{
		name:       "ddcbbc",
		af:         0xb430,
		bc:         0x7ac7,
		de:         0xb45f,
		hl:         0x28f7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x638e,
		iy:         0x3173,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbbd": fuseTest{
		name:    "ddcbbd",
		af:      0x4e71,
		bc:      0x6ffa,
		de:      0xa3f9,
		hl:      0xa25d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe3c4,
		iy:      0x02d4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe37d, 0x5d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbbe": fuseTest{
		name:    "ddcbbe",
		af:      0x4af8,
		bc:      0x99a5,
		de:      0xd6fd,
		hl:      0x7a16,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x58d3,
		iy:      0xce54,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5920, 0x68},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbbf": fuseTest{
		name:    "ddcbbf",
		af:      0x6231,
		bc:      0x0320,
		de:      0x134b,
		hl:      0x77c3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1734,
		iy:      0xbc2d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x175a, 0x62},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc0": fuseTest{
		name:    "ddcbc0",
		af:      0x75be,
		bc:      0x9393,
		de:      0x093d,
		hl:      0x1128,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x792e,
		iy:      0x31f7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x792e, 0x93},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc1": fuseTest{
		name:    "ddcbc1",
		af:      0x313f,
		bc:      0x821d,
		de:      0x5fcc,
		hl:      0x42c8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xdccc,
		iy:      0xd87b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdcc3, 0x1d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc2": fuseTest{
		name:    "ddcbc2",
		af:      0xa7e3,
		bc:      0xbf55,
		de:      0x317b,
		hl:      0x0a9d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0cfa,
		iy:      0xea4e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0c7f, 0x31},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc3": fuseTest{
		name:       "ddcbc3",
		af:         0xe076,
		bc:         0x2760,
		de:         0x1edd,
		hl:         0x9968,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5426,
		iy:         0xa1a0,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc4": fuseTest{
		name:       "ddcbc4",
		af:         0xa679,
		bc:         0xcc05,
		de:         0x3f4d,
		hl:         0x2799,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7acd,
		iy:         0x48d7,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc5": fuseTest{
		name:    "ddcbc5",
		af:      0xddfd,
		bc:      0x64d4,
		de:      0x2671,
		hl:      0x3521,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xba99,
		iy:      0xbd98,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xba35, 0x21},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc6": fuseTest{
		name:    "ddcbc6",
		af:      0xb324,
		bc:      0xdc0c,
		de:      0x1e35,
		hl:      0x8cd5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xab2c,
		iy:      0xb6f3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xaaf0, 0xb9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc7": fuseTest{
		name:    "ddcbc7",
		af:      0x9554,
		bc:      0x9e56,
		de:      0x6828,
		hl:      0x3189,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x64cb,
		iy:      0xdfad,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x64c3, 0x95},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc8": fuseTest{
		name:       "ddcbc8",
		af:         0x8aca,
		bc:         0x8f9e,
		de:         0xe652,
		hl:         0x248b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6e7a,
		iy:         0x189a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbc9": fuseTest{
		name:    "ddcbc9",
		af:      0xf15f,
		bc:      0x85bb,
		de:      0xa21f,
		hl:      0x8a59,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb670,
		iy:      0x4f79,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb66b, 0xbb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbca": fuseTest{
		name:       "ddcbca",
		af:         0xdfab,
		bc:         0xa031,
		de:         0x7e78,
		hl:         0xad3a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa887,
		iy:         0x7334,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbcb": fuseTest{
		name:       "ddcbcb",
		af:         0xebd6,
		bc:         0x376e,
		de:         0xc373,
		hl:         0xb10c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa447,
		iy:         0x31d6,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbcc": fuseTest{
		name:       "ddcbcc",
		af:         0x0212,
		bc:         0xdc46,
		de:         0x8f41,
		hl:         0x724e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1f5a,
		iy:         0x07ca,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbcd": fuseTest{
		name:    "ddcbcd",
		af:      0x3344,
		bc:      0xd73c,
		de:      0xd6b8,
		hl:      0x921e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5376,
		iy:      0x6d3a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x535f, 0x1e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbce": fuseTest{
		name:    "ddcbce",
		af:      0x9e47,
		bc:      0xfc93,
		de:      0x9ffc,
		hl:      0xaace,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0313,
		iy:      0x7f66,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0298, 0x12},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbcf": fuseTest{
		name:    "ddcbcf",
		af:      0xb7e8,
		bc:      0xd379,
		de:      0x87d5,
		hl:      0x10b0,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc5d0,
		iy:      0x4f7f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc5b2, 0xb7},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd0": fuseTest{
		name:    "ddcbd0",
		af:      0x3278,
		bc:      0x5514,
		de:      0xd25d,
		hl:      0x1cf8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xad43,
		iy:      0x99fc,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xadc2, 0x55},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd1": fuseTest{
		name:       "ddcbd1",
		af:         0xc0b8,
		bc:         0x372c,
		de:         0x6472,
		hl:         0xd92d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x10b2,
		iy:         0x3074,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd2": fuseTest{
		name:       "ddcbd2",
		af:         0x5bb6,
		bc:         0xcaa8,
		de:         0x9cdb,
		hl:         0xaf84,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb9a1,
		iy:         0x7b5f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd3": fuseTest{
		name:    "ddcbd3",
		af:      0xdb6a,
		bc:      0x4fe2,
		de:      0x9e64,
		hl:      0xa034,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xda36,
		iy:      0x88a0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd9f3, 0x64},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd4": fuseTest{
		name:       "ddcbd4",
		af:         0xcc1c,
		bc:         0xb884,
		de:         0x6ad2,
		hl:         0x5e21,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xef26,
		iy:         0x41de,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd5": fuseTest{
		name:    "ddcbd5",
		af:      0xc41d,
		bc:      0xc8b0,
		de:      0xcacb,
		hl:      0x7675,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8dbc,
		iy:      0xcc25,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8dfd, 0x75},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd6": fuseTest{
		name:    "ddcbd6",
		af:      0x09eb,
		bc:      0x769d,
		de:      0x7e07,
		hl:      0x51f9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5f03,
		iy:      0x6280,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5eed, 0x77},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd7": fuseTest{
		name:    "ddcbd7",
		af:      0x641b,
		bc:      0xee10,
		de:      0xc152,
		hl:      0x2f6d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe725,
		iy:      0xc0d7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe6a5, 0x64},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd8": fuseTest{
		name:    "ddcbd8",
		af:      0xe3dc,
		bc:      0x9e81,
		de:      0xc97b,
		hl:      0xcb42,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb30f,
		iy:      0xb32a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb35b, 0x9e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbd9": fuseTest{
		name:       "ddcbd9",
		af:         0xe9a0,
		bc:         0xa7ef,
		de:         0xa476,
		hl:         0x6057,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2642,
		iy:         0x58a0,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbda": fuseTest{
		name:    "ddcbda",
		af:      0x6787,
		bc:      0x26a7,
		de:      0x8a94,
		hl:      0x11d3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2d76,
		iy:      0x7f80,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2d60, 0x8a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbdb": fuseTest{
		name:    "ddcbdb",
		af:      0xf986,
		bc:      0x6a4b,
		de:      0x6518,
		hl:      0xd2c8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2b7d,
		iy:      0x5847,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2bca, 0x18},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbdc": fuseTest{
		name:    "ddcbdc",
		af:      0x4c9e,
		bc:      0xd94d,
		de:      0x9760,
		hl:      0x4d07,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7ed4,
		iy:      0x5cc5,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7ea7, 0x4d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbdd": fuseTest{
		name:    "ddcbdd",
		af:      0x4b3b,
		bc:      0xd351,
		de:      0x9be9,
		hl:      0x2328,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x58c1,
		iy:      0xe430,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5930, 0x28},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbde": fuseTest{
		name:       "ddcbde",
		af:         0x3b62,
		bc:         0xca1e,
		de:         0xa41a,
		hl:         0x227a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x89d2,
		iy:         0x7011,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbdf": fuseTest{
		name:    "ddcbdf",
		af:      0x7a8a,
		bc:      0x5b42,
		de:      0x50dd,
		hl:      0x4be0,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd227,
		iy:      0x4913,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd216, 0x7a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe0": fuseTest{
		name:    "ddcbe0",
		af:      0x440a,
		bc:      0x563d,
		de:      0xacfc,
		hl:      0xf762,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1c4b,
		iy:      0xb6ba,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1cad, 0x56},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe1": fuseTest{
		name:       "ddcbe1",
		af:         0xc219,
		bc:         0xaa75,
		de:         0xdfbf,
		hl:         0x6f10,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb931,
		iy:         0xd3d6,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe2": fuseTest{
		name:       "ddcbe2",
		af:         0x66d7,
		bc:         0xabd0,
		de:         0x7248,
		hl:         0x8054,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xef50,
		iy:         0x9997,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe3": fuseTest{
		name:       "ddcbe3",
		af:         0x7013,
		bc:         0xe7ed,
		de:         0x7e34,
		hl:         0x57fb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7ec6,
		iy:         0x75eb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe4": fuseTest{
		name:       "ddcbe4",
		af:         0x1108,
		bc:         0x6e70,
		de:         0xf0af,
		hl:         0x340c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x95c7,
		iy:         0x6501,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe5": fuseTest{
		name:    "ddcbe5",
		af:      0x57cc,
		bc:      0x5511,
		de:      0x2696,
		hl:      0xb83e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6ab0,
		iy:      0x0e90,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x6aa2, 0x3e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe6": fuseTest{
		name:    "ddcbe6",
		af:      0x207a,
		bc:      0xa441,
		de:      0x1e03,
		hl:      0xac60,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd866,
		iy:      0x5fdc,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd88b, 0x5c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe7": fuseTest{
		name:    "ddcbe7",
		af:      0xfbc5,
		bc:      0x7fa9,
		de:      0x4e07,
		hl:      0xe02d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2a1b,
		iy:      0x55b7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2a0e, 0xfb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe8": fuseTest{
		name:       "ddcbe8",
		af:         0x6d1c,
		bc:         0xbac4,
		de:         0x93f0,
		hl:         0xa0b4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4bda,
		iy:         0x7761,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbe9": fuseTest{
		name:    "ddcbe9",
		af:      0xebe5,
		bc:      0x0c2a,
		de:      0x1a2a,
		hl:      0x2720,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x72dd,
		iy:      0xa354,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7267, 0x2a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbea": fuseTest{
		name:    "ddcbea",
		af:      0x42d2,
		bc:      0xda7a,
		de:      0x7f7f,
		hl:      0x6da6,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa7e9,
		iy:      0xb933,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa7ed, 0x7f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbeb": fuseTest{
		name:       "ddcbeb",
		af:         0xe945,
		bc:         0x10aa,
		de:         0xf5f3,
		hl:         0x7647,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x16df,
		iy:         0x93fb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbec": fuseTest{
		name:    "ddcbec",
		af:      0x7180,
		bc:      0xbc85,
		de:      0x7dd3,
		hl:      0x2067,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xdd88,
		iy:      0x6a41,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdde8, 0x20},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbed": fuseTest{
		name:       "ddcbed",
		af:         0x6b2f,
		bc:         0x9762,
		de:         0x1f0a,
		hl:         0xdb6b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf772,
		iy:         0x33e3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbee": fuseTest{
		name:       "ddcbee",
		af:         0x79ea,
		bc:         0xdc8a,
		de:         0x7887,
		hl:         0x3baa,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6c28,
		iy:         0xabbc,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbef": fuseTest{
		name:    "ddcbef",
		af:      0x31c3,
		bc:      0x2fc2,
		de:      0x8690,
		hl:      0xa836,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xcc68,
		iy:      0xa8ce,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xcc98, 0x31},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf0": fuseTest{
		name:    "ddcbf0",
		af:      0xb330,
		bc:      0xed69,
		de:      0x362b,
		hl:      0xb515,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x13c0,
		iy:      0x6479,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x13ef, 0xed},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf1": fuseTest{
		name:       "ddcbf1",
		af:         0x94c0,
		bc:         0x9a78,
		de:         0xa0fd,
		hl:         0x7c1d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x47ba,
		iy:         0x8c81,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf2": fuseTest{
		name:    "ddcbf2",
		af:      0x5302,
		bc:      0x9204,
		de:      0x61ec,
		hl:      0xd640,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc947,
		iy:      0x4ef1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc956, 0x61},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf3": fuseTest{
		name:       "ddcbf3",
		af:         0x9950,
		bc:         0xa3d2,
		de:         0x50e4,
		hl:         0x5ccc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1d96,
		iy:         0x7c75,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf4": fuseTest{
		name:       "ddcbf4",
		af:         0x3712,
		bc:         0x1f99,
		de:         0x4863,
		hl:         0xe1de,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1702,
		iy:         0xc042,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf5": fuseTest{
		name:       "ddcbf5",
		af:         0xd83f,
		bc:         0x1ec9,
		de:         0xd0da,
		hl:         0x41c5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xeb3f,
		iy:         0x1ead,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf6": fuseTest{
		name:    "ddcbf6",
		af:      0x4d6c,
		bc:      0x93ac,
		de:      0x810d,
		hl:      0xcfe1,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xdc5a,
		iy:      0xc33c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdcd5, 0xe2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf7": fuseTest{
		name:    "ddcbf7",
		af:      0xe940,
		bc:      0x7887,
		de:      0xb9de,
		hl:      0xc013,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x301e,
		iy:      0x9710,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2fe1, 0xe9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf8": fuseTest{
		name:    "ddcbf8",
		af:      0x8278,
		bc:      0xa8a4,
		de:      0x1e5c,
		hl:      0x4952,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x427f,
		iy:      0x41e1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x42d8, 0xa8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbf9": fuseTest{
		name:    "ddcbf9",
		af:      0xb2df,
		bc:      0xe994,
		de:      0x56c3,
		hl:      0x16ff,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd88f,
		iy:      0x0bab,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd8e4, 0x94},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbfa": fuseTest{
		name:       "ddcbfa",
		af:         0x01f1,
		bc:         0xbc0d,
		de:         0xfe76,
		hl:         0x1510,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9420,
		iy:         0x93a3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbfb": fuseTest{
		name:    "ddcbfb",
		af:      0x709b,
		bc:      0x14eb,
		de:      0xec82,
		hl:      0xb844,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3453,
		iy:      0xf2b0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3402, 0x82},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbfc": fuseTest{
		name:    "ddcbfc",
		af:      0x6c89,
		bc:      0xa96e,
		de:      0xd27b,
		hl:      0x90a7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6139,
		iy:      0xb4c1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x60da, 0x90},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbfd": fuseTest{
		name:       "ddcbfd",
		af:         0xfb3f,
		bc:         0x83f6,
		de:         0x2094,
		hl:         0x33c2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3ed0,
		iy:         0x6f0e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbfe": fuseTest{
		name:       "ddcbfe",
		af:         0xfc42,
		bc:         0x50b7,
		de:         0xe98d,
		hl:         0x3e45,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x41b5,
		iy:         0x3410,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddcbff": fuseTest{
		name:    "ddcbff",
		af:      0xab66,
		bc:      0x94d2,
		de:      0xac90,
		hl:      0x8f45,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0655,
		iy:      0xba29,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0628, 0xab},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dde1": fuseTest{
		name:       "dde1",
		af:         0x8a15,
		bc:         0x6bf0,
		de:         0x0106,
		hl:         0x3dd0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x099a,
		iy:         0x8716,
		sp:         0x5961,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dde3": fuseTest{
		name:    "dde3",
		af:      0x068e,
		bc:      0x58e6,
		de:      0x2713,
		hl:      0x500f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3f15,
		iy:      0x4308,
		sp:      0x57bd,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x57bd, 0x05},
			[]int{0x57be, 0xbe},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dde5": fuseTest{
		name:    "dde5",
		af:      0x7462,
		bc:      0x9b6c,
		de:      0xbfe5,
		hl:      0x0330,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb282,
		iy:      0xe272,
		sp:      0x075f,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0x075f, 0x82},
			[]int{0x0760, 0xb2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"dde9": fuseTest{
		name:       "dde9",
		af:         0x75a7,
		bc:         0x139b,
		de:         0xf9a3,
		hl:         0x94bb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x64f0,
		iy:         0x3433,
		sp:         0x0000,
		pc:         0x64f0,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddf9": fuseTest{
		name:       "ddf9",
		af:         0x8709,
		bc:         0x15dd,
		de:         0x7fa6,
		hl:         0x3c5c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd3a7,
		iy:         0x1d7b,
		sp:         0xd3a7,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ddfd00": fuseTest{
		name:       "ddfd00",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x04,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    16,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"de": fuseTest{
		name:       "de",
		af:         0x4502,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"df": fuseTest{
		name:    "df",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0018,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e0_1": fuseTest{
		name:       "e0_1",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e0_2": fuseTest{
		name:       "e0_2",
		af:         0x009c,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e1": fuseTest{
		name:       "e1",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0xe8ce,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x4145,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e2_1": fuseTest{
		name:       "e2_1",
		af:         0x0083,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e2_2": fuseTest{
		name:       "e2_2",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e3": fuseTest{
		name:    "e3",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0xe18e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0373,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x0373, 0x22},
			[]int{0x0374, 0x4d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e4_1": fuseTest{
		name:    "e4_1",
		af:      0x000a,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e4_2": fuseTest{
		name:       "e4_2",
		af:         0x000e,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e5": fuseTest{
		name:    "e5",
		af:      0x53e3,
		bc:      0x1459,
		de:      0x775f,
		hl:      0x1a2f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xec10,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0xec10, 0x2f},
			[]int{0xec11, 0x1a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e6": fuseTest{
		name:       "e6",
		af:         0x4114,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e7": fuseTest{
		name:    "e7",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0020,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e8_1": fuseTest{
		name:       "e8_1",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e8_2": fuseTest{
		name:       "e8_2",
		af:         0x009c,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"e9": fuseTest{
		name:       "e9",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0xcaba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xcaba,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ea_1": fuseTest{
		name:       "ea_1",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ea_2": fuseTest{
		name:       "ea_2",
		af:         0x0083,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"eb": fuseTest{
		name:       "eb",
		af:         0x0000,
		bc:         0x0000,
		de:         0x942e,
		hl:         0xb879,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ec_1": fuseTest{
		name:    "ec_1",
		af:      0x000e,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ec_2": fuseTest{
		name:       "ec_2",
		af:         0x000a,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed40": fuseTest{
		name:    "ed40",
		af:      0x8329,
		bc:      0x296b,
		de:      0x7034,
		hl:      0x1f2f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0x6b, 0x29},
		},
		portWrites: [][]int{},
	},
	"ed41": fuseTest{
		name:      "ed41",
		af:        0x29a2,
		bc:        0x0881,
		de:        0xd7dd,
		hl:        0xff4e,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x81, 0x08},
		},
	},
	"ed42": fuseTest{
		name:       "ed42",
		af:         0xcb12,
		bc:         0x1c8f,
		de:         0xd456,
		hl:         0x14ce,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed43": fuseTest{
		name:    "ed43",
		af:      0xda36,
		bc:      0x2732,
		de:      0x91cc,
		hl:      0x9798,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5f73,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 20,
		memory: [][]int{
			[]int{0x54c6, 0x32},
			[]int{0x54c7, 0x27},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed44": fuseTest{
		name:       "ed44",
		af:         0x0213,
		bc:         0x040f,
		de:         0xdeb6,
		hl:         0xafc3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5ca8,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed45": fuseTest{
		name:       "ed45",
		af:         0x001d,
		bc:         0x5b63,
		de:         0xa586,
		hl:         0x1451,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x3102,
		pc:         0x221f,
		i:          0x00,
		r:          0x02,
		iff1:       1,
		iff2:       1,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed46": fuseTest{
		name:       "ed46",
		af:         0xb6ec,
		bc:         0x8afb,
		de:         0xce09,
		hl:         0x70a1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x8dea,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed47": fuseTest{
		name:       "ed47",
		af:         0x9a99,
		bc:         0x9e5a,
		de:         0x9913,
		hl:         0xcacc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x9a,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    9,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed48": fuseTest{
		name:    "ed48",
		af:      0xdb2d,
		bc:      0x7d7d,
		de:      0x141d,
		hl:      0x5fb4,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0x1b, 0x7d},
		},
		portWrites: [][]int{},
	},
	"ed49": fuseTest{
		name:      "ed49",
		af:        0x07a5,
		bc:        0x59ec,
		de:        0xf459,
		hl:        0x4316,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xec, 0xec},
		},
	},
	"ed4a": fuseTest{
		name:       "ed4a",
		af:         0x57a8,
		bc:         0x24b5,
		de:         0x83d2,
		hl:         0xbf7e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed4b": fuseTest{
		name:       "ed4b",
		af:         0x650c,
		bc:         0xd4f3,
		de:         0x0448,
		hl:         0xa3b9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xb554,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed4c": fuseTest{
		name:       "ed4c",
		af:         0xaabb,
		bc:         0x7dde,
		de:         0xb049,
		hl:         0x939d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xc7bb,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed4d": fuseTest{
		name:       "ed4d",
		af:         0x1bed,
		bc:         0xc358,
		de:         0x5fd5,
		hl:         0x6093,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x6810,
		pc:         0x7c03,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed4e": fuseTest{
		name:       "ed4e",
		af:         0x8e01,
		bc:         0xe7c6,
		de:         0x880f,
		hl:         0xd2a2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x85da,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed4f": fuseTest{
		name:       "ed4f",
		af:         0x2ae3,
		bc:         0xc115,
		de:         0xeff8,
		hl:         0x9f6d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x2a,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    9,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed50": fuseTest{
		name:    "ed50",
		af:      0x85ac,
		bc:      0xbbcc,
		de:      0xbba8,
		hl:      0xf219,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xcc, 0xbb},
		},
		portWrites: [][]int{},
	},
	"ed51": fuseTest{
		name:      "ed51",
		af:        0x2c4c,
		bc:        0xc0a4,
		de:        0x5303,
		hl:        0xbc25,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xa4, 0x53},
		},
	},
	"ed52": fuseTest{
		name:       "ed52",
		af:         0xfc82,
		bc:         0x1fc8,
		de:         0x47b6,
		hl:         0x92c5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed53": fuseTest{
		name:    "ed53",
		af:      0x1f88,
		bc:      0x4692,
		de:      0x5cb2,
		hl:      0x4915,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x7d8c,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 20,
		memory: [][]int{
			[]int{0x21ff, 0xb2},
			[]int{0x2200, 0x5c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed54": fuseTest{
		name:       "ed54",
		af:         0x5313,
		bc:         0x5661,
		de:         0x547c,
		hl:         0xc322,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xd9eb,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed55": fuseTest{
		name:       "ed55",
		af:         0xb05b,
		bc:         0x5e84,
		de:         0xd6e9,
		hl:         0xcb3e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xd4b6,
		pc:         0xc9ea,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed56": fuseTest{
		name:       "ed56",
		af:         0x5cc0,
		bc:         0x9100,
		de:         0x356b,
		hl:         0x4bfd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x2c93,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         1,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed57": fuseTest{
		name:       "ed57",
		af:         0x1e08,
		bc:         0xdfc7,
		de:         0xa621,
		hl:         0x1022,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x1e,
		r:          0x19,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    9,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed58": fuseTest{
		name:    "ed58",
		af:      0xc900,
		bc:      0x4091,
		de:      0x9e40,
		hl:      0x873a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0x91, 0x40},
		},
		portWrites: [][]int{},
	},
	"ed59": fuseTest{
		name:      "ed59",
		af:        0x388a,
		bc:        0xd512,
		de:        0xecc5,
		hl:        0x93af,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x12, 0xc5},
		},
	},
	"ed5a": fuseTest{
		name:       "ed5a",
		af:         0xa408,
		bc:         0x751c,
		de:         0x19ce,
		hl:         0x1e62,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed5b": fuseTest{
		name:       "ed5b",
		af:         0x5df1,
		bc:         0x982e,
		de:         0x4d84,
		hl:         0xadb9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xf398,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed5c": fuseTest{
		name:       "ed5c",
		af:         0xefbb,
		bc:         0xb86c,
		de:         0x2042,
		hl:         0xc958,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x93dc,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed5d": fuseTest{
		name:       "ed5d",
		af:         0x1152,
		bc:         0x1d20,
		de:         0x3f86,
		hl:         0x64fc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x530a,
		pc:         0xe026,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed5e": fuseTest{
		name:       "ed5e",
		af:         0x611a,
		bc:         0xc8cf,
		de:         0xf215,
		hl:         0xd92b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x4d86,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         2,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed5f": fuseTest{
		name:       "ed5f",
		af:         0xf5a1,
		bc:         0xfc09,
		de:         0x2dfa,
		hl:         0xbab9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0xd7,
		r:          0xf5,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    9,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed60": fuseTest{
		name:    "ed60",
		af:      0x2c08,
		bc:      0x0dae,
		de:      0x621e,
		hl:      0x0d66,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xae, 0x0d},
		},
		portWrites: [][]int{},
	},
	"ed61": fuseTest{
		name:      "ed61",
		af:        0xffa8,
		bc:        0x90ca,
		de:        0x0340,
		hl:        0xd847,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xca, 0xd8},
		},
	},
	"ed62": fuseTest{
		name:       "ed62",
		af:         0xa6bb,
		bc:         0xd9aa,
		de:         0x6623,
		hl:         0xffff,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed63": fuseTest{
		name:    "ed63",
		af:      0x5222,
		bc:      0x88f9,
		de:      0x9d9a,
		hl:      0xe4d3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xa2f0,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 20,
		memory: [][]int{
			[]int{0x6567, 0xd3},
			[]int{0x6568, 0xe4},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed64": fuseTest{
		name:       "ed64",
		af:         0xdf9b,
		bc:         0xe425,
		de:         0x66ac,
		hl:         0xb2a3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f2,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed65": fuseTest{
		name:       "ed65",
		af:         0x63d2,
		bc:         0x1fa1,
		de:         0x0788,
		hl:         0x881c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xf209,
		pc:         0x0eeb,
		i:          0x00,
		r:          0x02,
		iff1:       1,
		iff2:       1,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed66": fuseTest{
		name:       "ed66",
		af:         0x4088,
		bc:         0xa7e1,
		de:         0x3ffd,
		hl:         0x919b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xd193,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed67": fuseTest{
		name:    "ed67",
		af:      0x3324,
		bc:      0xb16a,
		de:      0xa4db,
		hl:      0xb9de,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 18,
		memory: [][]int{
			[]int{0xb9de, 0x69},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed68": fuseTest{
		name:    "ed68",
		af:      0x5320,
		bc:      0x624b,
		de:      0x7311,
		hl:      0x3162,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0x4b, 0x62},
		},
		portWrites: [][]int{},
	},
	"ed69": fuseTest{
		name:      "ed69",
		af:        0xabd8,
		bc:        0x8d2f,
		de:        0x89c7,
		hl:        0xc3d6,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x2f, 0xd6},
		},
	},
	"ed6a": fuseTest{
		name:       "ed6a",
		af:         0xbb9c,
		bc:         0x6fed,
		de:         0x59bb,
		hl:         0x9c80,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed6b": fuseTest{
		name:       "ed6b",
		af:         0x9e35,
		bc:         0xd240,
		de:         0x1998,
		hl:         0xbe3f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x9275,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed6c": fuseTest{
		name:       "ed6c",
		af:         0xf1b3,
		bc:         0x7d5b,
		de:         0xcadb,
		hl:         0x0893,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xd983,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed6d": fuseTest{
		name:       "ed6d",
		af:         0x3860,
		bc:         0x42da,
		de:         0x5935,
		hl:         0xdc10,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5cd5,
		pc:         0x73a9,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed6e": fuseTest{
		name:       "ed6e",
		af:         0x7752,
		bc:         0xbec3,
		de:         0x0457,
		hl:         0x8c95,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xa787,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed6f": fuseTest{
		name:    "ed6f",
		af:      0x6c2d,
		bc:      0x7a7a,
		de:      0xecf0,
		hl:      0x403c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 18,
		memory: [][]int{
			[]int{0x403c, 0x45},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed70": fuseTest{
		name:    "ed70",
		af:      0xc6a1,
		bc:      0xf7d6,
		de:      0xa3cb,
		hl:      0x288d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0xd6, 0xf7},
		},
		portWrites: [][]int{},
	},
	"ed71": fuseTest{
		name:      "ed71",
		af:        0xafa0,
		bc:        0x20b3,
		de:        0x7b33,
		hl:        0x4ac1,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xb3, 0x00},
		},
	},
	"ed72": fuseTest{
		name:       "ed72",
		af:         0x5f3e,
		bc:         0x05cb,
		de:         0x0c6c,
		hl:         0x7daf,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x53db,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed73": fuseTest{
		name:    "ed73",
		af:      0x41c4,
		bc:      0x763a,
		de:      0xecb0,
		hl:      0xee62,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xaed5,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 20,
		memory: [][]int{
			[]int{0x792a, 0xd5},
			[]int{0x792b, 0xae},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed74": fuseTest{
		name:       "ed74",
		af:         0xbcbb,
		bc:         0xf2d2,
		de:         0x8340,
		hl:         0x7e76,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0323,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed75": fuseTest{
		name:       "ed75",
		af:         0x7ca4,
		bc:         0x1615,
		de:         0x5d2a,
		hl:         0xa95b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x7d02,
		pc:         0x4ffd,
		i:          0x00,
		r:          0x02,
		iff1:       1,
		iff2:       1,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed76": fuseTest{
		name:       "ed76",
		af:         0xcabf,
		bc:         0xff9a,
		de:         0xb98c,
		hl:         0xa8e6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xfe8e,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         1,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed78": fuseTest{
		name:    "ed78",
		af:      0xf2a1,
		bc:      0xf206,
		de:      0x2d6a,
		hl:      0xaf16,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 12,
		memory:  [][]int{},
		portReads: [][]int{
			[]int{0x06, 0xf2},
		},
		portWrites: [][]int{},
	},
	"ed79": fuseTest{
		name:      "ed79",
		af:        0xe000,
		bc:        0x4243,
		de:        0x8f7f,
		hl:        0xed90,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   12,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x43, 0xe0},
		},
	},
	"ed7a": fuseTest{
		name:       "ed7a",
		af:         0x32b8,
		bc:         0xd819,
		de:         0xd873,
		hl:         0xeaf2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5d22,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed7b": fuseTest{
		name:       "ed7b",
		af:         0x4f97,
		bc:         0x24b7,
		de:         0xe105,
		hl:         0x1bf2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x48d8,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed7c": fuseTest{
		name:       "ed7c",
		af:         0x2d3b,
		bc:         0x29ca,
		de:         0x9622,
		hl:         0xb452,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0be6,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed7d": fuseTest{
		name:       "ed7d",
		af:         0xecb6,
		bc:         0x073e,
		de:         0xdc1e,
		hl:         0x38d9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x66f2,
		pc:         0xfb4f,
		i:          0x00,
		r:          0x02,
		iff1:       1,
		iff2:       1,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ed7e": fuseTest{
		name:       "ed7e",
		af:         0xb246,
		bc:         0x1a1a,
		de:         0x933a,
		hl:         0x4b8b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x2242,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         2,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"eda0": fuseTest{
		name:    "eda0",
		af:      0x1be5,
		bc:      0x3d10,
		de:      0x95c2,
		hl:      0xd098,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x95c1, 0xb7},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"eda1": fuseTest{
		name:       "eda1",
		af:         0xec0f,
		bc:         0x7665,
		de:         0x537f,
		hl:         0x3bc4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    16,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"eda2": fuseTest{
		name:    "eda2",
		af:      0x019f,
		bc:      0x9982,
		de:      0x5bbd,
		hl:      0x2667,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x2666, 0x9a},
		},
		portReads: [][]int{
			[]int{0x82, 0x9a},
		},
		portWrites: [][]int{},
	},
	"eda2_01": fuseTest{
		name:    "eda2_01",
		af:      0x0000,
		bc:      0x0100,
		de:      0x0000,
		hl:      0x8001,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x8000, 0x02},
		},
		portReads: [][]int{
			[]int{0x00, 0x02},
		},
		portWrites: [][]int{},
	},
	"eda2_02": fuseTest{
		name:    "eda2_02",
		af:      0x0000,
		bc:      0x559a,
		de:      0x0000,
		hl:      0x8001,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x8000, 0x56},
		},
		portReads: [][]int{
			[]int{0x9a, 0x56},
		},
		portWrites: [][]int{},
	},
	"eda2_03": fuseTest{
		name:    "eda2_03",
		af:      0x00bf,
		bc:      0xaacc,
		de:      0x0000,
		hl:      0x8001,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x8000, 0xab},
		},
		portReads: [][]int{
			[]int{0xcc, 0xab},
		},
		portWrites: [][]int{},
	},
	"eda3": fuseTest{
		name:      "eda3",
		af:        0x4233,
		bc:        0x6234,
		de:        0x1e28,
		hl:        0x32fb,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x34, 0xb3},
		},
	},
	"eda3_01": fuseTest{
		name:      "eda3_01",
		af:        0x0044,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0200,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_02": fuseTest{
		name:      "eda3_02",
		af:        0x0040,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0101,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_03": fuseTest{
		name:      "eda3_03",
		af:        0x0044,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0108,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_04": fuseTest{
		name:      "eda3_04",
		af:        0x0046,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x0200,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x80},
		},
	},
	"eda3_05": fuseTest{
		name:      "eda3_05",
		af:        0x0055,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x01fe,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x12},
		},
	},
	"eda3_06": fuseTest{
		name:      "eda3_06",
		af:        0x0051,
		bc:        0x0000,
		de:        0x0000,
		hl:        0x01ff,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x12},
		},
	},
	"eda3_07": fuseTest{
		name:      "eda3_07",
		af:        0x0000,
		bc:        0x0100,
		de:        0x0000,
		hl:        0x0200,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_08": fuseTest{
		name:      "eda3_08",
		af:        0x0004,
		bc:        0x0700,
		de:        0x0000,
		hl:        0x01ff,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_09": fuseTest{
		name:      "eda3_09",
		af:        0x0080,
		bc:        0x8000,
		de:        0x0000,
		hl:        0x0200,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_10": fuseTest{
		name:      "eda3_10",
		af:        0x0084,
		bc:        0x8100,
		de:        0x0000,
		hl:        0x0200,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda3_11": fuseTest{
		name:      "eda3_11",
		af:        0x00a8,
		bc:        0xa800,
		de:        0x0000,
		hl:        0x0200,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x00},
		},
	},
	"eda8": fuseTest{
		name:    "eda8",
		af:      0x2aa4,
		bc:      0x1606,
		de:      0x5937,
		hl:      0x12e7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x5938, 0xd8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"eda9": fuseTest{
		name:       "eda9",
		af:         0x14bf,
		bc:         0xfb41,
		de:         0x0466,
		hl:         0x0dbd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    16,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"edaa": fuseTest{
		name:    "edaa",
		af:      0x2097,
		bc:      0xd691,
		de:      0xa912,
		hl:      0xa532,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0xa533, 0xd7},
		},
		portReads: [][]int{
			[]int{0x91, 0xd7},
		},
		portWrites: [][]int{},
	},
	"edaa_01": fuseTest{
		name:    "edaa_01",
		af:      0x0040,
		bc:      0x0001,
		de:      0x0000,
		hl:      0x7fff,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x8000, 0x01},
		},
		portReads: [][]int{
			[]int{0x01, 0x01},
		},
		portWrites: [][]int{},
	},
	"edaa_02": fuseTest{
		name:    "edaa_02",
		af:      0x0000,
		bc:      0x55aa,
		de:      0x0000,
		hl:      0x7fff,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x8000, 0x56},
		},
		portReads: [][]int{
			[]int{0xaa, 0x56},
		},
		portWrites: [][]int{},
	},
	"edaa_03": fuseTest{
		name:    "edaa_03",
		af:      0x00bf,
		bc:      0xaacc,
		de:      0x0000,
		hl:      0x7fff,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 16,
		memory: [][]int{
			[]int{0x8000, 0xab},
		},
		portReads: [][]int{
			[]int{0xcc, 0xab},
		},
		portWrites: [][]int{},
	},
	"edab": fuseTest{
		name:      "edab",
		af:        0x00a4,
		bc:        0xf234,
		de:        0xd3e1,
		hl:        0x199e,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x34, 0x49},
		},
	},
	"edab_01": fuseTest{
		name:      "edab_01",
		af:        0x0000,
		bc:        0x5700,
		de:        0x0000,
		hl:        0x0079,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0x7f},
		},
	},
	"edab_02": fuseTest{
		name:      "edab_02",
		af:        0x00bf,
		bc:        0xaa00,
		de:        0x0000,
		hl:        0x00f0,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x02,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   16,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x00, 0xcd},
		},
	},
	"edb0": fuseTest{
		name:    "edb0",
		af:      0x1049,
		bc:      0x0000,
		de:      0xaae8,
		hl:      0x559e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x20,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 331,
		memory: [][]int{
			[]int{0xaad8, 0x53},
			[]int{0xaad9, 0x94},
			[]int{0xaada, 0x30},
			[]int{0xaadb, 0x05},
			[]int{0xaadc, 0x44},
			[]int{0xaadd, 0x24},
			[]int{0xaade, 0x22},
			[]int{0xaadf, 0xb9},
			[]int{0xaae0, 0xe9},
			[]int{0xaae1, 0x77},
			[]int{0xaae2, 0x23},
			[]int{0xaae3, 0x71},
			[]int{0xaae4, 0xe2},
			[]int{0xaae5, 0x5c},
			[]int{0xaae6, 0xfb},
			[]int{0xaae7, 0x49},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"edb1": fuseTest{
		name:       "edb1",
		af:         0xf447,
		bc:         0x0004,
		de:         0xe4e0,
		hl:         0x9829,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x08,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    79,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"edb2": fuseTest{
		name:    "edb2",
		af:      0x8a40,
		bc:      0x0040,
		de:      0xd98c,
		hl:      0x37d8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x14,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 205,
		memory: [][]int{
			[]int{0x37ce, 0x0a},
			[]int{0x37cf, 0x09},
			[]int{0x37d0, 0x08},
			[]int{0x37d1, 0x07},
			[]int{0x37d2, 0x06},
			[]int{0x37d3, 0x05},
			[]int{0x37d4, 0x04},
			[]int{0x37d5, 0x03},
			[]int{0x37d6, 0x02},
			[]int{0x37d7, 0x01},
		},
		portReads: [][]int{
			[]int{0x40, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01},
		},
		portWrites: [][]int{},
	},
	"edb3": fuseTest{
		name:      "edb3",
		af:        0x3453,
		bc:        0x00e0,
		de:        0x41b9,
		hl:        0x1d7f,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x06,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   58,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0xe0, 0xaa},
		},
	},
	"edb8": fuseTest{
		name:    "edb8",
		af:      0xe569,
		bc:      0x0000,
		de:      0x68e0,
		hl:      0x4dc7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x10,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 163,
		memory: [][]int{
			[]int{0x68e1, 0x29},
			[]int{0x68e2, 0x85},
			[]int{0x68e3, 0xa7},
			[]int{0x68e4, 0xc3},
			[]int{0x68e5, 0x55},
			[]int{0x68e6, 0x74},
			[]int{0x68e7, 0x23},
			[]int{0x68e8, 0x0a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"edb9": fuseTest{
		name:       "edb9",
		af:         0xff0b,
		bc:         0x0000,
		de:         0xa171,
		hl:         0xc741,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x10,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    163,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"edba": fuseTest{
		name:    "edba",
		af:      0x2540,
		bc:      0x009f,
		de:      0xd40d,
		hl:      0x6b4f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x0000,
		pc:      0x0002,
		i:       0x00,
		r:       0x0c,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 121,
		memory: [][]int{
			[]int{0x6b50, 0x01},
			[]int{0x6b51, 0x02},
			[]int{0x6b52, 0x03},
			[]int{0x6b53, 0x04},
			[]int{0x6b54, 0x05},
			[]int{0x6b55, 0x06},
		},
		portReads: [][]int{
			[]int{0x9f, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01},
		},
		portWrites: [][]int{},
	},
	"edbb": fuseTest{
		name:      "edbb",
		af:        0x0957,
		bc:        0x003b,
		de:        0xbe49,
		hl:        0x1dcc,
		af1:       0x0000,
		bc1:       0x0000,
		de1:       0x0000,
		hl1:       0x0000,
		ix:        0x0000,
		iy:        0x0000,
		sp:        0x0000,
		pc:        0x0002,
		i:         0x00,
		r:         0x08,
		iff1:      0,
		iff2:      0,
		im:        0,
		halt:      0,
		tstates:   79,
		memory:    [][]int{},
		portReads: [][]int{},
		portWrites: [][]int{
			[]int{0x3b, 0xf9},
		},
	},
	"ee": fuseTest{
		name:       "ee",
		af:         0xeeac,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ef": fuseTest{
		name:    "ef",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0028,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f0_1": fuseTest{
		name:       "f0_1",
		af:         0x0018,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f0_2": fuseTest{
		name:       "f0_2",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f1": fuseTest{
		name:       "f1",
		af:         0xe8ce,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x4145,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f2_1": fuseTest{
		name:       "f2_1",
		af:         0x0007,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f2_2": fuseTest{
		name:       "f2_2",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f3": fuseTest{
		name:       "f3",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f4_1": fuseTest{
		name:    "f4_1",
		af:      0x000e,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f4_2": fuseTest{
		name:       "f4_2",
		af:         0x008e,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f5": fuseTest{
		name:    "f5",
		af:      0x53e3,
		bc:      0x1459,
		de:      0x775f,
		hl:      0x1a2f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0xec10,
		pc:      0x0001,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0xec10, 0xe3},
			[]int{0xec11, 0x53},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f6": fuseTest{
		name:       "f6",
		af:         0xa7a0,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f7": fuseTest{
		name:    "f7",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0030,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f8_1": fuseTest{
		name:       "f8_1",
		af:         0x0018,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f7,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    5,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f8_2": fuseTest{
		name:       "f8_2",
		af:         0x0098,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x43f9,
		pc:         0xafe9,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"f9": fuseTest{
		name:       "f9",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0xce32,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0xce32,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    6,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fa_1": fuseTest{
		name:       "fa_1",
		af:         0x0087,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0xe11b,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fa_2": fuseTest{
		name:       "fa_2",
		af:         0x0007,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fb": fuseTest{
		name:       "fb",
		af:         0x0000,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0001,
		i:          0x00,
		r:          0x01,
		iff1:       1,
		iff2:       1,
		im:         0,
		halt:       0,
		tstates:    4,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fc_1": fuseTest{
		name:    "fc_1",
		af:      0x008e,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5696,
		pc:      0x9c61,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 17,
		memory: [][]int{
			[]int{0x5696, 0x03},
			[]int{0x5697, 0x00},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fc_2": fuseTest{
		name:       "fc_2",
		af:         0x000e,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x5698,
		pc:         0x0003,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd09": fuseTest{
		name:       "fd09",
		af:         0x4649,
		bc:         0xa623,
		de:         0xbab2,
		hl:         0xd788,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc9e8,
		iy:         0x9cbb,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd19": fuseTest{
		name:       "fd19",
		af:         0xb3ec,
		bc:         0x5336,
		de:         0x76cb,
		hl:         0x54e2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb9ce,
		iy:         0xfcef,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd21": fuseTest{
		name:       "fd21",
		af:         0xc924,
		bc:         0x5c83,
		de:         0xe0e2,
		hl:         0xeddb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6e9f,
		iy:         0x4746,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd22": fuseTest{
		name:    "fd22",
		af:      0x1235,
		bc:      0xf0b6,
		de:      0xb74c,
		hl:      0xcc9f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8b00,
		iy:      0x81e4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 20,
		memory: [][]int{
			[]int{0xe29a, 0xe4},
			[]int{0xe29b, 0x81},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd23": fuseTest{
		name:       "fd23",
		af:         0x69f2,
		bc:         0xc1d3,
		de:         0x0f6f,
		hl:         0x2169,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe39e,
		iy:         0x2606,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd24": fuseTest{
		name:       "fd24",
		af:         0x5520,
		bc:         0x9684,
		de:         0xd36a,
		hl:         0xdac3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7803,
		iy:         0x6534,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd25": fuseTest{
		name:       "fd25",
		af:         0xcd03,
		bc:         0xb5e4,
		de:         0xa754,
		hl:         0x9526,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3dcb,
		iy:         0x02b2,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd26": fuseTest{
		name:       "fd26",
		af:         0x2452,
		bc:         0x300b,
		de:         0xb4a1,
		hl:         0x929d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc259,
		iy:         0x7730,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd29": fuseTest{
		name:       "fd29",
		af:         0x5830,
		bc:         0x49d0,
		de:         0xec95,
		hl:         0x011c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xec6c,
		iy:         0xb298,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd2a": fuseTest{
		name:       "fd2a",
		af:         0x0f82,
		bc:         0x3198,
		de:         0x87e3,
		hl:         0x7c1c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1bb4,
		iy:         0xbf92,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd2b": fuseTest{
		name:       "fd2b",
		af:         0xab27,
		bc:         0x942f,
		de:         0x82fa,
		hl:         0x6f2f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9438,
		iy:         0xebbb,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd2c": fuseTest{
		name:       "fd2c",
		af:         0x66a9,
		bc:         0x0ab1,
		de:         0x5656,
		hl:         0xe5a9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5fb9,
		iy:         0x4df8,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd2d": fuseTest{
		name:       "fd2d",
		af:         0x320b,
		bc:         0xf78a,
		de:         0xb906,
		hl:         0x31d0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc72a,
		iy:         0xe91b,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd2e": fuseTest{
		name:       "fd2e",
		af:         0x2114,
		bc:         0x4923,
		de:         0x6e65,
		hl:         0x006c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xda39,
		iy:         0xc049,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    11,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd34": fuseTest{
		name:    "fd34",
		af:      0xd5a0,
		bc:      0x6f24,
		de:      0x7df7,
		hl:      0x74f0,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x365a,
		iy:      0xefc4,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xef7c, 0xe1},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd35": fuseTest{
		name:    "fd35",
		af:      0x8ca2,
		bc:      0x35d8,
		de:      0x7c1a,
		hl:      0x1c0a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x62bb,
		iy:      0xaec6,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xae71, 0xa5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd36": fuseTest{
		name:    "fd36",
		af:      0xe0f9,
		bc:      0xae1f,
		de:      0x4aef,
		hl:      0xc9d5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc0db,
		iy:      0xbdd4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0xbd55, 0xc5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd39": fuseTest{
		name:       "fd39",
		af:         0x2631,
		bc:         0x726f,
		de:         0x9c7f,
		hl:         0xcd46,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xdc45,
		iy:         0x312c,
		sp:         0xdc57,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    15,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd44": fuseTest{
		name:       "fd44",
		af:         0x0e58,
		bc:         0x6892,
		de:         0x3580,
		hl:         0x9be4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1b79,
		iy:         0x685e,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd45": fuseTest{
		name:       "fd45",
		af:         0x6555,
		bc:         0x7788,
		de:         0x5ae8,
		hl:         0xc948,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd7b8,
		iy:         0xa177,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd46": fuseTest{
		name:       "fd46",
		af:         0x87f3,
		bc:         0xc9d5,
		de:         0x5eea,
		hl:         0x830b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xdcee,
		iy:         0x3afc,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd4c": fuseTest{
		name:       "fd4c",
		af:         0x7e6b,
		bc:         0xbd01,
		de:         0x24b6,
		hl:         0xff94,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x862d,
		iy:         0x01d0,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd4d": fuseTest{
		name:       "fd4d",
		af:         0x50cf,
		bc:         0xe3c9,
		de:         0x998e,
		hl:         0xdba2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc4f5,
		iy:         0xc7c9,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd4e": fuseTest{
		name:       "fd4e",
		af:         0x2c0f,
		bc:         0x699d,
		de:         0x748a,
		hl:         0x9290,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x904f,
		iy:         0xbb9a,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd54": fuseTest{
		name:       "fd54",
		af:         0xd7f9,
		bc:         0xf65b,
		de:         0xd401,
		hl:         0xd4c4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4b8e,
		iy:         0xd437,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd55": fuseTest{
		name:       "fd55",
		af:         0xab98,
		bc:         0xfdab,
		de:         0xa94a,
		hl:         0x010e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x126b,
		iy:         0x13a9,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd56": fuseTest{
		name:       "fd56",
		af:         0xd3e8,
		bc:         0xdf10,
		de:         0x7842,
		hl:         0xb641,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa5a0,
		iy:         0xfda2,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd5c": fuseTest{
		name:       "fd5c",
		af:         0x11d5,
		bc:         0xc489,
		de:         0xe2d8,
		hl:         0x434e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3244,
		iy:         0xd8bb,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd5d": fuseTest{
		name:       "fd5d",
		af:         0xe945,
		bc:         0xdbae,
		de:         0x324e,
		hl:         0x4f7e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfa56,
		iy:         0x074e,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd5e": fuseTest{
		name:       "fd5e",
		af:         0x6f3b,
		bc:         0xe9dc,
		de:         0x7a8c,
		hl:         0x14f3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xec76,
		iy:         0x8aaa,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd60": fuseTest{
		name:       "fd60",
		af:         0x8579,
		bc:         0x005d,
		de:         0xd9ee,
		hl:         0xfaee,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x382d,
		iy:         0x0095,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd61": fuseTest{
		name:       "fd61",
		af:         0x5682,
		bc:         0xdbc3,
		de:         0xb495,
		hl:         0x9799,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x85b2,
		iy:         0xc31e,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd62": fuseTest{
		name:       "fd62",
		af:         0x906b,
		bc:         0xf52e,
		de:         0xf3d8,
		hl:         0x1e8c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xddba,
		iy:         0xf302,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd63": fuseTest{
		name:       "fd63",
		af:         0x9d59,
		bc:         0xbeb9,
		de:         0xd826,
		hl:         0x0eaa,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4290,
		iy:         0x26b9,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd64": fuseTest{
		name:       "fd64",
		af:         0x7b0e,
		bc:         0xe394,
		de:         0x8a25,
		hl:         0xcddf,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9784,
		iy:         0x2116,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd65": fuseTest{
		name:       "fd65",
		af:         0xb827,
		bc:         0xeb4f,
		de:         0xf666,
		hl:         0xc52a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6206,
		iy:         0x1f1f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd66": fuseTest{
		name:       "fd66",
		af:         0x9129,
		bc:         0xe4ee,
		de:         0xe3a3,
		hl:         0x77ca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4d93,
		iy:         0x5b24,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd67": fuseTest{
		name:       "fd67",
		af:         0xdb7a,
		bc:         0xb40b,
		de:         0x7b58,
		hl:         0x49fd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x266f,
		iy:         0xdb7b,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd68": fuseTest{
		name:       "fd68",
		af:         0x4d1d,
		bc:         0x4fd9,
		de:         0x783e,
		hl:         0x0745,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0c3d,
		iy:         0x824f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd69": fuseTest{
		name:       "fd69",
		af:         0x1589,
		bc:         0x5ceb,
		de:         0xb5db,
		hl:         0x922a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3c3a,
		iy:         0xdceb,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd6a": fuseTest{
		name:       "fd6a",
		af:         0x607a,
		bc:         0xe035,
		de:         0x5bb9,
		hl:         0xdac0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfc04,
		iy:         0xb55b,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd6b": fuseTest{
		name:       "fd6b",
		af:         0xdb2a,
		bc:         0xe244,
		de:         0x1182,
		hl:         0x096f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x198e,
		iy:         0x9182,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd6c": fuseTest{
		name:       "fd6c",
		af:         0xa0be,
		bc:         0x34ef,
		de:         0x8fcd,
		hl:         0x40a7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4481,
		iy:         0xc2c2,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd6d": fuseTest{
		name:       "fd6d",
		af:         0xfdfc,
		bc:         0x727a,
		de:         0xb839,
		hl:         0x50a6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe782,
		iy:         0x02e5,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd6e": fuseTest{
		name:       "fd6e",
		af:         0xcfd4,
		bc:         0x6ef1,
		de:         0xc07d,
		hl:         0xebf8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb0f9,
		iy:         0xb0a3,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd6f": fuseTest{
		name:       "fd6f",
		af:         0x8e1d,
		bc:         0xa138,
		de:         0xf20a,
		hl:         0x298e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb600,
		iy:         0x0c8e,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd70": fuseTest{
		name:    "fd70",
		af:      0x2677,
		bc:      0x33c5,
		de:      0xc0dc,
		hl:      0x262f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd3dc,
		iy:      0x23a1,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x23f4, 0x33},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd71": fuseTest{
		name:    "fd71",
		af:      0x892e,
		bc:      0x04ae,
		de:      0xd67f,
		hl:      0x81ec,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7757,
		iy:      0xbfab,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0xbf5f, 0xae},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd72": fuseTest{
		name:    "fd72",
		af:      0xd2dc,
		bc:      0xc23c,
		de:      0xdd54,
		hl:      0x6559,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb32b,
		iy:      0x7c80,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x7c63, 0xdd},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd73": fuseTest{
		name:    "fd73",
		af:      0x49ef,
		bc:      0xbff2,
		de:      0x8409,
		hl:      0x02dd,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xaf95,
		iy:      0x8762,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x8779, 0x09},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd74": fuseTest{
		name:    "fd74",
		af:      0x9479,
		bc:      0x9817,
		de:      0xfa2e,
		hl:      0x1fe0,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa395,
		iy:      0x92db,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x92d1, 0x1f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd75": fuseTest{
		name:    "fd75",
		af:      0xc8d6,
		bc:      0x6aa4,
		de:      0x180e,
		hl:      0xe37b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x02cf,
		iy:      0x1724,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x16cf, 0x7b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd77": fuseTest{
		name:    "fd77",
		af:      0x6f9e,
		bc:      0x7475,
		de:      0x78ad,
		hl:      0x2b8c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc6b7,
		iy:      0x6b4d,
		sp:      0x0000,
		pc:      0x0003,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 19,
		memory: [][]int{
			[]int{0x6b44, 0x6f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd7c": fuseTest{
		name:       "fd7c",
		af:         0xc628,
		bc:         0x93fc,
		de:         0xa3d4,
		hl:         0xdc9e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x21ac,
		iy:         0xc617,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd7d": fuseTest{
		name:       "fd7d",
		af:         0xb9e5,
		bc:         0x3cbe,
		de:         0x02c3,
		hl:         0x26c2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xca81,
		iy:         0x92b9,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd7e": fuseTest{
		name:       "fd7e",
		af:         0xaa96,
		bc:         0xdaba,
		de:         0x147b,
		hl:         0xf362,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7110,
		iy:         0xd45f,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd84": fuseTest{
		name:       "fd84",
		af:         0x7f2d,
		bc:         0x7cae,
		de:         0xc4da,
		hl:         0x7aee,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x43ee,
		iy:         0xc08e,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd85": fuseTest{
		name:       "fd85",
		af:         0xeba8,
		bc:         0x1dea,
		de:         0x324f,
		hl:         0x84e7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe7a8,
		iy:         0xf799,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd86": fuseTest{
		name:       "fd86",
		af:         0xdd89,
		bc:         0xb882,
		de:         0x43f9,
		hl:         0x3e15,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9781,
		iy:         0x8b33,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd8c": fuseTest{
		name:       "fd8c",
		af:         0x3839,
		bc:         0x42b1,
		de:         0x5e8a,
		hl:         0x081c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xcb58,
		iy:         0x3b4e,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd8d": fuseTest{
		name:       "fd8d",
		af:         0x8f89,
		bc:         0x7750,
		de:         0x8ad6,
		hl:         0x295c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x695c,
		iy:         0x99fb,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd8e": fuseTest{
		name:       "fd8e",
		af:         0x0101,
		bc:         0x398f,
		de:         0xf6dc,
		hl:         0x06f3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf34a,
		iy:         0x1aa2,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd94": fuseTest{
		name:       "fd94",
		af:         0x2f3b,
		bc:         0xd255,
		de:         0xb9d6,
		hl:         0x20bb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1e6a,
		iy:         0xd5ef,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd95": fuseTest{
		name:       "fd95",
		af:         0xf4a3,
		bc:         0xb455,
		de:         0x2388,
		hl:         0xec1e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7637,
		iy:         0xcb97,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd96": fuseTest{
		name:       "fd96",
		af:         0x2536,
		bc:         0x22ac,
		de:         0x0413,
		hl:         0x4b13,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb44e,
		iy:         0xc08b,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd9c": fuseTest{
		name:       "fd9c",
		af:         0xf3a3,
		bc:         0x3ecf,
		de:         0xced3,
		hl:         0x66ec,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4bff,
		iy:         0xb133,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd9d": fuseTest{
		name:       "fd9d",
		af:         0xfdbb,
		bc:         0x8bd0,
		de:         0x131b,
		hl:         0x3094,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xafc3,
		iy:         0x7409,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fd9e": fuseTest{
		name:       "fd9e",
		af:         0xc583,
		bc:         0x981f,
		de:         0xbb8e,
		hl:         0xd6d5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5c3b,
		iy:         0xf66c,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fda4": fuseTest{
		name:       "fda4",
		af:         0x0054,
		bc:         0x79c0,
		de:         0x2c7c,
		hl:         0x3e06,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7399,
		iy:         0x037a,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fda5": fuseTest{
		name:       "fda5",
		af:         0x0054,
		bc:         0x654d,
		de:         0x9653,
		hl:         0x2b33,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x61a4,
		iy:         0x8f88,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fda6": fuseTest{
		name:       "fda6",
		af:         0x9594,
		bc:         0x40bb,
		de:         0x3742,
		hl:         0x6ff1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xad28,
		iy:         0x659b,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdac": fuseTest{
		name:       "fdac",
		af:         0x2724,
		bc:         0x72e3,
		de:         0xdd4d,
		hl:         0x1b62,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4753,
		iy:         0x5d63,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdad": fuseTest{
		name:       "fdad",
		af:         0xeca8,
		bc:         0x2573,
		de:         0x19cc,
		hl:         0x78fb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5248,
		iy:         0x8391,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdae": fuseTest{
		name:       "fdae",
		af:         0x6b28,
		bc:         0xbc27,
		de:         0x257b,
		hl:         0x5489,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfa59,
		iy:         0x81f8,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdb4": fuseTest{
		name:       "fdb4",
		af:         0xcf8c,
		bc:         0x3461,
		de:         0xf173,
		hl:         0x8ad3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc1a2,
		iy:         0x8265,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdb5": fuseTest{
		name:       "fdb5",
		af:         0x3720,
		bc:         0xe6ea,
		de:         0xf919,
		hl:         0x327c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4299,
		iy:         0x9733,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdb6": fuseTest{
		name:       "fdb6",
		af:         0xffac,
		bc:         0x3509,
		de:         0xd6ca,
		hl:         0xb16a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa099,
		iy:         0xdf6d,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdbc": fuseTest{
		name:       "fdbc",
		af:         0xb49a,
		bc:         0x9302,
		de:         0xe35d,
		hl:         0x31bc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5c12,
		iy:         0x1c92,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdbd": fuseTest{
		name:       "fdbd",
		af:         0x391a,
		bc:         0x7b82,
		de:         0xdfeb,
		hl:         0x03ee,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xbe7b,
		iy:         0xb30f,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdbe": fuseTest{
		name:       "fdbe",
		af:         0x0903,
		bc:         0x0b31,
		de:         0xf4ad,
		hl:         0x9d4c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb95a,
		iy:         0xa96b,
		sp:         0x0000,
		pc:         0x0003,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    19,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb00": fuseTest{
		name:    "fdcb00",
		af:      0x85a4,
		bc:      0xa0d0,
		de:      0xa135,
		hl:      0x20c5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb8de,
		iy:      0x2776,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2781, 0xa0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb01": fuseTest{
		name:    "fdcb01",
		af:      0x5781,
		bc:      0x2b97,
		de:      0x3576,
		hl:      0x280a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xae22,
		iy:      0x5c35,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5bfd, 0x97},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb02": fuseTest{
		name:    "fdcb02",
		af:      0xdca0,
		bc:      0x2b37,
		de:      0xb0c8,
		hl:      0x5dd9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb2d2,
		iy:      0x3df2,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3e06, 0xb0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb03": fuseTest{
		name:    "fdcb03",
		af:      0x5720,
		bc:      0xc179,
		de:      0xb234,
		hl:      0x7058,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3f2e,
		iy:      0x57e7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5821, 0x34},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb04": fuseTest{
		name:    "fdcb04",
		af:      0xed21,
		bc:      0x3f03,
		de:      0x3327,
		hl:      0x255a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xcbf2,
		iy:      0x5071,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x50d8, 0x25},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb05": fuseTest{
		name:    "fdcb05",
		af:      0x7a8c,
		bc:      0x0858,
		de:      0xdb6c,
		hl:      0xdbcc,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x157a,
		iy:      0xb25b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb279, 0xcc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb06": fuseTest{
		name:    "fdcb06",
		af:      0xf2a1,
		bc:      0x89a2,
		de:      0xe78f,
		hl:      0xef74,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x140d,
		iy:      0xff27,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xff99, 0xe3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb07": fuseTest{
		name:    "fdcb07",
		af:      0x5d09,
		bc:      0xf3a7,
		de:      0x3a6e,
		hl:      0x8f0a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8423,
		iy:      0x07eb,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x080f, 0x5d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb08": fuseTest{
		name:    "fdcb08",
		af:      0xa681,
		bc:      0xc1ec,
		de:      0xc958,
		hl:      0x7bda,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x194d,
		iy:      0x6137,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x615c, 0xc1},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb09": fuseTest{
		name:    "fdcb09",
		af:      0x5485,
		bc:      0xfa93,
		de:      0x84e8,
		hl:      0x4fa5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1ad3,
		iy:      0x19da,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x197a, 0x93},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb0a": fuseTest{
		name:    "fdcb0a",
		af:      0xb389,
		bc:      0xa2bb,
		de:      0x8cd6,
		hl:      0x9617,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf946,
		iy:      0xeef6,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xeed7, 0x8c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb0b": fuseTest{
		name:    "fdcb0b",
		af:      0xae28,
		bc:      0x8c4e,
		de:      0xe179,
		hl:      0x1c54,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe108,
		iy:      0xc68f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc69b, 0x79},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb0c": fuseTest{
		name:    "fdcb0c",
		af:      0x8700,
		bc:      0x6b16,
		de:      0x4c3b,
		hl:      0x570a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x175a,
		iy:      0x8c9d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8c74, 0x57},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb0d": fuseTest{
		name:    "fdcb0d",
		af:      0x128d,
		bc:      0xe0cb,
		de:      0x3ab1,
		hl:      0x248d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1de4,
		iy:      0xfe2d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xfe3e, 0x8d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb0e": fuseTest{
		name:    "fdcb0e",
		af:      0x8da9,
		bc:      0x8f91,
		de:      0xfc5a,
		hl:      0x5e2c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb2f2,
		iy:      0xf223,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf22f, 0xfb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb0f": fuseTest{
		name:    "fdcb0f",
		af:      0x2224,
		bc:      0x2ac9,
		de:      0xec6b,
		hl:      0x6511,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc93a,
		iy:      0xce38,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xce4d, 0x22},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb10": fuseTest{
		name:    "fdcb10",
		af:      0x252c,
		bc:      0x3952,
		de:      0x590d,
		hl:      0xac66,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x144f,
		iy:      0x42a2,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x431c, 0x39},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb11": fuseTest{
		name:    "fdcb11",
		af:      0xbca8,
		bc:      0x61bc,
		de:      0xf5f8,
		hl:      0xaf24,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4019,
		iy:      0x9c90,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9d0b, 0xbc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb12": fuseTest{
		name:    "fdcb12",
		af:      0x4e09,
		bc:      0x3a25,
		de:      0x4f17,
		hl:      0xbcc7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0d7e,
		iy:      0x8537,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8598, 0x4f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb13": fuseTest{
		name:    "fdcb13",
		af:      0xb225,
		bc:      0xb79b,
		de:      0x8466,
		hl:      0xff7d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x414c,
		iy:      0xe798,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe74b, 0x66},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb14": fuseTest{
		name:    "fdcb14",
		af:      0xab08,
		bc:      0x451a,
		de:      0xfc65,
		hl:      0x0da1,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0f4d,
		iy:      0xd93c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd900, 0x0d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb15": fuseTest{
		name:    "fdcb15",
		af:      0x2824,
		bc:      0x9532,
		de:      0x8631,
		hl:      0x7524,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe327,
		iy:      0x2d7b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2d92, 0x24},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb16": fuseTest{
		name:    "fdcb16",
		af:      0x0c05,
		bc:      0xdcd7,
		de:      0xadcc,
		hl:      0x196d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x87e2,
		iy:      0xf0b4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf0d7, 0x12},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb17": fuseTest{
		name:    "fdcb17",
		af:      0x7125,
		bc:      0xd016,
		de:      0x066e,
		hl:      0x6638,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5e92,
		iy:      0x2013,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1f9d, 0x71},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb18": fuseTest{
		name:    "fdcb18",
		af:      0x23a8,
		bc:      0xfd17,
		de:      0x16e0,
		hl:      0x6894,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb908,
		iy:      0x3216,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x31d6, 0xfd},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb19": fuseTest{
		name:    "fdcb19",
		af:      0x11a5,
		bc:      0xc2a5,
		de:      0xa9f3,
		hl:      0x2014,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6db0,
		iy:      0x4d2e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4cd0, 0xa5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb1a": fuseTest{
		name:    "fdcb1a",
		af:      0xbc24,
		bc:      0x6168,
		de:      0x2241,
		hl:      0xb630,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0207,
		iy:      0x40d3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x414b, 0x22},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb1b": fuseTest{
		name:    "fdcb1b",
		af:      0x7a0c,
		bc:      0x1286,
		de:      0xfe5c,
		hl:      0xc42d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe290,
		iy:      0x71b0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x71c6, 0x5c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb1c": fuseTest{
		name:    "fdcb1c",
		af:      0x9381,
		bc:      0x097b,
		de:      0x6928,
		hl:      0xc7a3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xff2d,
		iy:      0xdf62,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdee8, 0xc7},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb1d": fuseTest{
		name:    "fdcb1d",
		af:      0x978d,
		bc:      0x2b30,
		de:      0x2645,
		hl:      0x04db,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x186a,
		iy:      0xd667,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd68e, 0xdb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb1e": fuseTest{
		name:    "fdcb1e",
		af:      0x2f81,
		bc:      0x2470,
		de:      0xb521,
		hl:      0x6ca3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1066,
		iy:      0xda38,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xda72, 0x92},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb1f": fuseTest{
		name:    "fdcb1f",
		af:      0x8284,
		bc:      0x49a3,
		de:      0xda18,
		hl:      0x3afd,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa4f1,
		iy:      0x2095,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2110, 0x82},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb20": fuseTest{
		name:    "fdcb20",
		af:      0x3d05,
		bc:      0x128f,
		de:      0x206f,
		hl:      0x8894,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xddab,
		iy:      0xda25,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xda9f, 0x12},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb21": fuseTest{
		name:    "fdcb21",
		af:      0x1600,
		bc:      0x6046,
		de:      0x641a,
		hl:      0x6598,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x473b,
		iy:      0xde36,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdeb1, 0x46},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb22": fuseTest{
		name:    "fdcb22",
		af:      0xada9,
		bc:      0xefb2,
		de:      0xa803,
		hl:      0xe732,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc11d,
		iy:      0x8926,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x88c0, 0xa8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb23": fuseTest{
		name:    "fdcb23",
		af:      0x218c,
		bc:      0xd678,
		de:      0xa7ca,
		hl:      0x25d7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4ca8,
		iy:      0x5255,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x524a, 0xca},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb24": fuseTest{
		name:    "fdcb24",
		af:      0x1cac,
		bc:      0xda3e,
		de:      0xcc7c,
		hl:      0xfc19,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x572c,
		iy:      0xaffe,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xafb2, 0xfc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb25": fuseTest{
		name:    "fdcb25",
		af:      0x9508,
		bc:      0x097c,
		de:      0xa341,
		hl:      0x894c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x435d,
		iy:      0x23e9,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x238f, 0x4c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb26": fuseTest{
		name:    "fdcb26",
		af:      0x582d,
		bc:      0x0e19,
		de:      0xd277,
		hl:      0xbf7f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6504,
		iy:      0xd4e4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd4a1, 0x7e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb27": fuseTest{
		name:    "fdcb27",
		af:      0x4e0d,
		bc:      0x8c06,
		de:      0x2c4c,
		hl:      0xd7c8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9239,
		iy:      0x8d42,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8d9b, 0x4e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb28": fuseTest{
		name:    "fdcb28",
		af:      0x412d,
		bc:      0x2e9b,
		de:      0x7745,
		hl:      0x76f5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa1bb,
		iy:      0xab43,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xaac6, 0x2e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb29": fuseTest{
		name:    "fdcb29",
		af:      0x0b80,
		bc:      0xafc2,
		de:      0xfea6,
		hl:      0x9478,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x32bb,
		iy:      0x0343,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x03c0, 0xc2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb2a": fuseTest{
		name:    "fdcb2a",
		af:      0xf2ad,
		bc:      0x8c31,
		de:      0xee32,
		hl:      0x7feb,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7db7,
		iy:      0xabe7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xabe0, 0xee},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb2b": fuseTest{
		name:    "fdcb2b",
		af:      0x2425,
		bc:      0x6945,
		de:      0xdc24,
		hl:      0xd643,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5be1,
		iy:      0x4a94,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4adf, 0x24},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb2c": fuseTest{
		name:    "fdcb2c",
		af:      0x110c,
		bc:      0xb32b,
		de:      0xe530,
		hl:      0x1e5a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2416,
		iy:      0xccd1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xccb7, 0x1e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb2d": fuseTest{
		name:    "fdcb2d",
		af:      0xd02c,
		bc:      0x344b,
		de:      0x1bb0,
		hl:      0x3e3c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfe11,
		iy:      0xe4e6,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe545, 0x3c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb2e": fuseTest{
		name:    "fdcb2e",
		af:      0xf481,
		bc:      0xb832,
		de:      0x4b7f,
		hl:      0xe2b7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9386,
		iy:      0x42fd,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4303, 0xd6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb2f": fuseTest{
		name:    "fdcb2f",
		af:      0x0c0c,
		bc:      0xf2c2,
		de:      0x9f2f,
		hl:      0xc946,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5fe0,
		iy:      0x16b8,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x16e1, 0x0c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb30": fuseTest{
		name:    "fdcb30",
		af:      0xac0d,
		bc:      0x4b32,
		de:      0xf9ed,
		hl:      0xcabc,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfabd,
		iy:      0xd646,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd661, 0x4b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb31": fuseTest{
		name:    "fdcb31",
		af:      0x2ba1,
		bc:      0x51e3,
		de:      0x83a7,
		hl:      0x7eee,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7750,
		iy:      0xbfe0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbfd0, 0xe3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb32": fuseTest{
		name:    "fdcb32",
		af:      0xb2a0,
		bc:      0xa4b1,
		de:      0xb385,
		hl:      0xf66e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa9a1,
		iy:      0x5ade,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5aa3, 0xb3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb33": fuseTest{
		name:    "fdcb33",
		af:      0x9ca1,
		bc:      0x2c90,
		de:      0xd0b5,
		hl:      0x2be3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2691,
		iy:      0x1964,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x19e3, 0xb5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb34": fuseTest{
		name:    "fdcb34",
		af:      0x60ad,
		bc:      0xfbcd,
		de:      0x5348,
		hl:      0xa947,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5338,
		iy:      0x5696,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5668, 0xa9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb35": fuseTest{
		name:    "fdcb35",
		af:      0x9604,
		bc:      0x21c6,
		de:      0x4cb6,
		hl:      0xb417,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x673a,
		iy:      0x00f8,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0169, 0x17},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb36": fuseTest{
		name:    "fdcb36",
		af:      0xdc28,
		bc:      0x0892,
		de:      0x3cc7,
		hl:      0x1494,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8598,
		iy:      0x1ade,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1ab8, 0x79},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb37": fuseTest{
		name:    "fdcb37",
		af:      0x3f2d,
		bc:      0x4524,
		de:      0x208f,
		hl:      0x076f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xad10,
		iy:      0xe7ec,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe7b7, 0x3f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb38": fuseTest{
		name:    "fdcb38",
		af:      0x4f05,
		bc:      0x0650,
		de:      0x40c6,
		hl:      0x4fb7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf37e,
		iy:      0xd096,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd024, 0x06},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb39": fuseTest{
		name:    "fdcb39",
		af:      0xbc29,
		bc:      0xf57a,
		de:      0x8dee,
		hl:      0xe514,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x48bc,
		iy:      0xf433,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf4b2, 0x7a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb3a": fuseTest{
		name:    "fdcb3a",
		af:      0xd000,
		bc:      0x2ef5,
		de:      0x5410,
		hl:      0x9ca5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb155,
		iy:      0xcb03,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xcb20, 0x54},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb3b": fuseTest{
		name:    "fdcb3b",
		af:      0x500c,
		bc:      0xa85b,
		de:      0xcf59,
		hl:      0xde8c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9c5b,
		iy:      0xd263,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd268, 0x59},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb3c": fuseTest{
		name:    "fdcb3c",
		af:      0x970c,
		bc:      0x4456,
		de:      0x0b52,
		hl:      0x4bad,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6d2a,
		iy:      0xa80f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa7bd, 0x4b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb3d": fuseTest{
		name:    "fdcb3d",
		af:      0x7d2d,
		bc:      0x9303,
		de:      0xe12b,
		hl:      0xbf7d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4c0f,
		iy:      0xe52a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe53d, 0x7d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb3e": fuseTest{
		name:    "fdcb3e",
		af:      0x0d2c,
		bc:      0x3e02,
		de:      0x8f74,
		hl:      0x0f82,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x85df,
		iy:      0xb2d1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb2ff, 0x28},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb3f": fuseTest{
		name:    "fdcb3f",
		af:      0x3c2c,
		bc:      0x12f6,
		de:      0x426c,
		hl:      0x52d4,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd9f7,
		iy:      0xc1ac,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc1cd, 0x3c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb40": fuseTest{
		name:       "fdcb40",
		af:         0x5410,
		bc:         0x2c34,
		de:         0x6784,
		hl:         0xb376,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8ff9,
		iy:         0x4195,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb41": fuseTest{
		name:       "fdcb41",
		af:         0x8c11,
		bc:         0x5a58,
		de:         0xb71c,
		hl:         0x6777,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xdeca,
		iy:         0x03cb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb42": fuseTest{
		name:       "fdcb42",
		af:         0x555d,
		bc:         0x9c29,
		de:         0x2feb,
		hl:         0x97ff,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7f17,
		iy:         0x9f56,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb43": fuseTest{
		name:       "fdcb43",
		af:         0xb45c,
		bc:         0xe58c,
		de:         0xe62e,
		hl:         0x2a32,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7130,
		iy:         0x1fd1,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb44": fuseTest{
		name:       "fdcb44",
		af:         0xa930,
		bc:         0x68f4,
		de:         0x9fa4,
		hl:         0x7f66,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0209,
		iy:         0xf4f3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb45": fuseTest{
		name:       "fdcb45",
		af:         0x7311,
		bc:         0x8dde,
		de:         0x5e4f,
		hl:         0x84a7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4e24,
		iy:         0x93ed,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb46": fuseTest{
		name:       "fdcb46",
		af:         0x0e74,
		bc:         0xb1f9,
		de:         0x475f,
		hl:         0xebfc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7765,
		iy:         0x63b1,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb47": fuseTest{
		name:       "fdcb47",
		af:         0x9b7d,
		bc:         0x7f38,
		de:         0x0753,
		hl:         0xd5e7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb9c3,
		iy:         0x6e0e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb48": fuseTest{
		name:       "fdcb48",
		af:         0x7d7c,
		bc:         0x50a9,
		de:         0x2511,
		hl:         0x8f9f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb612,
		iy:         0xaba9,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb49": fuseTest{
		name:       "fdcb49",
		af:         0x697c,
		bc:         0x3a39,
		de:         0xb834,
		hl:         0x74b6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0eb7,
		iy:         0x3e21,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb4a": fuseTest{
		name:       "fdcb4a",
		af:         0x3139,
		bc:         0x68e0,
		de:         0xfe2f,
		hl:         0xa2c4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xac96,
		iy:         0xe7db,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb4b": fuseTest{
		name:       "fdcb4b",
		af:         0x0919,
		bc:         0x2453,
		de:         0x9186,
		hl:         0xa32a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x71af,
		iy:         0x883f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb4c": fuseTest{
		name:       "fdcb4c",
		af:         0x4a7c,
		bc:         0x1e5b,
		de:         0xbe2e,
		hl:         0x3ee4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xaf79,
		iy:         0x7f22,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb4d": fuseTest{
		name:       "fdcb4d",
		af:         0x9f75,
		bc:         0x6c8f,
		de:         0x34f4,
		hl:         0x5a79,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd3cc,
		iy:         0xa770,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb4e": fuseTest{
		name:       "fdcb4e",
		af:         0x3031,
		bc:         0x5626,
		de:         0x52bc,
		hl:         0x5503,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x303b,
		iy:         0xe1c8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb4f": fuseTest{
		name:       "fdcb4f",
		af:         0x605c,
		bc:         0xe079,
		de:         0x7152,
		hl:         0x671f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8c22,
		iy:         0x1cf8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb50": fuseTest{
		name:       "fdcb50",
		af:         0x8c10,
		bc:         0x1409,
		de:         0x6d69,
		hl:         0xe5b2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4a0c,
		iy:         0xc75f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb51": fuseTest{
		name:       "fdcb51",
		af:         0x8f75,
		bc:         0x40cb,
		de:         0x9543,
		hl:         0x9b3a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1942,
		iy:         0x3495,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb52": fuseTest{
		name:       "fdcb52",
		af:         0x8919,
		bc:         0x3e41,
		de:         0x7ab4,
		hl:         0x37f6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf82d,
		iy:         0x8b0d,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb53": fuseTest{
		name:       "fdcb53",
		af:         0xef38,
		bc:         0xe345,
		de:         0x09a3,
		hl:         0xf0b2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc378,
		iy:         0x7ee1,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb54": fuseTest{
		name:       "fdcb54",
		af:         0x7218,
		bc:         0xcb82,
		de:         0xd966,
		hl:         0x2fc6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3c00,
		iy:         0x5b6b,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb55": fuseTest{
		name:       "fdcb55",
		af:         0x8530,
		bc:         0xc23b,
		de:         0x6aab,
		hl:         0x9b00,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfe93,
		iy:         0xb4b2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb56": fuseTest{
		name:       "fdcb56",
		af:         0xf539,
		bc:         0xf9f6,
		de:         0x1e8c,
		hl:         0x9e08,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x716a,
		iy:         0x6932,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb57": fuseTest{
		name:       "fdcb57",
		af:         0x3731,
		bc:         0xb7dc,
		de:         0xbe1c,
		hl:         0x38ea,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5e82,
		iy:         0xa3bb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb58": fuseTest{
		name:       "fdcb58",
		af:         0x755c,
		bc:         0x7296,
		de:         0x3ea5,
		hl:         0x1143,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd7cc,
		iy:         0x1e94,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb59": fuseTest{
		name:       "fdcb59",
		af:         0x8038,
		bc:         0xbf2a,
		de:         0x1809,
		hl:         0xed31,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfe2b,
		iy:         0xfad3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb5a": fuseTest{
		name:       "fdcb5a",
		af:         0xcc38,
		bc:         0xa108,
		de:         0x65d4,
		hl:         0x6f66,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0008,
		iy:         0x7bb8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb5b": fuseTest{
		name:       "fdcb5b",
		af:         0x5c75,
		bc:         0xb3bd,
		de:         0x25bd,
		hl:         0x98cf,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2ba1,
		iy:         0x315c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb5c": fuseTest{
		name:       "fdcb5c",
		af:         0xb354,
		bc:         0xd43d,
		de:         0xd9c0,
		hl:         0xb04d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x21a9,
		iy:         0x543e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb5d": fuseTest{
		name:       "fdcb5d",
		af:         0x9f39,
		bc:         0x43dd,
		de:         0xccb3,
		hl:         0x085a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf130,
		iy:         0x3b84,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb5e": fuseTest{
		name:       "fdcb5e",
		af:         0x6f75,
		bc:         0xeff5,
		de:         0x993b,
		hl:         0x22b5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0f30,
		iy:         0xe165,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb5f": fuseTest{
		name:       "fdcb5f",
		af:         0xd774,
		bc:         0xa57a,
		de:         0xaca6,
		hl:         0x667e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x5c33,
		iy:         0xf81b,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb60": fuseTest{
		name:       "fdcb60",
		af:         0x1519,
		bc:         0x8d30,
		de:         0x43f4,
		hl:         0xc65e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1e34,
		iy:         0x8c44,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb61": fuseTest{
		name:       "fdcb61",
		af:         0x7b55,
		bc:         0xd421,
		de:         0x5570,
		hl:         0xcb85,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x32ec,
		iy:         0x92e4,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb62": fuseTest{
		name:       "fdcb62",
		af:         0xba39,
		bc:         0x4fbb,
		de:         0x67a7,
		hl:         0xc5db,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x470b,
		iy:         0x7eb1,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb63": fuseTest{
		name:       "fdcb63",
		af:         0xc011,
		bc:         0x2cc2,
		de:         0xce12,
		hl:         0xe77c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x71c5,
		iy:         0x1713,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb64": fuseTest{
		name:       "fdcb64",
		af:         0x0c75,
		bc:         0x7847,
		de:         0x2494,
		hl:         0x71eb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x315c,
		iy:         0xb336,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb65": fuseTest{
		name:       "fdcb65",
		af:         0x525d,
		bc:         0xa82d,
		de:         0x1112,
		hl:         0x8f09,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x672a,
		iy:         0x89f4,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb66": fuseTest{
		name:       "fdcb66",
		af:         0x5839,
		bc:         0xc13e,
		de:         0xb136,
		hl:         0x6bc5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3ef9,
		iy:         0x6948,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb67": fuseTest{
		name:       "fdcb67",
		af:         0x3130,
		bc:         0x0f7d,
		de:         0x48b5,
		hl:         0xcc5f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2103,
		iy:         0x6572,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb68": fuseTest{
		name:       "fdcb68",
		af:         0xe354,
		bc:         0x39fb,
		de:         0xa03a,
		hl:         0x59bc,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe04a,
		iy:         0x03be,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb69": fuseTest{
		name:       "fdcb69",
		af:         0x1874,
		bc:         0x5bc2,
		de:         0xd4d9,
		hl:         0x4e8a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3716,
		iy:         0xa603,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb6a": fuseTest{
		name:       "fdcb6a",
		af:         0x5b11,
		bc:         0x0099,
		de:         0x34f8,
		hl:         0x3e96,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf251,
		iy:         0x93be,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb6b": fuseTest{
		name:       "fdcb6b",
		af:         0xbb39,
		bc:         0x9e6c,
		de:         0xabd1,
		hl:         0x515f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x73db,
		iy:         0xaa2f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb6c": fuseTest{
		name:       "fdcb6c",
		af:         0x1411,
		bc:         0x3af2,
		de:         0x8f80,
		hl:         0x7be5,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc379,
		iy:         0x86ba,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb6d": fuseTest{
		name:       "fdcb6d",
		af:         0x6330,
		bc:         0xd077,
		de:         0x668d,
		hl:         0x6e4a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb0a8,
		iy:         0x62c8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb6e": fuseTest{
		name:       "fdcb6e",
		af:         0x2d54,
		bc:         0xf872,
		de:         0x692d,
		hl:         0x92c4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x36b5,
		iy:         0x4210,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb6f": fuseTest{
		name:       "fdcb6f",
		af:         0xdf11,
		bc:         0xc7aa,
		de:         0x9002,
		hl:         0x86b8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1347,
		iy:         0x004e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb70": fuseTest{
		name:       "fdcb70",
		af:         0x6e39,
		bc:         0x018d,
		de:         0x5075,
		hl:         0xcf4e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xcd2b,
		iy:         0x3e68,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb71": fuseTest{
		name:       "fdcb71",
		af:         0x1b5c,
		bc:         0xe3af,
		de:         0x94d5,
		hl:         0x0996,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xcad5,
		iy:         0x999a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb72": fuseTest{
		name:       "fdcb72",
		af:         0xe839,
		bc:         0x26b1,
		de:         0x8608,
		hl:         0xf3cb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6323,
		iy:         0xfd31,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb73": fuseTest{
		name:       "fdcb73",
		af:         0x1075,
		bc:         0x446c,
		de:         0xc2f9,
		hl:         0xb9b1,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0820,
		iy:         0xf5d8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb74": fuseTest{
		name:       "fdcb74",
		af:         0x6819,
		bc:         0x38c2,
		de:         0x0ea4,
		hl:         0x0825,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd255,
		iy:         0x5e4a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb75": fuseTest{
		name:       "fdcb75",
		af:         0x5674,
		bc:         0xc034,
		de:         0x6e11,
		hl:         0xd35e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe702,
		iy:         0x60be,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb76": fuseTest{
		name:       "fdcb76",
		af:         0x7375,
		bc:         0xcaff,
		de:         0xdd80,
		hl:         0xc8ed,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7e39,
		iy:         0x6623,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb77": fuseTest{
		name:       "fdcb77",
		af:         0xab18,
		bc:         0x983e,
		de:         0x0bdc,
		hl:         0x3b46,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xae51,
		iy:         0x8841,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb78": fuseTest{
		name:       "fdcb78",
		af:         0x27b9,
		bc:         0xce2f,
		de:         0x4824,
		hl:         0x6930,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xae69,
		iy:         0xfecb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb79": fuseTest{
		name:       "fdcb79",
		af:         0xb498,
		bc:         0x6355,
		de:         0x7896,
		hl:         0x8a7c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9090,
		iy:         0x1cae,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb7a": fuseTest{
		name:       "fdcb7a",
		af:         0x5998,
		bc:         0xca21,
		de:         0x1482,
		hl:         0x3fae,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc6c9,
		iy:         0xd923,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb7b": fuseTest{
		name:       "fdcb7b",
		af:         0x6398,
		bc:         0x0240,
		de:         0x5efa,
		hl:         0x5e7b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3e50,
		iy:         0x0a83,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb7c": fuseTest{
		name:       "fdcb7c",
		af:         0x2254,
		bc:         0xaff4,
		de:         0xb89b,
		hl:         0x4dca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0ac2,
		iy:         0xd371,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb7d": fuseTest{
		name:       "fdcb7d",
		af:         0x1cb9,
		bc:         0xd615,
		de:         0x825a,
		hl:         0x5e64,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x32fb,
		iy:         0xac3b,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb7e": fuseTest{
		name:       "fdcb7e",
		af:         0x5090,
		bc:         0x8dfe,
		de:         0x1019,
		hl:         0x6778,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf7df,
		iy:         0x9484,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb7f": fuseTest{
		name:       "fdcb7f",
		af:         0x1b5d,
		bc:         0x9ec3,
		de:         0x14be,
		hl:         0x5ebe,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1178,
		iy:         0xce69,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    20,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb80": fuseTest{
		name:    "fdcb80",
		af:      0xe196,
		bc:      0xa8ea,
		de:      0x507e,
		hl:      0x6457,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xab75,
		iy:      0x920d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9198, 0xa8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb81": fuseTest{
		name:       "fdcb81",
		af:         0x3d3d,
		bc:         0xb2fa,
		de:         0x8759,
		hl:         0x0cb0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe078,
		iy:         0x82a5,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb82": fuseTest{
		name:    "fdcb82",
		af:      0x4e10,
		bc:      0x5d8d,
		de:      0x9ca0,
		hl:      0xffff,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xee0a,
		iy:      0x5dd8,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5d74, 0x9c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb83": fuseTest{
		name:    "fdcb83",
		af:      0x3c7f,
		bc:      0xfd81,
		de:      0x47d4,
		hl:      0x9f12,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xcbf9,
		iy:      0x374a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3772, 0xd4},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb84": fuseTest{
		name:       "fdcb84",
		af:         0x6872,
		bc:         0x81b1,
		de:         0x1e7a,
		hl:         0xea7e,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9b4c,
		iy:         0xf1c3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb85": fuseTest{
		name:       "fdcb85",
		af:         0x25b3,
		bc:         0x5694,
		de:         0x57cd,
		hl:         0xf3e0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8ed2,
		iy:         0x0433,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb86": fuseTest{
		name:       "fdcb86",
		af:         0x152b,
		bc:         0x8ce1,
		de:         0x818d,
		hl:         0x40f2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9b7a,
		iy:         0x2a50,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb87": fuseTest{
		name:    "fdcb87",
		af:      0x641d,
		bc:      0x5353,
		de:      0x618d,
		hl:      0x3266,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1a53,
		iy:      0x246a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x24c3, 0x64},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb88": fuseTest{
		name:    "fdcb88",
		af:      0x7d14,
		bc:      0xd4ec,
		de:      0x1e47,
		hl:      0x76e1,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3871,
		iy:      0xc60d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc5e1, 0xd4},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb89": fuseTest{
		name:       "fdcb89",
		af:         0x86c3,
		bc:         0x50b0,
		de:         0x8592,
		hl:         0xd6ca,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x947b,
		iy:         0x0a01,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb8a": fuseTest{
		name:       "fdcb8a",
		af:         0x599c,
		bc:         0x961a,
		de:         0xd8f9,
		hl:         0x8470,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd2a5,
		iy:         0xd4d2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb8b": fuseTest{
		name:       "fdcb8b",
		af:         0x2715,
		bc:         0xa209,
		de:         0xabdc,
		hl:         0x3eac,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf352,
		iy:         0xc71e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb8c": fuseTest{
		name:    "fdcb8c",
		af:      0x2818,
		bc:      0x4259,
		de:      0xa9b0,
		hl:      0x65a0,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6471,
		iy:      0xa202,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa199, 0x65},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb8d": fuseTest{
		name:    "fdcb8d",
		af:      0x14e3,
		bc:      0xc330,
		de:      0x9aa2,
		hl:      0x8498,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0d4f,
		iy:      0x5669,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5632, 0x98},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb8e": fuseTest{
		name:    "fdcb8e",
		af:      0xcb79,
		bc:      0x0fff,
		de:      0xb244,
		hl:      0xc902,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6246,
		iy:      0x4c81,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4c43, 0x7d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb8f": fuseTest{
		name:       "fdcb8f",
		af:         0x59b4,
		bc:         0x5fbb,
		de:         0x6c9b,
		hl:         0xd0e3,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xac5a,
		iy:         0x6b51,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb90": fuseTest{
		name:       "fdcb90",
		af:         0x1305,
		bc:         0x70e1,
		de:         0xd627,
		hl:         0x7402,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb470,
		iy:         0xd7f5,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb91": fuseTest{
		name:    "fdcb91",
		af:      0x10df,
		bc:      0xc40a,
		de:      0x0213,
		hl:      0xfc7e,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbfab,
		iy:      0x47d2,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4791, 0x0a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb92": fuseTest{
		name:    "fdcb92",
		af:      0x6a11,
		bc:      0xf89e,
		de:      0xf29d,
		hl:      0xc115,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbc5d,
		iy:      0x313a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3145, 0xf2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb93": fuseTest{
		name:       "fdcb93",
		af:         0x61e5,
		bc:         0xcc2c,
		de:         0x9538,
		hl:         0xb52b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfa64,
		iy:         0x2940,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb94": fuseTest{
		name:       "fdcb94",
		af:         0x31b4,
		bc:         0x3e5a,
		de:         0xfb3d,
		hl:         0x4883,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa801,
		iy:         0xfe1c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb95": fuseTest{
		name:       "fdcb95",
		af:         0x337e,
		bc:         0x63a7,
		de:         0x2918,
		hl:         0xedeb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb12c,
		iy:         0xe776,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb96": fuseTest{
		name:    "fdcb96",
		af:      0x5d99,
		bc:      0xd9ec,
		de:      0xb6d0,
		hl:      0x5ed5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5d9d,
		iy:      0xe6cf,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe66d, 0xf8},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb97": fuseTest{
		name:    "fdcb97",
		af:      0x99b6,
		bc:      0x8406,
		de:      0x72c6,
		hl:      0x1ba7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6dca,
		iy:      0x187f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x18e3, 0x99},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb98": fuseTest{
		name:       "fdcb98",
		af:         0x0495,
		bc:         0x152f,
		de:         0x8000,
		hl:         0xb749,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe9cb,
		iy:         0x43b8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb99": fuseTest{
		name:       "fdcb99",
		af:         0x2824,
		bc:         0xa4b5,
		de:         0xa30b,
		hl:         0xb286,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x10b0,
		iy:         0xd86c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb9a": fuseTest{
		name:    "fdcb9a",
		af:      0xb0cc,
		bc:      0xc40c,
		de:      0x951a,
		hl:      0x014a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2ff9,
		iy:      0xd717,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd6b3, 0x95},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb9b": fuseTest{
		name:       "fdcb9b",
		af:         0xd092,
		bc:         0xa6c2,
		de:         0x7995,
		hl:         0x5448,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfab0,
		iy:         0xcb1e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb9c": fuseTest{
		name:    "fdcb9c",
		af:      0xb58d,
		bc:      0x1ed1,
		de:      0xe93b,
		hl:      0x700c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5605,
		iy:      0x03b3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x03d1, 0x70},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb9d": fuseTest{
		name:       "fdcb9d",
		af:         0xc7e9,
		bc:         0x18d3,
		de:         0x8eed,
		hl:         0xbd53,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9a7f,
		iy:         0xc087,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb9e": fuseTest{
		name:       "fdcb9e",
		af:         0x81c7,
		bc:         0x71df,
		de:         0x45d5,
		hl:         0x0ca7,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x648f,
		iy:         0x41bd,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcb9f": fuseTest{
		name:    "fdcb9f",
		af:      0x81f5,
		bc:      0xdc9f,
		de:      0xd490,
		hl:      0x15be,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0e12,
		iy:      0x9d49,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9d99, 0x81},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba0": fuseTest{
		name:    "fdcba0",
		af:      0x8ccb,
		bc:      0xc457,
		de:      0xbc19,
		hl:      0xe543,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8c5d,
		iy:      0xd68d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd703, 0xc4},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba1": fuseTest{
		name:       "fdcba1",
		af:         0xeee6,
		bc:         0x6dec,
		de:         0x3a20,
		hl:         0x8bba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1de7,
		iy:         0x66c8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba2": fuseTest{
		name:       "fdcba2",
		af:         0x3f89,
		bc:         0x5120,
		de:         0x47d1,
		hl:         0xe669,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2993,
		iy:         0x04bf,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba3": fuseTest{
		name:    "fdcba3",
		af:      0x4439,
		bc:      0x6b8b,
		de:      0x6149,
		hl:      0x1246,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4cdb,
		iy:      0xad77,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xad7c, 0x49},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba4": fuseTest{
		name:       "fdcba4",
		af:         0x3385,
		bc:         0x261e,
		de:         0xa487,
		hl:         0xc5bd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4b8f,
		iy:         0xc0cd,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba5": fuseTest{
		name:       "fdcba5",
		af:         0x6e70,
		bc:         0xb7ed,
		de:         0x22cd,
		hl:         0xae44,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x46de,
		iy:         0xf1a1,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba6": fuseTest{
		name:    "fdcba6",
		af:      0x814b,
		bc:      0x6408,
		de:      0x3dcb,
		hl:      0x971f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5716,
		iy:      0x93f3,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9469, 0xac},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba7": fuseTest{
		name:       "fdcba7",
		af:         0x2ec2,
		bc:         0x679e,
		de:         0xc313,
		hl:         0x61df,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x67e6,
		iy:         0x79c4,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba8": fuseTest{
		name:    "fdcba8",
		af:      0x537c,
		bc:      0x97ed,
		de:      0x6cbb,
		hl:      0xbd26,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc638,
		iy:      0x0d46,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0cef, 0x97},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcba9": fuseTest{
		name:       "fdcba9",
		af:         0xba5a,
		bc:         0x308f,
		de:         0xcdd7,
		hl:         0x298d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x59ab,
		iy:         0x0f54,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbaa": fuseTest{
		name:    "fdcbaa",
		af:      0x406a,
		bc:      0x2ed6,
		de:      0x1a8c,
		hl:      0xc633,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x87cb,
		iy:      0xb3d1,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb3dc, 0x1a},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbab": fuseTest{
		name:       "fdcbab",
		af:         0xda61,
		bc:         0x0521,
		de:         0xa11f,
		hl:         0xc7fa,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb71a,
		iy:         0x8ece,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbac": fuseTest{
		name:       "fdcbac",
		af:         0x34a3,
		bc:         0x81ce,
		de:         0x07d6,
		hl:         0x9ca4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x430b,
		iy:         0x0525,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbad": fuseTest{
		name:    "fdcbad",
		af:      0x5010,
		bc:      0x918e,
		de:      0xddbc,
		hl:      0x4f17,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x88c5,
		iy:      0x948f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x94dd, 0x17},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbae": fuseTest{
		name:    "fdcbae",
		af:      0xec0d,
		bc:      0xb57e,
		de:      0x18c6,
		hl:      0x7b01,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbac6,
		iy:      0x0c1d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0c29, 0x89},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbaf": fuseTest{
		name:       "fdcbaf",
		af:         0x4422,
		bc:         0x6731,
		de:         0xdaad,
		hl:         0x8d38,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xdd8f,
		iy:         0x26eb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb0": fuseTest{
		name:    "fdcbb0",
		af:      0xb984,
		bc:      0x366c,
		de:      0x44b1,
		hl:      0xfef9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4069,
		iy:      0xa0cb,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa125, 0x36},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb1": fuseTest{
		name:    "fdcbb1",
		af:      0x59c3,
		bc:      0xab39,
		de:      0x42ee,
		hl:      0xb764,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x8f7f,
		iy:      0xf398,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xf31a, 0x39},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb2": fuseTest{
		name:    "fdcbb2",
		af:      0xf310,
		bc:      0xceec,
		de:      0x3bfb,
		hl:      0x3569,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4a6f,
		iy:      0x33f9,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x341c, 0x3b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb3": fuseTest{
		name:       "fdcbb3",
		af:         0x9c05,
		bc:         0x0f92,
		de:         0xbd37,
		hl:         0x553d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc75e,
		iy:         0x51d2,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb4": fuseTest{
		name:    "fdcbb4",
		af:      0x3e55,
		bc:      0x1338,
		de:      0x638d,
		hl:      0xa93c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x44ad,
		iy:      0x4d17,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4cdc, 0xa9},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb5": fuseTest{
		name:       "fdcbb5",
		af:         0x2f3a,
		bc:         0xb709,
		de:         0x4167,
		hl:         0x570f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xb543,
		iy:         0x8edd,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb6": fuseTest{
		name:       "fdcbb6",
		af:         0xa887,
		bc:         0x519b,
		de:         0xc91b,
		hl:         0xcc91,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xa416,
		iy:         0x1e16,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb7": fuseTest{
		name:       "fdcbb7",
		af:         0x3835,
		bc:         0xa599,
		de:         0x9fbf,
		hl:         0xc111,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8bc5,
		iy:         0x00a9,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb8": fuseTest{
		name:       "fdcbb8",
		af:         0xd146,
		bc:         0x1738,
		de:         0x1a45,
		hl:         0x8259,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x6a03,
		iy:         0xd087,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbb9": fuseTest{
		name:    "fdcbb9",
		af:      0x757b,
		bc:      0x0b34,
		de:      0x767b,
		hl:      0x2ad1,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1498,
		iy:      0xb84e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb889, 0x34},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbba": fuseTest{
		name:    "fdcbba",
		af:      0x43ef,
		bc:      0x1c58,
		de:      0x56a3,
		hl:      0x4519,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xb67b,
		iy:      0x383f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3877, 0x56},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbbb": fuseTest{
		name:       "fdcbbb",
		af:         0xdccb,
		bc:         0x7ab3,
		de:         0x766e,
		hl:         0x4161,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2942,
		iy:         0xe2fe,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbbc": fuseTest{
		name:    "fdcbbc",
		af:      0x0e07,
		bc:      0x34f5,
		de:      0x0995,
		hl:      0x4f42,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x9d42,
		iy:      0xaf0c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xaf04, 0x4f},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbbd": fuseTest{
		name:    "fdcbbd",
		af:      0x30ef,
		bc:      0xe60c,
		de:      0x9bf0,
		hl:      0xa10d,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xbd1c,
		iy:      0xdf0d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdeb7, 0x0d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbbe": fuseTest{
		name:    "fdcbbe",
		af:      0x1133,
		bc:      0xbef6,
		de:      0x5059,
		hl:      0x1089,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd558,
		iy:      0x3d0f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3cd7, 0x21},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbbf": fuseTest{
		name:    "fdcbbf",
		af:      0x2cd6,
		bc:      0xc893,
		de:      0x8db8,
		hl:      0x716b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0956,
		iy:      0xbde7,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbde4, 0x2c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc0": fuseTest{
		name:    "fdcbc0",
		af:      0x3666,
		bc:      0xed6c,
		de:      0x35e5,
		hl:      0xdb0a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xea93,
		iy:      0x2b31,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x2b3b, 0xed},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc1": fuseTest{
		name:    "fdcbc1",
		af:      0x3902,
		bc:      0xd4ef,
		de:      0xaf62,
		hl:      0x9821,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x48b8,
		iy:      0xbd67,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xbcee, 0xef},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc2": fuseTest{
		name:    "fdcbc2",
		af:      0xad26,
		bc:      0x5a6d,
		de:      0xc362,
		hl:      0x16c9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x495a,
		iy:      0x5b2c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5ab9, 0xc3},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc3": fuseTest{
		name:       "fdcbc3",
		af:         0x3e6c,
		bc:         0x9a74,
		de:         0xa24f,
		hl:         0x9838,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xeafa,
		iy:         0xe666,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc4": fuseTest{
		name:       "fdcbc4",
		af:         0xbf68,
		bc:         0xd00b,
		de:         0x5283,
		hl:         0x61c2,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x517c,
		iy:         0x5d10,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc5": fuseTest{
		name:       "fdcbc5",
		af:         0x127b,
		bc:         0xdb6a,
		de:         0x00b9,
		hl:         0x51cd,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x98f6,
		iy:         0x02bb,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc6": fuseTest{
		name:    "fdcbc6",
		af:      0x35da,
		bc:      0x98c2,
		de:      0x3f57,
		hl:      0x44a4,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2771,
		iy:      0x76c4,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x76b2, 0x83},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc7": fuseTest{
		name:       "fdcbc7",
		af:         0xd73f,
		bc:         0xb86f,
		de:         0x12d3,
		hl:         0x7e2d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xd870,
		iy:         0xf30b,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc8": fuseTest{
		name:    "fdcbc8",
		af:      0x1f81,
		bc:      0xebc0,
		de:      0x85da,
		hl:      0x3cdd,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd854,
		iy:      0xc412,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc422, 0xeb},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbc9": fuseTest{
		name:       "fdcbc9",
		af:         0xed19,
		bc:         0x3fb7,
		de:         0x1370,
		hl:         0xe084,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4fdd,
		iy:         0x8b42,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbca": fuseTest{
		name:    "fdcbca",
		af:      0xc7e5,
		bc:      0x233b,
		de:      0x9212,
		hl:      0xf7f9,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe417,
		iy:      0x5190,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x51aa, 0x92},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbcb": fuseTest{
		name:    "fdcbcb",
		af:      0xbdba,
		bc:      0xa964,
		de:      0xea72,
		hl:      0x9422,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfca3,
		iy:      0x9a72,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x9ad0, 0x72},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbcc": fuseTest{
		name:       "fdcbcc",
		af:         0x0f4f,
		bc:         0x0261,
		de:         0x21b0,
		hl:         0x4e97,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x575d,
		iy:         0x14f9,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbcd": fuseTest{
		name:       "fdcbcd",
		af:         0x1b79,
		bc:         0x8f9f,
		de:         0x31bf,
		hl:         0x9c66,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7ecb,
		iy:         0xbbe9,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbce": fuseTest{
		name:    "fdcbce",
		af:      0x8e13,
		bc:      0x968e,
		de:      0x1784,
		hl:      0x0a0a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1e87,
		iy:      0xb8a2,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb8d8, 0x47},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbcf": fuseTest{
		name:       "fdcbcf",
		af:         0x7a0a,
		bc:         0xa073,
		de:         0xc4ba,
		hl:         0x5b69,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x3b47,
		iy:         0xc29c,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd0": fuseTest{
		name:    "fdcbd0",
		af:      0xe2bb,
		bc:      0x2435,
		de:      0x650c,
		hl:      0x689a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1294,
		iy:      0x3beb,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x3ba7, 0x24},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd1": fuseTest{
		name:    "fdcbd1",
		af:      0x5df8,
		bc:      0xf7bd,
		de:      0x9494,
		hl:      0x4967,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xad00,
		iy:      0x8c65,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8c76, 0xbd},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd2": fuseTest{
		name:    "fdcbd2",
		af:      0x9876,
		bc:      0x4bd9,
		de:      0x5548,
		hl:      0x665a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x7eac,
		iy:      0xc051,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc04c, 0x55},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd3": fuseTest{
		name:    "fdcbd3",
		af:      0x8f90,
		bc:      0xbacd,
		de:      0xe8e4,
		hl:      0x538f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xfe5a,
		iy:      0x0a87,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0ac5, 0xe4},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd4": fuseTest{
		name:       "fdcbd4",
		af:         0x15e2,
		bc:         0x1820,
		de:         0x5588,
		hl:         0x7d7f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x7193,
		iy:         0x9478,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd5": fuseTest{
		name:    "fdcbd5",
		af:      0x1409,
		bc:      0x6535,
		de:      0xc371,
		hl:      0xab9c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x2e10,
		iy:      0x8608,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8650, 0x9c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd6": fuseTest{
		name:       "fdcbd6",
		af:         0x7801,
		bc:         0x78b6,
		de:         0xd191,
		hl:         0x054a,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2065,
		iy:         0x6aa3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd7": fuseTest{
		name:       "fdcbd7",
		af:         0x956a,
		bc:         0x266e,
		de:         0x387f,
		hl:         0x7fcb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x1941,
		iy:         0x36ab,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd8": fuseTest{
		name:       "fdcbd8",
		af:         0x7b1b,
		bc:         0xd891,
		de:         0xefee,
		hl:         0x55b9,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xf789,
		iy:         0x43f8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbd9": fuseTest{
		name:    "fdcbd9",
		af:      0x0faf,
		bc:      0x4efc,
		de:      0xc556,
		hl:      0x6ed3,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x3fc3,
		iy:      0x0a66,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0a7c, 0xfc},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbda": fuseTest{
		name:       "fdcbda",
		af:         0x9ea1,
		bc:         0x8186,
		de:         0x6b45,
		hl:         0xd6e0,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x34d3,
		iy:         0xd0f0,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbdb": fuseTest{
		name:    "fdcbdb",
		af:      0x5ee0,
		bc:      0xbdea,
		de:      0xd01d,
		hl:      0x513f,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x690a,
		iy:      0x8c29,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8ca3, 0x1d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbdc": fuseTest{
		name:    "fdcbdc",
		af:      0x5cfa,
		bc:      0x2e2b,
		de:      0x1d17,
		hl:      0x1df6,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa4f2,
		iy:      0x593a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x599e, 0x1d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbdd": fuseTest{
		name:       "fdcbdd",
		af:         0x8773,
		bc:         0x70a6,
		de:         0x83ce,
		hl:         0x5228,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x35da,
		iy:         0x1d94,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbde": fuseTest{
		name:    "fdcbde",
		af:      0x8310,
		bc:      0xfa01,
		de:      0x6c69,
		hl:      0x252a,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x5291,
		iy:      0xc9e0,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xc9f7, 0x49},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbdf": fuseTest{
		name:       "fdcbdf",
		af:         0xef0d,
		bc:         0xa722,
		de:         0xe78e,
		hl:         0x50ba,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x9d67,
		iy:         0xeac3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe0": fuseTest{
		name:       "fdcbe0",
		af:         0x10ef,
		bc:         0xb901,
		de:         0x2ca5,
		hl:         0xf752,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4747,
		iy:         0x1507,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe1": fuseTest{
		name:       "fdcbe1",
		af:         0xe4cb,
		bc:         0x6f16,
		de:         0x1c11,
		hl:         0x1426,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x189b,
		iy:         0x0e0d,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe2": fuseTest{
		name:    "fdcbe2",
		af:      0x11a9,
		bc:      0xbae8,
		de:      0xd28b,
		hl:      0xbac4,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd8ed,
		iy:      0xe49c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xe4ec, 0xd2},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe3": fuseTest{
		name:       "fdcbe3",
		af:         0x8832,
		bc:         0x952b,
		de:         0x02ba,
		hl:         0x26ef,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xfb55,
		iy:         0xada8,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe4": fuseTest{
		name:       "fdcbe4",
		af:         0x3989,
		bc:         0x4142,
		de:         0x89e2,
		hl:         0x7b5b,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0bf7,
		iy:         0x5474,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe5": fuseTest{
		name:    "fdcbe5",
		af:      0xe5c5,
		bc:      0xb86d,
		de:      0x41bb,
		hl:      0x315c,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x1a78,
		iy:      0xa52d,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xa507, 0x5c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe6": fuseTest{
		name:    "fdcbe6",
		af:      0xfd89,
		bc:      0xd888,
		de:      0x1e2f,
		hl:      0xddf5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x42f5,
		iy:      0x8b06,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x8b7c, 0x55},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe7": fuseTest{
		name:    "fdcbe7",
		af:      0xb625,
		bc:      0xd3e9,
		de:      0xd4b6,
		hl:      0xaa30,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x88bd,
		iy:      0xb597,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xb5a8, 0xb6},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe8": fuseTest{
		name:    "fdcbe8",
		af:      0x514d,
		bc:      0xf0ab,
		de:      0x37b5,
		hl:      0x57de,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xa4ec,
		iy:      0x0a77,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0a64, 0xf0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbe9": fuseTest{
		name:       "fdcbe9",
		af:         0x974e,
		bc:         0xd22f,
		de:         0xd5cb,
		hl:         0x6bd4,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x158a,
		iy:         0xa84e,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbea": fuseTest{
		name:    "fdcbea",
		af:      0x3ef4,
		bc:      0x3fc6,
		de:      0x3b44,
		hl:      0xe9a4,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc877,
		iy:      0x7593,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7526, 0x3b},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbeb": fuseTest{
		name:    "fdcbeb",
		af:      0x798f,
		bc:      0x5e9b,
		de:      0x9467,
		hl:      0x2e52,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd6ad,
		iy:      0x2411,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x23e1, 0x67},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbec": fuseTest{
		name:    "fdcbec",
		af:      0x38a4,
		bc:      0x07c0,
		de:      0x6cee,
		hl:      0x6915,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf160,
		iy:      0xd2eb,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xd2de, 0x69},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbed": fuseTest{
		name:    "fdcbed",
		af:      0xe0bc,
		bc:      0x70c1,
		de:      0xde35,
		hl:      0x8130,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xd57f,
		iy:      0x0eab,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x0f03, 0x30},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbee": fuseTest{
		name:    "fdcbee",
		af:      0x5fcb,
		bc:      0x9007,
		de:      0x1736,
		hl:      0xaca8,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x4bab,
		iy:      0x42bc,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x42be, 0xf0},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbef": fuseTest{
		name:    "fdcbef",
		af:      0x29e3,
		bc:      0xd344,
		de:      0xcb5b,
		hl:      0xaeb5,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xde5f,
		iy:      0x2272,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x22ca, 0x29},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf0": fuseTest{
		name:    "fdcbf0",
		af:      0x1080,
		bc:      0x6c70,
		de:      0x1b5b,
		hl:      0xa9b7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe89d,
		iy:      0xee9e,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xeee3, 0x6c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf1": fuseTest{
		name:       "fdcbf1",
		af:         0x1702,
		bc:         0xc4dc,
		de:         0xd138,
		hl:         0x316f,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8067,
		iy:         0x4783,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf2": fuseTest{
		name:       "fdcbf2",
		af:         0x732a,
		bc:         0x4cd1,
		de:         0x5efe,
		hl:         0x4814,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x42f1,
		iy:         0xea97,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf3": fuseTest{
		name:    "fdcbf3",
		af:      0x6b97,
		bc:      0x59d3,
		de:      0xf54c,
		hl:      0x7530,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x6670,
		iy:      0x7d90,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x7dc8, 0x4c},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf4": fuseTest{
		name:    "fdcbf4",
		af:      0x7af0,
		bc:      0xa81f,
		de:      0x5d3a,
		hl:      0x4e9b,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe12b,
		iy:      0x309c,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x306c, 0x4e},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf5": fuseTest{
		name:       "fdcbf5",
		af:         0x1370,
		bc:         0xf6b2,
		de:         0xaaa2,
		hl:         0x7ff8,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xc9f6,
		iy:         0x6b1f,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf6": fuseTest{
		name:       "fdcbf6",
		af:         0x7c43,
		bc:         0xfcd1,
		de:         0x34bd,
		hl:         0xf4ab,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xef33,
		iy:         0xc61a,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf7": fuseTest{
		name:       "fdcbf7",
		af:         0x66da,
		bc:         0x231a,
		de:         0x7bb1,
		hl:         0x800d,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xe37e,
		iy:         0x5789,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf8": fuseTest{
		name:    "fdcbf8",
		af:      0xfa29,
		bc:      0xfa74,
		de:      0xd7c4,
		hl:      0xafaf,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x512c,
		iy:      0xde7a,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0xdece, 0xfa},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbf9": fuseTest{
		name:       "fdcbf9",
		af:         0x4662,
		bc:         0xa7c6,
		de:         0x5065,
		hl:         0xed06,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x279e,
		iy:         0x99e3,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbfa": fuseTest{
		name:       "fdcbfa",
		af:         0x9426,
		bc:         0x53ec,
		de:         0xf416,
		hl:         0x6c99,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x8b99,
		iy:         0xbd79,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbfb": fuseTest{
		name:       "fdcbfb",
		af:         0x5343,
		bc:         0xb212,
		de:         0x09ed,
		hl:         0xe3c6,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xcd2b,
		iy:         0xf875,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbfc": fuseTest{
		name:    "fdcbfc",
		af:      0x0965,
		bc:      0x4392,
		de:      0xca25,
		hl:      0xe5aa,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xf023,
		iy:      0x6623,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x6679, 0xe5},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbfd": fuseTest{
		name:    "fdcbfd",
		af:      0x1751,
		bc:      0x233c,
		de:      0x6214,
		hl:      0xd1a7,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xc415,
		iy:      0x5d2b,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x5d50, 0xa7},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbfe": fuseTest{
		name:    "fdcbfe",
		af:      0xb4cf,
		bc:      0x5639,
		de:      0x677b,
		hl:      0x0ca2,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xddc5,
		iy:      0x4e4f,
		sp:      0x0000,
		pc:      0x0004,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x4dd7, 0xca},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdcbff": fuseTest{
		name:       "fdcbff",
		af:         0x9751,
		bc:         0x13da,
		de:         0x7c56,
		hl:         0xf025,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x2b36,
		iy:         0x2aed,
		sp:         0x0000,
		pc:         0x0004,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    23,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fde1": fuseTest{
		name:       "fde1",
		af:         0x828e,
		bc:         0x078b,
		de:         0x1e35,
		hl:         0x8f1c,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x4827,
		iy:         0x92d5,
		sp:         0x7170,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    14,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fde3": fuseTest{
		name:    "fde3",
		af:      0x4298,
		bc:      0xc805,
		de:      0x6030,
		hl:      0x4292,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x473b,
		iy:      0x0fe0,
		sp:      0x1a38,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 23,
		memory: [][]int{
			[]int{0x1a38, 0x10},
			[]int{0x1a39, 0x95},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fde5": fuseTest{
		name:    "fde5",
		af:      0xd139,
		bc:      0xaa0d,
		de:      0xbf2b,
		hl:      0x2a56,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0xe138,
		iy:      0xd4da,
		sp:      0xa8df,
		pc:      0x0002,
		i:       0x00,
		r:       0x02,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 15,
		memory: [][]int{
			[]int{0xa8df, 0xda},
			[]int{0xa8e0, 0xd4},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fde9": fuseTest{
		name:       "fde9",
		af:         0xc14f,
		bc:         0x2eb6,
		de:         0xedf0,
		hl:         0x27cf,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x09ee,
		iy:         0xa2a4,
		sp:         0x0000,
		pc:         0xa2a4,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    8,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fdf9": fuseTest{
		name:       "fdf9",
		af:         0xc260,
		bc:         0x992e,
		de:         0xd544,
		hl:         0x67fb,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0xba5e,
		iy:         0x3596,
		sp:         0x3596,
		pc:         0x0002,
		i:          0x00,
		r:          0x02,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    10,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"fe": fuseTest{
		name:       "fe",
		af:         0x6987,
		bc:         0x0000,
		de:         0x0000,
		hl:         0x0000,
		af1:        0x0000,
		bc1:        0x0000,
		de1:        0x0000,
		hl1:        0x0000,
		ix:         0x0000,
		iy:         0x0000,
		sp:         0x0000,
		pc:         0x0002,
		i:          0x00,
		r:          0x01,
		iff1:       0,
		iff2:       0,
		im:         0,
		halt:       0,
		tstates:    7,
		memory:     [][]int{},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
	"ff": fuseTest{
		name:    "ff",
		af:      0x0000,
		bc:      0x0000,
		de:      0x0000,
		hl:      0x0000,
		af1:     0x0000,
		bc1:     0x0000,
		de1:     0x0000,
		hl1:     0x0000,
		ix:      0x0000,
		iy:      0x0000,
		sp:      0x5505,
		pc:      0x0038,
		i:       0x00,
		r:       0x01,
		iff1:    0,
		iff2:    0,
		im:      0,
		halt:    0,
		tstates: 11,
		memory: [][]int{
			[]int{0x5505, 0x34},
			[]int{0x5506, 0x6d},
		},
		portReads:  [][]int{},
		portWrites: [][]int{},
	},
}


<|start_filename|>rcs/cbm/doc.go<|end_filename|>
// Package cbm contains components for Commodore Business Machines.
package cbm


<|start_filename|>rcs/m6502/dormann_test.go<|end_filename|>
// +build ext

package m6502

import (
	"io/ioutil"
	"log"
	"path/filepath"
	"testing"

	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
)

var (
	sourceDir = filepath.Join(config.ResourceDir(), "ext", "m6502")
)

func TestDormann(t *testing.T) {
	mem := rcs.NewMemory(1, 0x10000)
	ram := make([]uint8, 0x10000, 0x10000)
	code, err := ioutil.ReadFile(filepath.Join(sourceDir, "6502_functional_test.bin"))
	if err != nil {
		t.Fatalf("unable to load test runner: %v", err)
	}

	mem.MapRAM(0x0, ram)
	mem.MapRAM(0x0, code)

	cpu := New(mem)
	cpu.SetPC(0x03ff)
	log.SetFlags(0)
	cpu.WatchBRK = true
	dasm := cpu.NewDisassembler()
	for {
		here := cpu.PC() + cpu.Offset()
		// Success points
		if here == 0x346c || here == 0x3469 {
			break
		}
		dasm.SetPC(here)
		ppc := cpu.PC()
		cpu.Next()
		// If the PC hasn't moved, its a trap
		if ppc == cpu.PC() {
			t.Fatalf("\n[trap]\n%v", cpu)
		}
	}
}


<|start_filename|>rcs/m6502/doc.go<|end_filename|>
// Package m6502 is the MOS Technology 6502 series processor.
package m6502


<|start_filename|>app/monitor/cbm.go<|end_filename|>
package monitor

import (
	"fmt"
	"io/ioutil"
	"log"
	"strings"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/system/c128"
	"github.com/chzyer/readline"
)

type modC64 struct {
	mon *Monitor
}

func newModC64(mon *Monitor, comp rcs.Component) module {
	return &modC64{mon: mon}
}

func (m *modC64) Command(args []string) error {
	if err := checkLen(args, 1, maxArgs); err != nil {
		return err
	}
	switch args[0] {
	case "load-prg":
		return m.cmdLoadPrg(args[1:])
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modC64) cmdLoadPrg(args []string) error {
	if err := checkLen(args, 1, 2); err != nil {
		return err
	}
	// Is this a BASIC program?
	basic := true
	if len(args) == 2 {
		// TODO: "1" because of load "*", 8, 1 which is to use the address
		// found in the PRG header. If so, this probably isn't a BASIC
		// program. Is this actually correct?
		if strings.TrimSpace(args[1]) != "1" {
			return fmt.Errorf("invalid argument: %v", args[1])
		}
		basic = false
	}
	filename := loadPath(args[0])
	if !strings.HasSuffix(filename, ".prg") {
		filename += ".prg"
	}
	data, err := ioutil.ReadFile(filename)
	if err != nil {
		return err
	}
	// Header is two bytes so there must be at least 2 bytes.
	if len(data) < 2 {
		return fmt.Errorf("invalid prg file: %v", filename)
	}
	mem := m.mon.mach.CPU["cpu"].Memory()
	// First two bytes are the memory location where the data should
	// be stored
	addr := int(data[0]) | (int(data[1]) << 8)
	end := addr + len(data) - 2 // minus the address bytes
	for i, d := range data[2:] {
		mem.Write(addr+i, d)
	}
	// Update pointers if this is a BASIC program
	if basic {
		// new start of variables is after the program
		vstart := end + 1
		mem.WriteLE(0x002d, vstart) // basic variable storage
		mem.WriteLE(0x002f, vstart) // basic array storage
	}
	return nil
}

func (m *modC64) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("load-prg",
			readline.PcItemDynamic(acDataFiles(m.mon, ".prg")),
		),
	}
}

func (m *modC64) Silence() error {
	return nil
}

type modC128MMU struct {
	mon *Monitor
	out *log.Logger
	mmu *c128.MMU
}

func newModC128MMU(mon *Monitor, comp rcs.Component) module {
	return &modC128MMU{
		mon: mon,
		out: mon.out,
		mmu: comp.C.(*c128.MMU),
	}
}

func (m *modC128MMU) Command(args []string) error {
	if len(args) == 0 {
		return m.cmdInfo(args[0:])
	}
	switch args[0] {
	case "cr": // configuration register
		return valueFunc8(m.out, m.mmu.ReadCR, m.mmu.WriteCR, args[1:])
	case "info":
		return m.cmdInfo(args[1:])
	// case "mode":
	// 	return valueUint8(m.out, &m.mmu.Mode, args[1:])
	case "watch", "w":
		return m.cmdWatch(args[1:])
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modC128MMU) cmdWatch(args []string) error {
	if err := checkLen(args, 1, 2); err != nil {
		return err
	}
	switch args[0] {
	case "cr": // configuration register
		return valueRW(m.out, &m.mmu.WatchCR, args[1:])
	case "lcr": // load configuration register
		return valueRW(m.out, &m.mmu.WatchLCR, args[1:])
	case "pcr": // pre-configuration register
		return valueRW(m.out, &m.mmu.WatchPCR, args[1:])
	case "all":
		return terminal(args[1:], func() error {
			m.mmu.WatchCR.W = true
			m.mmu.WatchCR.R = true
			m.mmu.WatchLCR.W = true
			m.mmu.WatchLCR.R = true
			m.mmu.WatchPCR.W = true
			m.mmu.WatchPCR.R = true
			return nil
		})
	case "none":
		return terminal(args[1:], m.Silence)
	}
	return fmt.Errorf("invalid argument: %v", args[0])
}

func (m *modC128MMU) cmdInfo(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	info := fmt.Sprintf(`
cr : %v
lcr: %v %v %v %v
pcr: %v %v %v %v
`,
		rcs.X8(uint8(m.mmu.Mem.Bank())),
		rcs.X8(m.mmu.LCR[0]),
		rcs.X8(m.mmu.LCR[1]),
		rcs.X8(m.mmu.LCR[2]),
		rcs.X8(m.mmu.LCR[3]),
		rcs.X8(m.mmu.PCR[0]),
		rcs.X8(m.mmu.PCR[1]),
		rcs.X8(m.mmu.PCR[2]),
		rcs.X8(m.mmu.PCR[3]),
	)
	m.out.Println(strings.TrimSpace(info))
	return nil
}

func (m *modC128MMU) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("cr"),
		// readline.PcItem("mode"),
		readline.PcItem("watch",
			readline.PcItem("cr", acRW...),
			readline.PcItem("lcr", acRW...),
			readline.PcItem("pcr", acRW...),
			readline.PcItem("all"),
			readline.PcItem("none"),
		),
	}
}

func (m *modC128MMU) Silence() error {
	m.mmu.WatchCR.W = false
	m.mmu.WatchCR.R = false
	m.mmu.WatchLCR.W = false
	m.mmu.WatchLCR.R = false
	m.mmu.WatchPCR.W = false
	m.mmu.WatchPCR.R = false
	return nil
}

type modC128VDC struct {
	mon *Monitor
	out *log.Logger
	vdc *c128.VDC
}

func newModC128VDC(mon *Monitor, comp rcs.Component) module {
	return &modC128VDC{
		mon: mon,
		out: mon.out,
		vdc: comp.C.(*c128.VDC),
	}
}

func (m *modC128VDC) Command(args []string) error {
	if len(args) == 0 {
		return m.info(args[0:])
	}
	switch args[0] {
	case "info":
		return m.info(args[1:])
	case "watch", "w":
		return m.cmdWatch(args[1:])
	}
	return fmt.Errorf("no such command: %v", args[0])
}

func (m *modC128VDC) cmdWatch(args []string) error {
	if err := checkLen(args, 1, 2); err != nil {
		return err
	}
	switch args[0] {
	case "address":
		return valueRW(m.out, &m.vdc.WatchAddr, args[1:])
	case "data":
		return valueRW(m.out, &m.vdc.WatchData, args[1:])
	case "all":
		return terminal(args[1:], func() error {
			m.vdc.WatchAddr.W = true
			m.vdc.WatchStatus.R = true
			m.vdc.WatchData.W = true
			m.vdc.WatchData.R = true
			return nil
		})
	case "none":
		return terminal(args[1:], m.Silence)
	}
	return fmt.Errorf("invalid argument: %v", args[0])
}

func (m *modC128VDC) info(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	format := strings.TrimSpace(`
addr  : %v
status: %v %v %v
mempos: %v
vss   : %v %v %v
			`)
	m.out.Printf(format,
		rcs.X8(m.vdc.Addr),
		m.vdc.Status, rcs.X8(m.vdc.Status), rcs.B8(m.vdc.Status),
		rcs.X16(m.vdc.MemPos),
		m.vdc.VSS, rcs.X8(m.vdc.VSS), rcs.B8(m.vdc.VSS),
	)
	return nil
}

func (m *modC128VDC) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("info"),
		readline.PcItem("watch",
			readline.PcItem("address", acRW...),
			readline.PcItem("data", acRW...),
			readline.PcItem("all"),
			readline.PcItem("none"),
		),
	}
}

func (m *modC128VDC) Silence() error {
	m.vdc.WatchAddr.W = false
	m.vdc.WatchStatus.R = false
	m.vdc.WatchData.W = false
	m.vdc.WatchData.R = false
	return nil
}


<|start_filename|>rcs/memory_test.go<|end_filename|>
package rcs

import (
	"bytes"
	"fmt"
	"io/ioutil"
	"log"
	"os"
	"reflect"
	"strings"
	"testing"
)

func TestMemoryUnmapped(t *testing.T) {
	var buf bytes.Buffer
	log.SetFlags(0)
	log.SetOutput(&buf)
	defer func() {
		log.SetFlags(log.LstdFlags)
		log.SetOutput(os.Stderr)
	}()

	mem := NewMemory(1, 0x10000)
	mem.Write(0x1234, 0xaa)
	mem.Read(0x1234)

	msg := []string{
		"(!) mem: unmapped write, bank $0, addr $1234, val $aa",
		"(!) mem: unmapped read, bank $0, addr $1234",
		"",
	}
	have := buf.String()
	want := strings.Join(msg, "\n")
	if have != want {
		t.Errorf("\n have: \n%v \n want: \n%v", have, want)
	}
}

func TestMemoryRAM(t *testing.T) {
	in := []uint8{10, 11, 12, 13, 14}
	ram := make([]uint8, 5, 5)
	out := make([]uint8, 5, 5)
	mem := NewMemory(1, 15)
	mem.MapRAM(10, ram)

	for i := 0; i < 5; i++ {
		mem.Write(i+10, in[i])
	}
	for i := 0; i < 5; i++ {
		out[i] = mem.Read(i + 10)
	}
	if !reflect.DeepEqual(out, in) {
		t.Errorf("\n have: %v \n want: %v", out, in)
	}
}

func TestMemoryROM(t *testing.T) {
	var buf bytes.Buffer
	log.SetFlags(0)
	log.SetOutput(&buf)
	defer func() {
		log.SetFlags(log.LstdFlags)
		log.SetOutput(os.Stderr)
	}()

	rom := []uint8{10, 11, 12, 13, 14}
	out := make([]uint8, 5, 5)
	mem := NewMemory(1, 15)
	mem.MapROM(10, rom)

	for i := 0; i < 5; i++ {
		mem.Write(i+10, 0xff)
		out[i] = mem.Read(i + 10)
	}
	if !reflect.DeepEqual(out, rom) {
		t.Errorf("\n have: %v \n want: %v", out, rom)
	}

	msg := []string{
		"(!) mem: unmapped write, bank $0, addr $a, val $ff",
		"(!) mem: unmapped write, bank $0, addr $b, val $ff",
		"(!) mem: unmapped write, bank $0, addr $c, val $ff",
		"(!) mem: unmapped write, bank $0, addr $d, val $ff",
		"(!) mem: unmapped write, bank $0, addr $e, val $ff",
		"",
	}
	have := buf.String()
	want := strings.Join(msg, "\n")
	if have != want {
		t.Errorf("\n have: \n%v \n want: \n%v", have, want)
	}
}

func TestMemoryMapValue(t *testing.T) {
	in := []uint8{10, 11, 12, 13, 14}
	ram := make([]uint8, 5, 5)
	out := make([]uint8, 5, 5)

	mem := NewMemory(1, 15)
	mem.MapRW(10, &in[0])
	mem.MapRW(11, &in[1])
	mem.MapRW(12, &in[2])
	mem.MapRW(13, &in[3])
	mem.MapRW(14, &in[4])

	for i := 0; i < 5; i++ {
		mem.Write(i+10, ram[i])
	}
	for i := 0; i < 5; i++ {
		out[i] = mem.Read(i + 10)
	}
	if !reflect.DeepEqual(out, in) {
		t.Errorf("\n have: %v \n want: %v", out, in)
	}
}

func TestMemoryMapFunc(t *testing.T) {
	reads := 0
	writes := 0
	out := make([]uint8, 5, 5)

	mem := NewMemory(1, 15)
	for i := 0; i < 5; i++ {
		j := i
		mem.MapLoad(i+10, func() uint8 { reads++; return 40 + uint8(j) })
		mem.MapStore(i+10, func(uint8) { writes++ })
	}
	for i := 0; i < 5; i++ {
		out[i] = mem.Read(i + 10)
		mem.Write(i+10, 99)
	}
	want := []uint8{40, 41, 42, 43, 44}
	if !reflect.DeepEqual(out, want) {
		t.Errorf("\n have: %v \n want: %v", out, want)
	}
	if reads != 5 {
		t.Errorf("expected 5 reads, got %v", reads)
	}
	if writes != 5 {
		t.Errorf("expected 5 writes, got %v", writes)
	}
}

func TestMemoryMap(t *testing.T) {
	main := NewMemory(1, 15)
	mem := NewMemory(1, 5)
	mem.MapRAM(0, make([]uint8, 5, 5))
	main.Map(0, mem)
	main.Map(5, mem)

	main.Write(1, 22)
	have := main.Read(6)
	want := uint8(22)
	if have != want {
		t.Errorf("\n have: %04x \n want: %04x", have, want)
	}
}

func TestMemoryUnmap(t *testing.T) {
	var buf bytes.Buffer
	log.SetFlags(0)
	log.SetOutput(&buf)
	defer func() {
		log.SetFlags(log.LstdFlags)
		log.SetOutput(os.Stderr)
	}()

	mem := NewMemory(1, 10)
	mem.MapRAM(0, make([]uint8, 10, 10))
	mem.Write(7, 44)
	mem.Unmap(7)
	mem.Read(7)

	msg := []string{
		"(!) mem: unmapped read, bank $0, addr $7",
		"",
	}
	have := buf.String()
	want := strings.Join(msg, "\n")
	if have != want {
		t.Errorf("\n have: \n%v \n want: \n%v", have, want)
	}
}

func TestMemoryReadLE(t *testing.T) {
	mem := NewMemory(1, 2)
	mem.MapROM(0, []uint8{0xcd, 0xab})

	have := mem.ReadLE(0)
	want := 0xabcd
	if want != have {
		t.Errorf("\n have: %04x \n want: %04x", have, want)
	}
}

func TestMemoryWriteLE(t *testing.T) {
	mem := NewMemory(1, 2)
	ram := make([]uint8, 2, 2)
	mem.MapRAM(0, ram)

	mem.WriteLE(0, 0xabcd)
	want := []uint8{0xcd, 0xab}
	if !reflect.DeepEqual(ram, want) {
		t.Errorf("\n have: %v \n want: %v", ram, want)
	}
}

func TestWriteN(t *testing.T) {
	mem := NewMemory(1, 4)
	ram := make([]uint8, 4, 4)
	mem.MapRAM(0, ram)

	mem.WriteN(1, 10, 11, 12)
	want := []uint8{0, 10, 11, 12}
	if !reflect.DeepEqual(ram, want) {
		t.Errorf("\n have: %v \n want: %v", ram, want)
	}
}

func TestMemoryBank(t *testing.T) {
	mem := NewMemory(2, 2)
	ram0 := []uint8{10, 0}
	ram1 := []uint8{30, 0}
	mem.MapRAM(0, ram0)
	mem.SetBank(1)
	mem.MapRAM(0, ram1)

	out := make([]uint8, 4, 4)
	mem.SetBank(0)
	mem.Write(1, 20)
	out[0] = mem.Read(0)
	out[1] = mem.Read(1)

	mem.SetBank(1)
	mem.Write(1, 40)
	out[2] = mem.Read(0)
	out[3] = mem.Read(1)

	want := []uint8{10, 20, 30, 40}
	if !reflect.DeepEqual(out, want) {
		t.Errorf("\n have: %v \n want: %v", out, want)
	}
}

func TestMemoryMirror(t *testing.T) {
	mem := NewMemory(1, 20)
	ram := make([]uint8, 10, 10)
	mem.MapRAM(0, ram)
	mem.MapRAM(10, ram)
	mem.Write(4, 99)
	have := mem.Read(14)
	want := uint8(99)
	if have != want {
		t.Errorf("\n have: %v \n want: %v", have, want)
	}
}

func benchmarkMemoryW(count int, b *testing.B) {
	mem := NewMemory(1, count)
	mem.MapRAM(0, make([]uint8, count, count))
	b.ResetTimer()
	for n := 0; n < b.N; n++ {
		for i := 0; i < count; i++ {
			mem.Write(i, 0xff)
		}
	}
}

func benchmarkMemoryR(count int, b *testing.B) {
	mem := NewMemory(1, count)
	mem.MapRAM(0, make([]uint8, count, count))
	out := make([]uint8, count, count)
	b.ResetTimer()
	for n := 0; n < b.N; n++ {
		for i := 0; i < count; i++ {
			out[i] = mem.Read(i)
		}
	}
}

func BenchmarkMemoryW(b *testing.B)      { benchmarkMemoryW(1, b) }
func BenchmarkMemoryPageW(b *testing.B)  { benchmarkMemoryW(0x100, b) }
func BenchmarkMemorySpaceW(b *testing.B) { benchmarkMemoryW(0x10000, b) }

func BenchmarkMemoryR(b *testing.B)      { benchmarkMemoryR(1, b) }
func BenchmarkMemoryPageR(b *testing.B)  { benchmarkMemoryR(0x100, b) }
func BenchmarkMemorySpaceR(b *testing.B) { benchmarkMemoryR(0x10000, b) }

func TestPointerFetch(t *testing.T) {
	mem := NewMemory(1, 10)
	mem.MapRAM(0, make([]uint8, 10, 10))

	mem.Write(4, 44)
	p := NewPointer(mem)
	p.SetAddr(4)

	have := p.Fetch()
	want := uint8(44)
	if have != want {
		fmt.Printf("\n have: %v \n want: %v", have, want)
	}
}

func TestPointerFetch2(t *testing.T) {
	mem := NewMemory(1, 10)
	mem.MapRAM(0, make([]uint8, 10, 10))

	mem.Write(4, 44)
	mem.Write(5, 55)
	p := NewPointer(mem)
	p.SetAddr(4)

	p.Fetch()
	have := p.Fetch()
	want := uint8(55)
	if have != want {
		fmt.Printf("\n have: %v \n want: %v", have, want)
	}
}

func TestPeek(t *testing.T) {
	mem := NewMemory(1, 10)
	mem.MapRAM(0, make([]uint8, 10, 10))

	mem.Write(4, 44)
	p := NewPointer(mem)
	p.SetAddr(4)

	p.Peek()
	have := p.Peek()
	want := uint8(44)
	if have != want {
		fmt.Printf("\n have: %v \n want: %v", have, want)
	}
}

func TestFetchLE(t *testing.T) {
	mem := NewMemory(1, 10)
	mem.MapRAM(0, make([]uint8, 10, 10))

	mem.Write(4, 0x44)
	mem.Write(5, 0x55)
	p := NewPointer(mem)
	p.SetAddr(4)

	have := p.FetchLE()
	want := 0x5544
	if have != want {
		fmt.Printf("\n have: %04x \n want: %04x", have, want)
	}
}

func TestPutN(t *testing.T) {
	mem := NewMemory(1, 5)
	ram := make([]uint8, 5, 5)
	mem.MapRAM(0, ram)

	p := NewPointer(mem)
	p.PutN(1, 2, 3)
	p.PutN(4, 5)

	want := []uint8{1, 2, 3, 4, 5}
	if !reflect.DeepEqual(ram, want) {
		fmt.Printf("\n have: %04x \n want: %04x", ram, want)
	}
}

func TestLoadROMs(t *testing.T) {
	data0 := []byte{1, 2}
	data1 := []byte{3, 4}
	readFile = func(filename string) ([]byte, error) {
		switch filename {
		case "data0":
			return data0, nil
		case "data1":
			return data1, nil
		}
		return nil, fmt.Errorf("invalid file: %v", filename)
	}
	defer func() { readFile = ioutil.ReadFile }()

	rom0 := NewROM(" data0 ", " data0 ", "0ca623e2855f2c75c842ad302fe820e41b4d197d")
	rom1 := NewROM(" data1 ", " data1 ", "c512123626a98914cb55a769db20808db3df3af7")
	chunks, err := LoadROMs("", []ROM{rom0, rom1})
	if err != nil {
		t.Error(err)
	}
	want := map[string][]byte{
		"data0": data0,
		"data1": data1,
	}
	if !reflect.DeepEqual(chunks, want) {
		t.Errorf("\n have: %+v \n want: %+v", chunks, want)
	}
}

func TestLoadROMsCombine(t *testing.T) {
	data0 := []byte{1, 2}
	data1 := []byte{3, 4}
	readFile = func(filename string) ([]byte, error) {
		switch filename {
		case "data0":
			return data0, nil
		case "data1":
			return data1, nil
		}
		return nil, fmt.Errorf("invalid file")
	}
	defer func() { readFile = ioutil.ReadFile }()

	rom0 := NewROM(" data ", " data0 ", "0ca623e2855f2c75c842ad302fe820e41b4d197d")
	rom1 := NewROM(" data ", " data1 ", "c512123626a98914cb55a769db20808db3df3af7")
	chunks, err := LoadROMs("", []ROM{rom0, rom1})
	if err != nil {
		t.Error(err)
	}
	want := map[string][]byte{
		"data": []byte{1, 2, 3, 4},
	}
	if !reflect.DeepEqual(chunks, want) {
		t.Errorf("\n have: %+v \n want: %+v", chunks, want)
	}
}

func TestLoadROMsChecksumError(t *testing.T) {
	data0 := []byte{1, 2}
	readFile = func(filename string) ([]byte, error) {
		switch filename {
		case "/data0":
			return data0, nil
		}
		return nil, fmt.Errorf("invalid file")
	}
	defer func() { readFile = ioutil.ReadFile }()

	rom0 := NewROM("data0", "data0", "xx")
	_, err := LoadROMs("/", []ROM{rom0})
	if err == nil {
		t.Errorf("expected error")
	}
}


<|start_filename|>rcs/namco/n51xx.go<|end_filename|>
package namco

import "log"

type N51XX struct {
	WatchR bool
	WatchW bool
}

func NewN51XX() *N51XX {
	return &N51XX{}
}

func (n *N51XX) Write(v uint8) {
	if n.WatchW {
		log.Printf("write input controller: %02v", v)
	}
}

func (n *N51XX) Read() uint8 {
	if n.WatchR {
		log.Printf("read input controller")
	}
	return 0
}


<|start_filename|>rcs/m6502/cpu.go<|end_filename|>
package m6502

import (
	"fmt"
	"log"

	"github.com/blackchip-org/retro-cs/rcs"
)

// http://www.6502.org/tutorials/6502opcodes.html

const (
	addrStack = 0x0100 // starting address of the stack
	addrReset = 0xfffc // reset vector
)

// CPU is the MOS Technology 6502 series processor.
type CPU struct {
	Name string
	pc   uint16 // program counter
	A    uint8  // accumulator
	X    uint8  // x register
	Y    uint8  // y register
	SP   uint8  // stack pointer
	SR   uint8  // status register

	IRQ bool // interrupt request

	BreakFunc  func()
	WatchIRQ   bool
	WatchBRK   bool
	WatchStack bool

	mem       *rcs.Memory          // CPU's view into memory
	ops       map[uint8]func(*CPU) // opcode table
	addrLoad  int                  // memory address where the last value was loaded from
	pageCross bool                 // if set, add a one cycle penalty for crossing a page boundary
}

const (
	// FlagC is the carry flag
	FlagC = uint8(1 << 0)

	// FlagZ is the zero flag
	FlagZ = uint8(1 << 1)

	// FlagI is the interrupt disable flag
	FlagI = uint8(1 << 2)

	// FlagD is the decimal mode flag
	FlagD = uint8(1 << 3)

	// FlagB is the break flag
	FlagB = uint8(1 << 4)

	// Flag5 is the 5th bit flag, always on
	Flag5 = uint8(1 << 5)

	// FlagV is the overflow flag
	FlagV = uint8(1 << 6)

	// FlagN is the signed/negative flag
	FlagN = uint8(1 << 7)
)

// New creates a new CPU with a view of the provided memory.
func New(mem *rcs.Memory) *CPU {
	return &CPU{
		Name: "cpu",
		mem:  mem,
		pc:   uint16(mem.ReadLE(addrReset) - 1), // reset vector
		ops:  opcodes,
	}
}

// Next executes the next instruction.
func (c *CPU) Next() {
	here := uint16(c.PC() + 1)
	c.pageCross = false
	opcode := c.fetch()
	execute, ok := c.ops[opcode]
	if !ok {
		log.Printf("(!) %v: illegal instruction %v, pc %v", c.Name, rcs.X8(opcode), rcs.X16(here))
		return
	}
	execute(c)
	c.SR |= Flag5
	c.SR &^= FlagB

	if c.IRQ {
		c.IRQ = false
		if c.SR&FlagI == 0 {
			c.irqAck(false)
		}
	}
}

// interrupt handler
func (c *CPU) irqAck(brk bool) {
	here := uint16(c.pc)
	// http://www.6502.org/tutorials/6502opcodes.html#RTI
	// Note that unlike RTS, the return address on the stack is the
	// actual address rather than the address-1.
	ret := c.pc + 1
	vector := uint16(c.mem.ReadLE(0xfffe))
	if !brk && c.WatchIRQ {
		log.Printf("%v: irq, vector %v, return %v", c.Name, rcs.X16(vector), rcs.X16(ret))
	}
	if brk && c.WatchBRK {
		log.Printf("%v: brk, vector %v, pc %v", c.Name, rcs.X16(vector), rcs.X16(here))
	}

	c.push2(ret)
	sr := c.SR | Flag5
	if brk {
		sr |= FlagB
	}
	c.push(sr)
	c.SR |= FlagI
	c.pc = vector - 1
}

// PC returns the value of the program counter.
func (c *CPU) PC() int {
	return int(c.pc)
}

// SetPC sets the value of the program counter.
func (c *CPU) SetPC(addr int) {
	c.pc = uint16(addr)
}

// Offset is the value to be added to the program counter to get the
// address of the next instruction. The value is 1 for this CPU since
// the program counter is incremented before fetching the opcode.
func (c *CPU) Offset() int {
	return 1
}

// Memory is the memory that can been seen by this CPU.
func (c *CPU) Memory() *rcs.Memory {
	return c.mem
}

// NewDisassembler creates a disassembler that can handle 6502 machine
// code.
func (c *CPU) NewDisassembler() *rcs.Disassembler {
	dasm := rcs.NewDisassembler(c.mem, Reader, Formatter())
	return dasm
}

// String returns the status of the CPU in the form of:
// 		 pc  sr ac xr yr sp  n v - b d i z c
// 		1234 20 00 00 00 ff  . . * . . . . .
func (c *CPU) String() string {
	b := func(v bool) string {
		if v {
			return "*"
		}
		return "."
	}
	return fmt.Sprintf(""+
		" pc  sr ac xr yr sp  n v - - d i z c\n"+
		"%04x %02x %02x %02x %02x %02x  %s %s %s %s %s %s %s %s",
		c.pc,
		c.SR|(1<<5), // bit 5 hard wired on
		c.A,
		c.X,
		c.Y,
		c.SP,
		b(c.SR&FlagN != 0),
		b(c.SR&FlagV != 0),
		b(true),
		b(false),
		b(c.SR&FlagD != 0),
		b(c.SR&FlagI != 0),
		b(c.SR&FlagZ != 0),
		b(c.SR&FlagC != 0),
	)
}

// Increment the program counter and return the 8-bit value at the
// program counter.
func (c *CPU) fetch() uint8 {
	c.pc++
	return c.mem.Read(int(c.pc))
}

// Like fetch, but return the next 16-bit value.
func (c *CPU) fetch2() int {
	return int(c.fetch()) + (int(c.fetch()) << 8)
}

// Push a 8-bit value to the stack.
func (c *CPU) push(v uint8) {
	if c.WatchStack {
		log.Printf("%v: stack[%v] <= %v", c.Name, rcs.X8(c.SP), rcs.X8(v))
	}
	c.mem.Write(addrStack+int(c.SP), v)
	if c.SP == 0 {
		log.Printf("(!) %v: stack overflow", c.Name)
	}
	c.SP--
}

// Push a 16-bit value to the stack.
func (c *CPU) push2(v uint16) {
	c.push(uint8(v >> 8))
	c.push(uint8(v))
}

// Pull a 8-bit value from the stack.
func (c *CPU) pull() uint8 {
	if c.SP == 0xff {
		log.Printf("(!) %v: stack underflow", c.Name)
	}
	c.SP++
	v := c.mem.Read(addrStack + int(c.SP))
	if c.WatchStack {
		log.Printf("%v: %v <= stack[%v]", c.Name, rcs.X8(v), rcs.X8(c.SP))
	}
	return v
}

// Pull a 16-bit value from the stack.
func (c *CPU) pull2() uint16 {
	return uint16(c.pull()) | uint16(c.pull())<<8
}

func (c *CPU) Save(enc *rcs.Encoder) {
	enc.Encode(c.pc)
	enc.Encode(c.A)
	enc.Encode(c.X)
	enc.Encode(c.Y)
	enc.Encode(c.SP)
	enc.Encode(c.SR)
}

func (c *CPU) Load(dec *rcs.Decoder) {
	dec.Decode(&c.pc)
	dec.Decode(&c.A)
	dec.Decode(&c.X)
	dec.Decode(&c.Y)
	dec.Decode(&c.SP)
	dec.Decode(&c.SR)
}


<|start_filename|>rcs/memory.go<|end_filename|>
package rcs

import (
	"bytes"
	"crypto/sha1"
	"errors"
	"fmt"
	"io/ioutil"
	"log"
	"path/filepath"
	"strings"
)

type MemoryEvent struct {
	Read  bool
	Bank  int
	Addr  int
	Value uint8
}

/*
Memory represents an address space used to access RAM, ROM, IO ports,
and external devices.

To create a memory space with a 16 line address bus and a single bank, use:

	mem := rcs.NewMemory(1, 0x10000)

This struct is just a container for the address space and has no actual
memory mapped to it yet. Reads or writes to an unmapped address emit a
warning through the standard logger.

Single values are mapped for read/write access using the MapRW method. This is
useful for mapping ports or registers of a device into the address space. In
this example from the Commodore 64, the X coordinate for sprite #0 is mapped to
0xd000 and the Y coordinate is mapped to 0xd001:

	mem.MapRW(0xd000, &sprites[0].X)
	mem.MapRW(0xd001, &sprites[0].Y)

Use MapRO for a read-only mapping and MapWO for a write-only mapping. In
this example from Pac-Man, the value of port IN0 is read through address
0x5000 but interrupts can be enabled or disabled by writing to address
0x5000:

	mem.MapRO(0x5000, &portIN0)
	mem.MapWO(0x5000, &irqEnable)

A range of addresses can map to the same value with:

	for i := 0x50c0; i <= 0x50ff; i++ {
		mem.MapWO(i, &watchdogReset)
	}

Large blocks can be mapped by passing in a uint8 slice using MapRAM
for read/write access and MapROM for read-only access. The following example
maps a 16KB block of ROM to 0x0000 - 0x3fff and a 48KB block of RAM
to 0x4000 - 0xffff:

	rom := []uint8{ ... 16KB data ... }
	ram := make([]uint8, 48*1024, 48*1024)
	mem.MapROM(0x0000, rom)
	mem.MapRAM(0x4000, ram)

To "overlay" ROM on top of RAM, first use MapRAM and then MapROM which will
replace the read mappings while leaving the write mappings untouched. In
the following example, reads in the first 16KB come from the ROM but
writes go to the RAM:

	rom := []uint8{ ... 16KB data ... }
	ram := make([]uint8, 64*1024, 64*1024)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0x0000, rom)

To use banked memory, create memory with more than one bank:

	mem := rcs.NewMemory(2, 0x10000)

All map, read, and write operations are performed on the selected bank
which by default is zero. The following example has a ROM overlay
in bank 0 and full access to the RAM in bank 1:

	rom := []uint8{ ... 16KB data ... }
	ram := make([]uint8, 64*1024, 64*1024)

	mem.SetBank(0)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0x0000, rom)

	mem.SetBank(1)
	mem.MapRAM(0x0000, ram)
*/
type Memory struct {
	Name     string
	MaxAddr  int               // maximum valid address
	Callback func(MemoryEvent) // function called on watch events
	NBank    int               // number of banks

	// read and write functions for each bank
	reads  [][]Load8
	writes [][]Store8

	// previous read and write functions are stored here during watches
	preads  [][]Load8
	pwrites [][]Store8

	// selected bank index
	bank int

	// read and write functions for the selected bank
	read  []Load8
	write []Store8
}

// NewMemory creates a memory space of uint8 values that are addressable
// from 0 to size - 1. This function only creates the address space;
// values must be mapped using the Map methods. To create banked memory, use a
// value greater than one for the banks argument.
func NewMemory(banks int, size int) *Memory {
	if banks < 1 {
		banks = 1
	}
	mem := &Memory{
		Name:    "mem",
		MaxAddr: size - 1,
		NBank:   banks,
		reads:   make([][]Load8, banks, banks),
		writes:  make([][]Store8, banks, banks),
		preads:  make([][]Load8, banks, banks),
		pwrites: make([][]Store8, banks, banks),
	}
	for b := 0; b < banks; b++ {
		mem.reads[b] = make([]Load8, size, size)
		mem.writes[b] = make([]Store8, size, size)
		mem.preads[b] = make([]Load8, size, size)
		mem.pwrites[b] = make([]Store8, size, size)
	}
	mem.read = mem.reads[0]
	mem.write = mem.writes[0]
	mem.Callback = func(MemoryEvent) {}
	return mem
}

// Read returns the 8-bit value at the given address.
func (m *Memory) Read(addr int) uint8 {
	if m.read[addr] == nil {
		log.Printf("(!) %v: unmapped read, bank %v, addr %v", m.Name,
			X(m.bank), X(addr))
		return 0
	}
	v := m.read[addr]()
	return v
}

// Write sets the 8-bit value at the given address.
func (m *Memory) Write(addr int, val uint8) {
	if m.write[addr] == nil {
		log.Printf("(!) %v: unmapped write, bank %v, addr %v, val %v",
			m.Name, X(m.bank), X(addr), X8(val))
		return
	}
	m.write[addr](val)
}

// WriteN sets multiple 8-bit values starting with the given address.
func (m *Memory) WriteN(addr int, values ...uint8) {
	for i, val := range values {
		m.write[addr+i](val)
	}
}

// ReadLE returns the 16-bit value at addr and addr+1 stored in little endian
// byte order.
func (m *Memory) ReadLE(addr int) int {
	lo := int(m.Read(addr))
	hi := int(m.Read(addr + 1))
	return hi<<8 + lo
}

// WriteLE puts a 16-bit value at addr and addr+1 stored in little endian
// byte order.
func (m *Memory) WriteLE(addr int, val int) {
	hi := uint8(val >> 8)
	lo := uint8(val)
	m.Write(addr, lo)
	m.Write(addr+1, hi)
}

// MapRAM adds read/write maps to all of the 8-bit values in ram starting at
// addr. Any existing read or write maps are replaced.
func (m *Memory) MapRAM(addr int, ram []uint8) {
	for i := 0; i < len(ram); i++ {
		j := i
		m.read[addr+i] = func() uint8 { return ram[j] }
		m.write[addr+i] = func(v uint8) { ram[j] = v }
	}
}

// MapROM adds read maps to all of the 8-bit values in rom starting at
// addr. Any existing read maps are replaced but write maps are not altered.
// If the rom passed in is nil, no mappings are changed.
func (m *Memory) MapROM(addr int, rom []uint8) {
	if rom == nil {
		return
	}
	for i := 0; i < len(rom); i++ {
		j := i
		m.read[addr+i] = func() uint8 { return rom[j] }
	}
}

// MapRW adds a read and write to the given 8-bit value at addr. Any existing
// mappings are replaced.
func (m *Memory) MapRW(addr int, b *uint8) {
	m.MapRO(addr, b)
	m.MapWO(addr, b)
}

// MapRO adds a read mapping to the given 8-bit value at addr. If there is
// already a read mapping, it is replaced. Write mappings are not altered.
func (m *Memory) MapRO(addr int, b *uint8) {
	m.read[addr] = func() uint8 { return *b }
}

// MapWO adds a write mapping to the given 8-bit value at addr. If there is
// already a write mapping, it is replaced. Read mappings are not altered.
func (m *Memory) MapWO(addr int, b *uint8) {
	m.write[addr] = func(v uint8) { *b = v }
}

// MapLoad adds a read mapping to the given function. When this address is
// read from, the function is invoked to get the value. If there is already a
// read mapping for this address, it is replaced. Write mappings are not
// altered.
func (m *Memory) MapLoad(addr int, load Load8) {
	m.read[addr] = load
}

// MapStore adds a write mapping to the given function. When this address is
// written to, the function is invoked with the value to write. If there
// is already a write mapping for this address, it is replaced. Read mappings
// are not altered.
func (m *Memory) MapStore(addr int, store Store8) {
	m.write[addr] = store
}

// Map maps the contents of another memory to this memory at the starting
// address. This copies the bindings in the other memory at call time;
// later updates to the map of the other memory will not be seen in this
// memory.
func (m *Memory) Map(startAddr int, m1 *Memory) {
	endAddr := startAddr + len(m1.read)
	for i, addr := 0, startAddr; addr < endAddr; i, addr = i+1, addr+1 {
		m.read[addr] = m1.read[i]
		m.write[addr] = m1.write[i]
	}
}

// Unmap removes the read and write mappings at the address.
func (m *Memory) Unmap(addr int) {
	m.read[addr] = nil
	m.write[addr] = nil
}

// MapNil creates an empty read and write mapping at the address.
func (m *Memory) MapNil(addr int) {
	m.read[addr] = func() uint8 { return 0 }
	m.write[addr] = func(uint8) {}
}

// WatchRO creates a read watch on the address. When a value is read to that
// address, a MemoryEvent is sent to the Callback function.
func (m *Memory) WatchRO(addr int) {
	if m.preads[m.bank][addr] != nil {
		return
	}
	prev := m.reads[m.bank][addr]
	m.read[addr] = func() uint8 {
		value := prev()
		m.Callback(MemoryEvent{
			Read:  true,
			Bank:  m.bank,
			Addr:  addr,
			Value: value,
		})
		return value
	}
	m.preads[m.bank][addr] = prev
}

// WatchWO creates a write watch on the address. When a value is written to
// that address, a MemoryEvent is sent to the Callback function.
func (m *Memory) WatchWO(addr int) {
	if m.pwrites[m.bank][addr] != nil {
		return
	}
	prev := m.writes[m.bank][addr]
	m.write[addr] = func(value uint8) {
		prev(value)
		m.Callback(MemoryEvent{
			Read:  false,
			Bank:  m.bank,
			Addr:  addr,
			Value: value,
		})
	}
	m.pwrites[m.bank][addr] = prev
}

// WatchRW creats a read and write watch on the address. When a value is
// read from or written to that address, a MemorYEvent is sent to the
// Callback function.
func (m *Memory) WatchRW(addr int) {
	m.WatchRO(addr)
	m.WatchWO(addr)
}

// Unwatch removes read nad write watches on the address.
func (m *Memory) Unwatch(addr int) {
	if prev := m.pwrites[m.bank][addr]; prev != nil {
		m.write[addr] = prev
		m.pwrites[m.bank][addr] = nil
	}
	if prev := m.preads[m.bank][addr]; prev != nil {
		m.read[addr] = prev
		m.preads[m.bank][addr] = nil
	}
}

// Bank returns the number of the selected bank. Banks are numbered starting
// with zero.
func (m *Memory) Bank() int {
	return m.bank
}

// SetBank changes the selected bank. Banks are numbered starting with zero.
func (m *Memory) SetBank(bank int) {
	m.bank = bank
	m.read = m.reads[bank]
	m.write = m.writes[bank]
}

// Pointer points to a location in memory.
type Pointer struct {
	addr int     // Current position.
	Mask int     // Address mask
	Mem  *Memory // Memory view
}

// NewPointer creates pointer at address zero on the provided memory.
func NewPointer(mem *Memory) *Pointer {
	return &Pointer{Mem: mem, Mask: 0xffff}
}

func (p *Pointer) Addr() int {
	return p.addr
}

func (p *Pointer) SetAddr(addr int) {
	p.addr = addr & p.Mask
}

// Fetch returns the byte at current position as an 8-bit value and advances
// the pointer by one.
func (p *Pointer) Fetch() uint8 {
	value := p.Mem.Read(p.addr)
	p.addr = (p.addr + 1) & p.Mask
	return value
}

// Peek returns the byte at the current position as an 8-bit value. The
// pointer is not moved.
func (p *Pointer) Peek() uint8 {
	return p.Mem.Read(p.addr)
}

// FetchLE returns the next two bytes as a 16-bit value stored in little
// endian format and advances the pointer by two.
func (p *Pointer) FetchLE() int {
	lo := int(p.Fetch())
	hi := int(p.Fetch())
	return hi<<8 + lo
}

// Put sets the value at the current address and advances the pointer by one.
func (p *Pointer) Put(value uint8) {
	p.Mem.Write(p.addr, value)
	p.addr = (p.addr + 1) & p.Mask
}

// PutN calls Put for each value.
func (p *Pointer) PutN(values ...uint8) {
	for _, value := range values {
		p.Put(value)
	}
}

/*
ROM represents a dump of read-only memory data found on disk.

To load in a set of ROMs, define a slice of ROM definitions each with
the "name" of the ROM, the filename found on disk, and its SHA1
checksum as a string of hexadecimal values.

	roms := []rcs.ROM{
		NewROM("code"  ", "chip1.rom  ", "da39a3ee5e6b4b0d3255bfef95601890afd80709"),
		NewROM("code   ", "chip2.rom  ", "342d21fb707e89a6d407117c810795abcc481c52"),
		NewROM("sprites", "chip3az.rom", "38dc6d5fe1a085f2e885748a00fbe5b7b3b8b1a6"),
	}

Then call LoadROMs to return a map of names to byte slices:

	data, err := LoadROMs("/path/to/roms", roms)

*/
type ROM struct {
	Name     string
	File     string
	Checksum string
}

// NewROM creates a new ROM definition.
func NewROM(name string, file string, checksum string) ROM {
	return ROM{
		Name:     strings.TrimSpace(name),
		File:     strings.TrimSpace(file),
		Checksum: checksum,
	}
}

var readFile = ioutil.ReadFile

/*
LoadROMs loads all ROMs in the given slice of definitions. An attempt will be
made to load each ROM. Any errors encountered during the attempts are be
combined into a single error.

The returned map will contain a byte slice for each ROM identified by its name.
ROMS that are given the same name are concatenated together. Extra whitespace
found at the beginning or ending of the name or filename are removed and
is useful for aligning the ROM definitions in the source code.
*/
func LoadROMs(dir string, roms []ROM) (map[string][]byte, error) {
	buffers := make(map[string]bytes.Buffer)
	e := make([]string, 0, 0)
	for _, rom := range roms {
		buf := buffers[rom.Name]
		path := filepath.Join(dir, rom.File)
		data, err := readFile(path)
		if err != nil {
			e = append(e, err.Error())
			continue
		}
		checksum := fmt.Sprintf("%040x", sha1.Sum(data))
		if checksum != rom.Checksum {
			e = append(e, fmt.Sprintf("%v: invalid checksum", path))
			continue
		}
		buf.Write(data)
		buffers[rom.Name] = buf
	}
	if len(e) > 0 {
		return nil, errors.New(strings.Join(e, "\n"))
	}
	chunks := make(map[string][]byte)
	for name, buf := range buffers {
		chunks[name] = buf.Bytes()
	}
	return chunks, nil
}


<|start_filename|>rcs/namco/doc.go<|end_filename|>
// Package namco contains components for Namco systems.
package namco


<|start_filename|>rcs/namco/n06xx.go<|end_filename|>
package namco

import (
	"log"

	"github.com/blackchip-org/retro-cs/rcs"
)

type N06XX struct {
	DeviceR [4]rcs.Load8
	DeviceW [4]rcs.Store8

	ctrl    uint8
	elapsed int
	timing  bool
	NMI     func()

	WatchDataW bool
	WatchDataR bool
	WatchCtrlW bool
	WatchCtrlR bool
	WatchNMI   bool
}

func NewN06XX() *N06XX {
	n := &N06XX{}
	for i := 0; i < 4; i++ {
		j := i
		n.DeviceR[i] = func() uint8 {
			log.Printf("n06xx device %v not mapped for read", j)
			return 0
		}
		n.DeviceW[i] = func(uint8) {
			log.Printf("n06xx device %v not mapped for write", j)
		}
	}
	return n
}

func (n *N06XX) WriteData(addr int) rcs.Store8 {
	return func(v uint8) {
		if n.ctrl&0x10 != 0 {
			return
		}
		if n.WatchDataW {
			log.Printf("n06xx data write($%04x) => $%02x\n", addr, v)
		}
		dev := n.ctrl & 0x03
		switch dev {
		case 1 << 0:
			n.DeviceW[0](v)
		case 1 << 1:
			n.DeviceW[1](v)
		case 1 << 2:
			n.DeviceW[2](v)
		case 1 << 3:
			n.DeviceW[3](v)
		}
	}
}

func (n *N06XX) ReadData(addr int) rcs.Load8 {
	return func() uint8 {
		if n.ctrl&0x10 != 0 {
			return 0
		}
		dev := n.ctrl & 0x03
		v := uint8(0xff)
		switch dev {
		case 1 << 0:
			v = n.DeviceR[0]()
		case 1 << 1:
			v = n.DeviceR[1]()
		case 1 << 2:
			v = n.DeviceR[2]()
		case 1 << 3:
			v = n.DeviceR[3]()
		}
		if n.WatchDataR {
			log.Printf("n06xx data $%02x <= read($%04x)\n", v, addr)
		}
		return v
	}
}

func (n *N06XX) WriteCtrl(addr int) rcs.Store8 {
	return func(v uint8) {
		if n.WatchCtrlW {
			log.Printf("n06xx ctrl write($%04x) => $%02x\n", addr, v)
		}
		n.ctrl = v
		if v&0x0f == 0 {
			//n.timing = false
		} else {
			n.elapsed = 0
			n.timing = true
		}
	}
}

func (n *N06XX) ReadCtrl(addr int) rcs.Load8 {
	return func() uint8 {
		if n.WatchCtrlR {
			log.Printf("n06xx ctrl $%02x <= read(addr $%04x)\n", n.ctrl, addr)
		}
		return n.ctrl
	}
}

func (n *N06XX) Next() {
	if n.timing {
		n.elapsed++
		if n.elapsed > 2000 {
			if n.WatchNMI {
				log.Println("n06xx NMI")
			}
			n.NMI()
			n.elapsed = 0
		}
	}
}


<|start_filename|>rcs/namco/n54xx.go<|end_filename|>
package namco

import "log"

type N54XX struct {
	WatchR bool
	WatchW bool
}

func NewN54XX() *N54XX {
	return &N54XX{}
}

func (n *N54XX) Write(v uint8) {
	if n.WatchW {
		log.Printf("write noise generator: %02v\n", v)
	}
}

func (n *N54XX) Read() uint8 {
	if n.WatchR {
		log.Printf("read noise generator\n")
	}
	return 0
}


<|start_filename|>system/c128/c128.go<|end_filename|>
// Package c128 is the Commodore 128.
package c128

import (
	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/cbm"
	"github.com/blackchip-org/retro-cs/rcs/cbm/petscii"
	"github.com/blackchip-org/retro-cs/rcs/m6502"
)

type System struct {
	cpu    *m6502.CPU
	mem    *rcs.Memory
	mmu    *MMU
	screen rcs.Screen
	vdc    *VDC
	vic    *cbm.VIC

	BasicLo []uint8
	BasicHi []uint8
	CharGen []uint8
	Kernal  []uint8
	RAM0    []uint8
	RAM1    []uint8
	IORAM   []uint8
	IO      *rcs.Memory
}

func New(ctx rcs.SDLContext) (*rcs.Mach, error) {
	s := &System{}
	roms, err := rcs.LoadROMs(config.DataDir, SystemROM)
	if err != nil {
		return nil, err
	}
	s.mem = rcs.NewMemory(256, 0x10000)
	s.BasicLo = roms["basiclo"]
	s.BasicHi = roms["basichi"]
	s.CharGen = roms["chargen"]
	s.Kernal = roms["kernal"]
	s.RAM0 = make([]uint8, 0x10000, 0x10000)
	s.RAM1 = make([]uint8, 0xc000, 0xc000)

	s.IORAM = make([]uint8, 0x1000, 0x1000)
	s.IO = rcs.NewMemory(1, 0x1000)
	s.IO.MapRAM(0, s.IORAM)

	s.mmu = NewMMU(s.mem)
	s.vdc = NewVDC()
	v, err := cbm.NewVIC(ctx.Renderer, s.mem, roms["chargen"])
	if err != nil {
		return nil, err
	}
	s.vic = v
	s.screen = rcs.Screen{
		W:         v.W,
		H:         v.H,
		Texture:   v.Texture,
		ScanLineH: true,
		Draw:      v.Draw,
	}

	// IO mappings
	s.IO.MapRW(0x020, &s.vic.BorderColor)
	s.IO.MapRW(0x021, &s.vic.BgColor)
	s.IO.MapLoad(0x500, s.mmu.ReadCR)
	s.IO.MapStore(0x500, s.mmu.WriteCR)
	// PCR
	for i := 0; i < 4; i++ {
		i := i
		s.IO.MapLoad(0x501+i, func() uint8 { return s.mmu.ReadPCR(i) })
		s.IO.MapStore(0x501+i, func(v uint8) { s.mmu.WritePCR(i, v) })
	}
	// HACK
	s.IO.MapLoad(0x505, func() uint8 {
		return (1 << 7) | (1 << 4) | (1 << 5)
	})
	// HACK
	s.IO.MapLoad(0xd00, func() uint8 {
		return (1 << 7) | (1 << 6)
	})

	s.IO.MapLoad(0x600, s.vdc.ReadStatus)
	s.IO.MapStore(0x600, s.vdc.WriteAddr)
	s.IO.MapLoad(0x601, s.vdc.ReadData)
	s.IO.MapStore(0x601, s.vdc.WriteData)

	// map banks
	for _, i := range usedBanks {
		s.mem.SetBank(i)
		cr := uint8(i)
		blockRAM := rcs.SliceBits(cr, 6, 7)
		blockC000 := rcs.SliceBits(cr, 4, 5)
		block8000 := rcs.SliceBits(cr, 2, 3)
		block4000 := rcs.SliceBits(cr, 1, 1)
		blockIO := rcs.SliceBits(cr, 0, 0)

		switch blockRAM {
		case 0:
			s.mem.MapRAM(0x0000, s.RAM0)
		case 1:
			s.mem.MapRAM(0x0000, s.RAM0)
			s.mem.MapRAM(0x0400, s.RAM1)
		// no block RAM 2 or 3. If set, accesses 0 and 1 instead.
		case 2:
			s.mem.MapRAM(0x0000, s.RAM0)
		case 3:
			s.mem.MapRAM(0x0000, s.RAM0)
			s.mem.MapRAM(0x0400, s.RAM1)
		}

		switch blockC000 {
		case 0:
			s.mem.MapROM(0xd000, s.CharGen)
			s.mem.MapROM(0xc000, s.Kernal)
		case 1:
			// internal function ROM
		case 2:
			// external function ROM
		case 3:
			// RAM
		}

		switch block8000 {
		case 0:
			s.mem.MapROM(0x8000, s.BasicHi)
		case 1:
			// internal function ROM
		case 2:
			// external function ROM
		case 3:
			// RAM
		}

		switch block4000 {
		case 0:
			s.mem.MapROM(0x4000, s.BasicLo)
		case 1:
			// RAM
		}

		switch blockIO {
		case 0:
			s.mem.Map(0xd000, s.IO)
		case 1:
			// RAM or ROM as selected by bits 4 and 5
		}

		s.mem.MapLoad(0xff00, s.mmu.ReadCR)
		s.mem.MapStore(0xff00, s.mmu.WriteCR)
		for i := 0; i < 4; i++ {
			i := i
			s.mem.MapLoad(0xff01+i, func() uint8 { return s.mmu.ReadLCR(i) })
			s.mem.MapStore(0xff01+i, func(v uint8) { s.mmu.WriteLCR(i, v) })
		}
	}
	s.mem.SetBank(0) // bank 15

	s.mem.Write(0xd011, 0xff) // HACK
	s.mem.Write(0xd011, (1 << 7))
	s.mem.Write(0xd012, 0x09) // HACK: bcc on $8
	s.mem.Write(0xd600, 0xff) // HACK
	s.mem.Write(0xdc01, 0xff) // HACK: keyboard no press

	s.cpu = m6502.New(s.mem)
	mach := &rcs.Mach{
		Sys: s,
		Comps: []rcs.Component{
			rcs.NewComponent("cpu", "m6502", "mem", s.cpu),
			rcs.NewComponent("mem", "mem", "", s.mem),
			rcs.NewComponent("mmu", "c128/mmu", "", s.mmu),
			rcs.NewComponent("vdc", "c128/vdc", "", s.vdc),
		},
		CharDecoders: map[string]rcs.CharDecoder{
			"petscii":         petscii.Decoder,
			"petscii-shifted": petscii.ShiftedDecoder,
			"screen":          cbm.ScreenDecoder,
			"screen-shifted":  cbm.ScreenShiftedDecoder,
		},
		DefaultEncoding: "petscii",
		Ctx:             ctx,
		VBlankFunc: func() {
			s.cpu.IRQ = true
		},
		Screen: s.screen,
	}
	return mach, nil
}

var usedBanks = []int{
	0x3f, // bank 0
	0x7f, // bank 1
	0x01, // bank 14
	0x00, // bank 15

	0xc0, // on init
	0x80, // on init
	0x40, // on init
	0x2a, // on init
	0x16, // on init
}


<|start_filename|>rcs/z80/opcodes.go<|end_filename|>
// Code generated by gen/z80/opcodes/opcodes.go. DO NOT EDIT.

package z80

var opcodes = map[uint8]func(c *CPU){
	0x00: func(c *CPU) { nop() },
	0x01: func(c *CPU) { ld16(c, c.storeBC, c.loadImm16) },
	0x02: func(c *CPU) { ld(c, c.storeIndBC, c.loadA) },
	0x03: func(c *CPU) { inc16(c, c.storeBC, c.loadBC) },
	0x04: func(c *CPU) { inc(c, c.storeB, c.loadB) },
	0x05: func(c *CPU) { dec(c, c.storeB, c.loadB) },
	0x06: func(c *CPU) { ld(c, c.storeB, c.loadImm) },
	0x07: func(c *CPU) { rlca(c) },
	0x08: func(c *CPU) { ex(c, c.loadAF, c.storeAF, c.loadAF1, c.storeAF1) },
	0x09: func(c *CPU) { add16(c, c.storeHL, c.loadHL, c.loadBC) },
	0x0a: func(c *CPU) { ld(c, c.storeA, c.loadIndBC) },
	0x0b: func(c *CPU) { dec16(c, c.storeBC, c.loadBC) },
	0x0c: func(c *CPU) { inc(c, c.storeC, c.loadC) },
	0x0d: func(c *CPU) { dec(c, c.storeC, c.loadC) },
	0x0e: func(c *CPU) { ld(c, c.storeC, c.loadImm) },
	0x0f: func(c *CPU) { rrca(c) },
	0x10: func(c *CPU) { djnz(c, c.loadImm) },
	0x11: func(c *CPU) { ld16(c, c.storeDE, c.loadImm16) },
	0x12: func(c *CPU) { ld(c, c.storeIndDE, c.loadA) },
	0x13: func(c *CPU) { inc16(c, c.storeDE, c.loadDE) },
	0x14: func(c *CPU) { inc(c, c.storeD, c.loadD) },
	0x15: func(c *CPU) { dec(c, c.storeD, c.loadD) },
	0x16: func(c *CPU) { ld(c, c.storeD, c.loadImm) },
	0x17: func(c *CPU) { rla(c) },
	0x18: func(c *CPU) { jra(c, c.loadImm) },
	0x19: func(c *CPU) { add16(c, c.storeHL, c.loadHL, c.loadDE) },
	0x1a: func(c *CPU) { ld(c, c.storeA, c.loadIndDE) },
	0x1b: func(c *CPU) { dec16(c, c.storeDE, c.loadDE) },
	0x1c: func(c *CPU) { inc(c, c.storeE, c.loadE) },
	0x1d: func(c *CPU) { dec(c, c.storeE, c.loadE) },
	0x1e: func(c *CPU) { ld(c, c.storeE, c.loadImm) },
	0x1f: func(c *CPU) { rra(c) },
	0x20: func(c *CPU) { jr(c, FlagZ, false, c.loadImm) },
	0x21: func(c *CPU) { ld16(c, c.storeHL, c.loadImm16) },
	0x22: func(c *CPU) { ld16(c, c.store16IndImm, c.loadHL) },
	0x23: func(c *CPU) { inc16(c, c.storeHL, c.loadHL) },
	0x24: func(c *CPU) { inc(c, c.storeH, c.loadH) },
	0x25: func(c *CPU) { dec(c, c.storeH, c.loadH) },
	0x26: func(c *CPU) { ld(c, c.storeH, c.loadImm) },
	0x27: func(c *CPU) { daa(c) },
	0x28: func(c *CPU) { jr(c, FlagZ, true, c.loadImm) },
	0x29: func(c *CPU) { add16(c, c.storeHL, c.loadHL, c.loadHL) },
	0x2a: func(c *CPU) { ld16(c, c.storeHL, c.load16IndImm) },
	0x2b: func(c *CPU) { dec16(c, c.storeHL, c.loadHL) },
	0x2c: func(c *CPU) { inc(c, c.storeL, c.loadL) },
	0x2d: func(c *CPU) { dec(c, c.storeL, c.loadL) },
	0x2e: func(c *CPU) { ld(c, c.storeL, c.loadImm) },
	0x2f: func(c *CPU) { cpl(c) },
	0x30: func(c *CPU) { jr(c, FlagC, false, c.loadImm) },
	0x31: func(c *CPU) { ld16(c, c.storeSP, c.loadImm16) },
	0x32: func(c *CPU) { ld(c, c.storeIndImm, c.loadA) },
	0x33: func(c *CPU) { inc16(c, c.storeSP, c.loadSP) },
	0x34: func(c *CPU) { inc(c, c.storeIndHL, c.loadIndHL) },
	0x35: func(c *CPU) { dec(c, c.storeIndHL, c.loadIndHL) },
	0x36: func(c *CPU) { ld(c, c.storeIndHL, c.loadImm) },
	0x37: func(c *CPU) { scf(c) },
	0x38: func(c *CPU) { jr(c, FlagC, true, c.loadImm) },
	0x39: func(c *CPU) { add16(c, c.storeHL, c.loadHL, c.loadSP) },
	0x3a: func(c *CPU) { ld(c, c.storeA, c.loadIndImm) },
	0x3b: func(c *CPU) { dec16(c, c.storeSP, c.loadSP) },
	0x3c: func(c *CPU) { inc(c, c.storeA, c.loadA) },
	0x3d: func(c *CPU) { dec(c, c.storeA, c.loadA) },
	0x3e: func(c *CPU) { ld(c, c.storeA, c.loadImm) },
	0x3f: func(c *CPU) { ccf(c) },
	0x40: func(c *CPU) { ld(c, c.storeB, c.loadB) },
	0x41: func(c *CPU) { ld(c, c.storeB, c.loadC) },
	0x42: func(c *CPU) { ld(c, c.storeB, c.loadD) },
	0x43: func(c *CPU) { ld(c, c.storeB, c.loadE) },
	0x44: func(c *CPU) { ld(c, c.storeB, c.loadH) },
	0x45: func(c *CPU) { ld(c, c.storeB, c.loadL) },
	0x46: func(c *CPU) { ld(c, c.storeB, c.loadIndHL) },
	0x47: func(c *CPU) { ld(c, c.storeB, c.loadA) },
	0x48: func(c *CPU) { ld(c, c.storeC, c.loadB) },
	0x49: func(c *CPU) { ld(c, c.storeC, c.loadC) },
	0x4a: func(c *CPU) { ld(c, c.storeC, c.loadD) },
	0x4b: func(c *CPU) { ld(c, c.storeC, c.loadE) },
	0x4c: func(c *CPU) { ld(c, c.storeC, c.loadH) },
	0x4d: func(c *CPU) { ld(c, c.storeC, c.loadL) },
	0x4e: func(c *CPU) { ld(c, c.storeC, c.loadIndHL) },
	0x4f: func(c *CPU) { ld(c, c.storeC, c.loadA) },
	0x50: func(c *CPU) { ld(c, c.storeD, c.loadB) },
	0x51: func(c *CPU) { ld(c, c.storeD, c.loadC) },
	0x52: func(c *CPU) { ld(c, c.storeD, c.loadD) },
	0x53: func(c *CPU) { ld(c, c.storeD, c.loadE) },
	0x54: func(c *CPU) { ld(c, c.storeD, c.loadH) },
	0x55: func(c *CPU) { ld(c, c.storeD, c.loadL) },
	0x56: func(c *CPU) { ld(c, c.storeD, c.loadIndHL) },
	0x57: func(c *CPU) { ld(c, c.storeD, c.loadA) },
	0x58: func(c *CPU) { ld(c, c.storeE, c.loadB) },
	0x59: func(c *CPU) { ld(c, c.storeE, c.loadC) },
	0x5a: func(c *CPU) { ld(c, c.storeE, c.loadD) },
	0x5b: func(c *CPU) { ld(c, c.storeE, c.loadE) },
	0x5c: func(c *CPU) { ld(c, c.storeE, c.loadH) },
	0x5d: func(c *CPU) { ld(c, c.storeE, c.loadL) },
	0x5e: func(c *CPU) { ld(c, c.storeE, c.loadIndHL) },
	0x5f: func(c *CPU) { ld(c, c.storeE, c.loadA) },
	0x60: func(c *CPU) { ld(c, c.storeH, c.loadB) },
	0x61: func(c *CPU) { ld(c, c.storeH, c.loadC) },
	0x62: func(c *CPU) { ld(c, c.storeH, c.loadD) },
	0x63: func(c *CPU) { ld(c, c.storeH, c.loadE) },
	0x64: func(c *CPU) { ld(c, c.storeH, c.loadH) },
	0x65: func(c *CPU) { ld(c, c.storeH, c.loadL) },
	0x66: func(c *CPU) { ld(c, c.storeH, c.loadIndHL) },
	0x67: func(c *CPU) { ld(c, c.storeH, c.loadA) },
	0x68: func(c *CPU) { ld(c, c.storeL, c.loadB) },
	0x69: func(c *CPU) { ld(c, c.storeL, c.loadC) },
	0x6a: func(c *CPU) { ld(c, c.storeL, c.loadD) },
	0x6b: func(c *CPU) { ld(c, c.storeL, c.loadE) },
	0x6c: func(c *CPU) { ld(c, c.storeL, c.loadH) },
	0x6d: func(c *CPU) { ld(c, c.storeL, c.loadL) },
	0x6e: func(c *CPU) { ld(c, c.storeL, c.loadIndHL) },
	0x6f: func(c *CPU) { ld(c, c.storeL, c.loadA) },
	0x70: func(c *CPU) { ld(c, c.storeIndHL, c.loadB) },
	0x71: func(c *CPU) { ld(c, c.storeIndHL, c.loadC) },
	0x72: func(c *CPU) { ld(c, c.storeIndHL, c.loadD) },
	0x73: func(c *CPU) { ld(c, c.storeIndHL, c.loadE) },
	0x74: func(c *CPU) { ld(c, c.storeIndHL, c.loadH) },
	0x75: func(c *CPU) { ld(c, c.storeIndHL, c.loadL) },
	0x76: func(c *CPU) { halt(c) },
	0x77: func(c *CPU) { ld(c, c.storeIndHL, c.loadA) },
	0x78: func(c *CPU) { ld(c, c.storeA, c.loadB) },
	0x79: func(c *CPU) { ld(c, c.storeA, c.loadC) },
	0x7a: func(c *CPU) { ld(c, c.storeA, c.loadD) },
	0x7b: func(c *CPU) { ld(c, c.storeA, c.loadE) },
	0x7c: func(c *CPU) { ld(c, c.storeA, c.loadH) },
	0x7d: func(c *CPU) { ld(c, c.storeA, c.loadL) },
	0x7e: func(c *CPU) { ld(c, c.storeA, c.loadIndHL) },
	0x7f: func(c *CPU) { ld(c, c.storeA, c.loadA) },
	0x80: func(c *CPU) { add(c, c.loadA, c.loadB) },
	0x81: func(c *CPU) { add(c, c.loadA, c.loadC) },
	0x82: func(c *CPU) { add(c, c.loadA, c.loadD) },
	0x83: func(c *CPU) { add(c, c.loadA, c.loadE) },
	0x84: func(c *CPU) { add(c, c.loadA, c.loadH) },
	0x85: func(c *CPU) { add(c, c.loadA, c.loadL) },
	0x86: func(c *CPU) { add(c, c.loadA, c.loadIndHL) },
	0x87: func(c *CPU) { add(c, c.loadA, c.loadA) },
	0x88: func(c *CPU) { adc(c, c.loadA, c.loadB) },
	0x89: func(c *CPU) { adc(c, c.loadA, c.loadC) },
	0x8a: func(c *CPU) { adc(c, c.loadA, c.loadD) },
	0x8b: func(c *CPU) { adc(c, c.loadA, c.loadE) },
	0x8c: func(c *CPU) { adc(c, c.loadA, c.loadH) },
	0x8d: func(c *CPU) { adc(c, c.loadA, c.loadL) },
	0x8e: func(c *CPU) { adc(c, c.loadA, c.loadIndHL) },
	0x8f: func(c *CPU) { adc(c, c.loadA, c.loadA) },
	0x90: func(c *CPU) { sub(c, c.loadA, c.loadB) },
	0x91: func(c *CPU) { sub(c, c.loadA, c.loadC) },
	0x92: func(c *CPU) { sub(c, c.loadA, c.loadD) },
	0x93: func(c *CPU) { sub(c, c.loadA, c.loadE) },
	0x94: func(c *CPU) { sub(c, c.loadA, c.loadH) },
	0x95: func(c *CPU) { sub(c, c.loadA, c.loadL) },
	0x96: func(c *CPU) { sub(c, c.loadA, c.loadIndHL) },
	0x97: func(c *CPU) { sub(c, c.loadA, c.loadA) },
	0x98: func(c *CPU) { sbc(c, c.loadA, c.loadB) },
	0x99: func(c *CPU) { sbc(c, c.loadA, c.loadC) },
	0x9a: func(c *CPU) { sbc(c, c.loadA, c.loadD) },
	0x9b: func(c *CPU) { sbc(c, c.loadA, c.loadE) },
	0x9c: func(c *CPU) { sbc(c, c.loadA, c.loadH) },
	0x9d: func(c *CPU) { sbc(c, c.loadA, c.loadL) },
	0x9e: func(c *CPU) { sbc(c, c.loadA, c.loadIndHL) },
	0x9f: func(c *CPU) { sbc(c, c.loadA, c.loadA) },
	0xa0: func(c *CPU) { and(c, c.loadB) },
	0xa1: func(c *CPU) { and(c, c.loadC) },
	0xa2: func(c *CPU) { and(c, c.loadD) },
	0xa3: func(c *CPU) { and(c, c.loadE) },
	0xa4: func(c *CPU) { and(c, c.loadH) },
	0xa5: func(c *CPU) { and(c, c.loadL) },
	0xa6: func(c *CPU) { and(c, c.loadIndHL) },
	0xa7: func(c *CPU) { and(c, c.loadA) },
	0xa8: func(c *CPU) { xor(c, c.loadB) },
	0xa9: func(c *CPU) { xor(c, c.loadC) },
	0xaa: func(c *CPU) { xor(c, c.loadD) },
	0xab: func(c *CPU) { xor(c, c.loadE) },
	0xac: func(c *CPU) { xor(c, c.loadH) },
	0xad: func(c *CPU) { xor(c, c.loadL) },
	0xae: func(c *CPU) { xor(c, c.loadIndHL) },
	0xaf: func(c *CPU) { xor(c, c.loadA) },
	0xb0: func(c *CPU) { or(c, c.loadB) },
	0xb1: func(c *CPU) { or(c, c.loadC) },
	0xb2: func(c *CPU) { or(c, c.loadD) },
	0xb3: func(c *CPU) { or(c, c.loadE) },
	0xb4: func(c *CPU) { or(c, c.loadH) },
	0xb5: func(c *CPU) { or(c, c.loadL) },
	0xb6: func(c *CPU) { or(c, c.loadIndHL) },
	0xb7: func(c *CPU) { or(c, c.loadA) },
	0xb8: func(c *CPU) { cp(c, c.loadB) },
	0xb9: func(c *CPU) { cp(c, c.loadC) },
	0xba: func(c *CPU) { cp(c, c.loadD) },
	0xbb: func(c *CPU) { cp(c, c.loadE) },
	0xbc: func(c *CPU) { cp(c, c.loadH) },
	0xbd: func(c *CPU) { cp(c, c.loadL) },
	0xbe: func(c *CPU) { cp(c, c.loadIndHL) },
	0xbf: func(c *CPU) { cp(c, c.loadA) },
	0xc0: func(c *CPU) { ret(c, FlagZ, false) },
	0xc1: func(c *CPU) { pop(c, c.storeBC) },
	0xc2: func(c *CPU) { jp(c, FlagZ, false, c.loadImm16) },
	0xc3: func(c *CPU) { jpa(c, c.loadImm16) },
	0xc4: func(c *CPU) { call(c, FlagZ, false, c.loadImm16) },
	0xc5: func(c *CPU) { push(c, c.loadBC) },
	0xc6: func(c *CPU) { add(c, c.loadA, c.loadImm) },
	0xc7: func(c *CPU) { rst(c, 0) },
	0xc8: func(c *CPU) { ret(c, FlagZ, true) },
	0xc9: func(c *CPU) { reta(c) },
	0xca: func(c *CPU) { jp(c, FlagZ, true, c.loadImm16) },
	0xcc: func(c *CPU) { call(c, FlagZ, true, c.loadImm16) },
	0xcd: func(c *CPU) { calla(c, c.loadImm16) },
	0xce: func(c *CPU) { adc(c, c.loadA, c.loadImm) },
	0xcf: func(c *CPU) { rst(c, 1) },
	0xd0: func(c *CPU) { ret(c, FlagC, false) },
	0xd1: func(c *CPU) { pop(c, c.storeDE) },
	0xd2: func(c *CPU) { jp(c, FlagC, false, c.loadImm16) },
	0xd3: func(c *CPU) { ld(c, c.outIndImm, c.loadA) },
	0xd4: func(c *CPU) { call(c, FlagC, false, c.loadImm16) },
	0xd5: func(c *CPU) { push(c, c.loadDE) },
	0xd6: func(c *CPU) { sub(c, c.loadA, c.loadImm) },
	0xd7: func(c *CPU) { rst(c, 2) },
	0xd8: func(c *CPU) { ret(c, FlagC, true) },
	0xd9: func(c *CPU) { exx(c) },
	0xda: func(c *CPU) { jp(c, FlagC, true, c.loadImm16) },
	0xdb: func(c *CPU) { ld(c, c.storeA, c.inIndImm) },
	0xdc: func(c *CPU) { call(c, FlagC, true, c.loadImm16) },
	0xde: func(c *CPU) { sbc(c, c.loadA, c.loadImm) },
	0xdf: func(c *CPU) { rst(c, 3) },
	0xe0: func(c *CPU) { ret(c, FlagV, false) },
	0xe1: func(c *CPU) { pop(c, c.storeHL) },
	0xe2: func(c *CPU) { jp(c, FlagV, false, c.loadImm16) },
	0xe3: func(c *CPU) { ex(c, c.load16IndSP, c.store16IndSP, c.loadHL, c.storeHL) },
	0xe4: func(c *CPU) { call(c, FlagV, false, c.loadImm16) },
	0xe5: func(c *CPU) { push(c, c.loadHL) },
	0xe6: func(c *CPU) { and(c, c.loadImm) },
	0xe7: func(c *CPU) { rst(c, 4) },
	0xe8: func(c *CPU) { ret(c, FlagV, true) },
	0xe9: func(c *CPU) { jpa(c, c.loadHL) },
	0xea: func(c *CPU) { jp(c, FlagV, true, c.loadImm16) },
	0xeb: func(c *CPU) { ex(c, c.loadDE, c.storeDE, c.loadHL, c.storeHL) },
	0xec: func(c *CPU) { call(c, FlagV, true, c.loadImm16) },
	0xee: func(c *CPU) { xor(c, c.loadImm) },
	0xef: func(c *CPU) { rst(c, 5) },
	0xf0: func(c *CPU) { ret(c, FlagS, false) },
	0xf1: func(c *CPU) { pop(c, c.storeAF) },
	0xf2: func(c *CPU) { jp(c, FlagS, false, c.loadImm16) },
	0xf3: func(c *CPU) { di(c) },
	0xf4: func(c *CPU) { call(c, FlagS, false, c.loadImm16) },
	0xf5: func(c *CPU) { push(c, c.loadAF) },
	0xf6: func(c *CPU) { or(c, c.loadImm) },
	0xf7: func(c *CPU) { rst(c, 6) },
	0xf8: func(c *CPU) { ret(c, FlagS, true) },
	0xf9: func(c *CPU) { ld16(c, c.storeSP, c.loadHL) },
	0xfa: func(c *CPU) { jp(c, FlagS, true, c.loadImm16) },
	0xfb: func(c *CPU) { ei(c) },
	0xfc: func(c *CPU) { call(c, FlagS, true, c.loadImm16) },
	0xfe: func(c *CPU) { cp(c, c.loadImm) },
	0xff: func(c *CPU) { rst(c, 7) },
}
var opcodesCB = map[uint8]func(c *CPU){
	0x00: func(c *CPU) { rlc(c, c.storeB, c.loadB) },
	0x01: func(c *CPU) { rlc(c, c.storeC, c.loadC) },
	0x02: func(c *CPU) { rlc(c, c.storeD, c.loadD) },
	0x03: func(c *CPU) { rlc(c, c.storeE, c.loadE) },
	0x04: func(c *CPU) { rlc(c, c.storeH, c.loadH) },
	0x05: func(c *CPU) { rlc(c, c.storeL, c.loadL) },
	0x06: func(c *CPU) { rlc(c, c.storeIndHL, c.loadIndHL) },
	0x07: func(c *CPU) { rlc(c, c.storeA, c.loadA) },
	0x08: func(c *CPU) { rrc(c, c.storeB, c.loadB) },
	0x09: func(c *CPU) { rrc(c, c.storeC, c.loadC) },
	0x0a: func(c *CPU) { rrc(c, c.storeD, c.loadD) },
	0x0b: func(c *CPU) { rrc(c, c.storeE, c.loadE) },
	0x0c: func(c *CPU) { rrc(c, c.storeH, c.loadH) },
	0x0d: func(c *CPU) { rrc(c, c.storeL, c.loadL) },
	0x0e: func(c *CPU) { rrc(c, c.storeIndHL, c.loadIndHL) },
	0x0f: func(c *CPU) { rrc(c, c.storeA, c.loadA) },
	0x10: func(c *CPU) { rl(c, c.storeB, c.loadB) },
	0x11: func(c *CPU) { rl(c, c.storeC, c.loadC) },
	0x12: func(c *CPU) { rl(c, c.storeD, c.loadD) },
	0x13: func(c *CPU) { rl(c, c.storeE, c.loadE) },
	0x14: func(c *CPU) { rl(c, c.storeH, c.loadH) },
	0x15: func(c *CPU) { rl(c, c.storeL, c.loadL) },
	0x16: func(c *CPU) { rl(c, c.storeIndHL, c.loadIndHL) },
	0x17: func(c *CPU) { rl(c, c.storeA, c.loadA) },
	0x18: func(c *CPU) { rr(c, c.storeB, c.loadB) },
	0x19: func(c *CPU) { rr(c, c.storeC, c.loadC) },
	0x1a: func(c *CPU) { rr(c, c.storeD, c.loadD) },
	0x1b: func(c *CPU) { rr(c, c.storeE, c.loadE) },
	0x1c: func(c *CPU) { rr(c, c.storeH, c.loadH) },
	0x1d: func(c *CPU) { rr(c, c.storeL, c.loadL) },
	0x1e: func(c *CPU) { rr(c, c.storeIndHL, c.loadIndHL) },
	0x1f: func(c *CPU) { rr(c, c.storeA, c.loadA) },
	0x20: func(c *CPU) { sla(c, c.storeB, c.loadB) },
	0x21: func(c *CPU) { sla(c, c.storeC, c.loadC) },
	0x22: func(c *CPU) { sla(c, c.storeD, c.loadD) },
	0x23: func(c *CPU) { sla(c, c.storeE, c.loadE) },
	0x24: func(c *CPU) { sla(c, c.storeH, c.loadH) },
	0x25: func(c *CPU) { sla(c, c.storeL, c.loadL) },
	0x26: func(c *CPU) { sla(c, c.storeIndHL, c.loadIndHL) },
	0x27: func(c *CPU) { sla(c, c.storeA, c.loadA) },
	0x28: func(c *CPU) { sra(c, c.storeB, c.loadB) },
	0x29: func(c *CPU) { sra(c, c.storeC, c.loadC) },
	0x2a: func(c *CPU) { sra(c, c.storeD, c.loadD) },
	0x2b: func(c *CPU) { sra(c, c.storeE, c.loadE) },
	0x2c: func(c *CPU) { sra(c, c.storeH, c.loadH) },
	0x2d: func(c *CPU) { sra(c, c.storeL, c.loadL) },
	0x2e: func(c *CPU) { sra(c, c.storeIndHL, c.loadIndHL) },
	0x2f: func(c *CPU) { sra(c, c.storeA, c.loadA) },
	0x30: func(c *CPU) { sll(c, c.storeB, c.loadB) },
	0x31: func(c *CPU) { sll(c, c.storeC, c.loadC) },
	0x32: func(c *CPU) { sll(c, c.storeD, c.loadD) },
	0x33: func(c *CPU) { sll(c, c.storeE, c.loadE) },
	0x34: func(c *CPU) { sll(c, c.storeH, c.loadH) },
	0x35: func(c *CPU) { sll(c, c.storeL, c.loadL) },
	0x36: func(c *CPU) { sll(c, c.storeIndHL, c.loadIndHL) },
	0x37: func(c *CPU) { sll(c, c.storeA, c.loadA) },
	0x38: func(c *CPU) { srl(c, c.storeB, c.loadB) },
	0x39: func(c *CPU) { srl(c, c.storeC, c.loadC) },
	0x3a: func(c *CPU) { srl(c, c.storeD, c.loadD) },
	0x3b: func(c *CPU) { srl(c, c.storeE, c.loadE) },
	0x3c: func(c *CPU) { srl(c, c.storeH, c.loadH) },
	0x3d: func(c *CPU) { srl(c, c.storeL, c.loadL) },
	0x3e: func(c *CPU) { srl(c, c.storeIndHL, c.loadIndHL) },
	0x3f: func(c *CPU) { srl(c, c.storeA, c.loadA) },
	0x40: func(c *CPU) { bit(c, 0, c.loadB) },
	0x41: func(c *CPU) { bit(c, 0, c.loadC) },
	0x42: func(c *CPU) { bit(c, 0, c.loadD) },
	0x43: func(c *CPU) { bit(c, 0, c.loadE) },
	0x44: func(c *CPU) { bit(c, 0, c.loadH) },
	0x45: func(c *CPU) { bit(c, 0, c.loadL) },
	0x46: func(c *CPU) { bit(c, 0, c.loadIndHL) },
	0x47: func(c *CPU) { bit(c, 0, c.loadA) },
	0x48: func(c *CPU) { bit(c, 1, c.loadB) },
	0x49: func(c *CPU) { bit(c, 1, c.loadC) },
	0x4a: func(c *CPU) { bit(c, 1, c.loadD) },
	0x4b: func(c *CPU) { bit(c, 1, c.loadE) },
	0x4c: func(c *CPU) { bit(c, 1, c.loadH) },
	0x4d: func(c *CPU) { bit(c, 1, c.loadL) },
	0x4e: func(c *CPU) { bit(c, 1, c.loadIndHL) },
	0x4f: func(c *CPU) { bit(c, 1, c.loadA) },
	0x50: func(c *CPU) { bit(c, 2, c.loadB) },
	0x51: func(c *CPU) { bit(c, 2, c.loadC) },
	0x52: func(c *CPU) { bit(c, 2, c.loadD) },
	0x53: func(c *CPU) { bit(c, 2, c.loadE) },
	0x54: func(c *CPU) { bit(c, 2, c.loadH) },
	0x55: func(c *CPU) { bit(c, 2, c.loadL) },
	0x56: func(c *CPU) { bit(c, 2, c.loadIndHL) },
	0x57: func(c *CPU) { bit(c, 2, c.loadA) },
	0x58: func(c *CPU) { bit(c, 3, c.loadB) },
	0x59: func(c *CPU) { bit(c, 3, c.loadC) },
	0x5a: func(c *CPU) { bit(c, 3, c.loadD) },
	0x5b: func(c *CPU) { bit(c, 3, c.loadE) },
	0x5c: func(c *CPU) { bit(c, 3, c.loadH) },
	0x5d: func(c *CPU) { bit(c, 3, c.loadL) },
	0x5e: func(c *CPU) { bit(c, 3, c.loadIndHL) },
	0x5f: func(c *CPU) { bit(c, 3, c.loadA) },
	0x60: func(c *CPU) { bit(c, 4, c.loadB) },
	0x61: func(c *CPU) { bit(c, 4, c.loadC) },
	0x62: func(c *CPU) { bit(c, 4, c.loadD) },
	0x63: func(c *CPU) { bit(c, 4, c.loadE) },
	0x64: func(c *CPU) { bit(c, 4, c.loadH) },
	0x65: func(c *CPU) { bit(c, 4, c.loadL) },
	0x66: func(c *CPU) { bit(c, 4, c.loadIndHL) },
	0x67: func(c *CPU) { bit(c, 4, c.loadA) },
	0x68: func(c *CPU) { bit(c, 5, c.loadB) },
	0x69: func(c *CPU) { bit(c, 5, c.loadC) },
	0x6a: func(c *CPU) { bit(c, 5, c.loadD) },
	0x6b: func(c *CPU) { bit(c, 5, c.loadE) },
	0x6c: func(c *CPU) { bit(c, 5, c.loadH) },
	0x6d: func(c *CPU) { bit(c, 5, c.loadL) },
	0x6e: func(c *CPU) { bit(c, 5, c.loadIndHL) },
	0x6f: func(c *CPU) { bit(c, 5, c.loadA) },
	0x70: func(c *CPU) { bit(c, 6, c.loadB) },
	0x71: func(c *CPU) { bit(c, 6, c.loadC) },
	0x72: func(c *CPU) { bit(c, 6, c.loadD) },
	0x73: func(c *CPU) { bit(c, 6, c.loadE) },
	0x74: func(c *CPU) { bit(c, 6, c.loadH) },
	0x75: func(c *CPU) { bit(c, 6, c.loadL) },
	0x76: func(c *CPU) { bit(c, 6, c.loadIndHL) },
	0x77: func(c *CPU) { bit(c, 6, c.loadA) },
	0x78: func(c *CPU) { bit(c, 7, c.loadB) },
	0x79: func(c *CPU) { bit(c, 7, c.loadC) },
	0x7a: func(c *CPU) { bit(c, 7, c.loadD) },
	0x7b: func(c *CPU) { bit(c, 7, c.loadE) },
	0x7c: func(c *CPU) { bit(c, 7, c.loadH) },
	0x7d: func(c *CPU) { bit(c, 7, c.loadL) },
	0x7e: func(c *CPU) { bit(c, 7, c.loadIndHL) },
	0x7f: func(c *CPU) { bit(c, 7, c.loadA) },
	0x80: func(c *CPU) { res(c, 0, c.storeB, c.loadB) },
	0x81: func(c *CPU) { res(c, 0, c.storeC, c.loadC) },
	0x82: func(c *CPU) { res(c, 0, c.storeD, c.loadD) },
	0x83: func(c *CPU) { res(c, 0, c.storeE, c.loadE) },
	0x84: func(c *CPU) { res(c, 0, c.storeH, c.loadH) },
	0x85: func(c *CPU) { res(c, 0, c.storeL, c.loadL) },
	0x86: func(c *CPU) { res(c, 0, c.storeIndHL, c.loadIndHL) },
	0x87: func(c *CPU) { res(c, 0, c.storeA, c.loadA) },
	0x88: func(c *CPU) { res(c, 1, c.storeB, c.loadB) },
	0x89: func(c *CPU) { res(c, 1, c.storeC, c.loadC) },
	0x8a: func(c *CPU) { res(c, 1, c.storeD, c.loadD) },
	0x8b: func(c *CPU) { res(c, 1, c.storeE, c.loadE) },
	0x8c: func(c *CPU) { res(c, 1, c.storeH, c.loadH) },
	0x8d: func(c *CPU) { res(c, 1, c.storeL, c.loadL) },
	0x8e: func(c *CPU) { res(c, 1, c.storeIndHL, c.loadIndHL) },
	0x8f: func(c *CPU) { res(c, 1, c.storeA, c.loadA) },
	0x90: func(c *CPU) { res(c, 2, c.storeB, c.loadB) },
	0x91: func(c *CPU) { res(c, 2, c.storeC, c.loadC) },
	0x92: func(c *CPU) { res(c, 2, c.storeD, c.loadD) },
	0x93: func(c *CPU) { res(c, 2, c.storeE, c.loadE) },
	0x94: func(c *CPU) { res(c, 2, c.storeH, c.loadH) },
	0x95: func(c *CPU) { res(c, 2, c.storeL, c.loadL) },
	0x96: func(c *CPU) { res(c, 2, c.storeIndHL, c.loadIndHL) },
	0x97: func(c *CPU) { res(c, 2, c.storeA, c.loadA) },
	0x98: func(c *CPU) { res(c, 3, c.storeB, c.loadB) },
	0x99: func(c *CPU) { res(c, 3, c.storeC, c.loadC) },
	0x9a: func(c *CPU) { res(c, 3, c.storeD, c.loadD) },
	0x9b: func(c *CPU) { res(c, 3, c.storeE, c.loadE) },
	0x9c: func(c *CPU) { res(c, 3, c.storeH, c.loadH) },
	0x9d: func(c *CPU) { res(c, 3, c.storeL, c.loadL) },
	0x9e: func(c *CPU) { res(c, 3, c.storeIndHL, c.loadIndHL) },
	0x9f: func(c *CPU) { res(c, 3, c.storeA, c.loadA) },
	0xa0: func(c *CPU) { res(c, 4, c.storeB, c.loadB) },
	0xa1: func(c *CPU) { res(c, 4, c.storeC, c.loadC) },
	0xa2: func(c *CPU) { res(c, 4, c.storeD, c.loadD) },
	0xa3: func(c *CPU) { res(c, 4, c.storeE, c.loadE) },
	0xa4: func(c *CPU) { res(c, 4, c.storeH, c.loadH) },
	0xa5: func(c *CPU) { res(c, 4, c.storeL, c.loadL) },
	0xa6: func(c *CPU) { res(c, 4, c.storeIndHL, c.loadIndHL) },
	0xa7: func(c *CPU) { res(c, 4, c.storeA, c.loadA) },
	0xa8: func(c *CPU) { res(c, 5, c.storeB, c.loadB) },
	0xa9: func(c *CPU) { res(c, 5, c.storeC, c.loadC) },
	0xaa: func(c *CPU) { res(c, 5, c.storeD, c.loadD) },
	0xab: func(c *CPU) { res(c, 5, c.storeE, c.loadE) },
	0xac: func(c *CPU) { res(c, 5, c.storeH, c.loadH) },
	0xad: func(c *CPU) { res(c, 5, c.storeL, c.loadL) },
	0xae: func(c *CPU) { res(c, 5, c.storeIndHL, c.loadIndHL) },
	0xaf: func(c *CPU) { res(c, 5, c.storeA, c.loadA) },
	0xb0: func(c *CPU) { res(c, 6, c.storeB, c.loadB) },
	0xb1: func(c *CPU) { res(c, 6, c.storeC, c.loadC) },
	0xb2: func(c *CPU) { res(c, 6, c.storeD, c.loadD) },
	0xb3: func(c *CPU) { res(c, 6, c.storeE, c.loadE) },
	0xb4: func(c *CPU) { res(c, 6, c.storeH, c.loadH) },
	0xb5: func(c *CPU) { res(c, 6, c.storeL, c.loadL) },
	0xb6: func(c *CPU) { res(c, 6, c.storeIndHL, c.loadIndHL) },
	0xb7: func(c *CPU) { res(c, 6, c.storeA, c.loadA) },
	0xb8: func(c *CPU) { res(c, 7, c.storeB, c.loadB) },
	0xb9: func(c *CPU) { res(c, 7, c.storeC, c.loadC) },
	0xba: func(c *CPU) { res(c, 7, c.storeD, c.loadD) },
	0xbb: func(c *CPU) { res(c, 7, c.storeE, c.loadE) },
	0xbc: func(c *CPU) { res(c, 7, c.storeH, c.loadH) },
	0xbd: func(c *CPU) { res(c, 7, c.storeL, c.loadL) },
	0xbe: func(c *CPU) { res(c, 7, c.storeIndHL, c.loadIndHL) },
	0xbf: func(c *CPU) { res(c, 7, c.storeA, c.loadA) },
	0xc0: func(c *CPU) { set(c, 0, c.storeB, c.loadB) },
	0xc1: func(c *CPU) { set(c, 0, c.storeC, c.loadC) },
	0xc2: func(c *CPU) { set(c, 0, c.storeD, c.loadD) },
	0xc3: func(c *CPU) { set(c, 0, c.storeE, c.loadE) },
	0xc4: func(c *CPU) { set(c, 0, c.storeH, c.loadH) },
	0xc5: func(c *CPU) { set(c, 0, c.storeL, c.loadL) },
	0xc6: func(c *CPU) { set(c, 0, c.storeIndHL, c.loadIndHL) },
	0xc7: func(c *CPU) { set(c, 0, c.storeA, c.loadA) },
	0xc8: func(c *CPU) { set(c, 1, c.storeB, c.loadB) },
	0xc9: func(c *CPU) { set(c, 1, c.storeC, c.loadC) },
	0xca: func(c *CPU) { set(c, 1, c.storeD, c.loadD) },
	0xcb: func(c *CPU) { set(c, 1, c.storeE, c.loadE) },
	0xcc: func(c *CPU) { set(c, 1, c.storeH, c.loadH) },
	0xcd: func(c *CPU) { set(c, 1, c.storeL, c.loadL) },
	0xce: func(c *CPU) { set(c, 1, c.storeIndHL, c.loadIndHL) },
	0xcf: func(c *CPU) { set(c, 1, c.storeA, c.loadA) },
	0xd0: func(c *CPU) { set(c, 2, c.storeB, c.loadB) },
	0xd1: func(c *CPU) { set(c, 2, c.storeC, c.loadC) },
	0xd2: func(c *CPU) { set(c, 2, c.storeD, c.loadD) },
	0xd3: func(c *CPU) { set(c, 2, c.storeE, c.loadE) },
	0xd4: func(c *CPU) { set(c, 2, c.storeH, c.loadH) },
	0xd5: func(c *CPU) { set(c, 2, c.storeL, c.loadL) },
	0xd6: func(c *CPU) { set(c, 2, c.storeIndHL, c.loadIndHL) },
	0xd7: func(c *CPU) { set(c, 2, c.storeA, c.loadA) },
	0xd8: func(c *CPU) { set(c, 3, c.storeB, c.loadB) },
	0xd9: func(c *CPU) { set(c, 3, c.storeC, c.loadC) },
	0xda: func(c *CPU) { set(c, 3, c.storeD, c.loadD) },
	0xdb: func(c *CPU) { set(c, 3, c.storeE, c.loadE) },
	0xdc: func(c *CPU) { set(c, 3, c.storeH, c.loadH) },
	0xdd: func(c *CPU) { set(c, 3, c.storeL, c.loadL) },
	0xde: func(c *CPU) { set(c, 3, c.storeIndHL, c.loadIndHL) },
	0xdf: func(c *CPU) { set(c, 3, c.storeA, c.loadA) },
	0xe0: func(c *CPU) { set(c, 4, c.storeB, c.loadB) },
	0xe1: func(c *CPU) { set(c, 4, c.storeC, c.loadC) },
	0xe2: func(c *CPU) { set(c, 4, c.storeD, c.loadD) },
	0xe3: func(c *CPU) { set(c, 4, c.storeE, c.loadE) },
	0xe4: func(c *CPU) { set(c, 4, c.storeH, c.loadH) },
	0xe5: func(c *CPU) { set(c, 4, c.storeL, c.loadL) },
	0xe6: func(c *CPU) { set(c, 4, c.storeIndHL, c.loadIndHL) },
	0xe7: func(c *CPU) { set(c, 4, c.storeA, c.loadA) },
	0xe8: func(c *CPU) { set(c, 5, c.storeB, c.loadB) },
	0xe9: func(c *CPU) { set(c, 5, c.storeC, c.loadC) },
	0xea: func(c *CPU) { set(c, 5, c.storeD, c.loadD) },
	0xeb: func(c *CPU) { set(c, 5, c.storeE, c.loadE) },
	0xec: func(c *CPU) { set(c, 5, c.storeH, c.loadH) },
	0xed: func(c *CPU) { set(c, 5, c.storeL, c.loadL) },
	0xee: func(c *CPU) { set(c, 5, c.storeIndHL, c.loadIndHL) },
	0xef: func(c *CPU) { set(c, 5, c.storeA, c.loadA) },
	0xf0: func(c *CPU) { set(c, 6, c.storeB, c.loadB) },
	0xf1: func(c *CPU) { set(c, 6, c.storeC, c.loadC) },
	0xf2: func(c *CPU) { set(c, 6, c.storeD, c.loadD) },
	0xf3: func(c *CPU) { set(c, 6, c.storeE, c.loadE) },
	0xf4: func(c *CPU) { set(c, 6, c.storeH, c.loadH) },
	0xf5: func(c *CPU) { set(c, 6, c.storeL, c.loadL) },
	0xf6: func(c *CPU) { set(c, 6, c.storeIndHL, c.loadIndHL) },
	0xf7: func(c *CPU) { set(c, 6, c.storeA, c.loadA) },
	0xf8: func(c *CPU) { set(c, 7, c.storeB, c.loadB) },
	0xf9: func(c *CPU) { set(c, 7, c.storeC, c.loadC) },
	0xfa: func(c *CPU) { set(c, 7, c.storeD, c.loadD) },
	0xfb: func(c *CPU) { set(c, 7, c.storeE, c.loadE) },
	0xfc: func(c *CPU) { set(c, 7, c.storeH, c.loadH) },
	0xfd: func(c *CPU) { set(c, 7, c.storeL, c.loadL) },
	0xfe: func(c *CPU) { set(c, 7, c.storeIndHL, c.loadIndHL) },
	0xff: func(c *CPU) { set(c, 7, c.storeA, c.loadA) },
}
var opcodesED = map[uint8]func(c *CPU){
	0x40: func(c *CPU) { in(c, c.storeB, c.loadIndC) },
	0x41: func(c *CPU) { ld(c, c.outIndC, c.loadB) },
	0x42: func(c *CPU) { sbc16(c, c.storeHL, c.loadHL, c.loadBC) },
	0x43: func(c *CPU) { ld16(c, c.store16IndImm, c.loadBC) },
	0x44: func(c *CPU) { neg(c) },
	0x45: func(c *CPU) { retn(c) },
	0x46: func(c *CPU) { im(c, 0) },
	0x47: func(c *CPU) { ld(c, c.storeI, c.loadA) },
	0x48: func(c *CPU) { in(c, c.storeC, c.loadIndC) },
	0x49: func(c *CPU) { ld(c, c.outIndC, c.loadC) },
	0x4a: func(c *CPU) { adc16(c, c.storeHL, c.loadHL, c.loadBC) },
	0x4b: func(c *CPU) { ld16(c, c.storeBC, c.load16IndImm) },
	0x4c: func(c *CPU) { neg(c) },
	0x4d: func(c *CPU) { reti(c) },
	0x4e: func(c *CPU) { im(c, 0) },
	0x4f: func(c *CPU) { ld(c, c.storeR, c.loadA) },
	0x50: func(c *CPU) { in(c, c.storeD, c.loadIndC) },
	0x51: func(c *CPU) { ld(c, c.outIndC, c.loadD) },
	0x52: func(c *CPU) { sbc16(c, c.storeHL, c.loadHL, c.loadDE) },
	0x53: func(c *CPU) { ld16(c, c.store16IndImm, c.loadDE) },
	0x54: func(c *CPU) { neg(c) },
	0x55: func(c *CPU) { retn(c) },
	0x56: func(c *CPU) { im(c, 1) },
	0x57: func(c *CPU) { ldair(c, c.loadI) },
	0x58: func(c *CPU) { in(c, c.storeE, c.loadIndC) },
	0x59: func(c *CPU) { ld(c, c.outIndC, c.loadE) },
	0x5a: func(c *CPU) { adc16(c, c.storeHL, c.loadHL, c.loadDE) },
	0x5b: func(c *CPU) { ld16(c, c.storeDE, c.load16IndImm) },
	0x5c: func(c *CPU) { neg(c) },
	0x5d: func(c *CPU) { retn(c) },
	0x5e: func(c *CPU) { im(c, 2) },
	0x5f: func(c *CPU) { ldair(c, c.loadR) },
	0x60: func(c *CPU) { in(c, c.storeH, c.loadIndC) },
	0x61: func(c *CPU) { ld(c, c.outIndC, c.loadH) },
	0x62: func(c *CPU) { sbc16(c, c.storeHL, c.loadHL, c.loadHL) },
	0x63: func(c *CPU) { ld16(c, c.store16IndImm, c.loadHL) },
	0x64: func(c *CPU) { neg(c) },
	0x65: func(c *CPU) { retn(c) },
	0x66: func(c *CPU) { im(c, 0) },
	0x67: func(c *CPU) { rrd(c) },
	0x68: func(c *CPU) { in(c, c.storeL, c.loadIndC) },
	0x69: func(c *CPU) { ld(c, c.outIndC, c.loadL) },
	0x6a: func(c *CPU) { adc16(c, c.storeHL, c.loadHL, c.loadHL) },
	0x6b: func(c *CPU) { ld16(c, c.storeHL, c.load16IndImm) },
	0x6c: func(c *CPU) { neg(c) },
	0x6d: func(c *CPU) { retn(c) },
	0x6e: func(c *CPU) { im(c, 0) },
	0x6f: func(c *CPU) { rld(c) },
	0x70: func(c *CPU) { in(c, c.storeNil, c.loadIndC) },
	0x71: func(c *CPU) { ld(c, c.outIndC, c.loadZero) },
	0x72: func(c *CPU) { sbc16(c, c.storeHL, c.loadHL, c.loadSP) },
	0x73: func(c *CPU) { ld16(c, c.store16IndImm, c.loadSP) },
	0x74: func(c *CPU) { neg(c) },
	0x75: func(c *CPU) { retn(c) },
	0x76: func(c *CPU) { im(c, 1) },
	0x78: func(c *CPU) { in(c, c.storeA, c.loadIndC) },
	0x79: func(c *CPU) { ld(c, c.outIndC, c.loadA) },
	0x7a: func(c *CPU) { adc16(c, c.storeHL, c.loadHL, c.loadSP) },
	0x7b: func(c *CPU) { ld16(c, c.storeSP, c.load16IndImm) },
	0x7c: func(c *CPU) { neg(c) },
	0x7d: func(c *CPU) { retn(c) },
	0x7e: func(c *CPU) { im(c, 2) },
	0xa0: func(c *CPU) { ldx(c, 1) },
	0xa1: func(c *CPU) { cpx(c, 1) },
	0xa2: func(c *CPU) { inx(c, 1) },
	0xa3: func(c *CPU) { outx(c, 1) },
	0xa8: func(c *CPU) { ldx(c, -1) },
	0xa9: func(c *CPU) { cpx(c, -1) },
	0xaa: func(c *CPU) { inx(c, -1) },
	0xab: func(c *CPU) { outx(c, -1) },
	0xb0: func(c *CPU) { ldxr(c, 1) },
	0xb1: func(c *CPU) { cpxr(c, 1) },
	0xb2: func(c *CPU) { inxr(c, 1) },
	0xb3: func(c *CPU) { outxr(c, 1) },
	0xb8: func(c *CPU) { ldxr(c, -1) },
	0xb9: func(c *CPU) { cpxr(c, -1) },
	0xba: func(c *CPU) { inxr(c, -1) },
	0xbb: func(c *CPU) { outxr(c, -1) },
}
var opcodesDD = map[uint8]func(c *CPU){
	0x00: func(c *CPU) { nop() },
	0x01: func(c *CPU) { ld16(c, c.storeBC, c.loadImm16) },
	0x02: func(c *CPU) { ld(c, c.storeIndBC, c.loadA) },
	0x03: func(c *CPU) { inc16(c, c.storeBC, c.loadBC) },
	0x04: func(c *CPU) { inc(c, c.storeB, c.loadB) },
	0x05: func(c *CPU) { dec(c, c.storeB, c.loadB) },
	0x06: func(c *CPU) { ld(c, c.storeB, c.loadImm) },
	0x07: func(c *CPU) { rlca(c) },
	0x08: func(c *CPU) { ex(c, c.loadAF, c.storeAF, c.loadAF1, c.storeAF1) },
	0x09: func(c *CPU) { add16(c, c.storeIX, c.loadIX, c.loadBC) },
	0x0a: func(c *CPU) { ld(c, c.storeA, c.loadIndBC) },
	0x0b: func(c *CPU) { dec16(c, c.storeBC, c.loadBC) },
	0x0c: func(c *CPU) { inc(c, c.storeC, c.loadC) },
	0x0d: func(c *CPU) { dec(c, c.storeC, c.loadC) },
	0x0e: func(c *CPU) { ld(c, c.storeC, c.loadImm) },
	0x0f: func(c *CPU) { rrca(c) },
	0x10: func(c *CPU) { djnz(c, c.loadImm) },
	0x11: func(c *CPU) { ld16(c, c.storeDE, c.loadImm16) },
	0x12: func(c *CPU) { ld(c, c.storeIndDE, c.loadA) },
	0x13: func(c *CPU) { inc16(c, c.storeDE, c.loadDE) },
	0x14: func(c *CPU) { inc(c, c.storeD, c.loadD) },
	0x15: func(c *CPU) { dec(c, c.storeD, c.loadD) },
	0x16: func(c *CPU) { ld(c, c.storeD, c.loadImm) },
	0x17: func(c *CPU) { rla(c) },
	0x18: func(c *CPU) { jra(c, c.loadImm) },
	0x19: func(c *CPU) { add16(c, c.storeIX, c.loadIX, c.loadDE) },
	0x1a: func(c *CPU) { ld(c, c.storeA, c.loadIndDE) },
	0x1b: func(c *CPU) { dec16(c, c.storeDE, c.loadDE) },
	0x1c: func(c *CPU) { inc(c, c.storeE, c.loadE) },
	0x1d: func(c *CPU) { dec(c, c.storeE, c.loadE) },
	0x1e: func(c *CPU) { ld(c, c.storeE, c.loadImm) },
	0x1f: func(c *CPU) { rra(c) },
	0x20: func(c *CPU) { jr(c, FlagZ, false, c.loadImm) },
	0x21: func(c *CPU) { ld16(c, c.storeIX, c.loadImm16) },
	0x22: func(c *CPU) { ld16(c, c.store16IndImm, c.loadIX) },
	0x23: func(c *CPU) { inc16(c, c.storeIX, c.loadIX) },
	0x24: func(c *CPU) { inc(c, c.storeIXH, c.loadIXH) },
	0x25: func(c *CPU) { dec(c, c.storeIXH, c.loadIXH) },
	0x26: func(c *CPU) { ld(c, c.storeIXH, c.loadImm) },
	0x27: func(c *CPU) { daa(c) },
	0x28: func(c *CPU) { jr(c, FlagZ, true, c.loadImm) },
	0x29: func(c *CPU) { add16(c, c.storeIX, c.loadIX, c.loadIX) },
	0x2a: func(c *CPU) { ld16(c, c.storeIX, c.load16IndImm) },
	0x2b: func(c *CPU) { dec16(c, c.storeIX, c.loadIX) },
	0x2c: func(c *CPU) { inc(c, c.storeIXL, c.loadIXL) },
	0x2d: func(c *CPU) { dec(c, c.storeIXL, c.loadIXL) },
	0x2e: func(c *CPU) { ld(c, c.storeIXL, c.loadImm) },
	0x2f: func(c *CPU) { cpl(c) },
	0x30: func(c *CPU) { jr(c, FlagC, false, c.loadImm) },
	0x31: func(c *CPU) { ld16(c, c.storeSP, c.loadImm16) },
	0x32: func(c *CPU) { ld(c, c.storeIndImm, c.loadA) },
	0x33: func(c *CPU) { inc16(c, c.storeSP, c.loadSP) },
	0x34: func(c *CPU) { c.fetchd(); inc(c, c.storeIndIX, c.loadIndIX) },
	0x35: func(c *CPU) { c.fetchd(); dec(c, c.storeIndIX, c.loadIndIX) },
	0x36: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadImm) },
	0x37: func(c *CPU) { scf(c) },
	0x38: func(c *CPU) { jr(c, FlagC, true, c.loadImm) },
	0x39: func(c *CPU) { add16(c, c.storeIX, c.loadIX, c.loadSP) },
	0x3a: func(c *CPU) { ld(c, c.storeA, c.loadIndImm) },
	0x3b: func(c *CPU) { dec16(c, c.storeSP, c.loadSP) },
	0x3c: func(c *CPU) { inc(c, c.storeA, c.loadA) },
	0x3d: func(c *CPU) { dec(c, c.storeA, c.loadA) },
	0x3e: func(c *CPU) { ld(c, c.storeA, c.loadImm) },
	0x3f: func(c *CPU) { ccf(c) },
	0x40: func(c *CPU) { ld(c, c.storeB, c.loadB) },
	0x41: func(c *CPU) { ld(c, c.storeB, c.loadC) },
	0x42: func(c *CPU) { ld(c, c.storeB, c.loadD) },
	0x43: func(c *CPU) { ld(c, c.storeB, c.loadE) },
	0x44: func(c *CPU) { ld(c, c.storeB, c.loadIXH) },
	0x45: func(c *CPU) { ld(c, c.storeB, c.loadIXL) },
	0x46: func(c *CPU) { c.fetchd(); ld(c, c.storeB, c.loadIndIX) },
	0x47: func(c *CPU) { ld(c, c.storeB, c.loadA) },
	0x48: func(c *CPU) { ld(c, c.storeC, c.loadB) },
	0x49: func(c *CPU) { ld(c, c.storeC, c.loadC) },
	0x4a: func(c *CPU) { ld(c, c.storeC, c.loadD) },
	0x4b: func(c *CPU) { ld(c, c.storeC, c.loadE) },
	0x4c: func(c *CPU) { ld(c, c.storeC, c.loadIXH) },
	0x4d: func(c *CPU) { ld(c, c.storeC, c.loadIXL) },
	0x4e: func(c *CPU) { c.fetchd(); ld(c, c.storeC, c.loadIndIX) },
	0x4f: func(c *CPU) { ld(c, c.storeC, c.loadA) },
	0x50: func(c *CPU) { ld(c, c.storeD, c.loadB) },
	0x51: func(c *CPU) { ld(c, c.storeD, c.loadC) },
	0x52: func(c *CPU) { ld(c, c.storeD, c.loadD) },
	0x53: func(c *CPU) { ld(c, c.storeD, c.loadE) },
	0x54: func(c *CPU) { ld(c, c.storeD, c.loadIXH) },
	0x55: func(c *CPU) { ld(c, c.storeD, c.loadIXL) },
	0x56: func(c *CPU) { c.fetchd(); ld(c, c.storeD, c.loadIndIX) },
	0x57: func(c *CPU) { ld(c, c.storeD, c.loadA) },
	0x58: func(c *CPU) { ld(c, c.storeE, c.loadB) },
	0x59: func(c *CPU) { ld(c, c.storeE, c.loadC) },
	0x5a: func(c *CPU) { ld(c, c.storeE, c.loadD) },
	0x5b: func(c *CPU) { ld(c, c.storeE, c.loadE) },
	0x5c: func(c *CPU) { ld(c, c.storeE, c.loadIXH) },
	0x5d: func(c *CPU) { ld(c, c.storeE, c.loadIXL) },
	0x5e: func(c *CPU) { c.fetchd(); ld(c, c.storeE, c.loadIndIX) },
	0x5f: func(c *CPU) { ld(c, c.storeE, c.loadA) },
	0x60: func(c *CPU) { ld(c, c.storeIXH, c.loadB) },
	0x61: func(c *CPU) { ld(c, c.storeIXH, c.loadC) },
	0x62: func(c *CPU) { ld(c, c.storeIXH, c.loadD) },
	0x63: func(c *CPU) { ld(c, c.storeIXH, c.loadE) },
	0x64: func(c *CPU) { ld(c, c.storeIXH, c.loadIXH) },
	0x65: func(c *CPU) { ld(c, c.storeIXH, c.loadIXL) },
	0x66: func(c *CPU) { c.fetchd(); ld(c, c.storeH, c.loadIndIX) },
	0x67: func(c *CPU) { ld(c, c.storeIXH, c.loadA) },
	0x68: func(c *CPU) { ld(c, c.storeIXL, c.loadB) },
	0x69: func(c *CPU) { ld(c, c.storeIXL, c.loadC) },
	0x6a: func(c *CPU) { ld(c, c.storeIXL, c.loadD) },
	0x6b: func(c *CPU) { ld(c, c.storeIXL, c.loadE) },
	0x6c: func(c *CPU) { ld(c, c.storeIXL, c.loadIXH) },
	0x6d: func(c *CPU) { ld(c, c.storeIXL, c.loadIXL) },
	0x6e: func(c *CPU) { c.fetchd(); ld(c, c.storeL, c.loadIndIX) },
	0x6f: func(c *CPU) { ld(c, c.storeIXL, c.loadA) },
	0x70: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadB) },
	0x71: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadC) },
	0x72: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadD) },
	0x73: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadE) },
	0x74: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadH) },
	0x75: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadL) },
	0x76: func(c *CPU) { halt(c) },
	0x77: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIX, c.loadA) },
	0x78: func(c *CPU) { ld(c, c.storeA, c.loadB) },
	0x79: func(c *CPU) { ld(c, c.storeA, c.loadC) },
	0x7a: func(c *CPU) { ld(c, c.storeA, c.loadD) },
	0x7b: func(c *CPU) { ld(c, c.storeA, c.loadE) },
	0x7c: func(c *CPU) { ld(c, c.storeA, c.loadIXH) },
	0x7d: func(c *CPU) { ld(c, c.storeA, c.loadIXL) },
	0x7e: func(c *CPU) { c.fetchd(); ld(c, c.storeA, c.loadIndIX) },
	0x7f: func(c *CPU) { ld(c, c.storeA, c.loadA) },
	0x80: func(c *CPU) { add(c, c.loadA, c.loadB) },
	0x81: func(c *CPU) { add(c, c.loadA, c.loadC) },
	0x82: func(c *CPU) { add(c, c.loadA, c.loadD) },
	0x83: func(c *CPU) { add(c, c.loadA, c.loadE) },
	0x84: func(c *CPU) { add(c, c.loadA, c.loadIXH) },
	0x85: func(c *CPU) { add(c, c.loadA, c.loadIXL) },
	0x86: func(c *CPU) { c.fetchd(); add(c, c.loadA, c.loadIndIX) },
	0x87: func(c *CPU) { add(c, c.loadA, c.loadA) },
	0x88: func(c *CPU) { adc(c, c.loadA, c.loadB) },
	0x89: func(c *CPU) { adc(c, c.loadA, c.loadC) },
	0x8a: func(c *CPU) { adc(c, c.loadA, c.loadD) },
	0x8b: func(c *CPU) { adc(c, c.loadA, c.loadE) },
	0x8c: func(c *CPU) { adc(c, c.loadA, c.loadIXH) },
	0x8d: func(c *CPU) { adc(c, c.loadA, c.loadIXL) },
	0x8e: func(c *CPU) { c.fetchd(); adc(c, c.loadA, c.loadIndIX) },
	0x8f: func(c *CPU) { adc(c, c.loadA, c.loadA) },
	0x90: func(c *CPU) { sub(c, c.loadA, c.loadB) },
	0x91: func(c *CPU) { sub(c, c.loadA, c.loadC) },
	0x92: func(c *CPU) { sub(c, c.loadA, c.loadD) },
	0x93: func(c *CPU) { sub(c, c.loadA, c.loadE) },
	0x94: func(c *CPU) { sub(c, c.loadA, c.loadIXH) },
	0x95: func(c *CPU) { sub(c, c.loadA, c.loadIXL) },
	0x96: func(c *CPU) { c.fetchd(); sub(c, c.loadA, c.loadIndIX) },
	0x97: func(c *CPU) { sub(c, c.loadA, c.loadA) },
	0x98: func(c *CPU) { sbc(c, c.loadA, c.loadB) },
	0x99: func(c *CPU) { sbc(c, c.loadA, c.loadC) },
	0x9a: func(c *CPU) { sbc(c, c.loadA, c.loadD) },
	0x9b: func(c *CPU) { sbc(c, c.loadA, c.loadE) },
	0x9c: func(c *CPU) { sbc(c, c.loadA, c.loadIXH) },
	0x9d: func(c *CPU) { sbc(c, c.loadA, c.loadIXL) },
	0x9e: func(c *CPU) { c.fetchd(); sbc(c, c.loadA, c.loadIndIX) },
	0x9f: func(c *CPU) { sbc(c, c.loadA, c.loadA) },
	0xa0: func(c *CPU) { and(c, c.loadB) },
	0xa1: func(c *CPU) { and(c, c.loadC) },
	0xa2: func(c *CPU) { and(c, c.loadD) },
	0xa3: func(c *CPU) { and(c, c.loadE) },
	0xa4: func(c *CPU) { and(c, c.loadIXH) },
	0xa5: func(c *CPU) { and(c, c.loadIXL) },
	0xa6: func(c *CPU) { c.fetchd(); and(c, c.loadIndIX) },
	0xa7: func(c *CPU) { and(c, c.loadA) },
	0xa8: func(c *CPU) { xor(c, c.loadB) },
	0xa9: func(c *CPU) { xor(c, c.loadC) },
	0xaa: func(c *CPU) { xor(c, c.loadD) },
	0xab: func(c *CPU) { xor(c, c.loadE) },
	0xac: func(c *CPU) { xor(c, c.loadIXH) },
	0xad: func(c *CPU) { xor(c, c.loadIXL) },
	0xae: func(c *CPU) { c.fetchd(); xor(c, c.loadIndIX) },
	0xaf: func(c *CPU) { xor(c, c.loadA) },
	0xb0: func(c *CPU) { or(c, c.loadB) },
	0xb1: func(c *CPU) { or(c, c.loadC) },
	0xb2: func(c *CPU) { or(c, c.loadD) },
	0xb3: func(c *CPU) { or(c, c.loadE) },
	0xb4: func(c *CPU) { or(c, c.loadIXH) },
	0xb5: func(c *CPU) { or(c, c.loadIXL) },
	0xb6: func(c *CPU) { c.fetchd(); or(c, c.loadIndIX) },
	0xb7: func(c *CPU) { or(c, c.loadA) },
	0xb8: func(c *CPU) { cp(c, c.loadB) },
	0xb9: func(c *CPU) { cp(c, c.loadC) },
	0xba: func(c *CPU) { cp(c, c.loadD) },
	0xbb: func(c *CPU) { cp(c, c.loadE) },
	0xbc: func(c *CPU) { cp(c, c.loadIXH) },
	0xbd: func(c *CPU) { cp(c, c.loadIXL) },
	0xbe: func(c *CPU) { c.fetchd(); cp(c, c.loadIndIX) },
	0xbf: func(c *CPU) { cp(c, c.loadA) },
	0xc0: func(c *CPU) { ret(c, FlagZ, false) },
	0xc1: func(c *CPU) { pop(c, c.storeBC) },
	0xc2: func(c *CPU) { jp(c, FlagZ, false, c.loadImm16) },
	0xc3: func(c *CPU) { jpa(c, c.loadImm16) },
	0xc4: func(c *CPU) { call(c, FlagZ, false, c.loadImm16) },
	0xc5: func(c *CPU) { push(c, c.loadBC) },
	0xc6: func(c *CPU) { add(c, c.loadA, c.loadImm) },
	0xc7: func(c *CPU) { rst(c, 0) },
	0xc8: func(c *CPU) { ret(c, FlagZ, true) },
	0xc9: func(c *CPU) { reta(c) },
	0xca: func(c *CPU) { jp(c, FlagZ, true, c.loadImm16) },
	0xcc: func(c *CPU) { call(c, FlagZ, true, c.loadImm16) },
	0xcd: func(c *CPU) { calla(c, c.loadImm16) },
	0xce: func(c *CPU) { adc(c, c.loadA, c.loadImm) },
	0xcf: func(c *CPU) { rst(c, 1) },
	0xd0: func(c *CPU) { ret(c, FlagC, false) },
	0xd1: func(c *CPU) { pop(c, c.storeDE) },
	0xd2: func(c *CPU) { jp(c, FlagC, false, c.loadImm16) },
	0xd3: func(c *CPU) { ld(c, c.outIndImm, c.loadA) },
	0xd4: func(c *CPU) { call(c, FlagC, false, c.loadImm16) },
	0xd5: func(c *CPU) { push(c, c.loadDE) },
	0xd6: func(c *CPU) { sub(c, c.loadA, c.loadImm) },
	0xd7: func(c *CPU) { rst(c, 2) },
	0xd8: func(c *CPU) { ret(c, FlagC, true) },
	0xd9: func(c *CPU) { exx(c) },
	0xda: func(c *CPU) { jp(c, FlagC, true, c.loadImm16) },
	0xdb: func(c *CPU) { ld(c, c.storeA, c.inIndImm) },
	0xdc: func(c *CPU) { call(c, FlagC, true, c.loadImm16) },
	0xde: func(c *CPU) { sbc(c, c.loadA, c.loadImm) },
	0xdf: func(c *CPU) { rst(c, 3) },
	0xe0: func(c *CPU) { ret(c, FlagV, false) },
	0xe1: func(c *CPU) { pop(c, c.storeIX) },
	0xe2: func(c *CPU) { jp(c, FlagV, false, c.loadImm16) },
	0xe3: func(c *CPU) { ex(c, c.load16IndSP, c.store16IndSP, c.loadIX, c.storeIX) },
	0xe4: func(c *CPU) { call(c, FlagV, false, c.loadImm16) },
	0xe5: func(c *CPU) { push(c, c.loadIX) },
	0xe6: func(c *CPU) { and(c, c.loadImm) },
	0xe7: func(c *CPU) { rst(c, 4) },
	0xe8: func(c *CPU) { ret(c, FlagV, true) },
	0xe9: func(c *CPU) { jpa(c, c.loadIX) },
	0xea: func(c *CPU) { jp(c, FlagV, true, c.loadImm16) },
	0xeb: func(c *CPU) { ex(c, c.loadDE, c.storeDE, c.loadHL, c.storeHL) },
	0xec: func(c *CPU) { call(c, FlagV, true, c.loadImm16) },
	0xee: func(c *CPU) { xor(c, c.loadImm) },
	0xef: func(c *CPU) { rst(c, 5) },
	0xf0: func(c *CPU) { ret(c, FlagS, false) },
	0xf1: func(c *CPU) { pop(c, c.storeAF) },
	0xf2: func(c *CPU) { jp(c, FlagS, false, c.loadImm16) },
	0xf3: func(c *CPU) { di(c) },
	0xf4: func(c *CPU) { call(c, FlagS, false, c.loadImm16) },
	0xf5: func(c *CPU) { push(c, c.loadAF) },
	0xf6: func(c *CPU) { or(c, c.loadImm) },
	0xf7: func(c *CPU) { rst(c, 6) },
	0xf8: func(c *CPU) { ret(c, FlagS, true) },
	0xf9: func(c *CPU) { ld16(c, c.storeSP, c.loadIX) },
	0xfa: func(c *CPU) { jp(c, FlagS, true, c.loadImm16) },
	0xfb: func(c *CPU) { ei(c) },
	0xfc: func(c *CPU) { call(c, FlagS, true, c.loadImm16) },
	0xfe: func(c *CPU) { cp(c, c.loadImm) },
	0xff: func(c *CPU) { rst(c, 7) },
}
var opcodesFD = map[uint8]func(c *CPU){
	0x00: func(c *CPU) { nop() },
	0x01: func(c *CPU) { ld16(c, c.storeBC, c.loadImm16) },
	0x02: func(c *CPU) { ld(c, c.storeIndBC, c.loadA) },
	0x03: func(c *CPU) { inc16(c, c.storeBC, c.loadBC) },
	0x04: func(c *CPU) { inc(c, c.storeB, c.loadB) },
	0x05: func(c *CPU) { dec(c, c.storeB, c.loadB) },
	0x06: func(c *CPU) { ld(c, c.storeB, c.loadImm) },
	0x07: func(c *CPU) { rlca(c) },
	0x08: func(c *CPU) { ex(c, c.loadAF, c.storeAF, c.loadAF1, c.storeAF1) },
	0x09: func(c *CPU) { add16(c, c.storeIY, c.loadIY, c.loadBC) },
	0x0a: func(c *CPU) { ld(c, c.storeA, c.loadIndBC) },
	0x0b: func(c *CPU) { dec16(c, c.storeBC, c.loadBC) },
	0x0c: func(c *CPU) { inc(c, c.storeC, c.loadC) },
	0x0d: func(c *CPU) { dec(c, c.storeC, c.loadC) },
	0x0e: func(c *CPU) { ld(c, c.storeC, c.loadImm) },
	0x0f: func(c *CPU) { rrca(c) },
	0x10: func(c *CPU) { djnz(c, c.loadImm) },
	0x11: func(c *CPU) { ld16(c, c.storeDE, c.loadImm16) },
	0x12: func(c *CPU) { ld(c, c.storeIndDE, c.loadA) },
	0x13: func(c *CPU) { inc16(c, c.storeDE, c.loadDE) },
	0x14: func(c *CPU) { inc(c, c.storeD, c.loadD) },
	0x15: func(c *CPU) { dec(c, c.storeD, c.loadD) },
	0x16: func(c *CPU) { ld(c, c.storeD, c.loadImm) },
	0x17: func(c *CPU) { rla(c) },
	0x18: func(c *CPU) { jra(c, c.loadImm) },
	0x19: func(c *CPU) { add16(c, c.storeIY, c.loadIY, c.loadDE) },
	0x1a: func(c *CPU) { ld(c, c.storeA, c.loadIndDE) },
	0x1b: func(c *CPU) { dec16(c, c.storeDE, c.loadDE) },
	0x1c: func(c *CPU) { inc(c, c.storeE, c.loadE) },
	0x1d: func(c *CPU) { dec(c, c.storeE, c.loadE) },
	0x1e: func(c *CPU) { ld(c, c.storeE, c.loadImm) },
	0x1f: func(c *CPU) { rra(c) },
	0x20: func(c *CPU) { jr(c, FlagZ, false, c.loadImm) },
	0x21: func(c *CPU) { ld16(c, c.storeIY, c.loadImm16) },
	0x22: func(c *CPU) { ld16(c, c.store16IndImm, c.loadIY) },
	0x23: func(c *CPU) { inc16(c, c.storeIY, c.loadIY) },
	0x24: func(c *CPU) { inc(c, c.storeIYH, c.loadIYH) },
	0x25: func(c *CPU) { dec(c, c.storeIYH, c.loadIYH) },
	0x26: func(c *CPU) { ld(c, c.storeIYH, c.loadImm) },
	0x27: func(c *CPU) { daa(c) },
	0x28: func(c *CPU) { jr(c, FlagZ, true, c.loadImm) },
	0x29: func(c *CPU) { add16(c, c.storeIY, c.loadIY, c.loadIY) },
	0x2a: func(c *CPU) { ld16(c, c.storeIY, c.load16IndImm) },
	0x2b: func(c *CPU) { dec16(c, c.storeIY, c.loadIY) },
	0x2c: func(c *CPU) { inc(c, c.storeIYL, c.loadIYL) },
	0x2d: func(c *CPU) { dec(c, c.storeIYL, c.loadIYL) },
	0x2e: func(c *CPU) { ld(c, c.storeIYL, c.loadImm) },
	0x2f: func(c *CPU) { cpl(c) },
	0x30: func(c *CPU) { jr(c, FlagC, false, c.loadImm) },
	0x31: func(c *CPU) { ld16(c, c.storeSP, c.loadImm16) },
	0x32: func(c *CPU) { ld(c, c.storeIndImm, c.loadA) },
	0x33: func(c *CPU) { inc16(c, c.storeSP, c.loadSP) },
	0x34: func(c *CPU) { c.fetchd(); inc(c, c.storeIndIY, c.loadIndIY) },
	0x35: func(c *CPU) { c.fetchd(); dec(c, c.storeIndIY, c.loadIndIY) },
	0x36: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadImm) },
	0x37: func(c *CPU) { scf(c) },
	0x38: func(c *CPU) { jr(c, FlagC, true, c.loadImm) },
	0x39: func(c *CPU) { add16(c, c.storeIY, c.loadIY, c.loadSP) },
	0x3a: func(c *CPU) { ld(c, c.storeA, c.loadIndImm) },
	0x3b: func(c *CPU) { dec16(c, c.storeSP, c.loadSP) },
	0x3c: func(c *CPU) { inc(c, c.storeA, c.loadA) },
	0x3d: func(c *CPU) { dec(c, c.storeA, c.loadA) },
	0x3e: func(c *CPU) { ld(c, c.storeA, c.loadImm) },
	0x3f: func(c *CPU) { ccf(c) },
	0x40: func(c *CPU) { ld(c, c.storeB, c.loadB) },
	0x41: func(c *CPU) { ld(c, c.storeB, c.loadC) },
	0x42: func(c *CPU) { ld(c, c.storeB, c.loadD) },
	0x43: func(c *CPU) { ld(c, c.storeB, c.loadE) },
	0x44: func(c *CPU) { ld(c, c.storeB, c.loadIYH) },
	0x45: func(c *CPU) { ld(c, c.storeB, c.loadIYL) },
	0x46: func(c *CPU) { c.fetchd(); ld(c, c.storeB, c.loadIndIY) },
	0x47: func(c *CPU) { ld(c, c.storeB, c.loadA) },
	0x48: func(c *CPU) { ld(c, c.storeC, c.loadB) },
	0x49: func(c *CPU) { ld(c, c.storeC, c.loadC) },
	0x4a: func(c *CPU) { ld(c, c.storeC, c.loadD) },
	0x4b: func(c *CPU) { ld(c, c.storeC, c.loadE) },
	0x4c: func(c *CPU) { ld(c, c.storeC, c.loadIYH) },
	0x4d: func(c *CPU) { ld(c, c.storeC, c.loadIYL) },
	0x4e: func(c *CPU) { c.fetchd(); ld(c, c.storeC, c.loadIndIY) },
	0x4f: func(c *CPU) { ld(c, c.storeC, c.loadA) },
	0x50: func(c *CPU) { ld(c, c.storeD, c.loadB) },
	0x51: func(c *CPU) { ld(c, c.storeD, c.loadC) },
	0x52: func(c *CPU) { ld(c, c.storeD, c.loadD) },
	0x53: func(c *CPU) { ld(c, c.storeD, c.loadE) },
	0x54: func(c *CPU) { ld(c, c.storeD, c.loadIYH) },
	0x55: func(c *CPU) { ld(c, c.storeD, c.loadIYL) },
	0x56: func(c *CPU) { c.fetchd(); ld(c, c.storeD, c.loadIndIY) },
	0x57: func(c *CPU) { ld(c, c.storeD, c.loadA) },
	0x58: func(c *CPU) { ld(c, c.storeE, c.loadB) },
	0x59: func(c *CPU) { ld(c, c.storeE, c.loadC) },
	0x5a: func(c *CPU) { ld(c, c.storeE, c.loadD) },
	0x5b: func(c *CPU) { ld(c, c.storeE, c.loadE) },
	0x5c: func(c *CPU) { ld(c, c.storeE, c.loadIYH) },
	0x5d: func(c *CPU) { ld(c, c.storeE, c.loadIYL) },
	0x5e: func(c *CPU) { c.fetchd(); ld(c, c.storeE, c.loadIndIY) },
	0x5f: func(c *CPU) { ld(c, c.storeE, c.loadA) },
	0x60: func(c *CPU) { ld(c, c.storeIYH, c.loadB) },
	0x61: func(c *CPU) { ld(c, c.storeIYH, c.loadC) },
	0x62: func(c *CPU) { ld(c, c.storeIYH, c.loadD) },
	0x63: func(c *CPU) { ld(c, c.storeIYH, c.loadE) },
	0x64: func(c *CPU) { ld(c, c.storeIYH, c.loadIYH) },
	0x65: func(c *CPU) { ld(c, c.storeIYH, c.loadIYL) },
	0x66: func(c *CPU) { c.fetchd(); ld(c, c.storeH, c.loadIndIY) },
	0x67: func(c *CPU) { ld(c, c.storeIYH, c.loadA) },
	0x68: func(c *CPU) { ld(c, c.storeIYL, c.loadB) },
	0x69: func(c *CPU) { ld(c, c.storeIYL, c.loadC) },
	0x6a: func(c *CPU) { ld(c, c.storeIYL, c.loadD) },
	0x6b: func(c *CPU) { ld(c, c.storeIYL, c.loadE) },
	0x6c: func(c *CPU) { ld(c, c.storeIYL, c.loadIYH) },
	0x6d: func(c *CPU) { ld(c, c.storeIYL, c.loadIYL) },
	0x6e: func(c *CPU) { c.fetchd(); ld(c, c.storeL, c.loadIndIY) },
	0x6f: func(c *CPU) { ld(c, c.storeIYL, c.loadA) },
	0x70: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadB) },
	0x71: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadC) },
	0x72: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadD) },
	0x73: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadE) },
	0x74: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadH) },
	0x75: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadL) },
	0x76: func(c *CPU) { halt(c) },
	0x77: func(c *CPU) { c.fetchd(); ld(c, c.storeIndIY, c.loadA) },
	0x78: func(c *CPU) { ld(c, c.storeA, c.loadB) },
	0x79: func(c *CPU) { ld(c, c.storeA, c.loadC) },
	0x7a: func(c *CPU) { ld(c, c.storeA, c.loadD) },
	0x7b: func(c *CPU) { ld(c, c.storeA, c.loadE) },
	0x7c: func(c *CPU) { ld(c, c.storeA, c.loadIYH) },
	0x7d: func(c *CPU) { ld(c, c.storeA, c.loadIYL) },
	0x7e: func(c *CPU) { c.fetchd(); ld(c, c.storeA, c.loadIndIY) },
	0x7f: func(c *CPU) { ld(c, c.storeA, c.loadA) },
	0x80: func(c *CPU) { add(c, c.loadA, c.loadB) },
	0x81: func(c *CPU) { add(c, c.loadA, c.loadC) },
	0x82: func(c *CPU) { add(c, c.loadA, c.loadD) },
	0x83: func(c *CPU) { add(c, c.loadA, c.loadE) },
	0x84: func(c *CPU) { add(c, c.loadA, c.loadIYH) },
	0x85: func(c *CPU) { add(c, c.loadA, c.loadIYL) },
	0x86: func(c *CPU) { c.fetchd(); add(c, c.loadA, c.loadIndIY) },
	0x87: func(c *CPU) { add(c, c.loadA, c.loadA) },
	0x88: func(c *CPU) { adc(c, c.loadA, c.loadB) },
	0x89: func(c *CPU) { adc(c, c.loadA, c.loadC) },
	0x8a: func(c *CPU) { adc(c, c.loadA, c.loadD) },
	0x8b: func(c *CPU) { adc(c, c.loadA, c.loadE) },
	0x8c: func(c *CPU) { adc(c, c.loadA, c.loadIYH) },
	0x8d: func(c *CPU) { adc(c, c.loadA, c.loadIYL) },
	0x8e: func(c *CPU) { c.fetchd(); adc(c, c.loadA, c.loadIndIY) },
	0x8f: func(c *CPU) { adc(c, c.loadA, c.loadA) },
	0x90: func(c *CPU) { sub(c, c.loadA, c.loadB) },
	0x91: func(c *CPU) { sub(c, c.loadA, c.loadC) },
	0x92: func(c *CPU) { sub(c, c.loadA, c.loadD) },
	0x93: func(c *CPU) { sub(c, c.loadA, c.loadE) },
	0x94: func(c *CPU) { sub(c, c.loadA, c.loadIYH) },
	0x95: func(c *CPU) { sub(c, c.loadA, c.loadIYL) },
	0x96: func(c *CPU) { c.fetchd(); sub(c, c.loadA, c.loadIndIY) },
	0x97: func(c *CPU) { sub(c, c.loadA, c.loadA) },
	0x98: func(c *CPU) { sbc(c, c.loadA, c.loadB) },
	0x99: func(c *CPU) { sbc(c, c.loadA, c.loadC) },
	0x9a: func(c *CPU) { sbc(c, c.loadA, c.loadD) },
	0x9b: func(c *CPU) { sbc(c, c.loadA, c.loadE) },
	0x9c: func(c *CPU) { sbc(c, c.loadA, c.loadIYH) },
	0x9d: func(c *CPU) { sbc(c, c.loadA, c.loadIYL) },
	0x9e: func(c *CPU) { c.fetchd(); sbc(c, c.loadA, c.loadIndIY) },
	0x9f: func(c *CPU) { sbc(c, c.loadA, c.loadA) },
	0xa0: func(c *CPU) { and(c, c.loadB) },
	0xa1: func(c *CPU) { and(c, c.loadC) },
	0xa2: func(c *CPU) { and(c, c.loadD) },
	0xa3: func(c *CPU) { and(c, c.loadE) },
	0xa4: func(c *CPU) { and(c, c.loadIYH) },
	0xa5: func(c *CPU) { and(c, c.loadIYL) },
	0xa6: func(c *CPU) { c.fetchd(); and(c, c.loadIndIY) },
	0xa7: func(c *CPU) { and(c, c.loadA) },
	0xa8: func(c *CPU) { xor(c, c.loadB) },
	0xa9: func(c *CPU) { xor(c, c.loadC) },
	0xaa: func(c *CPU) { xor(c, c.loadD) },
	0xab: func(c *CPU) { xor(c, c.loadE) },
	0xac: func(c *CPU) { xor(c, c.loadIYH) },
	0xad: func(c *CPU) { xor(c, c.loadIYL) },
	0xae: func(c *CPU) { c.fetchd(); xor(c, c.loadIndIY) },
	0xaf: func(c *CPU) { xor(c, c.loadA) },
	0xb0: func(c *CPU) { or(c, c.loadB) },
	0xb1: func(c *CPU) { or(c, c.loadC) },
	0xb2: func(c *CPU) { or(c, c.loadD) },
	0xb3: func(c *CPU) { or(c, c.loadE) },
	0xb4: func(c *CPU) { or(c, c.loadIYH) },
	0xb5: func(c *CPU) { or(c, c.loadIYL) },
	0xb6: func(c *CPU) { c.fetchd(); or(c, c.loadIndIY) },
	0xb7: func(c *CPU) { or(c, c.loadA) },
	0xb8: func(c *CPU) { cp(c, c.loadB) },
	0xb9: func(c *CPU) { cp(c, c.loadC) },
	0xba: func(c *CPU) { cp(c, c.loadD) },
	0xbb: func(c *CPU) { cp(c, c.loadE) },
	0xbc: func(c *CPU) { cp(c, c.loadIYH) },
	0xbd: func(c *CPU) { cp(c, c.loadIYL) },
	0xbe: func(c *CPU) { c.fetchd(); cp(c, c.loadIndIY) },
	0xbf: func(c *CPU) { cp(c, c.loadA) },
	0xc0: func(c *CPU) { ret(c, FlagZ, false) },
	0xc1: func(c *CPU) { pop(c, c.storeBC) },
	0xc2: func(c *CPU) { jp(c, FlagZ, false, c.loadImm16) },
	0xc3: func(c *CPU) { jpa(c, c.loadImm16) },
	0xc4: func(c *CPU) { call(c, FlagZ, false, c.loadImm16) },
	0xc5: func(c *CPU) { push(c, c.loadBC) },
	0xc6: func(c *CPU) { add(c, c.loadA, c.loadImm) },
	0xc7: func(c *CPU) { rst(c, 0) },
	0xc8: func(c *CPU) { ret(c, FlagZ, true) },
	0xc9: func(c *CPU) { reta(c) },
	0xca: func(c *CPU) { jp(c, FlagZ, true, c.loadImm16) },
	0xcc: func(c *CPU) { call(c, FlagZ, true, c.loadImm16) },
	0xcd: func(c *CPU) { calla(c, c.loadImm16) },
	0xce: func(c *CPU) { adc(c, c.loadA, c.loadImm) },
	0xcf: func(c *CPU) { rst(c, 1) },
	0xd0: func(c *CPU) { ret(c, FlagC, false) },
	0xd1: func(c *CPU) { pop(c, c.storeDE) },
	0xd2: func(c *CPU) { jp(c, FlagC, false, c.loadImm16) },
	0xd3: func(c *CPU) { ld(c, c.outIndImm, c.loadA) },
	0xd4: func(c *CPU) { call(c, FlagC, false, c.loadImm16) },
	0xd5: func(c *CPU) { push(c, c.loadDE) },
	0xd6: func(c *CPU) { sub(c, c.loadA, c.loadImm) },
	0xd7: func(c *CPU) { rst(c, 2) },
	0xd8: func(c *CPU) { ret(c, FlagC, true) },
	0xd9: func(c *CPU) { exx(c) },
	0xda: func(c *CPU) { jp(c, FlagC, true, c.loadImm16) },
	0xdb: func(c *CPU) { ld(c, c.storeA, c.inIndImm) },
	0xdc: func(c *CPU) { call(c, FlagC, true, c.loadImm16) },
	0xde: func(c *CPU) { sbc(c, c.loadA, c.loadImm) },
	0xdf: func(c *CPU) { rst(c, 3) },
	0xe0: func(c *CPU) { ret(c, FlagV, false) },
	0xe1: func(c *CPU) { pop(c, c.storeIY) },
	0xe2: func(c *CPU) { jp(c, FlagV, false, c.loadImm16) },
	0xe3: func(c *CPU) { ex(c, c.load16IndSP, c.store16IndSP, c.loadIY, c.storeIY) },
	0xe4: func(c *CPU) { call(c, FlagV, false, c.loadImm16) },
	0xe5: func(c *CPU) { push(c, c.loadIY) },
	0xe6: func(c *CPU) { and(c, c.loadImm) },
	0xe7: func(c *CPU) { rst(c, 4) },
	0xe8: func(c *CPU) { ret(c, FlagV, true) },
	0xe9: func(c *CPU) { jpa(c, c.loadIY) },
	0xea: func(c *CPU) { jp(c, FlagV, true, c.loadImm16) },
	0xeb: func(c *CPU) { ex(c, c.loadDE, c.storeDE, c.loadHL, c.storeHL) },
	0xec: func(c *CPU) { call(c, FlagV, true, c.loadImm16) },
	0xee: func(c *CPU) { xor(c, c.loadImm) },
	0xef: func(c *CPU) { rst(c, 5) },
	0xf0: func(c *CPU) { ret(c, FlagS, false) },
	0xf1: func(c *CPU) { pop(c, c.storeAF) },
	0xf2: func(c *CPU) { jp(c, FlagS, false, c.loadImm16) },
	0xf3: func(c *CPU) { di(c) },
	0xf4: func(c *CPU) { call(c, FlagS, false, c.loadImm16) },
	0xf5: func(c *CPU) { push(c, c.loadAF) },
	0xf6: func(c *CPU) { or(c, c.loadImm) },
	0xf7: func(c *CPU) { rst(c, 6) },
	0xf8: func(c *CPU) { ret(c, FlagS, true) },
	0xf9: func(c *CPU) { ld16(c, c.storeSP, c.loadIY) },
	0xfa: func(c *CPU) { jp(c, FlagS, true, c.loadImm16) },
	0xfb: func(c *CPU) { ei(c) },
	0xfc: func(c *CPU) { call(c, FlagS, true, c.loadImm16) },
	0xfe: func(c *CPU) { cp(c, c.loadImm) },
	0xff: func(c *CPU) { rst(c, 7) },
}
var opcodesDDCB = map[uint8]func(c *CPU){
	0x00: func(c *CPU) { rlc(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x01: func(c *CPU) { rlc(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x02: func(c *CPU) { rlc(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x03: func(c *CPU) { rlc(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x04: func(c *CPU) { rlc(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x05: func(c *CPU) { rlc(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x06: func(c *CPU) { rlc(c, c.storeLastInd, c.loadIndIX) },
	0x07: func(c *CPU) { rlc(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x08: func(c *CPU) { rrc(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x09: func(c *CPU) { rrc(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x0a: func(c *CPU) { rrc(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x0b: func(c *CPU) { rrc(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x0c: func(c *CPU) { rrc(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x0d: func(c *CPU) { rrc(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x0e: func(c *CPU) { rrc(c, c.storeLastInd, c.loadIndIX) },
	0x0f: func(c *CPU) { rrc(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x10: func(c *CPU) { rl(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x11: func(c *CPU) { rl(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x12: func(c *CPU) { rl(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x13: func(c *CPU) { rl(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x14: func(c *CPU) { rl(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x15: func(c *CPU) { rl(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x16: func(c *CPU) { rl(c, c.storeLastInd, c.loadIndIX) },
	0x17: func(c *CPU) { rl(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x18: func(c *CPU) { rr(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x19: func(c *CPU) { rr(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x1a: func(c *CPU) { rr(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x1b: func(c *CPU) { rr(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x1c: func(c *CPU) { rr(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x1d: func(c *CPU) { rr(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x1e: func(c *CPU) { rr(c, c.storeLastInd, c.loadIndIX) },
	0x1f: func(c *CPU) { rr(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x20: func(c *CPU) { sla(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x21: func(c *CPU) { sla(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x22: func(c *CPU) { sla(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x23: func(c *CPU) { sla(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x24: func(c *CPU) { sla(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x25: func(c *CPU) { sla(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x26: func(c *CPU) { sla(c, c.storeLastInd, c.loadIndIX) },
	0x27: func(c *CPU) { sla(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x28: func(c *CPU) { sra(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x29: func(c *CPU) { sra(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x2a: func(c *CPU) { sra(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x2b: func(c *CPU) { sra(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x2c: func(c *CPU) { sra(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x2d: func(c *CPU) { sra(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x2e: func(c *CPU) { sra(c, c.storeLastInd, c.loadIndIX) },
	0x2f: func(c *CPU) { sra(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x30: func(c *CPU) { sll(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x31: func(c *CPU) { sll(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x32: func(c *CPU) { sll(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x33: func(c *CPU) { sll(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x34: func(c *CPU) { sll(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x35: func(c *CPU) { sll(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x36: func(c *CPU) { sll(c, c.storeLastInd, c.loadIndIX) },
	0x37: func(c *CPU) { sll(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x38: func(c *CPU) { srl(c, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x39: func(c *CPU) { srl(c, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x3a: func(c *CPU) { srl(c, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x3b: func(c *CPU) { srl(c, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x3c: func(c *CPU) { srl(c, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x3d: func(c *CPU) { srl(c, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x3e: func(c *CPU) { srl(c, c.storeLastInd, c.loadIndIX) },
	0x3f: func(c *CPU) { srl(c, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x40: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x41: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x42: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x43: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x44: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x45: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x46: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x47: func(c *CPU) { biti(c, 0, c.loadIndIX) },
	0x48: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x49: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x4a: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x4b: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x4c: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x4d: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x4e: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x4f: func(c *CPU) { biti(c, 1, c.loadIndIX) },
	0x50: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x51: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x52: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x53: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x54: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x55: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x56: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x57: func(c *CPU) { biti(c, 2, c.loadIndIX) },
	0x58: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x59: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x5a: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x5b: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x5c: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x5d: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x5e: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x5f: func(c *CPU) { biti(c, 3, c.loadIndIX) },
	0x60: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x61: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x62: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x63: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x64: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x65: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x66: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x67: func(c *CPU) { biti(c, 4, c.loadIndIX) },
	0x68: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x69: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x6a: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x6b: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x6c: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x6d: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x6e: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x6f: func(c *CPU) { biti(c, 5, c.loadIndIX) },
	0x70: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x71: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x72: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x73: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x74: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x75: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x76: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x77: func(c *CPU) { biti(c, 6, c.loadIndIX) },
	0x78: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x79: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x7a: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x7b: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x7c: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x7d: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x7e: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x7f: func(c *CPU) { biti(c, 7, c.loadIndIX) },
	0x80: func(c *CPU) { res(c, 0, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x81: func(c *CPU) { res(c, 0, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x82: func(c *CPU) { res(c, 0, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x83: func(c *CPU) { res(c, 0, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x84: func(c *CPU) { res(c, 0, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x85: func(c *CPU) { res(c, 0, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x86: func(c *CPU) { res(c, 0, c.storeLastInd, c.loadIndIX) },
	0x87: func(c *CPU) { res(c, 0, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x88: func(c *CPU) { res(c, 1, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x89: func(c *CPU) { res(c, 1, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x8a: func(c *CPU) { res(c, 1, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x8b: func(c *CPU) { res(c, 1, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x8c: func(c *CPU) { res(c, 1, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x8d: func(c *CPU) { res(c, 1, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x8e: func(c *CPU) { res(c, 1, c.storeLastInd, c.loadIndIX) },
	0x8f: func(c *CPU) { res(c, 1, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x90: func(c *CPU) { res(c, 2, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x91: func(c *CPU) { res(c, 2, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x92: func(c *CPU) { res(c, 2, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x93: func(c *CPU) { res(c, 2, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x94: func(c *CPU) { res(c, 2, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x95: func(c *CPU) { res(c, 2, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x96: func(c *CPU) { res(c, 2, c.storeLastInd, c.loadIndIX) },
	0x97: func(c *CPU) { res(c, 2, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0x98: func(c *CPU) { res(c, 3, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0x99: func(c *CPU) { res(c, 3, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0x9a: func(c *CPU) { res(c, 3, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0x9b: func(c *CPU) { res(c, 3, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0x9c: func(c *CPU) { res(c, 3, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0x9d: func(c *CPU) { res(c, 3, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0x9e: func(c *CPU) { res(c, 3, c.storeLastInd, c.loadIndIX) },
	0x9f: func(c *CPU) { res(c, 3, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xa0: func(c *CPU) { res(c, 4, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xa1: func(c *CPU) { res(c, 4, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xa2: func(c *CPU) { res(c, 4, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xa3: func(c *CPU) { res(c, 4, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xa4: func(c *CPU) { res(c, 4, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xa5: func(c *CPU) { res(c, 4, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xa6: func(c *CPU) { res(c, 4, c.storeLastInd, c.loadIndIX) },
	0xa7: func(c *CPU) { res(c, 4, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xa8: func(c *CPU) { res(c, 5, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xa9: func(c *CPU) { res(c, 5, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xaa: func(c *CPU) { res(c, 5, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xab: func(c *CPU) { res(c, 5, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xac: func(c *CPU) { res(c, 5, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xad: func(c *CPU) { res(c, 5, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xae: func(c *CPU) { res(c, 5, c.storeLastInd, c.loadIndIX) },
	0xaf: func(c *CPU) { res(c, 5, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xb0: func(c *CPU) { res(c, 6, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xb1: func(c *CPU) { res(c, 6, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xb2: func(c *CPU) { res(c, 6, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xb3: func(c *CPU) { res(c, 6, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xb4: func(c *CPU) { res(c, 6, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xb5: func(c *CPU) { res(c, 6, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xb6: func(c *CPU) { res(c, 6, c.storeLastInd, c.loadIndIX) },
	0xb7: func(c *CPU) { res(c, 6, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xb8: func(c *CPU) { res(c, 7, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xb9: func(c *CPU) { res(c, 7, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xba: func(c *CPU) { res(c, 7, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xbb: func(c *CPU) { res(c, 7, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xbc: func(c *CPU) { res(c, 7, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xbd: func(c *CPU) { res(c, 7, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xbe: func(c *CPU) { res(c, 7, c.storeLastInd, c.loadIndIX) },
	0xbf: func(c *CPU) { res(c, 7, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xc0: func(c *CPU) { set(c, 0, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xc1: func(c *CPU) { set(c, 0, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xc2: func(c *CPU) { set(c, 0, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xc3: func(c *CPU) { set(c, 0, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xc4: func(c *CPU) { set(c, 0, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xc5: func(c *CPU) { set(c, 0, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xc6: func(c *CPU) { set(c, 0, c.storeLastInd, c.loadIndIX) },
	0xc7: func(c *CPU) { set(c, 0, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xc8: func(c *CPU) { set(c, 1, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xc9: func(c *CPU) { set(c, 1, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xca: func(c *CPU) { set(c, 1, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xcb: func(c *CPU) { set(c, 1, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xcc: func(c *CPU) { set(c, 1, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xcd: func(c *CPU) { set(c, 1, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xce: func(c *CPU) { set(c, 1, c.storeLastInd, c.loadIndIX) },
	0xcf: func(c *CPU) { set(c, 1, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xd0: func(c *CPU) { set(c, 2, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xd1: func(c *CPU) { set(c, 2, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xd2: func(c *CPU) { set(c, 2, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xd3: func(c *CPU) { set(c, 2, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xd4: func(c *CPU) { set(c, 2, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xd5: func(c *CPU) { set(c, 2, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xd6: func(c *CPU) { set(c, 2, c.storeLastInd, c.loadIndIX) },
	0xd7: func(c *CPU) { set(c, 2, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xd8: func(c *CPU) { set(c, 3, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xd9: func(c *CPU) { set(c, 3, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xda: func(c *CPU) { set(c, 3, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xdb: func(c *CPU) { set(c, 3, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xdc: func(c *CPU) { set(c, 3, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xdd: func(c *CPU) { set(c, 3, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xde: func(c *CPU) { set(c, 3, c.storeLastInd, c.loadIndIX) },
	0xdf: func(c *CPU) { set(c, 3, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xe0: func(c *CPU) { set(c, 4, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xe1: func(c *CPU) { set(c, 4, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xe2: func(c *CPU) { set(c, 4, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xe3: func(c *CPU) { set(c, 4, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xe4: func(c *CPU) { set(c, 4, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xe5: func(c *CPU) { set(c, 4, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xe6: func(c *CPU) { set(c, 4, c.storeLastInd, c.loadIndIX) },
	0xe7: func(c *CPU) { set(c, 4, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xe8: func(c *CPU) { set(c, 5, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xe9: func(c *CPU) { set(c, 5, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xea: func(c *CPU) { set(c, 5, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xeb: func(c *CPU) { set(c, 5, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xec: func(c *CPU) { set(c, 5, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xed: func(c *CPU) { set(c, 5, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xee: func(c *CPU) { set(c, 5, c.storeLastInd, c.loadIndIX) },
	0xef: func(c *CPU) { set(c, 5, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xf0: func(c *CPU) { set(c, 6, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xf1: func(c *CPU) { set(c, 6, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xf2: func(c *CPU) { set(c, 6, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xf3: func(c *CPU) { set(c, 6, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xf4: func(c *CPU) { set(c, 6, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xf5: func(c *CPU) { set(c, 6, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xf6: func(c *CPU) { set(c, 6, c.storeLastInd, c.loadIndIX) },
	0xf7: func(c *CPU) { set(c, 6, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
	0xf8: func(c *CPU) { set(c, 7, c.storeB, c.loadIndIX); ld(c, c.storeLastInd, c.loadB) },
	0xf9: func(c *CPU) { set(c, 7, c.storeC, c.loadIndIX); ld(c, c.storeLastInd, c.loadC) },
	0xfa: func(c *CPU) { set(c, 7, c.storeD, c.loadIndIX); ld(c, c.storeLastInd, c.loadD) },
	0xfb: func(c *CPU) { set(c, 7, c.storeE, c.loadIndIX); ld(c, c.storeLastInd, c.loadE) },
	0xfc: func(c *CPU) { set(c, 7, c.storeH, c.loadIndIX); ld(c, c.storeLastInd, c.loadH) },
	0xfd: func(c *CPU) { set(c, 7, c.storeL, c.loadIndIX); ld(c, c.storeLastInd, c.loadL) },
	0xfe: func(c *CPU) { set(c, 7, c.storeLastInd, c.loadIndIX) },
	0xff: func(c *CPU) { set(c, 7, c.storeA, c.loadIndIX); ld(c, c.storeLastInd, c.loadA) },
}
var opcodesFDCB = map[uint8]func(c *CPU){
	0x00: func(c *CPU) { rlc(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x01: func(c *CPU) { rlc(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x02: func(c *CPU) { rlc(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x03: func(c *CPU) { rlc(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x04: func(c *CPU) { rlc(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x05: func(c *CPU) { rlc(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x06: func(c *CPU) { rlc(c, c.storeLastInd, c.loadIndIY) },
	0x07: func(c *CPU) { rlc(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x08: func(c *CPU) { rrc(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x09: func(c *CPU) { rrc(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x0a: func(c *CPU) { rrc(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x0b: func(c *CPU) { rrc(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x0c: func(c *CPU) { rrc(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x0d: func(c *CPU) { rrc(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x0e: func(c *CPU) { rrc(c, c.storeLastInd, c.loadIndIY) },
	0x0f: func(c *CPU) { rrc(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x10: func(c *CPU) { rl(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x11: func(c *CPU) { rl(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x12: func(c *CPU) { rl(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x13: func(c *CPU) { rl(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x14: func(c *CPU) { rl(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x15: func(c *CPU) { rl(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x16: func(c *CPU) { rl(c, c.storeLastInd, c.loadIndIY) },
	0x17: func(c *CPU) { rl(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x18: func(c *CPU) { rr(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x19: func(c *CPU) { rr(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x1a: func(c *CPU) { rr(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x1b: func(c *CPU) { rr(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x1c: func(c *CPU) { rr(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x1d: func(c *CPU) { rr(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x1e: func(c *CPU) { rr(c, c.storeLastInd, c.loadIndIY) },
	0x1f: func(c *CPU) { rr(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x20: func(c *CPU) { sla(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x21: func(c *CPU) { sla(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x22: func(c *CPU) { sla(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x23: func(c *CPU) { sla(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x24: func(c *CPU) { sla(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x25: func(c *CPU) { sla(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x26: func(c *CPU) { sla(c, c.storeLastInd, c.loadIndIY) },
	0x27: func(c *CPU) { sla(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x28: func(c *CPU) { sra(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x29: func(c *CPU) { sra(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x2a: func(c *CPU) { sra(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x2b: func(c *CPU) { sra(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x2c: func(c *CPU) { sra(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x2d: func(c *CPU) { sra(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x2e: func(c *CPU) { sra(c, c.storeLastInd, c.loadIndIY) },
	0x2f: func(c *CPU) { sra(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x30: func(c *CPU) { sll(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x31: func(c *CPU) { sll(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x32: func(c *CPU) { sll(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x33: func(c *CPU) { sll(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x34: func(c *CPU) { sll(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x35: func(c *CPU) { sll(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x36: func(c *CPU) { sll(c, c.storeLastInd, c.loadIndIY) },
	0x37: func(c *CPU) { sll(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x38: func(c *CPU) { srl(c, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x39: func(c *CPU) { srl(c, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x3a: func(c *CPU) { srl(c, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x3b: func(c *CPU) { srl(c, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x3c: func(c *CPU) { srl(c, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x3d: func(c *CPU) { srl(c, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x3e: func(c *CPU) { srl(c, c.storeLastInd, c.loadIndIY) },
	0x3f: func(c *CPU) { srl(c, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x40: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x41: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x42: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x43: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x44: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x45: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x46: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x47: func(c *CPU) { biti(c, 0, c.loadIndIY) },
	0x48: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x49: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x4a: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x4b: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x4c: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x4d: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x4e: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x4f: func(c *CPU) { biti(c, 1, c.loadIndIY) },
	0x50: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x51: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x52: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x53: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x54: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x55: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x56: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x57: func(c *CPU) { biti(c, 2, c.loadIndIY) },
	0x58: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x59: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x5a: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x5b: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x5c: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x5d: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x5e: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x5f: func(c *CPU) { biti(c, 3, c.loadIndIY) },
	0x60: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x61: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x62: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x63: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x64: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x65: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x66: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x67: func(c *CPU) { biti(c, 4, c.loadIndIY) },
	0x68: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x69: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x6a: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x6b: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x6c: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x6d: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x6e: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x6f: func(c *CPU) { biti(c, 5, c.loadIndIY) },
	0x70: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x71: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x72: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x73: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x74: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x75: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x76: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x77: func(c *CPU) { biti(c, 6, c.loadIndIY) },
	0x78: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x79: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x7a: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x7b: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x7c: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x7d: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x7e: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x7f: func(c *CPU) { biti(c, 7, c.loadIndIY) },
	0x80: func(c *CPU) { res(c, 0, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x81: func(c *CPU) { res(c, 0, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x82: func(c *CPU) { res(c, 0, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x83: func(c *CPU) { res(c, 0, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x84: func(c *CPU) { res(c, 0, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x85: func(c *CPU) { res(c, 0, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x86: func(c *CPU) { res(c, 0, c.storeLastInd, c.loadIndIY) },
	0x87: func(c *CPU) { res(c, 0, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x88: func(c *CPU) { res(c, 1, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x89: func(c *CPU) { res(c, 1, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x8a: func(c *CPU) { res(c, 1, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x8b: func(c *CPU) { res(c, 1, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x8c: func(c *CPU) { res(c, 1, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x8d: func(c *CPU) { res(c, 1, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x8e: func(c *CPU) { res(c, 1, c.storeLastInd, c.loadIndIY) },
	0x8f: func(c *CPU) { res(c, 1, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x90: func(c *CPU) { res(c, 2, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x91: func(c *CPU) { res(c, 2, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x92: func(c *CPU) { res(c, 2, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x93: func(c *CPU) { res(c, 2, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x94: func(c *CPU) { res(c, 2, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x95: func(c *CPU) { res(c, 2, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x96: func(c *CPU) { res(c, 2, c.storeLastInd, c.loadIndIY) },
	0x97: func(c *CPU) { res(c, 2, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0x98: func(c *CPU) { res(c, 3, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0x99: func(c *CPU) { res(c, 3, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0x9a: func(c *CPU) { res(c, 3, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0x9b: func(c *CPU) { res(c, 3, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0x9c: func(c *CPU) { res(c, 3, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0x9d: func(c *CPU) { res(c, 3, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0x9e: func(c *CPU) { res(c, 3, c.storeLastInd, c.loadIndIY) },
	0x9f: func(c *CPU) { res(c, 3, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xa0: func(c *CPU) { res(c, 4, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xa1: func(c *CPU) { res(c, 4, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xa2: func(c *CPU) { res(c, 4, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xa3: func(c *CPU) { res(c, 4, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xa4: func(c *CPU) { res(c, 4, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xa5: func(c *CPU) { res(c, 4, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xa6: func(c *CPU) { res(c, 4, c.storeLastInd, c.loadIndIY) },
	0xa7: func(c *CPU) { res(c, 4, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xa8: func(c *CPU) { res(c, 5, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xa9: func(c *CPU) { res(c, 5, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xaa: func(c *CPU) { res(c, 5, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xab: func(c *CPU) { res(c, 5, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xac: func(c *CPU) { res(c, 5, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xad: func(c *CPU) { res(c, 5, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xae: func(c *CPU) { res(c, 5, c.storeLastInd, c.loadIndIY) },
	0xaf: func(c *CPU) { res(c, 5, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xb0: func(c *CPU) { res(c, 6, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xb1: func(c *CPU) { res(c, 6, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xb2: func(c *CPU) { res(c, 6, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xb3: func(c *CPU) { res(c, 6, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xb4: func(c *CPU) { res(c, 6, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xb5: func(c *CPU) { res(c, 6, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xb6: func(c *CPU) { res(c, 6, c.storeLastInd, c.loadIndIY) },
	0xb7: func(c *CPU) { res(c, 6, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xb8: func(c *CPU) { res(c, 7, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xb9: func(c *CPU) { res(c, 7, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xba: func(c *CPU) { res(c, 7, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xbb: func(c *CPU) { res(c, 7, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xbc: func(c *CPU) { res(c, 7, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xbd: func(c *CPU) { res(c, 7, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xbe: func(c *CPU) { res(c, 7, c.storeLastInd, c.loadIndIY) },
	0xbf: func(c *CPU) { res(c, 7, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xc0: func(c *CPU) { set(c, 0, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xc1: func(c *CPU) { set(c, 0, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xc2: func(c *CPU) { set(c, 0, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xc3: func(c *CPU) { set(c, 0, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xc4: func(c *CPU) { set(c, 0, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xc5: func(c *CPU) { set(c, 0, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xc6: func(c *CPU) { set(c, 0, c.storeLastInd, c.loadIndIY) },
	0xc7: func(c *CPU) { set(c, 0, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xc8: func(c *CPU) { set(c, 1, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xc9: func(c *CPU) { set(c, 1, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xca: func(c *CPU) { set(c, 1, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xcb: func(c *CPU) { set(c, 1, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xcc: func(c *CPU) { set(c, 1, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xcd: func(c *CPU) { set(c, 1, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xce: func(c *CPU) { set(c, 1, c.storeLastInd, c.loadIndIY) },
	0xcf: func(c *CPU) { set(c, 1, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xd0: func(c *CPU) { set(c, 2, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xd1: func(c *CPU) { set(c, 2, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xd2: func(c *CPU) { set(c, 2, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xd3: func(c *CPU) { set(c, 2, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xd4: func(c *CPU) { set(c, 2, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xd5: func(c *CPU) { set(c, 2, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xd6: func(c *CPU) { set(c, 2, c.storeLastInd, c.loadIndIY) },
	0xd7: func(c *CPU) { set(c, 2, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xd8: func(c *CPU) { set(c, 3, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xd9: func(c *CPU) { set(c, 3, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xda: func(c *CPU) { set(c, 3, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xdb: func(c *CPU) { set(c, 3, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xdc: func(c *CPU) { set(c, 3, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xdd: func(c *CPU) { set(c, 3, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xde: func(c *CPU) { set(c, 3, c.storeLastInd, c.loadIndIY) },
	0xdf: func(c *CPU) { set(c, 3, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xe0: func(c *CPU) { set(c, 4, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xe1: func(c *CPU) { set(c, 4, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xe2: func(c *CPU) { set(c, 4, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xe3: func(c *CPU) { set(c, 4, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xe4: func(c *CPU) { set(c, 4, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xe5: func(c *CPU) { set(c, 4, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xe6: func(c *CPU) { set(c, 4, c.storeLastInd, c.loadIndIY) },
	0xe7: func(c *CPU) { set(c, 4, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xe8: func(c *CPU) { set(c, 5, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xe9: func(c *CPU) { set(c, 5, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xea: func(c *CPU) { set(c, 5, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xeb: func(c *CPU) { set(c, 5, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xec: func(c *CPU) { set(c, 5, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xed: func(c *CPU) { set(c, 5, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xee: func(c *CPU) { set(c, 5, c.storeLastInd, c.loadIndIY) },
	0xef: func(c *CPU) { set(c, 5, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xf0: func(c *CPU) { set(c, 6, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xf1: func(c *CPU) { set(c, 6, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xf2: func(c *CPU) { set(c, 6, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xf3: func(c *CPU) { set(c, 6, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xf4: func(c *CPU) { set(c, 6, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xf5: func(c *CPU) { set(c, 6, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xf6: func(c *CPU) { set(c, 6, c.storeLastInd, c.loadIndIY) },
	0xf7: func(c *CPU) { set(c, 6, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
	0xf8: func(c *CPU) { set(c, 7, c.storeB, c.loadIndIY); ld(c, c.storeLastInd, c.loadB) },
	0xf9: func(c *CPU) { set(c, 7, c.storeC, c.loadIndIY); ld(c, c.storeLastInd, c.loadC) },
	0xfa: func(c *CPU) { set(c, 7, c.storeD, c.loadIndIY); ld(c, c.storeLastInd, c.loadD) },
	0xfb: func(c *CPU) { set(c, 7, c.storeE, c.loadIndIY); ld(c, c.storeLastInd, c.loadE) },
	0xfc: func(c *CPU) { set(c, 7, c.storeH, c.loadIndIY); ld(c, c.storeLastInd, c.loadH) },
	0xfd: func(c *CPU) { set(c, 7, c.storeL, c.loadIndIY); ld(c, c.storeLastInd, c.loadL) },
	0xfe: func(c *CPU) { set(c, 7, c.storeLastInd, c.loadIndIY) },
	0xff: func(c *CPU) { set(c, 7, c.storeA, c.loadIndIY); ld(c, c.storeLastInd, c.loadA) },
}


<|start_filename|>rcs/z80/doc.go<|end_filename|>
// Package z80 is the Zilog Z80 processor.
package z80


<|start_filename|>system/pacman/roms.go<|end_filename|>
package pacman

import "github.com/blackchip-org/retro-cs/rcs"

var ROM = map[string][]rcs.ROM{
	"pacman": []rcs.ROM{
		rcs.NewROM("code     ", "pacman.6e", "e87e059c5be45753f7e9f33dff851f16d6751181"),
		rcs.NewROM("code     ", "pacman.6f", "674d3a7f00d8be5e38b1fdc208ebef5a92d38329"),
		rcs.NewROM("code     ", "pacman.6h", "8e47e8c2c4d6117d174cdac150392042d3e0a881"),
		rcs.NewROM("code     ", "pacman.6j", "d4a70d56bb01d27d094d73db8667ffb00ca69cb9"),
		rcs.NewROM("tiles    ", "pacman.5e", "06ef227747a440831c9a3a613b76693d52a2f0a9"),
		rcs.NewROM("sprites  ", "pacman.5f", "4a937ac02216ea8c96477d4a15522070507fb599"),
		rcs.NewROM("colors   ", "82s123.7f", "8d0268dee78e47c712202b0ec4f1f51109b1f2a5"),
		rcs.NewROM("palettes ", "82s126.4a", "19097b5f60d1030f8b82d9f1d3a241f93e5c75d6"),
		rcs.NewROM("waveforms", "82s126.1m", "bbcec0570aeceb582ff8238a4bc8546a23430081"),
		rcs.NewROM("waveforms", "82s126.3m", "0c4d0bee858b97632411c440bea6948a74759746"),
	},
	"mspacman": []rcs.ROM{
		rcs.NewROM("code     ", "boot1    ", "bc2247ec946b639dd1f00bfc603fa157d0baaa97"),
		rcs.NewROM("code     ", "boot2    ", "13ea0c343de072508908be885e6a2a217bbb3047"),
		rcs.NewROM("code     ", "boot3    ", "5ea4d907dbb2690698db72c4e0b5be4d3e9a7786"),
		rcs.NewROM("code     ", "boot4    ", "3022a408118fa7420060e32a760aeef15b8a96cf"),
		rcs.NewROM("code2    ", "boot5    ", "fed6e9a2b210b07e7189a18574f6b8c4ec5bb49b"),
		rcs.NewROM("code2    ", "boot6    ", "387010a0c76319a1eab61b54c9bcb5c66c4b67a1"),
		rcs.NewROM("tiles    ", "5e       ", "5e8b472b615f12efca3fe792410c23619f067845"),
		rcs.NewROM("sprites  ", "5f       ", "fd6a1dde780b39aea76bf1c4befa5882573c2ef4"),
		rcs.NewROM("colors   ", "82s123.7f", "8d0268dee78e47c712202b0ec4f1f51109b1f2a5"),
		rcs.NewROM("palettes ", "82s126.4a", "19097b5f60d1030f8b82d9f1d3a241f93e5c75d6"),
		rcs.NewROM("waveforms", "82s126.1m", "bbcec0570aeceb582ff8238a4bc8546a23430081"),
		rcs.NewROM("waveforms", "82s126.3m", "0c4d0bee858b97632411c440bea6948a74759746"),
	},
}


<|start_filename|>system/c128/vdc.go<|end_filename|>
package c128

import (
	"log"

	"github.com/blackchip-org/retro-cs/rcs"
)

const (
	VBlankFlag = (1 << 5)
	StatusFlag = (1 << 7)
)

type VDC struct {
	Name   string
	Addr   uint8
	Status uint8
	MemPos uint16
	VSS    uint8 // vertical smooth scrolling and control register

	WatchAddr   rcs.FlagRW
	WatchStatus rcs.FlagRW
	WatchData   rcs.FlagRW
}

func NewVDC() *VDC {
	return &VDC{
		Name:   "vdc",
		Status: VBlankFlag | StatusFlag,
	}
}

func (v *VDC) WriteAddr(val uint8) {
	if v.WatchAddr.W {
		log.Printf("%v:addr <= %v", v.Name, rcs.X8(val))
	}
	v.Addr = val
}

func (v *VDC) ReadStatus() uint8 {
	if v.WatchAddr.R {
		log.Printf("%v <= %v:addr", rcs.X8(v.Status), v.Name)
	}
	return v.Status
}

func (v *VDC) ReadData() uint8 {
	val := uint8(0)
	switch v.Addr {
	case 0x12: // current memory address (high byte)
		val = uint8(v.MemPos >> 8)
	case 0x13: // current memory address (low byte)
		val = uint8(v.MemPos)
	case 0x18: // vertical smooth scrolling and control register
		val = v.VSS
	case 0x1f: // memory read/write register
		v.MemPos++
	default:
		log.Printf("(!) %v: read to unhandled addr %v", v.Name, rcs.X8(v.Addr))
	}
	if v.WatchData.R {
		log.Printf("%v <= %v[%v]", rcs.X8(val), v.Name, rcs.X8(v.Addr))
	}
	return val
}

func (v *VDC) WriteData(val uint8) {
	switch v.Addr {
	case 0x12: // current memory address (high byte)
		v.MemPos = uint16(val)<<8 | v.MemPos&0xff
	case 0x13: // current memory address (low byte)
		v.MemPos = v.MemPos&0xff00 | uint16(val)
	case 0x18: // vertical smooth scrolling and control register
		v.VSS = val
	case 0x1e: // number of bytes to copy or fill
		v.blockOp(val)
	case 0x1f: // memory read/write register
		v.MemPos++
	default:
		log.Printf("(!) %v: write to unhandled addr %v, value %v", v.Name, rcs.X8(v.Addr), rcs.X8(val))
	}
	if v.WatchData.W {
		log.Printf("%v[%v] <= %v", v.Name, rcs.X8(v.Addr), rcs.X8(val))
	}
}

func (v *VDC) blockOp(val uint8) {
	v.MemPos += uint16(val)
}


<|start_filename|>system/pacman/pacman.go<|end_filename|>
// Package pacman is the hardware cabinet for Pac-Man and Ms. Pac-Man.
package pacman

import (
	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/namco"
	"github.com/blackchip-org/retro-cs/rcs/z80"
)

type system struct {
	cpu   *z80.CPU
	mem   *rcs.Memory
	ram   []uint8
	video *namco.Video

	intSelect       uint8 // value sent during interrupt to select vector (port 0)
	in0             uint8 // joystick #1, rack advance, coin slot, service button
	interruptEnable uint8
	soundEnable     uint8
	unknown0        uint8
	flipScreen      uint8
	lampPlayer1     uint8
	lampPlayer2     uint8
	coinLockout     uint8
	coinCounter     uint8
	in1             uint8 // joystick #2, board test, start buttons, cabinet mode
	dipSwitches     uint8
	watchdogReset   uint8
}

func new(ctx rcs.SDLContext, set []rcs.ROM) (*rcs.Mach, error) {
	s := &system{}
	roms, err := rcs.LoadROMs(config.DataDir, set)
	if err != nil {
		return nil, err
	}

	s.mem = rcs.NewMemory(1, 0x10000)
	ram := make([]uint8, 0x1000, 0x1000)

	s.mem.MapROM(0x0000, roms["code"])
	s.mem.MapRAM(0x4000, ram)

	// Register range. Nil mappings first then add real mappings
	for i := 0x5000; i < 0x6000; i++ {
		s.mem.MapNil(i)
	}
	s.mem.MapWO(0x5000, &s.interruptEnable)
	for i := 0x5000; i < 0x503f; i++ {
		s.mem.MapRO(i, &s.in0)
	}
	s.mem.MapWO(0x5001, &s.soundEnable)
	s.mem.MapWO(0x5002, &s.unknown0)
	s.mem.MapRW(0x5003, &s.flipScreen)
	s.mem.MapRW(0x5004, &s.lampPlayer1)
	s.mem.MapRW(0x5005, &s.lampPlayer2)
	s.mem.MapRW(0x5006, &s.coinLockout)
	s.mem.MapRW(0x5007, &s.coinCounter)
	for i := 0x5040; i <= 0x507f; i++ {
		s.mem.MapRO(i, &s.in1)
	}
	for i := 0x5080; i <= 0x50bf; i++ {
		s.mem.MapRO(i, &s.dipSwitches)
	}
	for i := 0x50c0; i <= 0x50ff; i++ {
		s.mem.MapWO(i, &s.watchdogReset)
	}

	if code2, ok := roms["code2"]; ok {
		s.mem.MapROM(0x8000, code2)
	}

	// The first interrupt is executed without the stack pointer being set.
	// The machine attempts to write the return address to 0xffff and 0xfffe
	// but no memory is mapped there. Ms. Pac-Man also writes to 0xfffd
	// and 0xfffc. Remove this warning.
	s.mem.MapNil(0xfffc)
	s.mem.MapNil(0xfffd)
	s.mem.MapNil(0xfffe)
	s.mem.MapNil(0xffff)

	cpu := z80.New(s.mem)
	cpu.Ports.MapRW(0x00, &s.intSelect)

	var screen rcs.Screen
	var video *namco.Video
	if ctx.Renderer != nil {
		data := namco.Data{
			Palettes: roms["palettes"],
			Colors:   roms["colors"],
			Tiles:    roms["tiles"],
			Sprites:  roms["sprites"],
		}
		video, err = newVideo(ctx.Renderer, data)
		if err != nil {
			return nil, err
		}
		s.mem.MapRAM(0x4000, video.TileMemory)
		s.mem.MapRAM(0x4400, video.ColorMemory)

		// Pacman is missing address line A15 so an access to $c000 is the
		// same as accessing $4000. Ms. Pacman has additional ROMs in high
		// memory so it has an A15 line but it appears to have the RAM mapped at
		// $c000 as well. Text for HIGH SCORE and CREDIT accesses this high
		// memory when writing to video memory. Copy protection?
		s.mem.MapRAM(0xc000, video.TileMemory)
		s.mem.MapRAM(0xc400, video.ColorMemory)

		for i := 0; i < 8; i++ {
			s.mem.MapRW(0x5060+(i*2), &video.SpriteCoords[i].X)
			s.mem.MapRW(0x5061+(i*2), &video.SpriteCoords[i].Y)
			s.mem.MapRW(0x4ff0+(i*2), &video.SpriteInfo[i])
			s.mem.MapRW(0x4ff1+(i*2), &video.SpritePalettes[i])
		}
		screen = rcs.Screen{
			W:         namco.W,
			H:         namco.H,
			Texture:   video.Texture,
			ScanLineV: true,
			Draw:      video.Draw,
		}
	}

	var synth *audio
	if ctx.AudioSpec.Channels > 0 {
		data := audioData{
			waveforms: roms["waveforms"],
		}
		synth, err = newAudio(ctx.AudioSpec, data)
		if err != nil {
			return nil, err
		}
		s.mem.MapWO(0x5040, &synth.voices[0].acc[0])
		s.mem.MapWO(0x5041, &synth.voices[0].acc[1])
		s.mem.MapWO(0x5042, &synth.voices[0].acc[2])
		s.mem.MapWO(0x5043, &synth.voices[0].acc[3])
		s.mem.MapWO(0x5044, &synth.voices[0].acc[4])
		s.mem.MapWO(0x5045, &synth.voices[0].waveform)
		s.mem.MapWO(0x5046, &synth.voices[1].acc[0])
		s.mem.MapWO(0x5047, &synth.voices[1].acc[1])
		s.mem.MapWO(0x5048, &synth.voices[1].acc[2])
		s.mem.MapWO(0x5049, &synth.voices[1].acc[3])
		s.mem.MapWO(0x504a, &synth.voices[1].waveform)
		s.mem.MapWO(0x504b, &synth.voices[2].acc[0])
		s.mem.MapWO(0x504c, &synth.voices[2].acc[1])
		s.mem.MapWO(0x504d, &synth.voices[2].acc[2])
		s.mem.MapWO(0x504e, &synth.voices[2].acc[3])
		s.mem.MapRW(0x504f, &synth.voices[2].waveform)

		s.mem.MapWO(0x5050, &synth.voices[0].freq[0])
		s.mem.MapWO(0x5051, &synth.voices[0].freq[1])
		s.mem.MapWO(0x5052, &synth.voices[0].freq[2])
		s.mem.MapWO(0x5053, &synth.voices[0].freq[3])
		s.mem.MapWO(0x5054, &synth.voices[0].freq[4])
		s.mem.MapWO(0x5055, &synth.voices[0].vol)
		s.mem.MapWO(0x5056, &synth.voices[1].freq[0])
		s.mem.MapWO(0x5057, &synth.voices[1].freq[1])
		s.mem.MapWO(0x5058, &synth.voices[1].freq[2])
		s.mem.MapWO(0x5059, &synth.voices[1].freq[3])
		s.mem.MapWO(0x505a, &synth.voices[1].vol)
		s.mem.MapWO(0x505b, &synth.voices[2].freq[0])
		s.mem.MapWO(0x505c, &synth.voices[2].freq[1])
		s.mem.MapWO(0x505d, &synth.voices[2].freq[2])
		s.mem.MapWO(0x505e, &synth.voices[2].freq[3])
		s.mem.MapRW(0x505f, &synth.voices[2].vol)
	}

	keyboard := newKeyboard(s)
	joystick := newJoystick(s)

	// Note: If in0 and in1 are not initialized to valid values, the
	// game will crash during the game demo in attract mode.

	// Joystick #1 in neutral position
	// Rack advance not pressed
	// Coin slots clear
	// Service button released
	s.in0 = 0xbf

	// Joystick #2 in neutral position
	// Board test off
	// Player start buttons released
	// Upright cabinet
	s.in1 = 0xff

	s.dipSwitches |= (1 << 0)  // 1 coin per game
	s.dipSwitches &^= (1 << 1) // ...
	s.dipSwitches |= (1 << 3)  // 3 lives
	s.dipSwitches |= (1 << 7)  // Normal ghost names

	vblank := func() {
		if s.interruptEnable != 0 {
			cpu.IRQ = true
			cpu.IRQData = s.intSelect
		}
	}

	s.cpu = cpu
	s.ram = ram
	s.video = video

	mach := &rcs.Mach{
		Sys: s,
		Comps: []rcs.Component{
			rcs.NewComponent("mem", "mem", "", s.mem),
			rcs.NewComponent("cpu", "z80", "mem", s.cpu),
		},
		CharDecoders: map[string]rcs.CharDecoder{
			"pacman": PacmanDecoder,
		},
		Ctx:           ctx,
		Screen:        screen,
		VBlankFunc:    vblank,
		QueueAudio:    synth.queue,
		Keyboard:      keyboard.handle,
		ButtonHandler: joystick.buttonHandler,
	}

	return mach, nil
}

func (s *system) Components() []*rcs.Component {
	return []*rcs.Component{}
}

func (s *system) Save(enc *rcs.Encoder) {
	s.cpu.Save(enc)
	if s.video != nil {
		s.video.Save(enc)
	}
	enc.Encode(s.ram)
	enc.Encode(s.intSelect)
	enc.Encode(s.in0)
	enc.Encode(s.interruptEnable)
	enc.Encode(s.soundEnable)
	enc.Encode(s.unknown0)
	enc.Encode(s.flipScreen)
	enc.Encode(s.lampPlayer1)
	enc.Encode(s.lampPlayer2)
	enc.Encode(s.coinLockout)
	enc.Encode(s.coinCounter)
	enc.Encode(s.in1)
	enc.Encode(s.dipSwitches)
	enc.Encode(s.watchdogReset)
}

func (s *system) Load(dec *rcs.Decoder) {
	s.cpu.Load(dec)
	if s.video != nil {
		s.video.Load(dec)
	}
	dec.Decode(&s.ram)
	dec.Decode(&s.intSelect)
	dec.Decode(&s.in0)
	dec.Decode(&s.interruptEnable)
	dec.Decode(&s.soundEnable)
	dec.Decode(&s.unknown0)
	dec.Decode(&s.flipScreen)
	dec.Decode(&s.lampPlayer1)
	dec.Decode(&s.lampPlayer2)
	dec.Decode(&s.coinLockout)
	dec.Decode(&s.coinCounter)
	dec.Decode(&s.in1)
	dec.Decode(&s.dipSwitches)
	dec.Decode(&s.watchdogReset)
}

func New(ctx rcs.SDLContext) (*rcs.Mach, error) {
	return new(ctx, ROM["pacman"])
}

func NewMs(ctx rcs.SDLContext) (*rcs.Mach, error) {
	return new(ctx, ROM["mspacman"])
}


<|start_filename|>rcs/z80/instructions_test.go<|end_filename|>
package z80

import (
	"log"
	"os"
	"strings"
	"testing"

	"github.com/blackchip-org/retro-cs/mock"
	"github.com/blackchip-org/retro-cs/rcs"
)

// Set a test name here to test a single test
var testSingle = ""

// TODO: Write single tests for:
// ADC/SBC: Check that both bytes are zero for zero flag when doing 16-bits

func TestOps(t *testing.T) {
	for _, test := range fuseIn {
		if testSingle != "" && test.name != testSingle {
			continue
		}
		t.Run(test.name, func(t *testing.T) {
			log.SetOutput(&mock.PanicWriter{})
			defer func() {
				log.SetOutput(os.Stderr)
				if r := recover(); r != nil {
					msg := r.(string)
					if strings.HasSuffix(msg, ": dd00\n") {
						return
					}
					if strings.HasSuffix(msg, ": ddfd\n") {
						return
					}
					t.Errorf("unexpected panic: %v", r)
				}
			}()
			cpu := load(test)
			i := 0
			setupPorts(cpu, fuseExpected[test.name])
			for {
				cpu.Next()
				if test.name == "dd00" {
					if cpu.PC() == 0x0003 {
						break
					}
				} else if test.name == "ddfd00" {
					if cpu.PC() == 0x0004 {
						break
					}
				} else {
					if cpu.mem.Read(cpu.PC()) == 0 && cpu.PC() != 0 {
						break
					}
					if test.tstates == 1 {
						break
					}
				}
				if i > 100 {
					t.Fatalf("exceeded execution limit")
				}
				i++
			}
			expected := load(fuseExpected[test.name])

			if cpu.String() != expected.String() {
				t.Errorf("\n have: \n%v \n want: \n%v", cpu.String(), expected.String())
			}
			testMemory(t, cpu.mem, fuseExpected[test.name].memory)
			testMemory(t, cpu.Ports, fuseExpected[test.name].portWrites)
			testHalt(t, cpu, fuseExpected[test.name])
		})
	}
}

func testMemory(t *testing.T, mem *rcs.Memory, expected [][]int) {
	for _, av := range expected {
		addr := av[0]
		value := uint8(av[1])
		have := mem.Read(addr)
		if have != value {
			t.Errorf("\n addr %04x have: %02x \n addr %04x want: %02x", addr, have, addr, value)
		}
	}
}

func testHalt(t *testing.T, cpu *CPU, expected fuseTest) {
	if cpu.Halt != (expected.halt != 0) {
		t.Errorf("\n want: halt(%v) \n have: halt(%v)", cpu.Halt, expected.halt)
	}
}

func setupPorts(cpu *CPU, expected fuseTest) {
	for _, avs := range expected.portReads {
		addr := avs[0]
		values := avs[1:]
		cpu.Ports.MapLoad(addr, mock.MockRead(values))
	}
}

func load(test fuseTest) *CPU {
	mock.ResetMemory()
	cpu := New(mock.TestMemory)

	cpu.A, cpu.F = uint8(test.af>>8), uint8(test.af)
	cpu.B, cpu.C = uint8(test.bc>>8), uint8(test.bc)
	cpu.D, cpu.E = uint8(test.de>>8), uint8(test.de)
	cpu.H, cpu.L = uint8(test.hl>>8), uint8(test.hl)

	cpu.A1, cpu.F1 = uint8(test.af1>>8), uint8(test.af1)
	cpu.B1, cpu.C1 = uint8(test.bc1>>8), uint8(test.bc1)
	cpu.D1, cpu.E1 = uint8(test.de1>>8), uint8(test.de1)
	cpu.H1, cpu.L1 = uint8(test.hl1>>8), uint8(test.hl1)

	cpu.IXH, cpu.IXL = uint8(test.ix>>8), uint8(test.ix)
	cpu.IYH, cpu.IYL = uint8(test.iy>>8), uint8(test.iy)

	cpu.SP = test.sp
	cpu.SetPC(int(test.pc))
	cpu.I = test.i
	cpu.R = test.r
	cpu.IFF1 = test.iff1 != 0
	cpu.IFF2 = test.iff2 != 0
	cpu.IM = uint8(test.im)

	for _, av := range test.memory {
		addr := av[0]
		value := uint8(av[1])
		mock.TestMemory.Write(addr, value)
	}

	return cpu
}

type fuseTest struct {
	name    string
	af      uint16
	bc      uint16
	de      uint16
	hl      uint16
	af1     uint16
	bc1     uint16
	de1     uint16
	hl1     uint16
	ix      uint16
	iy      uint16
	sp      uint16
	pc      uint16
	i       uint8
	r       uint8
	iff1    int
	iff2    int
	im      int
	halt    int
	tstates int

	memory     [][]int
	portReads  [][]int
	portWrites [][]int
}


<|start_filename|>rcs/cpu.go<|end_filename|>
package rcs

import (
	"fmt"
	"strings"
)

type Proc interface {
	Next()
}

// CPU is a central processing unit.
//
// The program counter is an integer to accomodate address busses of at
// least 32-bit. The program counter stored within the actual struct
// should proablby be the actual size of the bus.
//
// Offset is for CPUs, like the 6502, that increment the program counter
// before fetching the instruction opcode. In this case, one should be
// returned. If the program counter is incremented after the fetch, zero
// should be returned.
type CPU interface {
	Next()           // Execute the next instruction
	PC() int         // Address of the program counter
	SetPC(int)       // Set the address of the program counter
	Offset() int     // The next instruction is at PC() + Offset()
	Memory() *Memory // View of memory
}

// CPUDisassembler provides a disassembler instance for CPUs that
// support this method.
type CPUDisassembler interface {
	NewDisassembler() *Disassembler
}

// Stmt represents a single statement in a disassembly.
type Stmt struct {
	Addr    int     // Address of the instruction
	Label   string  // Label for this address, "CHROUT"
	Op      string  // Formated operation, "lda #$40"
	Bytes   []uint8 // Bytes that represent this instruction
	Comment string  // Any notes from the source code
}

// CodeReader reads the next instruction using provided pointer and
// fills in the fields found in the Stmt.
type CodeReader func(StmtEval)

// CodeFormat formats a statement in a string suitible for display to the
// end user.
type CodeFormatter func(Stmt) string

type Disassembler struct {
	mem    *Memory
	ptr    *Pointer
	read   CodeReader
	format CodeFormatter
}

type StmtEval struct {
	Ptr  *Pointer
	Stmt *Stmt
}

func NewDisassembler(mem *Memory, r CodeReader, f CodeFormatter) *Disassembler {
	return &Disassembler{
		mem:    mem,
		ptr:    NewPointer(mem),
		read:   r,
		format: f,
	}
}

func (d *Disassembler) NextStmt() Stmt {
	eval := StmtEval{
		Ptr: d.ptr,
		Stmt: &Stmt{
			Bytes: make([]byte, 0, 0),
		},
	}
	d.read(eval)
	return *eval.Stmt
}

func (d *Disassembler) Next() string {
	return d.format(d.NextStmt())
}

func (d *Disassembler) SetPC(addr int) {
	d.ptr.SetAddr(addr)
}

func (d *Disassembler) PC() int {
	return d.ptr.Addr()
}

type FormatOptions struct {
	BytesFormat string
}

func FormatStmt(s Stmt, options FormatOptions) string {
	bytes := []string{}
	for _, b := range s.Bytes {
		bytes = append(bytes, fmt.Sprintf("%02x", b))
	}
	format := options.BytesFormat
	if format == "" {
		format = "%v"
	}
	sbytes := fmt.Sprintf(format, strings.Join(bytes, " "))
	return fmt.Sprintf("$%04x:  %s  %s", s.Addr, sbytes, s.Op)
}


<|start_filename|>system/galaga/galaga.go<|end_filename|>
// Package galaga is the hardware cabinet for Galaga.
package galaga

import (
	"github.com/blackchip-org/retro-cs/config"
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/namco"
	"github.com/blackchip-org/retro-cs/rcs/z80"
)

type System struct {
	cpu   [3]*z80.CPU
	mem   [3]*rcs.Memory
	ram   []uint8
	n06xx *namco.N06XX
	n51xx *namco.N51XX
	n54xx *namco.N54XX

	video *namco.Video

	InterruptEnable0 uint8 // low bit
	InterruptEnable1 uint8 // low bit
	InterruptEnable2 uint8 // low bit
	reset            uint8
	dipSwitches      [8]uint8
}

func new(ctx rcs.SDLContext, set []rcs.ROM) (*rcs.Mach, error) {
	s := &System{}
	roms, err := rcs.LoadROMs(config.DataDir, set)
	if err != nil {
		return nil, err
	}

	// construct the common memory first
	mem := rcs.NewMemory(1, 0x10000)
	ram := make([]uint8, 0x2000, 0x2000)

	mem.MapRAM(0x6800, make([]uint8, 0x100, 0x100)) // temporary
	for i := 0; i < 8; i++ {
		mem.MapRW(0x6800+i, &s.dipSwitches[i])
	}
	mem.MapRW(0x6820, &s.InterruptEnable0)
	mem.MapRW(0x6821, &s.InterruptEnable1)
	mem.MapRW(0x6822, &s.InterruptEnable2)
	mem.MapRW(0x6823, &s.reset)

	mem.MapRAM(0x7000, make([]uint8, 0x1000, 0x1000))
	mem.MapRAM(0x8000, ram)
	mem.MapRAM(0xa000, make([]uint8, 0x1000, 0x1000))

	s.n51xx = namco.NewN51XX()
	s.n54xx = namco.NewN54XX()

	s.n06xx = namco.NewN06XX()
	s.n06xx.DeviceW[0] = s.n51xx.Write
	s.n06xx.DeviceR[0] = s.n51xx.Read
	s.n06xx.DeviceW[3] = s.n54xx.Write
	s.n06xx.DeviceR[3] = s.n54xx.Read
	for i, addr := 0, 0x7000; addr < 0x7100; addr, i = addr+1, i+1 {
		j := i
		mem.MapLoad(addr, s.n06xx.ReadData(j))
		mem.MapStore(addr, s.n06xx.WriteData(j))
	}
	for i, addr := 0, 0x7100; addr < 0x7200; addr, i = addr+1, i+1 {
		j := i
		mem.MapLoad(addr, s.n06xx.ReadCtrl(j))
		mem.MapStore(addr, s.n06xx.WriteCtrl(j))
	}

	var screen rcs.Screen
	var video *namco.Video
	if ctx.Renderer != nil {
		data := namco.Data{
			Palettes: roms["palettes"],
			Colors:   roms["colors"],
			Tiles:    roms["tiles"],
			Sprites:  roms["sprites"],
		}
		video, err = newVideo(ctx.Renderer, data)
		if err != nil {
			return nil, err
		}
		mem.MapRAM(0x8000, video.TileMemory)
		mem.MapRAM(0x8400, video.ColorMemory)

		screen = rcs.Screen{
			W:         namco.W,
			H:         namco.H,
			Texture:   video.Texture,
			ScanLineV: true,
			Draw:      video.Draw,
		}
	}

	s.dipSwitches[3] = 1
	s.dipSwitches[4] = 2
	s.dipSwitches[5] = 1
	s.dipSwitches[6] = 1

	// HACK
	mem.Write(0x9100, 0xff)
	mem.Write(0x9101, 0xff)

	// memory for each CPU
	s.mem[0] = rcs.NewMemory(1, 0x10000)
	s.mem[0].Name = "mem1"
	s.mem[0].Map(0, mem)
	s.mem[0].MapROM(0x0000, roms["code1"])

	s.mem[1] = rcs.NewMemory(1, 0x10000)
	s.mem[1].Name = "mem2"
	s.mem[1].Map(0, mem)
	s.mem[1].MapROM(0x0000, roms["code2"])

	s.mem[2] = rcs.NewMemory(1, 0x10000)
	s.mem[2].Name = "mem3"
	s.mem[2].Map(0, mem)
	s.mem[2].MapROM(0x0000, roms["code3"])

	s.cpu[0] = z80.New(s.mem[0])
	s.cpu[0].Name = "cpu1"
	s.cpu[1] = z80.New(s.mem[1])
	s.cpu[1].Name = "cpu2"
	s.cpu[2] = z80.New(s.mem[2])
	s.cpu[2].Name = "cpu3"

	vblank := func() {
		if s.InterruptEnable0 != 0 {
			s.cpu[0].IRQ = true
		}
		if s.InterruptEnable1 != 0 {
			s.cpu[1].IRQ = true
		}
		//s.cpu[2].IRQ = true
		if s.InterruptEnable2 != 0 {
			// FIXME: Is this correct??? Probably not
			s.cpu[2].NMI = true
		}
		if s.reset != 0 {
			s.reset = 0
			s.cpu[1].RESET = true
			s.cpu[2].RESET = true
		}
	}

	s.n06xx.NMI = func() {
		s.cpu[0].NMI = true
	}

	mach := &rcs.Mach{
		Sys: s,
		Comps: []rcs.Component{
			rcs.NewComponent("galaga", "galaga", "", s),
			rcs.NewComponent("mem1", "mem", "", s.mem[0]),
			rcs.NewComponent("mem2", "mem", "", s.mem[1]),
			rcs.NewComponent("mem3", "mem", "", s.mem[2]),
			rcs.NewComponent("cpu1", "z80", "mem1", s.cpu[0]),
			rcs.NewComponent("cpu2", "z80", "mem2", s.cpu[1]),
			rcs.NewComponent("cpu3", "z80", "mem3", s.cpu[2]),
			rcs.NewComponent("n06xx", "n06xx", "", s.n06xx),
			rcs.NewComponent("n51xx", "n51xx", "", s.n51xx),
			rcs.NewComponent("n54xx", "n54xx", "", s.n54xx),
		},
		CharDecoders: map[string]rcs.CharDecoder{
			"galaga": GalagaDecoder,
		},
		Ctx:        ctx,
		Screen:     screen,
		VBlankFunc: vblank,
	}
	return mach, nil
}

func New(ctx rcs.SDLContext) (*rcs.Mach, error) {
	return new(ctx, ROM["galaga"])
}


<|start_filename|>rcs/cbm/petscii/petscii_table.go<|end_filename|>
package petscii

var tableUnshifted = map[uint8]rune{
	0x20: ' ',
	0x21: '!',
	0x22: '"',
	0x23: '#',
	0x24: '$',
	0x25: '%',
	0x26: '&',
	0x27: '\'',
	0x28: '(',
	0x29: ')',
	0x2a: '*',
	0x2b: '+',
	0x2c: ',',
	0x2d: '-',
	0x2e: '.',
	0x2f: '/',
	0x30: '0',
	0x31: '1',
	0x32: '2',
	0x33: '3',
	0x34: '4',
	0x35: '5',
	0x36: '6',
	0x37: '7',
	0x38: '8',
	0x39: '9',
	0x3a: ':',
	0x3b: ';',
	0x3c: '<',
	0x3d: '=',
	0x3e: '>',
	0x3f: '?',
	0x40: '@',
	0x41: 'A',
	0x42: 'B',
	0x43: 'C',
	0x44: 'D',
	0x45: 'E',
	0x46: 'F',
	0x47: 'G',
	0x48: 'H',
	0x49: 'I',
	0x4a: 'J',
	0x4b: 'K',
	0x4c: 'L',
	0x4d: 'M',
	0x4e: 'N',
	0x4f: 'O',
	0x50: 'P',
	0x51: 'Q',
	0x52: 'R',
	0x53: 'S',
	0x54: 'T',
	0x55: 'U',
	0x56: 'V',
	0x57: 'W',
	0x58: 'X',
	0x59: 'Y',
	0x5a: 'Z',
	0x5b: '[',
	0x5c: '£',
	0x5d: ']',
	0x5e: '↑',
	0x5f: '←',
	0x60: '─',
	0x61: '♠',
	0x62: '│',
	0x63: '─',
	0x64: '�',
	0x65: '�',
	0x66: '�',
	0x67: '�',
	0x68: '�',
	0x69: '╮',
	0x6a: '╰',
	0x6b: '╯',
	0x6c: '�',
	0x6d: '╲',
	0x6e: '╱',
	0x6f: '�',
	0x70: '�',
	0x71: '●',
	0x72: '�',
	0x73: '♥',
	0x74: '�',
	0x75: '╭',
	0x76: '╳',
	0x77: '○',
	0x78: '♣',
	0x79: '�',
	0x7a: '♦',
	0x7b: '┼',
	0x7c: '�',
	0x7d: '│',
	0x7e: 'π',
	0x7f: '◥',
	0xa0: ' ',
	0xa1: '▌',
	0xa2: '▄',
	0xa3: '▔',
	0xa4: '▁',
	0xa5: '▏',
	0xa6: '▒',
	0xa7: '▕',
	0xa8: '�',
	0xa9: '◤',
	0xaa: '�',
	0xab: '├',
	0xac: '▗',
	0xad: '└',
	0xae: '┐',
	0xaf: '▂',
	0xb0: '┌',
	0xb1: '┴',
	0xb2: '┬',
	0xb3: '┤',
	0xb4: '▎',
	0xb5: '▍',
	0xb6: '�',
	0xb7: '�',
	0xb8: '�',
	0xb9: '▃',
	0xba: '�',
	0xbb: '▖',
	0xbc: '▝',
	0xbd: '┘',
	0xbe: '▘',
	0xbf: '▚',
}
var tableShifted = map[uint8]rune{
	0x20: ' ',
	0x21: '!',
	0x22: '"',
	0x23: '#',
	0x24: '$',
	0x25: '%',
	0x26: '&',
	0x27: '\'',
	0x28: '(',
	0x29: ')',
	0x2a: '*',
	0x2b: '+',
	0x2c: ',',
	0x2d: '-',
	0x2e: '.',
	0x2f: '/',
	0x30: '0',
	0x31: '1',
	0x32: '2',
	0x33: '3',
	0x34: '4',
	0x35: '5',
	0x36: '6',
	0x37: '7',
	0x38: '8',
	0x39: '9',
	0x3a: ':',
	0x3b: ';',
	0x3c: '<',
	0x3d: '=',
	0x3e: '>',
	0x3f: '?',
	0x40: '@',
	0x41: 'a',
	0x42: 'b',
	0x43: 'c',
	0x44: 'd',
	0x45: 'e',
	0x46: 'f',
	0x47: 'g',
	0x48: 'h',
	0x49: 'i',
	0x4a: 'j',
	0x4b: 'k',
	0x4c: 'l',
	0x4d: 'm',
	0x4e: 'n',
	0x4f: 'o',
	0x50: 'p',
	0x51: 'q',
	0x52: 'r',
	0x53: 's',
	0x54: 't',
	0x55: 'u',
	0x56: 'v',
	0x57: 'w',
	0x58: 'x',
	0x59: 'y',
	0x5a: 'z',
	0x5b: '[',
	0x5c: '£',
	0x5d: ']',
	0x5e: '↑',
	0x5f: '←',
	0x60: '─',
	0x61: 'A',
	0x62: 'B',
	0x63: 'C',
	0x64: 'D',
	0x65: 'E',
	0x66: 'F',
	0x67: 'G',
	0x68: 'H',
	0x69: 'I',
	0x6a: 'J',
	0x6b: 'K',
	0x6c: 'L',
	0x6d: 'M',
	0x6e: 'N',
	0x6f: 'O',
	0x70: 'P',
	0x71: 'Q',
	0x72: 'R',
	0x73: 'S',
	0x74: 'T',
	0x75: 'U',
	0x76: 'V',
	0x77: 'W',
	0x78: 'X',
	0x79: 'Y',
	0x7a: 'Z',
	0x7b: '┼',
	0x7c: '�',
	0x7d: '│',
	0x7e: '▒',
	0x7f: '�',
	0xa0: ' ',
	0xa1: '▌',
	0xa2: '▄',
	0xa3: '▔',
	0xa4: '▁',
	0xa5: '▏',
	0xa6: '▒',
	0xa7: '▕',
	0xa8: '�',
	0xa9: '�',
	0xaa: '�',
	0xab: '├',
	0xac: '▗',
	0xad: '└',
	0xae: '┐',
	0xaf: '▂',
	0xb0: '┌',
	0xb1: '┴',
	0xb2: '┬',
	0xb3: '┤',
	0xb4: '▎',
	0xb5: '▍',
	0xb6: '�',
	0xb7: '�',
	0xb8: '�',
	0xb9: '▃',
	0xba: '✓',
	0xbb: '▖',
	0xbc: '▝',
	0xbd: '┘',
	0xbe: '▘',
	0xbf: '▚',
}


<|start_filename|>cmd/rcs-viewer/views.go<|end_filename|>
package main

import (
	"image/color"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/cbm"
	"github.com/blackchip-org/retro-cs/rcs/namco"
	"github.com/blackchip-org/retro-cs/system/c64"
	"github.com/blackchip-org/retro-cs/system/galaga"
	"github.com/blackchip-org/retro-cs/system/pacman"
	"github.com/veandco/go-sdl2/sdl"
)

var views = map[string]view{
	"c64:chars": view{
		system: "c64",
		roms:   c64.SystemROM,
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return cbm.CharGen(r, d["chargen"])
		},
	},
	"c64:colors": view{
		system: "c64",
		render: func(r *sdl.Renderer, _ map[string][]byte) (rcs.TileSheet, error) {
			palettes := [][]color.RGBA{cbm.Palette}
			return rcs.NewColorSheet(r, palettes)
		},
	},
	"galaga:sprites": view{
		system: "galaga",
		roms:   galaga.ROM["galaga"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return namco.NewTileSheet(r, d["sprites"],
				galaga.VideoConfig.SpriteLayout, namco.ViewerPalette)
		},
	},
	"galaga:tiles": view{
		system: "galaga",
		roms:   galaga.ROM["galaga"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return namco.NewTileSheet(r, d["tiles"],
				galaga.VideoConfig.TileLayout, namco.ViewerPalette)
		},
	},
	"mspacman:sprites": view{
		system: "mspacman",
		roms:   pacman.ROM["mspacman"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return namco.NewTileSheet(r, d["sprites"],
				pacman.VideoConfig.SpriteLayout, namco.ViewerPalette)
		},
	},
	"mspacman:tiles": view{
		system: "mspacman",
		roms:   pacman.ROM["mspacman"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return namco.NewTileSheet(r, d["tiles"],
				pacman.VideoConfig.TileLayout, namco.ViewerPalette)
		},
	},
	"pacman:colors": view{
		system: "pacman",
		roms:   pacman.ROM["pacman"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			config := pacman.VideoConfig
			colors := namco.ColorTable(config, d["colors"])
			return rcs.NewColorSheet(r, [][]color.RGBA{colors})
		},
	},
	"pacman:palettes": view{
		system: "pacman",
		roms:   pacman.ROM["pacman"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			config := pacman.VideoConfig
			colors := namco.ColorTable(config, d["colors"])
			palettes := namco.PaletteTable(config, d["palettes"], colors)
			return rcs.NewColorSheet(r, palettes)
		},
	},
	"pacman:sprites": view{
		system: "pacman",
		roms:   pacman.ROM["pacman"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return namco.NewTileSheet(r, d["sprites"],
				pacman.VideoConfig.SpriteLayout, namco.ViewerPalette)
		},
	},
	"pacman:tiles": view{
		system: "pacman",
		roms:   pacman.ROM["pacman"],
		render: func(r *sdl.Renderer, d map[string][]byte) (rcs.TileSheet, error) {
			return namco.NewTileSheet(r, d["tiles"],
				pacman.VideoConfig.TileLayout, namco.ViewerPalette)
		},
	},
}


<|start_filename|>rcs/z80/cpu.go<|end_filename|>
package z80

import (
	"fmt"
	"log"

	"github.com/blackchip-org/retro-cs/rcs"
)

// CPU is the Zilog Z80 processor.
type CPU struct {
	Name string

	pc uint16 // Program counter
	A  uint8  // Accumulator
	F  uint8  // Flags
	B  uint8
	C  uint8
	D  uint8
	E  uint8
	H  uint8
	L  uint8

	A1 uint8 // Shadow registers
	F1 uint8
	B1 uint8
	C1 uint8
	D1 uint8
	E1 uint8
	H1 uint8
	L1 uint8

	I   uint8 // Interrupt vector base
	R   uint8 // DRAM refresh counter
	IXH uint8
	IXL uint8
	IYH uint8
	IYL uint8
	SP  uint16 // Stack pointer

	IFF1 bool // Interrupt flip flops
	IFF2 bool
	IM   uint8 // Interrupt mode
	Halt bool  // Halted by instruction

	Ports   *rcs.Memory
	IRQ     bool
	IRQData uint8
	NMI     bool
	RESET   bool

	WatchIRQ bool

	opcodes     map[uint8]func(*CPU)
	opcodesCB   map[uint8]func(*CPU)
	opcodesED   map[uint8]func(*CPU)
	opcodesDD   map[uint8]func(*CPU)
	opcodesFD   map[uint8]func(*CPU)
	opcodesDDCB map[uint8]func(*CPU)
	opcodesFDCB map[uint8]func(*CPU)

	mem   *rcs.Memory
	delta uint8
	// address used to load on the last (IX+d) or (IY+d) instruction
	iaddr int
}

const (
	// FlagC is the carry flag
	FlagC = uint8(1 << 0)

	// FlagN is set after subtraction
	FlagN = uint8(1 << 1)

	// FlagV is the overflow flag (also parity)
	FlagV = uint8(1 << 2)

	// FlagP is the parity flag (also overflow)
	FlagP = uint8(1 << 2)

	// Flag3 is undefined
	Flag3 = uint8(1 << 3)

	// FlagH is the half-carry flag
	FlagH = uint8(1 << 4)

	// Flag5 is undefined
	Flag5 = uint8(1 << 5)

	// FlagZ is the zero flag
	FlagZ = uint8(1 << 6)

	// FlagS is the sign flag
	FlagS = uint8(1 << 7)
)

func New(mem *rcs.Memory) *CPU {
	c := &CPU{
		mem:         mem,
		Ports:       rcs.NewMemory(1, 0x100),
		opcodes:     opcodes,
		opcodesCB:   opcodesCB,
		opcodesED:   opcodesED,
		opcodesDD:   opcodesDD,
		opcodesFD:   opcodesFD,
		opcodesDDCB: opcodesDDCB,
		opcodesFDCB: opcodesFDCB,
	}
	c.Ports.MapRAM(0, make([]uint8, 0x100, 0x100))
	return c
}

func (c *CPU) Next() {
	if !c.Halt {
		c.execute()
	}
	if c.IRQ {
		c.IRQ = false
		if c.IFF1 {
			c.irqAck()
		}
	}
	if c.NMI {
		c.NMI = false
		c.nmiAck()
	}
	if c.RESET {
		c.RESET = false
		c.resetAck()
	}
}

func (c *CPU) execute() {
	here := c.PC()
	opcode := c.fetch()
	c.refreshR()

	prefix := ""
	var table map[uint8]func(*CPU)
	switch opcode {
	case 0xcb:
		table = c.opcodesCB
		opcode = c.fetch()
		c.refreshR()
		prefix = "cb"
	case 0xed:
		table = c.opcodesED
		opcode = c.fetch()
		c.refreshR()
		prefix = "ed"
	case 0xdd:
		table = c.opcodesDD
		opcode = c.fetch()
		c.refreshR()
		prefix = "dd"
		if opcode == 0xcb {
			table = c.opcodesDDCB
			c.fetchd()
			opcode = c.fetch()
			prefix = "ddcb"
		}
	case 0xfd:
		table = c.opcodesFD
		opcode = c.fetch()
		c.refreshR()
		prefix = "fd"
		if opcode == 0xcb {
			table = c.opcodesFDCB
			c.fetchd()
			opcode = c.fetch()
			prefix = "fdcb"
		}
	default:
		table = c.opcodes
	}

	opFunc, ok := table[opcode]
	if !ok {
		log.Printf("%04x: illegal instruction: %v%02x", here, prefix, opcode)
		return
	}
	opFunc(c)
}

func (c *CPU) irqAck() {
	if c.IM == 0 {
		log.Printf("(!) %v: unsupported interrupt mode 0", c.Name)
		return
	}
	retAddr := c.PC()
	c.Halt = false
	c.IFF1 = false
	c.IFF2 = false
	c.SP -= 2
	c.mem.WriteLE(int(c.SP), retAddr)
	if c.IM == 2 {
		vector := int(c.I)<<8 | int(c.IRQData)
		if c.WatchIRQ {
			log.Printf("%v: irq(2:%v), vector %v, return %v", c.Name,
				rcs.X8(c.IRQData), rcs.X(vector), rcs.X(retAddr))
		}
		c.SetPC(c.mem.ReadLE(vector))
	} else {
		if c.WatchIRQ {
			log.Printf("%v: irq(1), return %v", c.Name, rcs.X(retAddr))
		}
		c.pc = 0x0038
	}
}

func (c *CPU) nmiAck() {
	c.SP -= 2
	c.mem.WriteLE(int(c.SP), c.PC())
	c.pc = 0x0066
}

func (c *CPU) resetAck() {
	c.IFF1 = false
	c.IFF2 = false
	c.pc = 0
	c.I = 0
	c.R = 0
	c.IM = 0
}

// PC returns the value of the program counter.
func (c *CPU) PC() int {
	return int(c.pc)
}

// SetPC sets the value of the program counter.
func (c *CPU) SetPC(pc int) {
	c.pc = uint16(pc)
}

// Offset is the value to be added to the program counter to get the
// address of the next instruction. The value is 0 for this CPU since
// the program counter is incremented after fetching the opcode.
func (c *CPU) Offset() int {
	return 0
}

// Memory is the memory that can been seen by this CPU.
func (c *CPU) Memory() *rcs.Memory {
	return c.mem
}

// NewDisassembler creates a disassembler that can handle Z80 machine
// code.
func (c *CPU) NewDisassembler() *rcs.Disassembler {
	dasm := rcs.NewDisassembler(c.mem, Reader, Formatter())
	return dasm
}

func (c *CPU) fetch() uint8 {
	c.pc++
	return c.mem.Read(int(c.pc - 1))
}

func (c *CPU) fetch2() int {
	return int(c.fetch()) + (int(c.fetch()) << 8)
}

func (cpu *CPU) fetchd() {
	cpu.delta = cpu.fetch()
}

func (c *CPU) refreshR() {
	// Lower 7 bits of the refresh register are incremented on an instruction
	// fetch
	bit7 := c.R & 0x80
	c.R = (c.R+1)&0x7f | bit7
}

func (c *CPU) String() string {
	b := func(v uint8, ch string) string {
		if v != 0 {
			return ch
		}
		return "."
	}

	iff1 := ""
	if c.IFF1 {
		iff1 = "iff1"
	}
	iff2 := ""
	if c.IFF2 {
		iff2 = "iff2"
	}

	return fmt.Sprintf(""+
		" pc   af   bc   de   hl   ix   iy   sp   i  r\n"+
		"%04x %02x%02x %02x%02x %02x%02x %02x%02x %02x%02x %02x%02x %04x  %02x %02x %v\n"+
		"im %v %02x%02x %02x%02x %02x%02x %02x%02x      %v %v %v %v %v %v %v %v  %v\n",
		// line 1
		c.pc,
		c.A, c.F,
		c.B, c.C,
		c.D, c.E,
		c.H, c.L,
		c.IXH, c.IXL,
		c.IYH, c.IYL,
		c.SP,
		c.I,
		c.R,
		iff1,
		// line 2
		c.IM,
		c.A1, c.F1,
		c.B1, c.C1,
		c.D1, c.E1,
		c.H1, c.L1,
		// flags
		b(c.F&FlagS, "S"),
		b(c.F&FlagZ, "Z"),
		b(c.F&Flag5, "5"),
		b(c.F&FlagH, "H"),
		b(c.F&Flag3, "3"),
		b(c.F&FlagV, "V"),
		b(c.F&FlagN, "N"),
		b(c.F&FlagC, "C"),
		iff2,
	)
}

func (c *CPU) Save(enc *rcs.Encoder) {
	enc.Encode(c.A)
	enc.Encode(c.F)
	enc.Encode(c.B)
	enc.Encode(c.C)
	enc.Encode(c.D)
	enc.Encode(c.H)
	enc.Encode(c.L)

	enc.Encode(c.A1)
	enc.Encode(c.F1)
	enc.Encode(c.B1)
	enc.Encode(c.C1)
	enc.Encode(c.D1)
	enc.Encode(c.H1)
	enc.Encode(c.L1)

	enc.Encode(c.I)
	enc.Encode(c.R)
	enc.Encode(c.IXH)
	enc.Encode(c.IXL)
	enc.Encode(c.IYH)
	enc.Encode(c.IYL)
	enc.Encode(c.SP)
	enc.Encode(c.pc)

	enc.Encode(c.IFF1)
	enc.Encode(c.IFF2)
	enc.Encode(c.IM)
	enc.Encode(c.Halt)
}

func (c *CPU) Load(dec *rcs.Decoder) {
	dec.Decode(&c.A)
	dec.Decode(&c.F)
	dec.Decode(&c.B)
	dec.Decode(&c.C)
	dec.Decode(&c.D)
	dec.Decode(&c.H)
	dec.Decode(&c.L)

	dec.Decode(&c.A1)
	dec.Decode(&c.F1)
	dec.Decode(&c.B1)
	dec.Decode(&c.C1)
	dec.Decode(&c.D1)
	dec.Decode(&c.H1)
	dec.Decode(&c.L1)

	dec.Decode(&c.I)
	dec.Decode(&c.R)
	dec.Decode(&c.IXH)
	dec.Decode(&c.IXL)
	dec.Decode(&c.IYH)
	dec.Decode(&c.IYL)
	dec.Decode(&c.SP)
	dec.Decode(&c.pc)

	dec.Decode(&c.IFF1)
	dec.Decode(&c.IFF2)
	dec.Decode(&c.IM)
	dec.Decode(&c.Halt)
}

func (c *CPU) prefix() string {
	if c.Name == "" {
		return ""
	}
	return c.Name + "  "
}


<|start_filename|>mock/mach.go<|end_filename|>
package mock

import "github.com/blackchip-org/retro-cs/rcs"

func NewMach() *rcs.Mach {
	ResetMemory()
	return &rcs.Mach{
		Comps: []rcs.Component{
			rcs.NewComponent("mem", "mem", "", TestMemory),
			rcs.NewComponent("cpu", "cpu", "mem", NewCPU(TestMemory)),
		},
		CharDecoders: map[string]rcs.CharDecoder{
			"ascii": rcs.ASCIIDecoder,
			"az26":  AZ26Decoder,
		},
		DefaultEncoding: "ascii",
	}
}

var AZ26Decoder = func(code uint8) (rune, bool) {
	if code < 1 || code > 26 {
		return 0, false
	}
	return rune(64 + code), true
}


<|start_filename|>rcs/m6502/opcodes.go<|end_filename|>
package m6502

// http://www.6502.org/tutorials/6502opcodes.html

var opcodes = map[uint8]func(*CPU){
	0x00: func(c *CPU) { brk(c) },
	0x01: func(c *CPU) { ora(c, c.loadIndirectX) },
	0x05: func(c *CPU) { ora(c, c.loadZeroPage) },
	0x06: func(c *CPU) { asl(c, c.storeBack, c.loadZeroPage) },
	0x08: func(c *CPU) { php(c) }, // php
	0x09: func(c *CPU) { ora(c, c.loadImmediate) },
	0x0a: func(c *CPU) { asl(c, c.storeA, c.loadA) },
	0x0d: func(c *CPU) { ora(c, c.loadAbsolute) },
	0x0e: func(c *CPU) { asl(c, c.storeBack, c.loadAbsolute) },

	0x10: func(c *CPU) { branch(c, c.SR&FlagN == 0) }, // bpl
	0x11: func(c *CPU) { ora(c, c.loadIndirectY) },
	0x15: func(c *CPU) { ora(c, c.loadZeroPageX) },
	0x16: func(c *CPU) { asl(c, c.storeBack, c.loadZeroPageX) },
	0x18: func(c *CPU) { c.SR &^= FlagC }, // clc
	0x19: func(c *CPU) { ora(c, c.loadAbsoluteY) },
	0x1d: func(c *CPU) { ora(c, c.loadAbsoluteX) },
	0x1e: func(c *CPU) { asl(c, c.storeBack, c.loadAbsoluteX) },

	0x20: func(c *CPU) { jsr(c) },
	0x21: func(c *CPU) { and(c, c.loadIndirectX) },
	0x24: func(c *CPU) { bit(c, c.loadZeroPage) },
	0x25: func(c *CPU) { and(c, c.loadZeroPage) },
	0x26: func(c *CPU) { rol(c, c.storeBack, c.loadZeroPage) },
	0x28: func(c *CPU) { plp(c) },
	0x29: func(c *CPU) { and(c, c.loadImmediate) },
	0x2a: func(c *CPU) { rol(c, c.storeA, c.loadA) },
	0x2c: func(c *CPU) { bit(c, c.loadAbsolute) },
	0x2d: func(c *CPU) { and(c, c.loadAbsolute) },
	0x2e: func(c *CPU) { rol(c, c.storeBack, c.loadAbsolute) },

	0x30: func(c *CPU) { branch(c, c.SR&FlagN != 0) }, // bmi
	0x31: func(c *CPU) { and(c, c.loadIndirectY) },
	0x35: func(c *CPU) { and(c, c.loadZeroPageX) },
	0x36: func(c *CPU) { rol(c, c.storeBack, c.loadZeroPageX) },
	0x38: func(c *CPU) { c.SR |= FlagC }, // sec
	0x39: func(c *CPU) { and(c, c.loadAbsoluteY) },
	0x3d: func(c *CPU) { and(c, c.loadAbsoluteX) },
	0x3e: func(c *CPU) { rol(c, c.storeBack, c.loadAbsoluteX) },

	0x40: func(c *CPU) { rti(c) },
	0x41: func(c *CPU) { eor(c, c.loadIndirectX) },
	0x45: func(c *CPU) { eor(c, c.loadZeroPage) },
	0x46: func(c *CPU) { lsr(c, c.storeBack, c.loadZeroPage) },
	0x48: func(c *CPU) { c.push(c.A) }, // pha
	0x49: func(c *CPU) { eor(c, c.loadImmediate) },
	0x4a: func(c *CPU) { lsr(c, c.storeA, c.loadA) },
	0x4c: func(c *CPU) { jmp(c) },
	0x4d: func(c *CPU) { eor(c, c.loadAbsolute) },
	0x4e: func(c *CPU) { lsr(c, c.storeBack, c.loadAbsolute) },

	0x50: func(c *CPU) { branch(c, c.SR&FlagV == 0) }, // bvc
	0x51: func(c *CPU) { eor(c, c.loadIndirectY) },
	0x55: func(c *CPU) { eor(c, c.loadZeroPageX) },
	0x56: func(c *CPU) { lsr(c, c.storeBack, c.loadZeroPageX) },
	0x58: func(c *CPU) { c.SR &^= FlagI }, // cli
	0x59: func(c *CPU) { eor(c, c.loadAbsoluteY) },
	0x5d: func(c *CPU) { eor(c, c.loadAbsoluteX) },
	0x5e: func(c *CPU) { lsr(c, c.storeBack, c.loadAbsoluteX) },

	0x60: func(c *CPU) { c.pc = c.pull2() }, // rts
	0x61: func(c *CPU) { adc(c, c.loadIndirectX) },
	0x65: func(c *CPU) { adc(c, c.loadZeroPage) },
	0x66: func(c *CPU) { ror(c, c.storeBack, c.loadZeroPage) },
	0x68: func(c *CPU) { pla(c) },
	0x69: func(c *CPU) { adc(c, c.loadImmediate) },
	0x6a: func(c *CPU) { ror(c, c.storeA, c.loadA) },
	0x6c: func(c *CPU) { jmpIndirect(c) },
	0x6d: func(c *CPU) { adc(c, c.loadAbsolute) },
	0x6e: func(c *CPU) { ror(c, c.storeBack, c.loadAbsolute) },

	0x70: func(c *CPU) { branch(c, c.SR&FlagV != 0) }, // bvs
	0x71: func(c *CPU) { adc(c, c.loadIndirectY) },
	0x75: func(c *CPU) { adc(c, c.loadZeroPageX) },
	0x76: func(c *CPU) { ror(c, c.storeBack, c.loadZeroPageX) },
	0x78: func(c *CPU) { c.SR |= FlagI }, // sei
	0x79: func(c *CPU) { adc(c, c.loadAbsoluteY) },
	0x7d: func(c *CPU) { adc(c, c.loadAbsoluteX) },
	0x7e: func(c *CPU) { ror(c, c.storeBack, c.loadAbsoluteX) },

	0x81: func(c *CPU) { st(c, c.storeIndirectX, c.loadA) },
	0x84: func(c *CPU) { st(c, c.storeZeroPage, c.loadY) },
	0x85: func(c *CPU) { st(c, c.storeZeroPage, c.loadA) },
	0x86: func(c *CPU) { st(c, c.storeZeroPage, c.loadX) },
	0x88: func(c *CPU) { dec(c, c.storeY, c.loadY) },
	0x8a: func(c *CPU) { ld(c, c.storeA, c.loadX) }, // txa
	0x8c: func(c *CPU) { st(c, c.storeAbsolute, c.loadY) },
	0x8d: func(c *CPU) { st(c, c.storeAbsolute, c.loadA) },
	0x8e: func(c *CPU) { st(c, c.storeAbsolute, c.loadX) },

	0x90: func(c *CPU) { branch(c, c.SR&FlagC == 0) }, // bcc
	0x91: func(c *CPU) { st(c, c.storeIndirectY, c.loadA) },
	0x94: func(c *CPU) { st(c, c.storeZeroPageX, c.loadY) },
	0x95: func(c *CPU) { st(c, c.storeZeroPageX, c.loadA) },
	0x96: func(c *CPU) { st(c, c.storeZeroPageY, c.loadX) },
	0x98: func(c *CPU) { ld(c, c.storeA, c.loadY) }, // tya
	0x99: func(c *CPU) { st(c, c.storeAbsoluteY, c.loadA) },
	0x9a: func(c *CPU) { c.storeSP(c.loadX()) }, // txs: does not set NZ
	0x9d: func(c *CPU) { st(c, c.storeAbsoluteX, c.loadA) },

	0xa0: func(c *CPU) { ld(c, c.storeY, c.loadImmediate) },
	0xa1: func(c *CPU) { ld(c, c.storeA, c.loadIndirectX) },
	0xa2: func(c *CPU) { ld(c, c.storeX, c.loadImmediate) },
	0xa4: func(c *CPU) { ld(c, c.storeY, c.loadZeroPage) },
	0xa5: func(c *CPU) { ld(c, c.storeA, c.loadZeroPage) },
	0xa6: func(c *CPU) { ld(c, c.storeX, c.loadZeroPage) },
	0xa8: func(c *CPU) { ld(c, c.storeY, c.loadA) }, // tay
	0xa9: func(c *CPU) { ld(c, c.storeA, c.loadImmediate) },
	0xaa: func(c *CPU) { ld(c, c.storeX, c.loadA) }, // tax
	0xac: func(c *CPU) { ld(c, c.storeY, c.loadAbsolute) },
	0xad: func(c *CPU) { ld(c, c.storeA, c.loadAbsolute) },
	0xae: func(c *CPU) { ld(c, c.storeX, c.loadAbsolute) },

	0xb0: func(c *CPU) { branch(c, c.SR&FlagC != 0) }, // bcs
	0xb1: func(c *CPU) { ld(c, c.storeA, c.loadIndirectY) },
	0xb4: func(c *CPU) { ld(c, c.storeY, c.loadZeroPageX) },
	0xb5: func(c *CPU) { ld(c, c.storeA, c.loadZeroPageX) },
	0xb6: func(c *CPU) { ld(c, c.storeX, c.loadZeroPageY) },
	0xb8: func(c *CPU) { c.SR &^= FlagV }, // clv
	0xb9: func(c *CPU) { ld(c, c.storeA, c.loadAbsoluteY) },
	0xba: func(c *CPU) { ld(c, c.storeX, c.loadSP) }, // tsx
	0xbc: func(c *CPU) { ld(c, c.storeY, c.loadAbsoluteX) },
	0xbd: func(c *CPU) { ld(c, c.storeA, c.loadAbsoluteX) },
	0xbe: func(c *CPU) { ld(c, c.storeX, c.loadAbsoluteY) },

	0xc0: func(c *CPU) { cmp(c, c.loadY, c.loadImmediate) },
	0xc1: func(c *CPU) { cmp(c, c.loadA, c.loadIndirectX) },
	0xc4: func(c *CPU) { cmp(c, c.loadY, c.loadZeroPage) },
	0xc5: func(c *CPU) { cmp(c, c.loadA, c.loadZeroPage) },
	0xc6: func(c *CPU) { dec(c, c.storeBack, c.loadZeroPage) },
	0xc8: func(c *CPU) { inc(c, c.storeY, c.loadY) },
	0xc9: func(c *CPU) { cmp(c, c.loadA, c.loadImmediate) },
	0xca: func(c *CPU) { dec(c, c.storeX, c.loadX) },
	0xcc: func(c *CPU) { cmp(c, c.loadY, c.loadAbsolute) },
	0xcd: func(c *CPU) { cmp(c, c.loadA, c.loadAbsolute) },
	0xce: func(c *CPU) { dec(c, c.storeBack, c.loadAbsolute) },

	0xd0: func(c *CPU) { branch(c, c.SR&FlagZ == 0) }, // bne
	0xd1: func(c *CPU) { cmp(c, c.loadA, c.loadIndirectY) },
	0xd5: func(c *CPU) { cmp(c, c.loadA, c.loadZeroPageX) },
	0xd6: func(c *CPU) { dec(c, c.storeBack, c.loadZeroPageX) },
	0xd8: func(c *CPU) { c.SR &^= FlagD }, // cld
	0xd9: func(c *CPU) { cmp(c, c.loadA, c.loadAbsoluteY) },
	0xdd: func(c *CPU) { cmp(c, c.loadA, c.loadAbsoluteX) },
	0xde: func(c *CPU) { dec(c, c.storeBack, c.loadAbsoluteX) },

	0xe0: func(c *CPU) { cmp(c, c.loadX, c.loadImmediate) },
	0xe1: func(c *CPU) { sbc(c, c.loadIndirectX) },
	0xe4: func(c *CPU) { cmp(c, c.loadX, c.loadZeroPage) },
	0xe5: func(c *CPU) { sbc(c, c.loadZeroPage) },
	0xe6: func(c *CPU) { inc(c, c.storeBack, c.loadZeroPage) },
	0xe8: func(c *CPU) { inc(c, c.storeX, c.loadX) },
	0xe9: func(c *CPU) { sbc(c, c.loadImmediate) },
	0xea: func(c *CPU) {}, // nop
	0xec: func(c *CPU) { cmp(c, c.loadX, c.loadAbsolute) },
	0xed: func(c *CPU) { sbc(c, c.loadAbsolute) },
	0xee: func(c *CPU) { inc(c, c.storeBack, c.loadAbsolute) },

	0xf0: func(c *CPU) { branch(c, c.SR&FlagZ != 0) }, // beq
	0xf1: func(c *CPU) { sbc(c, c.loadIndirectY) },
	0xf5: func(c *CPU) { sbc(c, c.loadZeroPageX) },
	0xf6: func(c *CPU) { inc(c, c.storeBack, c.loadZeroPageX) },
	0xf8: func(c *CPU) { c.SR |= FlagD }, // sed
	0xf9: func(c *CPU) { sbc(c, c.loadAbsoluteY) },
	0xfd: func(c *CPU) { sbc(c, c.loadAbsoluteX) },
	0xfe: func(c *CPU) { inc(c, c.storeBack, c.loadAbsoluteX) },
}


<|start_filename|>system/c128/roms.go<|end_filename|>
package c128

import "github.com/blackchip-org/retro-cs/rcs"

var SystemROM = []rcs.ROM{
	rcs.NewROM("basichi", "basichi", "c4fb4a714e48a7bf6c28659de0302183a0e0d6c0"),
	rcs.NewROM("basiclo", "basiclo", "d53a7884404f7d18ebd60dd3080c8f8d71067441"),
	rcs.NewROM("chargen", "chargen", "29ed066d513f2d5c09ff26d9166ba23c2afb2b3f"),
	rcs.NewROM("kernal ", "kernal ", "ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab"),
}


<|start_filename|>app/systems.go<|end_filename|>
package app

import (
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/system/c128"
	"github.com/blackchip-org/retro-cs/system/c64"
	"github.com/blackchip-org/retro-cs/system/galaga"
	"github.com/blackchip-org/retro-cs/system/pacman"
)

var Systems = map[string]func(rcs.SDLContext) (*rcs.Mach, error){
	"c64":      c64.New,
	"c128":     c128.New,
	"galaga":   galaga.New,
	"pacman":   pacman.New,
	"mspacman": pacman.NewMs,
}


<|start_filename|>app/monitor/memory.go<|end_filename|>
package monitor

import (
	"bytes"
	"fmt"
	"log"
	"sort"
	"strings"

	"github.com/chzyer/readline"

	"github.com/blackchip-org/retro-cs/rcs"
)

type modMemory struct {
	name    string
	mon     *Monitor
	out     *log.Logger
	mem     *rcs.Memory
	ptr     *rcs.Pointer
	watches map[int]string
}

func newModMemory(mon *Monitor, comp rcs.Component) module {
	mem := comp.C.(*rcs.Memory)
	mod := &modMemory{
		name:    comp.Name,
		mon:     mon,
		out:     mon.out,
		mem:     mem,
		ptr:     rcs.NewPointer(mem),
		watches: make(map[int]string),
	}
	mem.Callback = mod.watchCallback
	return mod
}

func (m *modMemory) Command(args []string) error {
	if err := checkLen(args, 0, maxArgs); err != nil {
		return err
	}
	if len(args) == 0 {
		return m.cmdDump(args[0:])
	}
	switch args[0] {
	case "dump":
		return m.cmdDump(args[1:])
	case "fill":
		return m.cmdFill(args[1:])
	case "peek":
		return m.cmdPeek(args[1:])
	case "poke":
		return m.cmdPoke(args[1:])
	case "watch", "w":
		return m.cmdWatch(args[1:])
	}
	return m.cmdDump(args[0:])
}

func (m *modMemory) cmdDump(args []string) error {
	if err := checkLen(args, 0, 2); err != nil {
		return err
	}
	addrStart := 0
	if len(args) == 0 {
		addrStart = m.ptr.Addr()
	}
	if len(args) > 0 {
		addr, err := parseAddress(m.mem, args[0])
		if err != nil {
			return err
		}
		addrStart = addr
	}
	addrEnd := addrStart + (m.mon.memLines * 16)
	if len(args) > 1 {
		addr, err := parseAddress(m.mem, args[1])
		if err != nil {
			return err
		}
		addrEnd = addr
	}
	decoder, ok := m.mon.mach.CharDecoders[m.mon.encoding]
	if !ok {
		return fmt.Errorf("invalid encoding: %v", m.mon.encoding)
	}
	m.mon.out.Println(dump(m.mem, addrStart, addrEnd, decoder, m.prefix()))
	m.ptr.SetAddr(addrEnd)
	m.mon.defaultCmd = fmt.Sprintf("%v dump", m.name)
	return nil
}

func (m *modMemory) cmdFill(args []string) error {
	if err := checkLen(args, 3, 3); err != nil {
		return err
	}
	startAddr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return err
	}
	endAddr, err := parseAddress(m.mem, args[1])
	if err != nil {
		return err
	}
	value, err := parseValue8(args[2])
	if err != nil {
		return err
	}
	if startAddr > endAddr {
		return nil
	}
	for addr := startAddr; addr <= endAddr; addr++ {
		m.mem.Write(addr, value)
	}
	return nil
}

func (m *modMemory) cmdPeek(args []string) error {
	if err := checkLen(args, 1, 1); err != nil {
		return err
	}
	addr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return err
	}
	v := m.mem.Read(addr)
	m.mon.out.Print(formatValue(int(v)))
	return nil
}

func (m *modMemory) cmdPoke(args []string) error {
	if err := checkLen(args, 2, maxArgs); err != nil {
		return err
	}
	addr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return err
	}
	values := []uint8{}
	for _, str := range args[1:] {
		v, err := parseValue8(str)
		if err != nil {
			return err
		}
		values = append(values, v)
	}
	m.mem.WriteN(addr, values...)
	return nil
}

func (m *modMemory) cmdWatch(args []string) error {
	if len(args) == 0 {
		return m.cmdWatchList(args[0:])
	}
	switch args[0] {
	case "list":
		return m.cmdWatchList(args[1:])
	case "none":
		return m.cmdWatchNone(args[1:])
	}
	return m.cmdWatchSwitch(args[0:])
}

func (m *modMemory) cmdWatchClear(args []string) error {
	if err := checkLen(args, 1, 1); err != nil {
		return err
	}
	addr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return err
	}
	if _, ok := m.watches[addr]; ok {
		delete(m.watches, addr)
		m.mem.Unwatch(addr)
	}
	return nil
}

func (m *modMemory) cmdWatchList(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	if len(m.watches) == 0 {
		return nil
	}
	list := make([]string, 0, len(m.watches))
	for addr, mode := range m.watches {
		list = append(list, fmt.Sprintf("%v$%04x %v", m.prefix(), addr, mode))
	}
	sort.Strings(list)
	m.mon.out.Print(strings.Join(list, "\n"))
	return nil
}

func (m *modMemory) cmdWatchNone(args []string) error {
	if err := checkLen(args, 0, 0); err != nil {
		return err
	}
	for addr := range m.watches {
		delete(m.watches, addr)
		m.mem.Unwatch(addr)
	}
	return nil
}

func (m *modMemory) cmdWatchSwitch(args []string) error {
	if err := checkLen(args, 1, 2); err != nil {
		return nil
	}
	addr, err := parseAddress(m.mem, args[0])
	if err != nil {
		return fmt.Errorf("invalid address: %v", args[0])
	}
	if len(args) == 1 {
		if state, ok := m.watches[addr]; ok {
			m.out.Println(state)
		} else {
			m.out.Println("off")
		}
		return nil
	}
	mode := args[1]
	switch mode {
	case "r", "ro":
		m.mem.WatchRO(addr)
		m.watches[addr] = "r"
	case "w", "wo":
		m.mem.WatchWO(addr)
		m.watches[addr] = "w"
	case "rw":
		m.mem.WatchRW(addr)
		m.watches[addr] = "rw"
	case "off":
		m.mem.Unwatch(addr)
		delete(m.watches, addr)
	default:
		return fmt.Errorf("invalid argument: %v", mode)
	}
	return nil
}

func (m *modMemory) watchCallback(evt rcs.MemoryEvent) {
	// FIXME: hard coded address format
	a := fmt.Sprintf("$%04x", evt.Addr)
	if m.mem.NBank > 1 {
		a = fmt.Sprintf("%v:$%04x", evt.Bank, evt.Addr)
	}

	// CPU info
	execInfo := ""
	mach := m.mon.mach
	if mach.Executing != "" {
		execInfo = fmt.Sprintf(", %v pc %v", mach.Executing, formatAddress(mach.At))
	}

	if evt.Read {
		m.mon.out.Printf("%v <= %v[%v]%v", rcs.X8(evt.Value), m.name, a, execInfo)
	} else {
		m.mon.out.Printf("%v[%v] <= %v%v", m.name, a, rcs.X8(evt.Value), execInfo)
	}
}

func (m *modMemory) prefix() string {
	if m.name == "mem" {
		return ""
	}
	return m.name + "  "
}

func (m *modMemory) AutoComplete() []readline.PrefixCompleterInterface {
	return []readline.PrefixCompleterInterface{
		readline.PcItem("dump"),
		readline.PcItem("fill"),
		readline.PcItem("peek"),
		readline.PcItem("poke"),
		readline.PcItem("watch-clear"),
		readline.PcItem("watch-list"),
		readline.PcItem("watch-none"),
		readline.PcItem("watch-set"),
	}
}

func (m *modMemory) Silence() error {
	return m.cmdWatchNone([]string{})
}

func dump(m *rcs.Memory, start int, end int, decode rcs.CharDecoder, prefix string) string {
	var buf bytes.Buffer
	var chars bytes.Buffer

	a0 := start / 0x10 * 0x10
	a1 := end / 0x10 * 0x10
	if a1 != end {
		a1 += 0x10
	}
	for addr := a0; addr < a1; addr++ {
		if addr%0x10 == 0 {
			buf.WriteString(fmt.Sprintf("%v$%04x ", prefix, addr))
			chars.Reset()
		}
		if addr < start || addr > end {
			buf.WriteString("   ")
			chars.WriteString(" ")
		} else {
			value := m.Read(addr)
			buf.WriteString(fmt.Sprintf(" %02x", value))
			ch, printable := decode(value)
			if printable {
				chars.WriteString(fmt.Sprintf("%c", ch))
			} else {
				chars.WriteString(".")
			}
		}
		if addr%0x10 == 7 {
			buf.WriteString(" ")
		}
		if addr%0x10 == 0x0f {
			buf.WriteString("  " + chars.String())
			if addr < end-1 {
				buf.WriteString("\n")
			}
		}
	}
	return buf.String()
}


<|start_filename|>rcs/z80/reader.go<|end_filename|>
package z80

import (
	"fmt"
	"strings"

	"github.com/blackchip-org/retro-cs/rcs"
)

func Reader(e rcs.StmtEval) {
	e.Stmt.Addr = e.Ptr.Addr()
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = []uint8{opcode}
	dasmTable[opcode](e)
}

func Formatter() rcs.CodeFormatter {
	options := rcs.FormatOptions{
		BytesFormat: "%-11s",
	}
	return func(s rcs.Stmt) string {
		return rcs.FormatStmt(s, options)
	}
}

func NewDisassembler(mem *rcs.Memory) *rcs.Disassembler {
	return rcs.NewDisassembler(mem, Reader, Formatter())
}

func op1(e rcs.StmtEval, parts ...string) {
	var out strings.Builder
	for i, part := range parts {
		v := part
		switch {
		case i == 0:
			v = fmt.Sprintf("%-4s", part)
		case parts[0] == "rst" && i == 1:
			// Reset statements have the argment encoded in the opcode. Change
			// the hex notation from & to $ in the second part
			v = "$" + v[1:]
		case part == "&4546":
			// This is an address that is a 8-bit displacement from the
			// current program counter
			delta := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, delta)
			addr := displace(e.Stmt.Addr+2, delta)
			v = fmt.Sprintf("$%04x", addr)
		case part == "&0000":
			lo := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, lo)
			hi := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, hi)
			addr := int(hi)<<8 | int(lo)
			v = fmt.Sprintf("$%04x", addr)
		case part == "(&0000)":
			lo := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, lo)
			hi := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, hi)
			addr := int(hi)<<8 | int(lo)
			v = fmt.Sprintf("($%04x)", addr)
		case part == "&00":
			arg := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, arg)
			v = fmt.Sprintf("$%02x", arg)
		case part == "(&00)":
			arg := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, arg)
			v = fmt.Sprintf("($%02x)", arg)
		case part == "(ix+0)":
			delta := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, delta)
			v = fmt.Sprintf("(ix+$%02x)", delta)
		case part == "(iy+0)":
			delta := e.Ptr.Fetch()
			e.Stmt.Bytes = append(e.Stmt.Bytes, delta)
			v = fmt.Sprintf("(iy+$%02x)", delta)
		}

		if i == 1 {
			out.WriteString(" ")
		}
		if i == 2 {
			out.WriteString(",")
		}
		out.WriteString(v)
	}
	e.Stmt.Op = strings.TrimSpace(out.String())
}

func op2(e rcs.StmtEval, parts ...string) {
	var out strings.Builder
	for i, part := range parts {
		v := part
		switch {
		case i == 0:
			v = fmt.Sprintf("%-4s", part)
		case part == "(ix+0)":
			delta := e.Stmt.Bytes[len(e.Stmt.Bytes)-2]
			v = fmt.Sprintf("(ix+$%02x)", delta)
		case part == "(iy+0)":
			delta := e.Stmt.Bytes[len(e.Stmt.Bytes)-2]
			v = fmt.Sprintf("(iy+$%02x)", delta)
		}

		if i == 1 {
			out.WriteString(" ")
		}
		if i == 2 {
			out.WriteString(",")
		}
		out.WriteString(v)
	}
	e.Stmt.Op = strings.TrimSpace(out.String())
}

func opDD(e rcs.StmtEval) {
	next := e.Ptr.Peek()
	if next == 0xdd || next == 0xed || next == 0xfd {
		e.Stmt.Op = "?dd"
		return
	}
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	if opcode == 0xcb {
		opDDCB(e)
		return
	}
	dasmTableDD[opcode](e)
}

func opFD(e rcs.StmtEval) {
	next := e.Ptr.Peek()
	if next == 0xdd || next == 0xed || next == 0xfd {
		e.Stmt.Op = "?fd"
		return
	}
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	if opcode == 0xcb {
		opFDCB(e)
		return
	}
	dasmTableFD[opcode](e)
}

func opCB(e rcs.StmtEval) {
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	dasmTableCB[opcode](e)
}

func opED(e rcs.StmtEval) {
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	dasmTableED[opcode](e)
}

func opFDCB(e rcs.StmtEval) {
	delta := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, delta)
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	dasmTableFDCB[opcode](e)
}

func opDDCB(e rcs.StmtEval) {
	delta := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, delta)
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	dasmTableDDCB[opcode](e)
}

func displace(value int, delta uint8) uint16 {
	sdelta := int8(delta)
	v := int(value) + int(sdelta)
	return uint16(v)
}


<|start_filename|>rcs/z80/instructions.go<|end_filename|>
package z80

import (
	"github.com/blackchip-org/retro-cs/rcs"
)

// add
func add(cpu *CPU, load0 rcs.Load8, load1 rcs.Load8) {
	out, fc, fh, fv := rcs.Add(load0(), load1(), false)

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if fv {
		cpu.F |= FlagV
	}
	if fc {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// add with carry
func adc(cpu *CPU, load0 rcs.Load8, load1 rcs.Load8) {
	out, fc, fh, fv := rcs.Add(load0(), load1(), cpu.F&FlagC != 0)

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if fv {
		cpu.F |= FlagV
	}
	if fc {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// 16-bit addition, without carry
func add16(cpu *CPU, store rcs.Store, load0 rcs.Load, load1 rcs.Load) {
	in0 := load0()
	in1 := load1()

	lo, fc, _, _ := rcs.Add(uint8(in0), uint8(in1), false)
	hi, fc, fh, _ := rcs.Add(uint8(in0>>8), uint8(in1>>8), fc)

	cpu.F &^= FlagH | FlagN | FlagC | Flag5 | Flag3

	if fh {
		cpu.F |= FlagH
	}
	if fc {
		cpu.F |= FlagC
	}
	if hi&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if hi&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(int(hi)<<8 | int(lo))
}

// 16-bit addition, with carry
func adc16(cpu *CPU, store rcs.Store, load0 rcs.Load, load1 rcs.Load) {
	in0 := load0()
	in1 := load1()

	lo, fc, _, _ := rcs.Add(uint8(in0), uint8(in1), cpu.F&FlagC != 0)
	hi, fc, fh, fv := rcs.Add(uint8(in0>>8), uint8(in1>>8), fc)

	cpu.F = 0
	if hi&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if lo == 0 && hi == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if fv {
		cpu.F |= FlagV
	}
	if fc {
		cpu.F |= FlagC
	}
	if hi&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if hi&(1<<3) != 0 {
		cpu.F |= Flag3
	}

	store(int(hi)<<8 | int(lo))
}

// bitwise logical and
func and(cpu *CPU, load rcs.Load8) {
	out := cpu.A & load()

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	cpu.F |= FlagH
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// test bit
func bit(cpu *CPU, n int, load rcs.Load8) {
	bit := uint(n)
	out := load()
	cpu.F &^= FlagS | FlagZ | FlagV | FlagN | Flag5 | Flag3
	if n == 7 && out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out&(1<<bit) == 0 {
		cpu.F |= FlagZ
	}
	cpu.F |= FlagH
	if out&(1<<bit) == 0 {
		cpu.F |= FlagV
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

// bit n,(ix+d)
func biti(cpu *CPU, n int, load rcs.Load8) {
	bit(cpu, n, load)

	// http://www.z80.info/zip/z80-documented.pdf
	// "This is where things start to get strange"
	cpu.F &^= Flag5 | Flag3
	iaddrh := cpu.iaddr >> 8
	if iaddrh&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if iaddrh&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

// call, conditional
func call(cpu *CPU, flag uint8, condition bool, load rcs.Load) {
	addr := load()
	if (cpu.F&flag != 0) == condition {
		cpu.SP -= 2
		cpu.mem.WriteLE(int(cpu.SP), cpu.PC())
		cpu.SetPC(addr)
	}
}

// call, always
func calla(cpu *CPU, load rcs.Load) {
	addr := load()
	cpu.SP -= 2
	cpu.mem.WriteLE(int(cpu.SP), cpu.PC())
	cpu.SetPC(addr)
}

// invert carry flag
func ccf(cpu *CPU) {
	// The H flag was tricky. Correct definition in the Z80 User Manual
	carryIn := cpu.F&FlagC != 0
	cpu.F &^= FlagH | FlagN | FlagC | Flag5 | Flag3
	if carryIn {
		cpu.F |= FlagH
	}
	if !carryIn {
		cpu.F |= FlagC
	}
	if cpu.A&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if cpu.A&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

// CP is a subtraction from A that doesn't update A, only the flags it would
// have set/reset if it really was subtracted.
//
// F5 and F3 are copied from the operand, not the result
func cp(cpu *CPU, load rcs.Load8) {
	a := cpu.A
	in := load()
	sub(cpu, cpu.loadA, func() uint8 { return in })
	cpu.F &^= Flag5 | Flag3
	if in&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if in&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = a
}

// invert accumulator, one's complement
func cpl(cpu *CPU) {
	out := ^cpu.A
	cpu.F &^= Flag5 | Flag3
	cpu.F |= FlagH | FlagN
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

func cpx(cpu *CPU, increment int) {
	carry := cpu.F&FlagC != 0
	out, _, fh, _ := rcs.Sub(cpu.A, cpu.loadIndHL(), false)

	cpu.storeHL(cpu.loadHL() + int(increment))
	cpu.storeBC(cpu.loadBC() - int(1))

	dresult := out
	if fh {
		//dresult--
	}
	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if cpu.loadBC() != 0 {
		cpu.F |= FlagV
	}
	cpu.F |= FlagN
	if carry {
		cpu.F |= FlagC
	}
	if dresult&(1<<1) != 0 { // yes, one
		cpu.F |= Flag5
	}
	if dresult&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

func cpxr(cpu *CPU, increment int) {
	cpx(cpu, increment)
	if cpu.B == 0 && cpu.C == 0 {
		return
	}
	if cpu.F&FlagZ != 0 {
		return
	}
	cpu.SetPC(cpu.PC() - 2)
}

// decimal adjust in a
// http://datasheets.chipdb.org/Zilog/Z80/z80-documented-0.90.pdf
//
// Note: some documentation omits that the adjustment is negative when the
// N flag is set.
//
// Eventually ported directly from the MAME source code.
func daa(cpu *CPU) {
	out := cpu.A
	carry := false
	half := false
	if cpu.F&FlagN != 0 {
		if cpu.F&FlagH != 0 || cpu.A&0xf > 9 {
			out -= 6
		}
		if cpu.F&FlagC != 0 || cpu.A > 0x99 {
			out -= 0x60
			carry = true
		}
		if cpu.F&FlagH != 0 && cpu.A&0xf <= 0x5 {
			half = true
		}
	} else {
		if cpu.F&FlagH != 0 || cpu.A&0xf > 9 {
			out += 6
		}
		if cpu.F&FlagC != 0 || cpu.A > 0x99 {
			out += 0x60
			carry = true
		}
		if cpu.A&0xf > 0x9 {
			half = true
		}
	}

	cpu.F &^= FlagS | FlagZ | FlagH | FlagP | FlagC | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if half {
		cpu.F |= FlagH
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	/*
		if cpu.A > 0x99 {
			cpu.F |= FlagC
		}
	*/
	if carry {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// decrement
func dec(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	out, _, fh, fv := rcs.Sub(in, 1, false)

	cpu.F &^= FlagS | FlagZ | FlagH | FlagV | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	// The Z80 user manual says that the overflow flag is set if the value
	// "was 0x80 before operation". This conflicts with the FUSE tests which
	// assume the overflow flag is set as if subtraction was done.
	if fv {
		cpu.F |= FlagV
	}
	cpu.F |= FlagN
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// decrement 16-bit, no flags altered
func dec16(cpu *CPU, store rcs.Store, load rcs.Load) {
	in0 := uint16(load())
	store(int(in0 - 1))
}

// disable interrupts
func di(cpu *CPU) {
	cpu.IFF1 = false
	cpu.IFF2 = false
}

// decrement B and jump if not zero
func djnz(cpu *CPU, load rcs.Load8) {
	delta := load()
	cpu.B--
	if cpu.B != 0 {
		cpu.SetPC(cpu.PC() + int(int8(delta)))
	}
}

// enable interrupts
func ei(cpu *CPU) {
	cpu.IFF1 = true
	cpu.IFF2 = true
}

// exchange
func ex(cpu *CPU, load0 rcs.Load, store0 rcs.Store, load1 rcs.Load, store1 rcs.Store) {
	in0 := load0()
	in1 := load1()
	store0(in1)
	store1(in0)
}

// EXX exchanges BC, DE, and HL with shadow registers with BC', DE', and HL'.
func exx(cpu *CPU) {
	ex(cpu, cpu.loadBC, cpu.storeBC, cpu.loadBC1, cpu.storeBC1)
	ex(cpu, cpu.loadDE, cpu.storeDE, cpu.loadDE1, cpu.storeDE1)
	ex(cpu, cpu.loadHL, cpu.storeHL, cpu.loadHL1, cpu.storeHL1)
}

// halt
func halt(cpu *CPU) {
	cpu.Halt = true
}

// interrupt mode set
func im(cpu *CPU, mode int) {
	cpu.IM = uint8(mode)
}

// port in
func in(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	out := load()

	cpu.F &^= FlagS | FlagZ | FlagH | FlagV | FlagN | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// increment
func inc(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	out, _, fh, fv := rcs.Add(in, 1, false)

	cpu.F &^= FlagS | FlagZ | FlagH | FlagV | FlagN | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	// The Z80 user manual says that the overflow flag is set if the value
	// "was 0x80 before operation". This conflicts with the FUSE tests which
	// assume the overflow flag is set as if subtraction was done.
	if fv {
		cpu.F |= FlagV
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// increment 16-bit, no flags altered
func inc16(cpu *CPU, store rcs.Store, load rcs.Load) {
	in0 := uint16(load())
	store(int(in0 + 1))
}

// port in, blocked
func inx(cpu *CPU, increment int) {
	in := cpu.inIndC()
	cpu.B--

	// https://github.com/mamedev/mame/blob/master/src/devices/device/proc/z80/z80.cpp
	// I was unable to figure this out by reading all the conflicting
	// documentation for these "undefined" flags
	t := uint16(cpu.C+uint8(increment)) + uint16(in)
	p := uint8(t&0x07) ^ cpu.B // parity check
	halfAndCarry := t&0x100 != 0

	cpu.F = 0
	if cpu.B&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if cpu.B == 0 {
		cpu.F |= FlagZ
	}
	if halfAndCarry {
		cpu.F |= FlagH
	}
	if rcs.Parity(p) {
		cpu.F |= FlagP
	}
	if in&(1<<7) != 0 {
		cpu.F |= FlagN
	}
	if halfAndCarry {
		cpu.F |= FlagC
	}
	if cpu.B&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if cpu.B&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.storeIndHL(in)
	ihl := (int(cpu.H)<<8 | int(cpu.L)) + increment
	cpu.H, cpu.L = uint8(ihl>>8), uint8(ihl)
}

// port in, blocked, repeat
func inxr(cpu *CPU, increment int) {
	inx(cpu, increment)
	for cpu.B != 0 {
		cpu.refreshR()
		cpu.refreshR()
		inx(cpu, increment)
	}
}

// jump absolute, conditional
func jp(cpu *CPU, flag uint8, condition bool, load rcs.Load) {
	addr := load()
	if (cpu.F&flag != 0) == condition {
		cpu.SetPC(addr)
	}
}

// jump absolute, always
func jpa(cpu *CPU, load rcs.Load) {
	cpu.SetPC(load())
}

// jump relative, conditional
func jr(cpu *CPU, flag uint8, condition bool, load rcs.Load8) {
	delta := int(int8(load()))
	flagSet := cpu.F&flag != 0
	if flagSet == condition {
		cpu.SetPC(cpu.PC() + delta)
	}
}

// jump relative, always
func jra(cpu *CPU, load rcs.Load8) {
	delta := load()
	cpu.SetPC(cpu.PC() + int(int8(delta)))
}

// load
func ld(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	store(load())
}

// ld a, i or ld a, r
func ldair(cpu *CPU, load rcs.Load8) {
	out := load()

	cpu.F &^= FlagS | FlagZ | FlagH | FlagV | FlagN | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if cpu.IFF2 {
		cpu.F |= FlagV
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// load, 16-bit
func ld16(cpu *CPU, store rcs.Store, load rcs.Load) {
	store(load())
}

func ldx(cpu *CPU, increment int) {
	source := int(cpu.H)<<8 | int(cpu.L)
	target := int(cpu.D)<<8 | int(cpu.E)
	v := cpu.mem.Read(source)
	cpu.mem.Write(target, v)

	isource := source + increment
	itarget := target + increment

	cpu.H, cpu.L = uint8(isource>>8), uint8(isource)
	cpu.D, cpu.E = uint8(itarget>>8), uint8(itarget)

	counter := int(cpu.B)<<8 | int(cpu.C)
	counter--
	cpu.B, cpu.C = uint8(counter>>8), uint8(counter)

	cpu.F &^= FlagH | FlagV | FlagN | Flag5 | Flag3
	if counter != 0 {
		cpu.F |= FlagV
	}
	if (v+cpu.A)&(1<<1) != 0 { // yes, bit one
		cpu.F |= Flag5
	}
	if (v+cpu.A)&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

func ldxr(cpu *CPU, increment int) {
	ldx(cpu, increment)
	for cpu.B != 0 || cpu.C != 0 {
		cpu.refreshR()
		cpu.refreshR()
		ldx(cpu, increment)
	}
}

// no operation
func nop() {}

// negate accumulator
func neg(cpu *CPU) {
	sub(cpu, func() uint8 { return 0 }, cpu.loadA)
}

// bitwise logical or
func or(cpu *CPU, load rcs.Load8) {
	out := cpu.A | load()

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

func outx(cpu *CPU, increment int) {
	in := cpu.mem.Read(int(cpu.H)<<8 | int(cpu.L))
	cpu.B--
	ihl := (int(cpu.H)<<8 | int(cpu.L)) + increment
	cpu.H, cpu.L = uint8(ihl>>8), uint8(ihl)

	// https://github.com/mamedev/mame/blob/master/src/devices/device/proc/z80/z80.cpp
	// I was unable to figure this out by reading all the conflicting
	// documentation for these "undefined" flags
	t := uint16(cpu.L) + uint16(in)
	p := uint8(t&0x07) ^ cpu.B // parity check
	halfAndCarry := t&0x100 != 0

	cpu.F = 0
	if cpu.B&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if cpu.B == 0 {
		cpu.F |= FlagZ
	}
	if halfAndCarry {
		cpu.F |= FlagH
	}
	if rcs.Parity(p) {
		cpu.F |= FlagP
	}
	if in&(1<<7) != 0 {
		cpu.F |= FlagN
	}
	if halfAndCarry {
		cpu.F |= FlagC
	}
	if cpu.B&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if cpu.B&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.Ports.Write(int(cpu.C), in)
}

// port out, blocked, repeat
func outxr(cpu *CPU, increment int) {
	outx(cpu, increment)
	for cpu.B != 0 {
		cpu.refreshR()
		cpu.refreshR()
		outx(cpu, increment)
	}
}

// Copies the two bytes from (SP) into the operand, then increases SP by 2.
func pop(cpu *CPU, store rcs.Store) {
	store(cpu.mem.ReadLE(int(cpu.SP)))
	cpu.SP += 2
}

// Decrements the SP by 2 then copies the operand into (SP)
func push(cpu *CPU, load rcs.Load) {
	cpu.SP -= 2
	cpu.mem.WriteLE(int(cpu.SP), load())
}

// reset bit
func res(cpu *CPU, n int, store rcs.Store8, load rcs.Load8) {
	bit := uint(n)
	store(load() &^ (1 << bit))
}

// return, conditional
func ret(cpu *CPU, flag uint8, value bool) {
	if (cpu.F&flag != 0) == value {
		reta(cpu)
	}
}

// return, always
func reta(cpu *CPU) {
	cpu.SetPC(cpu.mem.ReadLE(int(cpu.SP)))
	cpu.SP += 2
}

// return from interrupt
func reti(cpu *CPU) {
	cpu.SetPC(cpu.mem.ReadLE(int(cpu.SP)))
	cpu.SP += 2
}

// return from non-maskable interrupt
func retn(cpu *CPU) {
	cpu.IFF1 = cpu.IFF2
	cpu.SetPC(cpu.mem.ReadLE(int(cpu.SP)))
	cpu.SP += 2
}

// rotate left
func rl(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<7) != 0
	out := in << 1
	if cpu.F&FlagC != 0 {
		out++
	}

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// rotate accumulator left
func rla(cpu *CPU) {
	carryOut := cpu.A&(1<<7) != 0
	out := cpu.A << 1
	if cpu.F&FlagC != 0 {
		out++
	}

	cpu.F &^= FlagH | FlagN | FlagC | Flag5 | Flag3
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// rotate accumulator left with carry
func rlca(cpu *CPU) {
	carryOut := cpu.A&(1<<7) != 0
	out := cpu.A << 1
	if carryOut {
		out++
	}

	cpu.F &^= FlagH | FlagN | FlagC | Flag5 | Flag3
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// rotate left with carry
func rlc(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<7) != 0
	out := in << 1
	if carryOut {
		out++
	}

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

func rld(cpu *CPU) {
	addr := int(cpu.H)<<8 | int(cpu.L)
	ahi, alo := cpu.A>>4, cpu.A&0x0f
	readv := cpu.mem.Read(addr)
	memhi, memlo := readv>>4, readv&0x0f

	cpu.A = ahi<<4 | memhi
	memval := memlo<<4 | alo
	cpu.mem.Write(addr, memval)

	out := cpu.A
	cpu.F &^= FlagS | FlagZ | FlagH | FlagV | FlagN | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if cpu.A&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if cpu.A&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

// rotate right
func rr(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&1 != 0
	out := in >> 1
	if cpu.F&FlagC != 0 {
		out |= (1 << 7)
	}

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// rotate accumulator right
func rra(cpu *CPU) {
	carryOut := cpu.A&1 != 0
	out := cpu.A >> 1
	if cpu.F&FlagC != 0 {
		out |= (1 << 7)
	}

	cpu.F &^= FlagH | FlagN | FlagC | Flag5 | Flag3
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// rotate right
func rrc(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&1 != 0
	out := in >> 1
	if carryOut {
		out |= (1 << 7)
	}

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}

	store(out)
}

// rotate accumulator right with carry
func rrca(cpu *CPU) {
	carryOut := cpu.A&1 != 0
	out := cpu.A >> 1
	if carryOut {
		out |= (1 << 7)
	}

	cpu.F &^= FlagH | FlagN | FlagC | Flag5 | Flag3
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

func rrd(cpu *CPU) {
	addr := int(cpu.H)<<8 | int(cpu.L)
	ahi, alo := cpu.A>>4, cpu.A&0x0f
	readv := cpu.mem.Read(addr)
	memhi, memlo := readv>>4, readv&0x0f

	cpu.A = ahi<<4 | memlo
	memval := alo<<4 | memhi
	cpu.mem.Write(addr, memval)

	out := cpu.A
	cpu.F &^= FlagS | FlagZ | FlagH | FlagV | FlagN | Flag5 | Flag3
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if cpu.A&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if cpu.A&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

// reset
func rst(cpu *CPU, y int) {
	cpu.SP -= 2
	cpu.mem.WriteLE(int(cpu.SP), cpu.PC())
	cpu.SetPC(y * 8)
}

// set carry flag
func scf(cpu *CPU) {
	cpu.F &^= FlagH | FlagN | Flag5 | Flag3
	cpu.F |= FlagC
	if cpu.A&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if cpu.A&(1<<3) != 0 {
		cpu.F |= Flag3
	}
}

// set bit
func set(cpu *CPU, n int, store rcs.Store8, load rcs.Load8) {
	bit := uint(n)
	store(load() | (1 << bit))
}

// shift left, arithemtic
func sla(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<7) != 0
	out := in << 1

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagV
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// shift right, arithemtic
func sra(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&1 != 0
	bit7 := in&(1<<7) != 0
	out := in >> 1
	if bit7 {
		out |= 1 << 7
	}

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagV
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// undocumented: shift left, logical
func sll(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<7) != 0
	out := in<<1 + 1

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagV
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// shift right, logical
func srl(cpu *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&1 != 0
	out := in >> 1

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagV
	}
	if carryOut {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(out)
}

// subtract
func sub(cpu *CPU, load0 rcs.Load8, load1 rcs.Load8) {
	out, fc, fh, fv := rcs.Sub(load0(), load1(), false)

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if fv {
		cpu.F |= FlagV
	}
	cpu.F |= FlagN
	if fc {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// subtract with carry
func sbc(cpu *CPU, load0 rcs.Load8, load1 rcs.Load8) {
	out, fc, fh, fv := rcs.Sub(load0(), load1(), cpu.F&FlagC != 0)

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if fv {
		cpu.F |= FlagV
	}
	cpu.F |= FlagN
	if fc {
		cpu.F |= FlagC
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}

// subtract 16-bit with carry
func sbc16(cpu *CPU, store rcs.Store, load0 rcs.Load, load1 rcs.Load) {
	in0 := load0()
	in1 := load1()

	lo, fc, _, _ := rcs.Sub(uint8(in0), uint8(in1), cpu.F&FlagC != 0)
	hi, fc, fh, fv := rcs.Sub(uint8(in0>>8), uint8(in1>>8), fc)

	cpu.F = 0
	if hi&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if hi == 0 && lo == 0 {
		cpu.F |= FlagZ
	}
	if fh {
		cpu.F |= FlagH
	}
	if fv {
		cpu.F |= FlagV
	}
	cpu.F |= FlagN
	if fc {
		cpu.F |= FlagC
	}
	if hi&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if hi&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	store(int(hi)<<8 | int(lo))
}

// bitwise logical exclusive or
func xor(cpu *CPU, load rcs.Load8) {
	out := cpu.A ^ load()

	cpu.F = 0
	if out&(1<<7) != 0 {
		cpu.F |= FlagS
	}
	if out == 0 {
		cpu.F |= FlagZ
	}
	if rcs.Parity(out) {
		cpu.F |= FlagP
	}
	if out&(1<<5) != 0 {
		cpu.F |= Flag5
	}
	if out&(1<<3) != 0 {
		cpu.F |= Flag3
	}
	cpu.A = out
}


<|start_filename|>rcs/mach.go<|end_filename|>
package rcs

import (
	"fmt"
	"log"
	"os"
	"time"
	"unsafe"

	"github.com/veandco/go-sdl2/img"
	"github.com/veandco/go-sdl2/sdl"
)

type Status int

const (
	Pause Status = iota
	Run
	Break
)

const (
	vblank   = time.Duration(16670 * time.Microsecond)
	perJiffy = 20000 // instructions per jiffy
)

func (s Status) String() string {
	switch s {
	case Pause:
		return "pause"
	case Run:
		return "run"
	case Break:
		return "break"
	}
	return "???"
}

type MachCmd int

const (
	MachExport MachCmd = iota
	MachImport
	MachPause
	MachSnapshot
	MachStart
	MachTrace
	MachTraceAll
	MachQuit
)

type message struct {
	Cmd  MachCmd
	Args []interface{}
}

type MachEvent int

const (
	StatusEvent MachEvent = iota
	TraceEvent
	ErrorEvent
)

type Mach struct {
	Sys             interface{}
	Comps           []Component
	CharDecoders    map[string]CharDecoder
	DefaultEncoding string
	Ctx             SDLContext
	Screen          Screen
	VBlankFunc      func()
	QueueAudio      func() error
	Keyboard        func(*sdl.KeyboardEvent) error
	ButtonHandler   func(*sdl.ControllerButtonEvent) error
	AxisHandler     func(*sdl.ControllerAxisEvent) error

	CPU         map[string]CPU
	Proc        map[string]Proc
	Status      Status
	Callback    func(MachEvent, ...interface{})
	Breakpoints map[string]map[int]struct{}
	Executing   string // name of the CPU that is executing
	At          int    // address of the executing instruction

	stuck     map[string]bool
	tracing   map[string]bool
	scanLines *sdl.Texture
	init      bool
	quit      bool
	cmd       chan message
	snapT     *sdl.Texture
	snapS     *sdl.Surface
}

func (m *Mach) Init() error {
	if m.init {
		return nil
	}
	m.CPU = make(map[string]CPU)
	m.Proc = make(map[string]Proc)
	m.stuck = make(map[string]bool)
	m.tracing = make(map[string]bool)
	for _, comp := range m.Comps {
		switch v := comp.C.(type) {
		case CPU:
			m.CPU[comp.Name] = v
			m.tracing[comp.Name] = false
		case Proc:
			m.Proc[comp.Name] = v
		}
	}

	m.quit = false
	if m.CharDecoders == nil {
		m.CharDecoders = map[string]CharDecoder{
			"ascii": ASCIIDecoder,
		}
		m.DefaultEncoding = "ascii"
	}
	m.cmd = make(chan message, 10)

	m.Breakpoints = make(map[string]map[int]struct{})
	for name := range m.CPU {
		m.Breakpoints[name] = make(map[int]struct{})
	}
	if m.VBlankFunc == nil {
		m.VBlankFunc = func() {}
	}
	if m.Keyboard == nil {
		m.Keyboard = func(*sdl.KeyboardEvent) error { return nil }
	}
	if m.ButtonHandler == nil {
		m.ButtonHandler = func(*sdl.ControllerButtonEvent) error { return nil }
	}
	if m.AxisHandler == nil {
		m.AxisHandler = func(*sdl.ControllerAxisEvent) error { return nil }
	}

	if m.Ctx.Window != nil && m.Screen.W > 0 {
		r := m.Ctx.Renderer
		winx, winy := m.Ctx.Window.GetSize()
		FitInWindow(winx, winy, &m.Screen)
		drawW := m.Screen.W * m.Screen.Scale
		drawH := m.Screen.H * m.Screen.Scale
		if m.Screen.ScanLineH {
			scanLines, err := NewScanLinesH(r, drawW, drawH, 2)
			if err != nil {
				return err
			}
			m.scanLines = scanLines
		} else if m.Screen.ScanLineV {
			scanLines, err := NewScanLinesV(r, drawW, drawH, 2)
			if err != nil {
				return err
			}
			m.scanLines = scanLines
		}
	}
	m.init = true
	return nil
}

func (m *Mach) Run() error {
	if err := m.Init(); err != nil {
		return err
	}
	ticker := time.NewTicker(vblank)
	panicked := true
	defer func() {
		if panicked {
			m.reportCrash()
		}
	}()
	for {
		select {
		case c := <-m.cmd:
			m.handleCommand(c)
		case <-ticker.C:
			m.jiffy()
		}
		if m.quit {
			break
		}
	}
	panicked = false
	return nil
}

func (m *Mach) Command(cmd MachCmd, args ...interface{}) {
	m.cmd <- message{Cmd: cmd, Args: args}
}

func (m *Mach) jiffy() {
	if m.Status == Run {
		m.execute()
	}
	if m.QueueAudio != nil && m.Ctx.AudioSpec.Freq != 0 {
		if err := m.QueueAudio(); err != nil {
			m.event(ErrorEvent, err)
		}
	}
	if m.Ctx.Renderer != nil && m.Screen.W > 0 {
		m.render()
	} else {
		time.Sleep(10 * time.Millisecond)
	}
	m.sdl()
	if m.Status == Run {
		m.VBlankFunc()
	}
}

func (m *Mach) execute() {
	for t := 0; t < perJiffy; t++ {
		for name, cpu := range m.CPU {
			m.Executing = name
			m.At = cpu.PC() + cpu.Offset()
			if m.tracing[name] && !m.stuck[name] {
				m.event(TraceEvent, name, cpu.PC())
			}
			cpu.Next()
			// if the program counter didn't change, it is either stuck
			// in an infinite loop or not advancing due to a halt-like
			// instruction
			m.stuck[name] = m.At == cpu.PC()
			// at a breakpoint? only honor it if the processor is not stuck.
			// when at a halt-like instruction, this causes a break once
			// instead of each time.
			addr := cpu.PC() + cpu.Offset()
			if _, yes := m.Breakpoints[name][addr]; yes && !m.stuck[name] {
				m.setStatus(Break)
				return
			}
		}
		m.Executing = ""
		m.At = 0
		for _, proc := range m.Proc {
			proc.Next()
		}
	}
}

func (m *Mach) render() error {
	r := m.Ctx.Renderer
	if err := m.Screen.Draw(r); err != nil {
		return err
	}
	dest := sdl.Rect{
		X: m.Screen.X,
		Y: m.Screen.Y,
		W: m.Screen.W * m.Screen.Scale,
		H: m.Screen.H * m.Screen.Scale,
	}
	m.renderToTarget(&dest)
	r.Present()
	return nil
}

func (m *Mach) renderToTarget(dest *sdl.Rect) {
	r := m.Ctx.Renderer
	r.Copy(m.Screen.Texture, nil, dest)
	if m.scanLines != nil {
		r.Copy(m.scanLines, nil, dest)
	}
}

func (m *Mach) sdl() {
	for event := sdl.PollEvent(); event != nil; event = sdl.PollEvent() {
		switch e := event.(type) {
		case *sdl.QuitEvent:
			m.quit = true
		case *sdl.KeyboardEvent:
			if e.Keysym.Sym == sdl.K_ESCAPE {
				m.quit = true
			} else {
				m.Keyboard(e)
			}
		case *sdl.ControllerDeviceEvent:
			id := e.Which
			switch e.GetType() {
			case sdl.CONTROLLERDEVICEREMOVED:
				c := m.Ctx.GameControllers[id]
				log.Printf("(-) controller %v: %v\n", id, c.Name())
				c.Close()
				m.Ctx.GameControllers[id] = nil
			case sdl.CONTROLLERDEVICEADDED:
				c := sdl.GameControllerOpen(int(id))
				log.Printf("(+) controller %v: %v\n", id, c.Name())
				m.Ctx.GameControllers[id] = c
			case sdl.CONTROLLERDEVICEREMAPPED:
				panic("game controller was remapped")
			}
		case *sdl.ControllerButtonEvent:
			m.ButtonHandler(e)
		}
	}
}

func (m *Mach) handleCommand(msg message) {
	switch msg.Cmd {
	case MachExport:
		m.cmdExport(msg.Args...)
	case MachImport:
		m.cmdImport(msg.Args...)
	case MachPause:
		m.setStatus(Pause)
	case MachSnapshot:
		m.cmdSnapshot(msg.Args...)
	case MachStart:
		m.setStatus(Run)
	case MachTrace:
		m.cmdTrace(msg.Args...)
	case MachTraceAll:
		m.cmdTraceAll(msg.Args...)
	case MachQuit:
		m.quit = true
	default:
		m.event(ErrorEvent, fmt.Errorf("unknown command: %v", msg.Cmd))
	}
}

func (m *Mach) cmdExport(args ...interface{}) {
	sys, ok := m.Sys.(Saver)
	if !ok {
		m.event(ErrorEvent, "exporting is not supported")
		return
	}
	filename := args[0].(string)
	out, err := os.Create(filename)
	if err != nil {
		m.event(ErrorEvent, fmt.Sprintf("unable toe xport: %v", err))
		return
	}
	enc := NewEncoder(out)
	sys.Save(enc)
	if enc.Err != nil {
		m.event(ErrorEvent, fmt.Sprintf("unable to export: %v", enc.Err))
		return
	}
}

func (m *Mach) cmdImport(args ...interface{}) {
	sys, ok := m.Sys.(Loader)
	if !ok {
		m.event(ErrorEvent, "importing is not supported")
		return
	}
	filename := args[0].(string)
	in, err := os.Open(filename)
	if err != nil {
		m.event(ErrorEvent, fmt.Sprintf("unable to import: %v", err))
		return
	}
	dec := NewDecoder(in)
	sys.Load(dec)
	if dec.Err != nil {
		m.event(ErrorEvent, fmt.Sprintf("unable to import: %v", dec.Err))
		return
	}
}

func (m *Mach) cmdSnapshot(args ...interface{}) {
	filename := args[0].(string)
	if m.Screen.Texture == nil {
		m.event(ErrorEvent, "no screen to snapshot")
		return
	}

	r := m.Ctx.Renderer
	w := m.Screen.W * m.Screen.Scale
	h := m.Screen.H * m.Screen.Scale
	if m.snapT == nil {
		tex, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888, sdl.TEXTUREACCESS_TARGET, w, h)
		if err != nil {
			m.event(ErrorEvent, err.Error())
			return
		}
		surf, err := sdl.CreateRGBSurface(0, w, h, 32, 0, 0, 0, 0)
		if err != nil {
			m.event(ErrorEvent, err.Error())
			return
		}
		m.snapT = tex
		m.snapS = surf
	}
	r.SetRenderTarget(m.snapT)
	m.renderToTarget(nil)

	r.SetRenderTarget(m.snapT)
	pixels := m.snapS.Pixels()
	ptr := unsafe.Pointer(&pixels[0])
	r.ReadPixels(nil, m.snapS.Format.Format, ptr, int(m.snapS.Pitch))

	if err := img.SavePNG(m.snapS, filename); err != nil {
		m.event(ErrorEvent, fmt.Sprintf("unable to save snapshot: %v", err))
		return
	}
}

func (m *Mach) cmdTrace(args ...interface{}) {
	name := args[0].(string)
	if len(args) == 1 {
		m.tracing[name] = !m.tracing[name]
		return
	}
	v, ok := args[1].(bool)
	if !ok {
		m.event(ErrorEvent, fmt.Sprintf("invalid trace mode: %v", args[0]))
		return
	}
	m.tracing[name] = v
}

func (m *Mach) cmdTraceAll(args ...interface{}) {
	v, ok := args[0].(bool)
	if !ok {
		m.event(ErrorEvent, fmt.Sprintf("invalid trace mode: %v", args[0]))
		return
	}
	fmt.Printf("trace all: %v", v)
	for name := range m.tracing {
		m.tracing[name] = v
	}
}

func (m *Mach) event(evt MachEvent, args ...interface{}) {
	if m.Callback == nil {
		return
	}
	m.Callback(evt, args...)
}

func (m *Mach) setStatus(s Status) {
	m.Status = s
	m.event(StatusEvent, s)
}

func (m *Mach) reportCrash() {
	for n, c := range m.CPU {
		fmt.Printf("[panic: %v]\n", n)
		fmt.Println(c)
	}
	fmt.Printf("BANK: %02x\n", m.CPU["cpu"].Memory().Bank())
}


<|start_filename|>system/c64/memory.go<|end_filename|>
package c64

import (
	"github.com/blackchip-org/retro-cs/rcs"
)

func newMemory(ram []uint8, io []uint8, roms map[string][]byte) *rcs.Memory {
	basic := roms["basic"]
	kernal := roms["kernal"]
	chargen := roms["chargen"]

	iomem := rcs.NewMemory(1, 0x1000)
	iomem.MapRAM(0, io)

	var cartlo, carthi []uint8
	cart, ok := roms["cart"]
	if ok {
		cartlo = cart[0x0000:0x2000]
		carthi = cart[0x2000:0x4000]
	}

	mem := rcs.NewMemory(32, 0x10000)

	// https://www.c64-wiki.com/wiki/Bank_Switching
	mem.SetBank(31)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0xa000, basic)
	mem.Map(0xd000, iomem)
	mem.MapROM(0xe000, kernal)

	for _, bank := range []int{30, 14} {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
		mem.Map(0xd000, iomem)
		mem.MapROM(0xe000, kernal)
	}

	for _, bank := range []int{29, 13} {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
		mem.Map(0xd000, iomem)
	}

	for _, bank := range []int{28, 24} {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
	}

	mem.SetBank(27)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0xa000, basic)
	mem.MapROM(0xd000, chargen)
	mem.MapROM(0xe000, kernal)

	for _, bank := range []int{26, 10} {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
		mem.MapROM(0xd000, chargen)
		mem.MapROM(0xe000, kernal)
	}

	for _, bank := range []int{25, 9} {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
		mem.MapROM(0xd000, chargen)
	}

	for bank := 23; bank >= 16; bank-- {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
		for addr := 0x1000; addr <= 0x7fff; addr++ {
			mem.Unmap(addr)
		}
		mem.MapROM(0x8000, cartlo)
		for addr := 0xa000; addr <= 0xcfff; addr++ {
			mem.Unmap(addr)
		}
		mem.Map(0xd000, iomem)
		mem.MapROM(0xe000, carthi)
	}

	mem.SetBank(15)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0x8000, cartlo)
	mem.MapROM(0xa000, basic)
	mem.Map(0xd000, iomem)
	mem.MapROM(0xe000, kernal)

	for _, bank := range []int{12, 8, 4, 0} {
		mem.SetBank(bank)
		mem.MapRAM(0x0000, ram)
	}

	mem.SetBank(11)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0x8000, cartlo)
	mem.MapROM(0xa000, basic)
	mem.MapROM(0xd000, chargen)
	mem.MapROM(0xe000, kernal)

	mem.SetBank(7)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0x8000, cartlo)
	mem.MapROM(0xa000, carthi)
	mem.Map(0xd000, iomem)
	mem.MapROM(0xe000, kernal)

	mem.SetBank(6)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0xa000, carthi)
	mem.Map(0xd000, iomem)
	mem.MapROM(0xe000, kernal)

	mem.SetBank(5)
	mem.MapRAM(0x0000, ram)
	mem.Map(0xd000, iomem)

	mem.SetBank(3)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0x8000, cartlo)
	mem.MapROM(0xa000, carthi)
	mem.MapROM(0xd000, chargen)
	mem.MapROM(0xe000, kernal)

	mem.SetBank(2)
	mem.MapRAM(0x0000, ram)
	mem.MapROM(0xa000, carthi)
	mem.MapROM(0xd000, chargen)
	mem.MapROM(0xe000, kernal)

	mem.SetBank(1)
	mem.MapRAM(0x0000, ram)

	return mem
}


<|start_filename|>system/galaga/video.go<|end_filename|>
package galaga

import (
	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/blackchip-org/retro-cs/rcs/namco"
	"github.com/veandco/go-sdl2/sdl"
)

func newVideo(r *sdl.Renderer, data namco.Data) (*namco.Video, error) {
	return namco.NewVideo(r, VideoConfig, data)
}

var VideoConfig = namco.Config{
	TileLayout: namco.SheetLayout{
		TileW:        8,
		TileH:        8,
		TextureW:     8 * 16,
		TextureH:     8 * 8,
		PixelLayout:  tilePixels,
		PixelReader:  pixelReader,
		BytesPerCell: 16,
	},
	SpriteLayout: namco.SheetLayout{
		TileW:        16,
		TileH:        16,
		TextureW:     16 * 16,
		TextureH:     16 * 8,
		PixelLayout:  spritePixels,
		PixelReader:  pixelReader,
		BytesPerCell: 64,
	},
	PaletteEntries: 32,
	PaletteColors:  8,
	Hack:           true,
}

var tilePixels = [][]int{
	[]int{63, 59, 55, 51, 47, 43, 39, 35},
	[]int{62, 58, 54, 50, 46, 42, 38, 34},
	[]int{61, 57, 53, 49, 45, 41, 37, 33},
	[]int{60, 56, 52, 48, 44, 40, 36, 32},

	[]int{31, 27, 23, 19, 15, 11, 7, 3},
	[]int{30, 26, 22, 18, 14, 10, 6, 2},
	[]int{29, 25, 21, 17, 13, 9, 5, 1},
	[]int{28, 24, 20, 16, 12, 8, 4, 0},
}

var spritePixels = [][]int{
	[]int{159, 155, 151, 147, 143, 139, 135, 131, 31, 27, 23, 19, 15, 11, 7, 3},
	[]int{158, 154, 150, 146, 142, 138, 134, 130, 30, 26, 22, 18, 14, 10, 6, 2},
	[]int{157, 153, 149, 145, 141, 137, 133, 129, 29, 25, 21, 17, 13, 9, 5, 1},
	[]int{156, 152, 148, 144, 140, 136, 132, 128, 28, 24, 20, 16, 12, 8, 4, 0},

	[]int{191, 187, 183, 179, 175, 171, 167, 163, 63, 59, 55, 51, 47, 43, 39, 35},
	[]int{190, 186, 182, 178, 174, 170, 166, 162, 62, 58, 54, 50, 46, 42, 38, 34},
	[]int{189, 185, 181, 177, 173, 169, 165, 161, 61, 57, 53, 49, 45, 41, 37, 33},
	[]int{188, 184, 180, 176, 172, 168, 164, 160, 60, 56, 52, 48, 44, 40, 36, 32},

	[]int{223, 219, 215, 211, 207, 203, 199, 195, 95, 91, 87, 83, 79, 75, 71, 67},
	[]int{222, 218, 214, 210, 206, 202, 198, 194, 94, 90, 86, 82, 78, 74, 70, 66},
	[]int{221, 217, 213, 209, 205, 201, 197, 193, 93, 89, 85, 81, 77, 73, 69, 65},
	[]int{220, 216, 212, 208, 204, 200, 196, 192, 92, 88, 84, 80, 76, 72, 68, 64},

	[]int{255, 251, 247, 243, 239, 235, 231, 227, 127, 123, 119, 115, 111, 107, 103, 99},
	[]int{254, 250, 246, 242, 238, 234, 230, 226, 126, 122, 118, 114, 110, 106, 102, 98},
	[]int{253, 249, 245, 241, 237, 233, 229, 225, 125, 121, 117, 113, 109, 105, 101, 97},
	[]int{252, 248, 244, 240, 236, 232, 228, 224, 124, 120, 116, 112, 108, 104, 100, 96},
}

func pixelReader(d []byte, base int, pixel int) uint8 {
	addr := base + (pixel / 4)
	offset := pixel % 4
	return rcs.BitPlane4(d[addr], offset)
}


<|start_filename|>tools/icmp/z80emu/icmp-z80emu.c<|end_filename|>
#include <stdio.h>

#include "z80emu.h"
#include "z80user.h"

typedef struct ix {
    Z80_STATE	    state;
	unsigned char	memory[1 << 16];
} ix;

void cpd() {
    struct ix context;
    for (int a = 0; a <= 0xff; a++) {
        for (int _hl = 0; _hl <= 0xff; _hl++) {
            for (int f = 0; f <= 1; f++) {
                for (int c = 2; c <= 2; c++) {
                    Z80Reset(&context.state);
                    context.memory[0x1234] = _hl;
                    context.state.registers.byte[Z80_B] = 0;
                    context.state.registers.byte[Z80_C] = c;
                    context.state.registers.byte[Z80_H] = 0x12;
                    context.state.registers.byte[Z80_L] = 0x34;
                    context.state.registers.byte[Z80_A] = a;
                    context.state.registers.byte[Z80_F] = f;
                    context.memory[0] = 0xed;
                    context.memory[1] = 0xb9;
                    Z80Emulate(&context.state, 0, &context);
                    printf("a:%02x _hl:%02x c:%02x f:%02x => b:%02x c:%02x f:%02x\n", a, _hl, c, f,
                        context.state.registers.byte[Z80_B],
                        context.state.registers.byte[Z80_C],
                        context.state.registers.byte[Z80_F]
                    );
                }
            }
        }
    }
}

void af() {
    struct ix context;
    for (int f = 0; f <= 0xff; f++) {
        for (int a = 0; a <= 0xff; a++) {
            Z80Reset(&context.state);
            context.memory[0] = 0x17;
            context.state.registers.byte[Z80_A] = a;
            context.state.registers.byte[Z80_F] = f;
            Z80Emulate(&context.state, 0, &context);
            printf("a:%02x f:%02x => a:%02x f:%02x\n", a, f,
                context.state.registers.byte[Z80_A],
                context.state.registers.byte[Z80_F]
            );
        }
    }
}

void SystemCall (ZEXTEST *zextest) {}

int main() {
    af();
}


<|start_filename|>rcs/namco/video.go<|end_filename|>
package namco

import (
	"fmt"
	"image/color"

	"github.com/blackchip-org/retro-cs/rcs"
	"github.com/veandco/go-sdl2/sdl"
)

type Data struct {
	Palettes []uint8
	Colors   []uint8
	Tiles    []uint8
	Sprites  []uint8
}

type Config struct {
	TileLayout     SheetLayout
	SpriteLayout   SheetLayout
	PaletteEntries int
	PaletteColors  int
	Hack           bool
}

const (
	W = int32(224)
	H = int32(288)
)

type SpriteCoord struct {
	X uint8
	Y uint8
}

type Video struct {
	SpriteCoords   []SpriteCoord
	SpriteInfo     []uint8
	SpritePalettes []uint8
	TileMemory     []uint8
	ColorMemory    []uint8

	Texture  *sdl.Texture
	config   Config
	tiles    [64]rcs.TileSheet
	sprites  [64]rcs.TileSheet
	colors   []color.RGBA
	palettes [][]color.RGBA
}

func NewVideo(r *sdl.Renderer, config Config, data Data) (*Video, error) {
	tex, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888, sdl.TEXTUREACCESS_TARGET, W, H)
	if err != nil {
		return nil, err
	}
	colors := ColorTable(config, data.Colors)
	palettes := PaletteTable(config, data.Palettes, colors)

	var tiles, sprites [64]rcs.TileSheet
	for pal := 0; pal < config.PaletteEntries; pal++ {
		t, err := NewTileSheet(r, data.Tiles, config.TileLayout, palettes[pal])
		if err != nil {
			return nil, err
		}
		tiles[pal] = t

		s, err := NewTileSheet(r, data.Sprites, config.SpriteLayout, palettes[pal])
		if err != nil {
			return nil, err
		}
		sprites[pal] = s
	}

	v := &Video{
		Texture:        tex,
		SpriteCoords:   make([]SpriteCoord, 8, 8),
		SpriteInfo:     make([]uint8, 8, 8),
		SpritePalettes: make([]uint8, 8, 8),
		TileMemory:     make([]uint8, 1024, 1024),
		ColorMemory:    make([]uint8, 1024, 1024),
		config:         config,
		tiles:          tiles,
		sprites:        sprites,
		colors:         colors,
		palettes:       palettes,
	}
	return v, nil
}

func (v *Video) Draw(r *sdl.Renderer) error {
	r.SetRenderTarget(v.Texture)
	r.SetDrawColorArray(0, 0, 0, 0xff)
	r.Clear()
	v.drawTiles(r)
	v.drawSprites(r)
	r.SetRenderTarget(nil)
	return nil
}

func (v *Video) drawTiles(r *sdl.Renderer) error {
	layout := v.config.TileLayout
	tileW := layout.TileW
	rowTiles := layout.TextureW / tileW

	// Render tiles
	for ty := 0; ty < 36; ty++ {
		for tx := 0; tx < 28; tx++ {
			var addr int
			if ty == 0 || ty == 1 {
				addr = 0x3dd + (ty * 0x20) - tx
			} else if ty == 34 || ty == 35 {
				addr = 0x01d + ((ty - 34) * 0x20) - tx
			} else {
				addr = 0x3a0 + (ty - 2) - (tx * 0x20)
			}

			tileN := int32(v.TileMemory[addr])
			sheetX := (tileN % rowTiles) * tileW
			sheetY := (tileN / rowTiles) * tileW
			src := sdl.Rect{
				X: int32(sheetX),
				Y: int32(sheetY),
				W: int32(layout.TileW),
				H: int32(layout.TileH),
			}
			screenX := int32(tx) * 8
			screenY := int32(ty) * 8
			dest := sdl.Rect{
				X: screenX,
				Y: screenY,
				W: layout.TileW,
				H: layout.TileH,
			}

			// Only 64 palettes, strip out the higher bits
			pal := v.ColorMemory[addr] & 0x3f
			r.Copy(v.tiles[pal].Texture, &src, &dest)
		}
	}
	return nil
}

func (v *Video) drawSprites(r *sdl.Renderer) error {
	// FIXME: Galaga testing
	if v.config.Hack {
		return nil
	}
	layout := v.config.SpriteLayout
	spriteW := layout.TileW
	spriteH := layout.TileH
	rowTiles := layout.TextureW / spriteW

	for s := 7; s >= 0; s-- {
		coordX := int32(v.SpriteCoords[s].X)
		coordY := int32(v.SpriteCoords[s].Y)
		info := v.SpriteInfo[s]
		spriteN := int32(info >> 2)
		flip := sdl.FLIP_NONE
		if info&0x02 > 0 {
			flip |= sdl.FLIP_HORIZONTAL
		}
		if info&0x01 > 0 {
			flip |= sdl.FLIP_VERTICAL
		}

		// do not render of off screen
		if coordX <= 30 || coordX >= 240 {
			continue
		}
		screenX := (W - coordX + spriteW)
		screenY := (H - coordY - spriteH)
		sheetX := (spriteN % rowTiles) * spriteW
		sheetY := (spriteN / rowTiles) * spriteH
		src := sdl.Rect{
			X: int32(sheetX),
			Y: int32(sheetY),
			W: spriteW,
			H: spriteH,
		}
		dest := sdl.Rect{
			X: screenX,
			Y: screenY,
			W: spriteW,
			H: spriteH,
		}
		// Only 64 palettes, strip out the higher bits
		pal := v.SpritePalettes[s] & 0x3f
		r.CopyEx(v.sprites[pal].Texture, &src, &dest, 0, nil, flip)
	}
	return nil
}

func (v *Video) Save(enc *rcs.Encoder) {
	enc.Encode(v.TileMemory)
	enc.Encode(v.ColorMemory)
}

func (v *Video) Load(enc *rcs.Decoder) {
	enc.Decode(&v.TileMemory)
	enc.Decode(&v.ColorMemory)
}

var ViewerPalette = []color.RGBA{
	color.RGBA{0, 0, 0, 0},
	color.RGBA{128, 128, 128, 255},
	color.RGBA{192, 192, 192, 255},
	color.RGBA{255, 255, 255, 255},
}

type SheetLayout struct {
	TextureW     int32
	TextureH     int32
	TileW        int32
	TileH        int32
	BytesPerCell int32
	PixelLayout  [][]int
	PixelReader  func([]byte, int, int) uint8
}

func NewTileSheet(r *sdl.Renderer, d []byte, l SheetLayout, pal []color.RGBA) (rcs.TileSheet, error) {
	t, err := r.CreateTexture(sdl.PIXELFORMAT_RGBA8888,
		sdl.TEXTUREACCESS_TARGET, l.TextureW, l.TextureH)
	if err != nil {
		return rcs.TileSheet{}, fmt.Errorf("unable to create sheet: %v", err)
	}
	r.SetRenderTarget(t)

	rowTiles := l.TextureW / l.TileW
	for i := int32(0); i < l.TextureW*l.TextureH; i++ {
		targetX := i % l.TextureW
		targetY := i / l.TextureW
		tileX := targetX / l.TileW
		offsetX := targetX % l.TileW
		tileY := targetY / l.TileH
		offsetY := targetY % l.TileH
		tileN := tileX + tileY*rowTiles
		baseAddr := int(tileN * l.BytesPerCell)
		pixelN := int(l.PixelLayout[offsetY][offsetX])
		value := l.PixelReader(d, baseAddr, pixelN)

		c := pal[value]
		r.SetDrawColor(c.R, c.G, c.B, c.A)
		r.DrawPoint(targetX, targetY)
	}
	t.SetBlendMode(sdl.BLENDMODE_BLEND)
	r.SetRenderTarget(nil)

	return rcs.TileSheet{
		TextureW: l.TextureW,
		TextureH: l.TextureH,
		TileW:    l.TileW,
		TileH:    l.TileH,
		Texture:  t,
	}, nil
}

func ColorTable(config Config, data []uint8) []color.RGBA {
	// FIXME: Galaga testing
	if config.Hack {
		return []color.RGBA{}
	}
	colors := make([]color.RGBA, 16, 16)
	for addr := 0; addr < 16; addr++ {
		r, g, b := uint8(0), uint8(0), uint8(0)
		c := data[addr]
		for bit := uint8(0); bit < 8; bit++ {
			if c&(1<<bit) != 0 {
				r += colorWeights[bit][0]
				g += colorWeights[bit][1]
				b += colorWeights[bit][2]
			}
		}
		alpha := uint8(0xff)
		// Color 0 is actually transparent
		if addr == 0 {
			alpha = 0x00
		}
		colors[addr] = color.RGBA{r, g, b, alpha}
	}
	return colors
}

func PaletteTable(config Config, data []uint8, colors []color.RGBA) [][]color.RGBA {
	palettes := make([][]color.RGBA, config.PaletteEntries, config.PaletteEntries)
	for pal := 0; pal < config.PaletteEntries; pal++ {
		// FIXME: Galaga testing
		if config.Hack {
			palettes[pal] = ViewerPalette
			continue
		}
		addr := pal * config.PaletteColors
		entry := make([]color.RGBA, config.PaletteColors, config.PaletteColors)
		for i := 0; i < config.PaletteColors; i++ {
			ref := data[addr+i] & 0x0f
			entry[i] = colors[ref]
		}
		palettes[pal] = entry
	}
	return palettes
}

var colorWeights = [][]uint8{
	[]uint8{0x21, 0x00, 0x00},
	[]uint8{0x47, 0x00, 0x00},
	[]uint8{0x97, 0x00, 0x00},
	[]uint8{0x00, 0x21, 0x00},
	[]uint8{0x00, 0x47, 0x00},
	[]uint8{0x00, 0x97, 0x00},
	[]uint8{0x00, 0x00, 0x51},
	[]uint8{0x00, 0x00, 0xae},
}


<|start_filename|>system/c128/mmu.go<|end_filename|>
package c128

import (
	"log"

	"github.com/blackchip-org/retro-cs/rcs"
)

var mmuRegs = []string{"A", "B", "C", "D"}

// MMU is the memory management unit
type MMU struct {
	Mem *rcs.Memory // configuration register is the bank number
	LCR [4]uint8    // load configuration register
	PCR [4]uint8    // pre-configuration register
	// FIXME: What is this for?
	// Mode uint8

	WatchCR  rcs.FlagRW
	WatchLCR rcs.FlagRW
	WatchPCR rcs.FlagRW
}

func NewMMU(mem *rcs.Memory) *MMU {
	return &MMU{
		Mem: mem,
	}
}

func (m *MMU) ReadCR() uint8 {
	v := uint8(m.Mem.Bank())
	if m.WatchCR.R {
		log.Printf("0x%02x <= mmu:cr", v)
	}
	return v
}

func (m *MMU) WriteCR(v uint8) {
	if m.WatchCR.W {
		log.Printf("mmu:cr <= 0x%02x", v)
	}
	m.Mem.SetBank(int(v))
}

func (m *MMU) ReadLCR(i int) uint8 {
	v := m.LCR[i]
	if m.WatchLCR.R {
		log.Printf("0x%02x <= mmu:lcr-%v", v, mmuRegs[i])
	}
	return v
}

func (m *MMU) WriteLCR(i int, v uint8) {
	if m.WatchLCR.W {
		log.Printf("mmu:lcr-%v <= 0x%02x", mmuRegs[i], v)
	}
	m.LCR[i] = v
	// FIXME: something is wrong here
	//m.StoreCR(m.LCR[i])
}

func (m *MMU) ReadPCR(i int) uint8 {
	v := m.PCR[i]
	if m.WatchPCR.R {
		log.Printf("0x%02x <= mmu:pcr-%v", v, mmuRegs[i])
	}
	return v
}

func (m *MMU) WritePCR(i int, v uint8) {
	if m.WatchPCR.W {
		log.Printf("mmu:pcr-%v <= 0x%02x", mmuRegs[i], v)
	}
	m.PCR[i] = v
}


<|start_filename|>rcs/m6502/dasm_test.go<|end_filename|>
package m6502

import (
	"fmt"
	"testing"

	"github.com/blackchip-org/retro-cs/mock"
	"github.com/blackchip-org/retro-cs/rcs"
)

func TestDisassembler(t *testing.T) {
	var b = func(values ...int) []uint8 {
		bytes := make([]uint8, 0)
		for _, v := range values {
			bytes = append(bytes, uint8(v))
		}
		return bytes
	}

	var disassemblerTests = []struct {
		bytes []uint8
		want  string
	}{
		{b(0x02, 0x00, 0x00), "$1234:  02        ?02"},

		{b(0x69, 0x56, 0x00), "$1234:  69 56     adc #$56"},
		{b(0x65, 0x56, 0x00), "$1234:  65 56     adc $56"},
		{b(0x75, 0x56, 0x00), "$1234:  75 56     adc $56,x"},
		{b(0x6d, 0x78, 0x56), "$1234:  6d 78 56  adc $5678"},
		{b(0x7d, 0x78, 0x56), "$1234:  7d 78 56  adc $5678,x"},
		{b(0x79, 0x78, 0x56), "$1234:  79 78 56  adc $5678,y"},
		{b(0x61, 0x56, 0x00), "$1234:  61 56     adc ($56,x)"},
		{b(0x71, 0x56, 0x00), "$1234:  71 56     adc ($56),y"},

		{b(0x29, 0x56, 0x00), "$1234:  29 56     and #$56"},
		{b(0x25, 0x56, 0x00), "$1234:  25 56     and $56"},
		{b(0x35, 0x56, 0x00), "$1234:  35 56     and $56,x"},
		{b(0x2d, 0x78, 0x56), "$1234:  2d 78 56  and $5678"},
		{b(0x3d, 0x78, 0x56), "$1234:  3d 78 56  and $5678,x"},
		{b(0x39, 0x78, 0x56), "$1234:  39 78 56  and $5678,y"},
		{b(0x21, 0x56, 0x00), "$1234:  21 56     and ($56,x)"},
		{b(0x31, 0x56, 0x00), "$1234:  31 56     and ($56),y"},

		{b(0x0a, 0x56, 0x00), "$1234:  0a        asl a"},
		{b(0x06, 0x56, 0x00), "$1234:  06 56     asl $56"},
		{b(0x16, 0x56, 0x00), "$1234:  16 56     asl $56,x"},
		{b(0x0e, 0x78, 0x56), "$1234:  0e 78 56  asl $5678"},
		{b(0x1e, 0x78, 0x56), "$1234:  1e 78 56  asl $5678,x"},

		{b(0x24, 0x56, 0x00), "$1234:  24 56     bit $56"},
		{b(0x2c, 0x78, 0x56), "$1234:  2c 78 56  bit $5678"},

		{b(0x10, 0x0a, 0x00), "$1234:  10 0a     bpl $1240"},
		{b(0x10, 0xfa, 0x00), "$1234:  10 fa     bpl $1230"},
		{b(0x30, 0x0a, 0x00), "$1234:  30 0a     bmi $1240"},
		{b(0x50, 0x0a, 0x00), "$1234:  50 0a     bvc $1240"},
		{b(0x70, 0x0a, 0x00), "$1234:  70 0a     bvs $1240"},
		{b(0x90, 0x0a, 0x00), "$1234:  90 0a     bcc $1240"},
		{b(0xb0, 0x0a, 0x00), "$1234:  b0 0a     bcs $1240"},
		{b(0xd0, 0x0a, 0x00), "$1234:  d0 0a     bne $1240"},
		{b(0xf0, 0x0a, 0x00), "$1234:  f0 0a     beq $1240"},

		{b(0x00, 0x00, 0x00), "$1234:  00        brk"},

		{b(0xc9, 0x56, 0x00), "$1234:  c9 56     cmp #$56"},
		{b(0xc5, 0x56, 0x00), "$1234:  c5 56     cmp $56"},
		{b(0xd5, 0x56, 0x00), "$1234:  d5 56     cmp $56,x"},
		{b(0xcd, 0x78, 0x56), "$1234:  cd 78 56  cmp $5678"},
		{b(0xdd, 0x78, 0x56), "$1234:  dd 78 56  cmp $5678,x"},
		{b(0xd9, 0x78, 0x56), "$1234:  d9 78 56  cmp $5678,y"},
		{b(0xc1, 0x56, 0x00), "$1234:  c1 56     cmp ($56,x)"},
		{b(0xd1, 0x56, 0x00), "$1234:  d1 56     cmp ($56),y"},

		{b(0xe0, 0x56, 0x00), "$1234:  e0 56     cpx #$56"},
		{b(0xe4, 0x56, 0x00), "$1234:  e4 56     cpx $56"},
		{b(0xec, 0x78, 0x56), "$1234:  ec 78 56  cpx $5678"},

		{b(0xc0, 0x56, 0x00), "$1234:  c0 56     cpy #$56"},
		{b(0xc4, 0x56, 0x00), "$1234:  c4 56     cpy $56"},
		{b(0xcc, 0x78, 0x56), "$1234:  cc 78 56  cpy $5678"},

		{b(0xc6, 0x56, 0x00), "$1234:  c6 56     dec $56"},
		{b(0xd6, 0x56, 0x00), "$1234:  d6 56     dec $56,x"},
		{b(0xce, 0x78, 0x56), "$1234:  ce 78 56  dec $5678"},
		{b(0xde, 0x78, 0x56), "$1234:  de 78 56  dec $5678,x"},

		{b(0x49, 0x56, 0x00), "$1234:  49 56     eor #$56"},
		{b(0x45, 0x56, 0x00), "$1234:  45 56     eor $56"},
		{b(0x55, 0x56, 0x00), "$1234:  55 56     eor $56,x"},
		{b(0x4d, 0x78, 0x56), "$1234:  4d 78 56  eor $5678"},
		{b(0x5d, 0x78, 0x56), "$1234:  5d 78 56  eor $5678,x"},
		{b(0x59, 0x78, 0x56), "$1234:  59 78 56  eor $5678,y"},
		{b(0x41, 0x56, 0x00), "$1234:  41 56     eor ($56,x)"},
		{b(0x51, 0x56, 0x00), "$1234:  51 56     eor ($56),y"},

		{b(0x18, 0x00, 0x00), "$1234:  18        clc"},
		{b(0x38, 0x00, 0x00), "$1234:  38        sec"},
		{b(0x58, 0x00, 0x00), "$1234:  58        cli"},
		{b(0x78, 0x00, 0x00), "$1234:  78        sei"},
		{b(0xb8, 0x00, 0x00), "$1234:  b8        clv"},
		{b(0xd8, 0x00, 0x00), "$1234:  d8        cld"},
		{b(0xf8, 0x00, 0x00), "$1234:  f8        sed"},

		{b(0xe6, 0x56, 0x00), "$1234:  e6 56     inc $56"},
		{b(0xf6, 0x56, 0x00), "$1234:  f6 56     inc $56,x"},
		{b(0xee, 0x78, 0x56), "$1234:  ee 78 56  inc $5678"},
		{b(0xfe, 0x78, 0x56), "$1234:  fe 78 56  inc $5678,x"},

		{b(0x4c, 0x78, 0x56), "$1234:  4c 78 56  jmp $5678"},
		{b(0x6c, 0x78, 0x56), "$1234:  6c 78 56  jmp ($5678)"},

		{b(0x20, 0x78, 0x56), "$1234:  20 78 56  jsr $5678"},

		{b(0xa9, 0x56, 0x00), "$1234:  a9 56     lda #$56"},
		{b(0xa5, 0x56, 0x00), "$1234:  a5 56     lda $56"},
		{b(0xb5, 0x56, 0x00), "$1234:  b5 56     lda $56,x"},
		{b(0xad, 0x78, 0x56), "$1234:  ad 78 56  lda $5678"},
		{b(0xbd, 0x78, 0x56), "$1234:  bd 78 56  lda $5678,x"},
		{b(0xb9, 0x78, 0x56), "$1234:  b9 78 56  lda $5678,y"},
		{b(0xa1, 0x56, 0x00), "$1234:  a1 56     lda ($56,x)"},
		{b(0xb1, 0x56, 0x00), "$1234:  b1 56     lda ($56),y"},

		{b(0xa2, 0x56, 0x00), "$1234:  a2 56     ldx #$56"},
		{b(0xa6, 0x56, 0x00), "$1234:  a6 56     ldx $56"},
		{b(0xb6, 0x56, 0x00), "$1234:  b6 56     ldx $56,y"},
		{b(0xae, 0x78, 0x56), "$1234:  ae 78 56  ldx $5678"},
		{b(0xbe, 0x78, 0x56), "$1234:  be 78 56  ldx $5678,y"},

		{b(0xa0, 0x56, 0x00), "$1234:  a0 56     ldy #$56"},
		{b(0xa4, 0x56, 0x00), "$1234:  a4 56     ldy $56"},
		{b(0xb4, 0x56, 0x00), "$1234:  b4 56     ldy $56,x"},
		{b(0xac, 0x78, 0x56), "$1234:  ac 78 56  ldy $5678"},
		{b(0xbc, 0x78, 0x56), "$1234:  bc 78 56  ldy $5678,x"},

		{b(0x4a, 0x56, 0x00), "$1234:  4a        lsr a"},
		{b(0x46, 0x56, 0x00), "$1234:  46 56     lsr $56"},
		{b(0x56, 0x56, 0x00), "$1234:  56 56     lsr $56,x"},
		{b(0x4e, 0x78, 0x56), "$1234:  4e 78 56  lsr $5678"},
		{b(0x5e, 0x78, 0x56), "$1234:  5e 78 56  lsr $5678,x"},

		{b(0xea, 0x00, 0x00), "$1234:  ea        nop"},

		{b(0x09, 0x56, 0x00), "$1234:  09 56     ora #$56"},
		{b(0x05, 0x56, 0x00), "$1234:  05 56     ora $56"},
		{b(0x15, 0x56, 0x00), "$1234:  15 56     ora $56,x"},
		{b(0x0d, 0x78, 0x56), "$1234:  0d 78 56  ora $5678"},
		{b(0x1d, 0x78, 0x56), "$1234:  1d 78 56  ora $5678,x"},
		{b(0x19, 0x78, 0x56), "$1234:  19 78 56  ora $5678,y"},
		{b(0x01, 0x56, 0x00), "$1234:  01 56     ora ($56,x)"},
		{b(0x11, 0x56, 0x00), "$1234:  11 56     ora ($56),y"},

		{b(0xaa, 0x00, 0x00), "$1234:  aa        tax"},
		{b(0x8a, 0x00, 0x00), "$1234:  8a        txa"},
		{b(0xca, 0x00, 0x00), "$1234:  ca        dex"},
		{b(0xe8, 0x00, 0x00), "$1234:  e8        inx"},
		{b(0xa8, 0x00, 0x00), "$1234:  a8        tay"},
		{b(0x98, 0x00, 0x00), "$1234:  98        tya"},
		{b(0x88, 0x00, 0x00), "$1234:  88        dey"},
		{b(0xc8, 0x00, 0x00), "$1234:  c8        iny"},

		{b(0x2a, 0x56, 0x00), "$1234:  2a        rol a"},
		{b(0x26, 0x56, 0x00), "$1234:  26 56     rol $56"},
		{b(0x36, 0x56, 0x00), "$1234:  36 56     rol $56,x"},
		{b(0x2e, 0x78, 0x56), "$1234:  2e 78 56  rol $5678"},
		{b(0x3e, 0x78, 0x56), "$1234:  3e 78 56  rol $5678,x"},

		{b(0x6a, 0x56, 0x00), "$1234:  6a        ror a"},
		{b(0x66, 0x56, 0x00), "$1234:  66 56     ror $56"},
		{b(0x76, 0x56, 0x00), "$1234:  76 56     ror $56,x"},
		{b(0x6e, 0x78, 0x56), "$1234:  6e 78 56  ror $5678"},
		{b(0x7e, 0x78, 0x56), "$1234:  7e 78 56  ror $5678,x"},

		{b(0x40, 0x00, 0x00), "$1234:  40        rti"},

		{b(0x60, 0x00, 0x00), "$1234:  60        rts"},

		{b(0xe9, 0x56, 0x00), "$1234:  e9 56     sbc #$56"},
		{b(0xe5, 0x56, 0x00), "$1234:  e5 56     sbc $56"},
		{b(0xf5, 0x56, 0x00), "$1234:  f5 56     sbc $56,x"},
		{b(0xed, 0x78, 0x56), "$1234:  ed 78 56  sbc $5678"},
		{b(0xfd, 0x78, 0x56), "$1234:  fd 78 56  sbc $5678,x"},
		{b(0xf9, 0x78, 0x56), "$1234:  f9 78 56  sbc $5678,y"},
		{b(0xe1, 0x56, 0x00), "$1234:  e1 56     sbc ($56,x)"},
		{b(0xf1, 0x56, 0x00), "$1234:  f1 56     sbc ($56),y"},

		{b(0x85, 0x56, 0x00), "$1234:  85 56     sta $56"},
		{b(0x95, 0x56, 0x00), "$1234:  95 56     sta $56,x"},
		{b(0x8d, 0x78, 0x56), "$1234:  8d 78 56  sta $5678"},
		{b(0x9d, 0x78, 0x56), "$1234:  9d 78 56  sta $5678,x"},
		{b(0x99, 0x78, 0x56), "$1234:  99 78 56  sta $5678,y"},
		{b(0x81, 0x56, 0x00), "$1234:  81 56     sta ($56,x)"},
		{b(0x91, 0x56, 0x00), "$1234:  91 56     sta ($56),y"},

		{b(0x9a, 0x00, 0x00), "$1234:  9a        txs"},
		{b(0xba, 0x00, 0x00), "$1234:  ba        tsx"},
		{b(0x48, 0x00, 0x00), "$1234:  48        pha"},
		{b(0x68, 0x00, 0x00), "$1234:  68        pla"},
		{b(0x08, 0x00, 0x00), "$1234:  08        php"},
		{b(0x28, 0x00, 0x00), "$1234:  28        plp"},

		{b(0x86, 0x56, 0x00), "$1234:  86 56     stx $56"},
		{b(0x96, 0x56, 0x00), "$1234:  96 56     stx $56,y"},
		{b(0x8e, 0x78, 0x56), "$1234:  8e 78 56  stx $5678"},

		{b(0x84, 0x56, 0x00), "$1234:  84 56     sty $56"},
		{b(0x94, 0x56, 0x00), "$1234:  94 56     sty $56,x"},
		{b(0x8c, 0x78, 0x56), "$1234:  8c 78 56  sty $5678"},
	}

	for _, test := range disassemblerTests {
		testName := fmt.Sprintf("opcode $%02x", test.bytes[0])
		t.Run(testName, func(t *testing.T) {
			mock.ResetMemory()
			mem := mock.TestMemory
			mem.WriteN(0x1234, test.bytes...)
			d := rcs.NewDisassembler(mem, Reader, Formatter())
			d.SetPC(0x1234)
			have := d.Next()
			if test.want != have {
				t.Errorf("\n want: %v \n have: %v", test.want, have)
			}
		})
	}
}


<|start_filename|>Dockerfile<|end_filename|>
FROM ubuntu:bionic

RUN apt-get update
RUN apt-get install -y \
    golang \
    git \
    libsdl2-dev \
    libsdl2-image-dev \
    libsdl2-mixer-dev \
    libsdl2-ttf-dev \
    libsdl2-gfx-dev

RUN mkdir -p /root/go/src/github.com/blackchip-org/retro-cs
RUN go get github.com/veandco/go-sdl2/sdl
RUN go get github.com/chzyer/readline


<|start_filename|>rcs/cbm/petscii/petscii.go<|end_filename|>
package petscii

const (
	White      = 0x05
	Red        = 0x1c
	Green      = 0x1e
	Blue       = 0x1f
	Orange     = 0x81
	Black      = 0x90
	Brown      = 0x95
	LightRed   = 0x96
	DarkGray   = 0x97
	MediumGray = 0x98
	LightGreen = 0x99
	LightBlue  = 0x9a
	LightGray  = 0x9b
	Purple     = 0x9c
	Yellow     = 0x9e
	Cyan       = 0x9f
)

// Decoder converts byte values to PETSCII equivilents in Unicode.
var Decoder = func(code uint8) (rune, bool) {
	ch, printable := tableUnshifted[code]
	return ch, printable
}

// ShiftedDecoder converts byte values to PETSCII equivilents in Unicode.
var ShiftedDecoder = func(code uint8) (rune, bool) {
	ch, printable := tableShifted[code]
	return ch, printable
}


<|start_filename|>rcs/m6502/reader.go<|end_filename|>
package m6502

import (
	"fmt"
	"strings"

	"github.com/blackchip-org/retro-cs/rcs"
)

func Reader(e rcs.StmtEval) {
	e.Stmt.Addr = e.Ptr.Addr()
	opcode := e.Ptr.Fetch()
	e.Stmt.Bytes = append(e.Stmt.Bytes, opcode)
	op, ok := dasmTable[opcode]
	if !ok {
		e.Stmt.Op = fmt.Sprintf("?%02x", opcode)
		return
	}

	len := operandLengths[op.mode]
	operand := 0
	switch len {
	case 1:
		operand = int(e.Ptr.Fetch())
		e.Stmt.Bytes = append(e.Stmt.Bytes, uint8(operand))
	case 2:
		operand = e.Ptr.FetchLE()
		e.Stmt.Bytes = append(e.Stmt.Bytes, uint8(operand), uint8(operand>>8))
	}
	e.Stmt.Op = op.inst + formatOp(op, operand, e.Stmt.Addr)
	return
}

func Formatter() rcs.CodeFormatter {
	options := rcs.FormatOptions{
		BytesFormat: "%-8s",
	}
	return func(s rcs.Stmt) string {
		return rcs.FormatStmt(s, options)
	}
}

func formatOp(op op, operand int, addr int) string {
	format, ok := operandFormats[op.mode]
	result := ""
	if ok {
		// If this is a branch instruction, the value of the operand needs to be
		// added to the current addresss. Add two as it is relative after consuming
		// the instruction
		value := operand
		if op.mode == relative {
			value8 := int8(value)
			if value8 >= 0 {
				value = addr + int(value8) + 2
			} else {
				value = addr - int(value8*-1) + 2
			}
		}
		// If the format does not contain a formatting directive, just use as is.
		// For example: "asl a"
		if strings.Contains(format, "%") {
			result = " " + fmt.Sprintf(format, value)
		} else {
			result = " " + format
		}
	}
	return result
}


<|start_filename|>gen/z80/fuse/fuse.go<|end_filename|>
package main

//go:generate go run .
//go:generate go fmt ../../../rcs/z80/fuse_in_test.go
//go:generate go fmt ../../../rcs/z80/fuse_expected_test.go

import (
	"bufio"
	"bytes"
	"fmt"
	"html/template"
	"io/ioutil"
	"os"
	"path/filepath"
	"regexp"
	"strconv"
	"strings"

	"github.com/blackchip-org/retro-cs/config"
)

var (
	root      = filepath.Join("..", "..", "..")
	targetDir = filepath.Join(root, "rcs", "z80")
	sourceDir = filepath.Join(config.ResourceDir(), "ext", "fuse")
)

var out bytes.Buffer
var whitespace = regexp.MustCompile(" +")

func main() {
	out.WriteString("// Code generated by gen/z80/fuse/fuse.go. DO NOT EDIT.\n\n")
	out.WriteString("package z80\n")
	out.WriteString("var fuseIn = []fuseTest{\n")
	loadTests()
	out.WriteString("}\n\n")

	fileIn := filepath.Join(targetDir, "fuse_in_test.go")
	err := ioutil.WriteFile(fileIn, out.Bytes(), 0644)
	if err != nil {
		fatal("unable to save file", err)
	}
	out.Reset()

	out.WriteString("// Code generated by gen/z80/fuse/fuse.go. DO NOT EDIT.\n\n")
	out.WriteString("package z80\n")
	out.WriteString("var fuseExpected = map[string]fuseTest{\n")
	loadExpected()
	out.WriteString("}\n")

	fileExpected := filepath.Join(targetDir, "fuse_expected_test.go")
	err = ioutil.WriteFile(fileExpected, out.Bytes(), 0644)
	if err != nil {
		fatal("unable to save file", err)
	}

}

func loadTests() {
	testsIn := filepath.Join(sourceDir, "tests.in")
	file, err := os.Open(testsIn)
	if err != nil {
		fatal("unable to open", err)
	}
	defer file.Close()

	scanner := bufio.NewScanner(file)
	for scanner.Scan() {
		line := scanner.Text()
		if line == "" {
			continue
		} else {
			name := line
			scanner.Scan()
			parseTest(name, scanner)
		}
	}
}

func loadExpected() {
	testsExp := filepath.Join(sourceDir, "tests.expected")
	file, err := os.Open(testsExp)
	if err != nil {
		fatal("unable to open", err)
	}
	defer file.Close()

	scanner := bufio.NewScanner(file)
	for scanner.Scan() {
		line := scanner.Text()
		if line == "" {
			continue
		} else {
			name := line
			out.WriteString("\"" + name + "\": ")
			line = ""
			scanner.Scan()
			parseTest(name, scanner)
		}
	}
}

func parseTest(name string, scanner *bufio.Scanner) {
	t := make(map[string]string)
	t["name"] = name

	// Scan for events (on expected results)
	portReadsMap := map[string][]string{}
	portWritesMap := map[string]string{}

	for {
		line := scanner.Text()
		// If the line does not start with a space, there are
		// no more events
		if !strings.HasPrefix(line, " ") {
			break
		}
		line = whitespace.ReplaceAllString(line, " ")
		f := strings.Fields(line)
		if f[1] == "PR" {
			addr := f[2][2:4]
			value := fmt.Sprintf("0x%v", f[3])
			values, ok := portReadsMap[addr]
			if !ok {
				portReadsMap[addr] = []string{"0x" + addr, value}
			} else {
				values = append(values, value)
				portReadsMap[addr] = values
			}
		} else if f[1] == "PW" {
			addr := f[2][2:4]
			value := f[3]
			portWritesMap[addr] = fmt.Sprintf(
				"[]int{0x%v, 0x%v},\n", addr, value)
		}
		scanner.Scan()
	}

	portWrites := ""
	for _, v := range portWritesMap {
		portWrites += v
	}

	portReads := ""
	for _, v := range portReadsMap {
		portReads += fmt.Sprintf("[]int{%v},\n", strings.Join(v, ","))
	}

	f1 := strings.Fields(scanner.Text())
	t["af"] = f1[0]
	t["bc"] = f1[1]
	t["de"] = f1[2]
	t["hl"] = f1[3]
	t["af1"] = f1[4]
	t["bc1"] = f1[5]
	t["de1"] = f1[6]
	t["hl1"] = f1[7]
	t["ix"] = f1[8]
	t["iy"] = f1[9]
	t["sp"] = f1[10]
	t["pc"] = f1[11]

	scanner.Scan()
	text2 := whitespace.ReplaceAllString(scanner.Text(), " ")
	f2 := strings.Fields(text2)
	t["i"] = f2[0]
	t["r"] = f2[1]
	t["iff1"] = f2[2]
	t["iff2"] = f2[3]
	t["im"] = f2[4]
	t["halt"] = f2[5]
	t["tstates"] = f2[6]

	t["memory"] = parseMemory(scanner)
	t["portReads"] = portReads
	t["portWrites"] = portWrites

	testTemplate.Execute(&out, t)
}

func parseMemory(scanner *bufio.Scanner) string {
	var tests bytes.Buffer
	for {
		scanner.Scan()
		line := strings.Fields(scanner.Text())
		if len(line) == 0 || line[0] == "-1" {
			break
		}
		addr, _ := strconv.ParseUint(line[0], 16, 16)
		for i, value := range line[1 : len(line)-1] {
			tests.WriteString(fmt.Sprintf("[]int{0x%04x, 0x%v},\n", int(addr)+i, value))
		}
	}
	return tests.String()
}

func fatal(message string, err error) {
	fmt.Printf("error: %v: %v\n", message, err)
	os.Exit(1)
}

var testTemplate = template.Must(template.New("").Parse(`fuseTest{
	name: "{{.name}}",
	af: 0x{{.af}},
	bc: 0x{{.bc}},
	de: 0x{{.de}},
	hl: 0x{{.hl}},
	af1: 0x{{.af1}},
	bc1: 0x{{.bc1}},
	de1: 0x{{.de1}},
	hl1: 0x{{.hl1}},
	ix: 0x{{.ix}},
	iy: 0x{{.iy}},
	sp: 0x{{.sp}},
	pc: 0x{{.pc}},
	i: 0x{{.i}},
	r: 0x{{.r}},
	iff1: {{.iff1}},
	iff2: {{.iff2}},
	im: {{.im}},
	halt: {{.halt}},
	tstates: {{.tstates}},
	memory: [][]int{
		{{.memory}}
	},
	portReads: [][]int{
		{{.portReads}}
	},
	portWrites: [][]int{
		{{.portWrites}}
	},
},
`))


<|start_filename|>rcs/z80/cpu_test.go<|end_filename|>
package z80

import (
	"testing"
)

func TestString(t *testing.T) {
	cpu := New(nil)
	cpu.A = 0x0a
	cpu.F = 0xff
	cpu.B = 0x0b
	cpu.C = 0x0c
	cpu.D = 0x0d
	cpu.E = 0x0e
	cpu.H = 0xf0
	cpu.L = 0x0f
	cpu.IXH = 0x12
	cpu.IXL = 0x34
	cpu.IYH = 0x56
	cpu.IYL = 0x78
	cpu.SP = 0xabcd
	cpu.I = 0xee
	cpu.R = 0xff

	cpu.A1 = 0xa0
	cpu.F1 = 0x88
	cpu.B1 = 0xb0
	cpu.C1 = 0xc0
	cpu.D1 = 0xd0
	cpu.E1 = 0xe0
	cpu.H1 = 0x0f
	cpu.L1 = 0xf0

	cpu.IFF1 = true
	cpu.IFF2 = true

	have := cpu.String()
	want := "" +
		" pc   af   bc   de   hl   ix   iy   sp   i  r\n" +
		"0000 0aff 0b0c 0d0e f00f 1234 5678 abcd  ee ff iff1\n" +
		"im 0 a088 b0c0 d0e0 0ff0      S Z 5 H 3 V N C  iff2\n"
	if have != want {
		t.Errorf("\n have: \n%v \n want: \n%v", have, want)
	}
}


<|start_filename|>system/galaga/roms.go<|end_filename|>
package galaga

import "github.com/blackchip-org/retro-cs/rcs"

var ROM = map[string][]rcs.ROM{
	"galaga": []rcs.ROM{
		rcs.NewROM("code1   ", "04m_g01.bin", "6907773db7c002ecde5e41853603d53387c5c7cd"),
		rcs.NewROM("code1   ", "04k_g02.bin", "666975aed5ce84f09794c54b550d64d95ab311f0"),
		rcs.NewROM("code1   ", "04j_g03.bin", "481f443aea3ed3504ec2f3a6bfcf3cd47e2f8f81"),
		rcs.NewROM("code1   ", "04h_g04.bin", "366cb0dbd31b787e64f88d182108b670d03b393e"),
		rcs.NewROM("code2   ", "04e_g05.bin", "d29b68d6aab3217fa2106b3507b9273ff3f927bf"),
		rcs.NewROM("code3   ", "04d_g06.bin", "d6cb439de0718826d1a0363c9d77de8740b18ecf"),
		rcs.NewROM("tiles   ", "07m_g08.bin", "62f1279a784ab2f8218c4137c7accda00e6a3490"),
		rcs.NewROM("sprites ", "07e_g10.bin", "e697c180178cabd1d32483c5d8889a40633f7857"),
		rcs.NewROM("sprites ", "07h_g09.bin", "c340ed8c25e0979629a9a1730edc762bd72d0cff"),
		rcs.NewROM("palettes", "5n.bin     ", "1a6dea13b4af155d9cb5b999a75d4f1eb9c71346"),
		rcs.NewROM("colors  ", "2n.bin     ", "7323084320bb61ae1530d916f5edd8835d4d2461"),
	},
}


<|start_filename|>rcs/m6502/instructions.go<|end_filename|>
package m6502

import (
	"github.com/blackchip-org/retro-cs/rcs"
)

// add with carry
func adc(cpu *CPU, load rcs.Load8) {
	if cpu.SR&FlagD != 0 {
		adcd(cpu, load)
		return
	}

	out, c, _, v := rcs.Add(cpu.A, load(), cpu.SR&FlagC != 0)
	cpu.SR &^= FlagN | FlagV | FlagZ | FlagC
	if out&(1<<7) != 0 {
		cpu.SR |= FlagN
	}
	if v {
		cpu.SR |= FlagV
	}
	if out == 0 {
		cpu.SR |= FlagZ
	}
	if c {
		cpu.SR |= FlagC
	}
	cpu.A = out
}

// add binary-coded decimal
func adcd(c *CPU, load rcs.Load8) {
	carry := 0
	if c.SR&FlagC != 0 {
		carry = 1
	}

	in0 := rcs.FromBCD(c.A)
	in1 := rcs.FromBCD(load())
	outn := uint16(in0) + uint16(in1) + uint16(carry)
	out := rcs.ToBCD(uint8(outn))

	c.SR &^= FlagC | FlagZ | FlagN
	if outn > 99 {
		c.SR |= FlagC
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	c.A = out
}

// logical and
func and(c *CPU, load rcs.Load8) {
	out := c.A & load()
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	c.A = out
}

// arithmetic shift left
func asl(c *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<7) != 0
	out := in << 1

	c.SR &^= FlagN | FlagZ | FlagC
	if carryOut {
		c.SR |= FlagC
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	store(out)
}

// test bits
func bit(c *CPU, load rcs.Load8) {
	in := load()

	if c.A&in == 0 {
		c.SR |= FlagZ
	} else {
		c.SR &^= FlagZ
	}

	if in&(1<<7) != 0 {
		c.SR |= FlagN
	} else {
		c.SR &^= FlagN
	}

	if in&(1<<6) != 0 {
		c.SR |= FlagV
	} else {
		c.SR &^= FlagV
	}
}

// branch instructions
func branch(c *CPU, do bool) {
	displacement := int8(c.fetch())
	if do {
		if displacement >= 0 {
			c.SetPC(c.PC() + int(displacement))
		} else {
			c.SetPC(c.PC() - int(displacement*-1))
		}
	}
}

// break
func brk(c *CPU) {
	if c.BreakFunc != nil {
		c.BreakFunc()
	} else {
		c.fetch()
		c.irqAck(true)
	}
}

// compare
func cmp(c *CPU, load0 rcs.Load8, load1 rcs.Load8) {
	// C set as if subtraction. Clear if 'borrow', otherwise set
	out := int16(load0()) - int16(load1())

	c.SR &^= FlagC | FlagN | FlagZ
	if out >= 0 {
		c.SR |= FlagC
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
}

// decrement
func dec(c *CPU, store rcs.Store8, load rcs.Load8) {
	out := load() - 1
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	store(out)
}

// exclusive or
func eor(c *CPU, load rcs.Load8) {
	out := c.A ^ load()
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	c.A = out
}

// increment
func inc(c *CPU, store rcs.Store8, load rcs.Load8) {
	out := load() + 1
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	store(out)
}

// jump
func jmp(c *CPU) {
	c.pc = uint16(c.fetch2() - 1)
}

// jump indirect
func jmpIndirect(c *CPU) {
	c.pc = uint16(c.mem.ReadLE(c.fetch2()) - 1)
}

// jump to subroutine
func jsr(c *CPU) {
	addr := uint16(c.fetch2())
	c.push2(c.pc)
	c.pc = addr - 1
}

// load
func ld(c *CPU, store rcs.Store8, load rcs.Load8) {
	out := load()
	store(out)
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
}

// logical shift right
func lsr(c *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<0) != 0
	out := in >> 1

	c.SR &^= FlagN | FlagZ | FlagC
	if carryOut {
		c.SR |= FlagC
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	store(out)
}

// logical or
func ora(c *CPU, load rcs.Load8) {
	out := c.A | load()
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	c.A = out
}

// push processor status
func php(c *CPU) {
	// https://wiki.nesdev.com/w/index.php/Status_flags
	c.push(c.SR | FlagB | Flag5)
}

// pull accumulator
func pla(c *CPU) {
	out := c.pull()
	c.SR &^= FlagN | FlagZ
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	c.A = out
}

// pull processor status
func plp(c *CPU) {
	sr := c.pull()
	// There is no break flag
	sr &^= FlagB
	c.SR = sr
}

// rotate left
func rol(c *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<7) != 0
	out := in << 1
	if c.SR&FlagC != 0 {
		out++
	}

	c.SR &^= FlagN | FlagZ | FlagC
	if carryOut {
		c.SR |= FlagC
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	store(out)
}

// rotate right
func ror(c *CPU, store rcs.Store8, load rcs.Load8) {
	in := load()
	carryOut := in&(1<<0) != 0
	out := in >> 1
	if c.SR&FlagC != 0 {
		out |= (1 << 7)
	}

	c.SR &^= FlagN | FlagZ | FlagC
	if carryOut {
		c.SR |= FlagC
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	store(out)
}

// return from interrupt
func rti(c *CPU) {
	// http://www.6502.org/tutorials/6502opcodes.html#RTI
	// Note that unlike RTS, the return address on the stack is the
	// actual address rather than the address-1.
	c.SR = c.pull()
	c.pc = c.pull2() - 1
}

// subtract with carry
func sbc(c *CPU, load rcs.Load8) {
	if c.SR&FlagD != 0 {
		sbcd(c, load)
		return
	}

	out, fc, _, fv := rcs.Sub(c.A, load(), c.SR&FlagC == 0) // carry clear on borrow
	c.SR &^= FlagN | FlagV | FlagZ | FlagC
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	if fv {
		c.SR |= FlagV
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	if !fc { // carry clear on borrow
		c.SR |= FlagC
	}
	c.A = out
}

// subtract, binary-coded decimal
func sbcd(c *CPU, load rcs.Load8) {
	borrow := 0
	if c.SR&FlagC == 0 {
		borrow = 1 // borrow on carry clear
	}

	in0 := rcs.FromBCD(c.A)
	in1 := rcs.FromBCD(load())
	outn := int16(in0) - int16(in1) - int16(borrow)
	carry := outn >= 0
	if outn < 0 {
		outn += 100
	}
	out := rcs.ToBCD(uint8(outn))

	c.SR &^= FlagC | FlagZ | FlagN
	if carry {
		c.SR |= FlagC
	}
	if out == 0 {
		c.SR |= FlagZ
	}
	if out&(1<<7) != 0 {
		c.SR |= FlagN
	}
	c.A = out
}

// store
func st(c *CPU, store rcs.Store8, load rcs.Load8) {
	store(load())
}
