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stringlengths 11
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stringlengths 211
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| ref
stringlengths 70
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|---|---|---|---|
Prob001_zero |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output zero
The module should always outputs a LOW.
|
module RefModule (
output zero
);
assign zero = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should 0");
repeat(20) @(posedge clk, negedge clk);
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_zero;
int errortime_zero;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic zero_ref;
logic zero_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,zero_ref,zero_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
RefModule good1 (
.zero(zero_ref) );
TopModule top_module1 (
.zero(zero_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_zero) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "zero", stats1.errors_zero, stats1.errortime_zero);
else $display("Hint: Output '%s' has no mismatches.", "zero");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { zero_ref } === ( { zero_ref } ^ { zero_dut } ^ { zero_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (zero_ref !== ( zero_ref ^ zero_dut ^ zero_ref ))
begin if (stats1.errors_zero == 0) stats1.errortime_zero = $time;
stats1.errors_zero = stats1.errors_zero+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob002_m2014_q4i |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output out
The module should always drive 0 (or logic low).
|
module RefModule (
output out
);
assign out = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
RefModule good1 (
.out(out_ref) );
TopModule top_module1 (
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob003_step_one |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output one
The module should always drive 1 (or logic high).
|
module RefModule (
output one
);
assign one = 1'b1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should be 1");
repeat(20) @(posedge clk, negedge clk);
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_one;
int errortime_one;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic one_ref;
logic one_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,one_ref,one_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
RefModule good1 (
.one(one_ref) );
TopModule top_module1 (
.one(one_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_one) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "one", stats1.errors_one, stats1.errortime_one);
else $display("Hint: Output '%s' has no mismatches.", "one");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { one_ref } === ( { one_ref } ^ { one_dut } ^ { one_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (one_ref !== ( one_ref ^ one_dut ^ one_ref ))
begin if (stats1.errors_one == 0) stats1.errortime_one = $time;
stats1.errors_one = stats1.errors_one+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob004_vector2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (32 bits)
- output out (32 bits)
The module should reverse the byte order of a 32-bit vector.
|
module RefModule (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [31:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Random inputs");
repeat(10) @(posedge clk, negedge clk)
in <= $random;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [31:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob005_notgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should implement a NOT gate.
|
module RefModule (
input in,
output out
);
assign out = ~in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 1'b0;
wavedrom_start("Inversion");
repeat(20) @(posedge clk)
in <= $random;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob006_vectorr |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output out (8 bits)
The module should reverse the bit ordering of the input port and write
the result to the output port.
|
module RefModule (
input [7:0] in,
output [7:0] out
);
assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) in <= 8'h1;
@(posedge clk) in <= 8'h2;
@(posedge clk) in <= 8'h4;
@(posedge clk) in <= 8'h8;
@(posedge clk) in <= 8'h80;
@(posedge clk) in <= 8'hc0;
@(posedge clk) in <= 8'he0;
@(posedge clk) in <= 8'hf0;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [7:0] out_ref;
logic [7:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob007_wire |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should behave like a wire.
|
module RefModule (
input in,
output out
);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should follow input");
repeat(20) @(posedge clk, negedge clk)
in <= $random;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob008_m2014_q4h |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should assign the output port to the same value as the input
port combinationally.
|
module RefModule (
input in,
output out
);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in = 0
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob009_popcount3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (3 bits)
- output out (2 bits)
The module should implement a "population count" circuit that counts the
number of '1's in the input vector.
|
module RefModule (
input [2:0] in,
output [1:0] out
);
assign out = in[0]+in[1]+in[2];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [2:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 7;
@(negedge clk);
wavedrom_start();
repeat(9) @(posedge clk) in <= in + 1'b1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] in;
logic [1:0] out_ref;
logic [1:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob010_mt2015_q4a |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x
- input y
- output z
The module should implement the boolean function z = (x^y) & x.
|
module RefModule (
input x,
input y,
output z
);
assign z = (x^y) & x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(101) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic y;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.x,
.y,
.z(z_ref) );
TopModule top_module1 (
.x,
.y,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob011_norgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement a NOR gate.
|
module RefModule (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("NOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob012_xnorgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement an XNOR gate.
|
module RefModule (
input a,
input b,
output out
);
assign out = ~(a^b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("XNOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob013_m2014_q4e |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- output out
The module should implement a 2-input NOR gate.
|
module RefModule (
input in1,
input in2,
output logic out
);
assign out = ~(in1 | in2);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in1;
logic in2;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in1,
.in2 );
RefModule good1 (
.in1,
.in2,
.out(out_ref) );
TopModule top_module1 (
.in1,
.in2,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob014_andgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement a 2-input AND gate.
|
module RefModule (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("AND gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob015_vector1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (16 bits)
- output out_hi ( 8 bits)
- output out_lo ( 8 bits)
The module should implement a combinational circuit that splits an input
half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.
|
module RefModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [15:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
in <= $random;
initial begin
wavedrom_start("Random inputs");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_hi;
int errortime_out_hi;
int errors_out_lo;
int errortime_out_lo;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [15:0] in;
logic [7:0] out_hi_ref;
logic [7:0] out_hi_dut;
logic [7:0] out_lo_ref;
logic [7:0] out_lo_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_hi_ref,out_hi_dut,out_lo_ref,out_lo_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out_hi(out_hi_ref),
.out_lo(out_lo_ref) );
TopModule top_module1 (
.in,
.out_hi(out_hi_dut),
.out_lo(out_lo_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_hi) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_hi", stats1.errors_out_hi, stats1.errortime_out_hi);
else $display("Hint: Output '%s' has no mismatches.", "out_hi");
if (stats1.errors_out_lo) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_lo", stats1.errors_out_lo, stats1.errortime_out_lo);
else $display("Hint: Output '%s' has no mismatches.", "out_lo");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_hi_ref, out_lo_ref } === ( { out_hi_ref, out_lo_ref } ^ { out_hi_dut, out_lo_dut } ^ { out_hi_ref, out_lo_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_hi_ref !== ( out_hi_ref ^ out_hi_dut ^ out_hi_ref ))
begin if (stats1.errors_out_hi == 0) stats1.errortime_out_hi = $time;
stats1.errors_out_hi = stats1.errors_out_hi+1'b1; end
if (out_lo_ref !== ( out_lo_ref ^ out_lo_dut ^ out_lo_ref ))
begin if (stats1.errors_out_lo == 0) stats1.errortime_out_lo = $time;
stats1.errors_out_lo = stats1.errors_out_lo+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob016_m2014_q4j |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- input y (4 bits)
- output sum (5 bits)
Implement a 4-bit adder with full adders. The output sum should include
the overflow bit.
|
module RefModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
assign sum = x+y;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] x,y
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{x,y} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_sum;
int errortime_sum;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] x;
logic [3:0] y;
logic [4:0] sum_ref;
logic [4:0] sum_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,sum_ref,sum_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.x,
.y,
.sum(sum_ref) );
TopModule top_module1 (
.x,
.y,
.sum(sum_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_sum) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "sum", stats1.errors_sum, stats1.errortime_sum);
else $display("Hint: Output '%s' has no mismatches.", "sum");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { sum_ref } === ( { sum_ref } ^ { sum_dut } ^ { sum_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))
begin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;
stats1.errors_sum = stats1.errors_sum+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob017_mux2to1v |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (100 bits)
- input b (100 bits)
- input sel
- output out (100 bits)
The module should implement a 2-1 multiplexer. When sel=0, choose a. When
sel=1, choose b.
|
module RefModule (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [99:0] a,b,
output logic sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
a <= 'hdeadbeef;
b <= 'h5eaf00d;
sel <= 0;
@(negedge clk);
wavedrom_start("Beef or seafood?");
repeat(6) @(posedge clk) sel <= ~sel;
@(negedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= {$random, $random, $random, $random, $random, $random, $random};
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] a;
logic [99:0] b;
logic sel;
logic [99:0] out_ref;
logic [99:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel );
RefModule good1 (
.a,
.b,
.sel,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob018_mux256to1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (256 bits)
- input sel ( 8 bits)
- output out
The module should implement a 1-bit wide, 256-to-1 multiplexer. The 256
inputs are all packed into a single 256-bit input vector. sel=0 should
select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.
|
module RefModule (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [255:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<8; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [255:0] in;
logic [7:0] sel;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.sel );
RefModule good1 (
.in,
.sel,
.out(out_ref) );
TopModule top_module1 (
.in,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob019_m2014_q4f |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- output out
The module should implement the following circuit in Verilog. Two inputs
(in1 and in2) go to an AND gate, but the in2 input to the AND gate has a
bubble. The output of the AND gate is connected to 'out'.
|
module RefModule (
input in1,
input in2,
output logic out
);
assign out = in1 & ~in2;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in1;
logic in2;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in1,
.in2 );
RefModule good1 (
.in1,
.in2,
.out(out_ref) );
TopModule top_module1 (
.in1,
.in2,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob020_mt2015_eq2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input A (2 bits)
- input B (2 bits)
- output z
The module should implement a circuit that has two 2-bit inputs A[1:0]
and B[1:0], and produces an output z. The value of z should be 1 if A =
B, otherwise z should be 0.
|
module RefModule (
input [1:0] A,
input [1:0] B,
output z
);
assign z = A[1:0]==B[1:0];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 1k. 2-bit equality comparator.
*/
module stimulus_gen (
input clk,
output logic [1:0] A,
output logic [1:0] B
);
always @(posedge clk, negedge clk)
{A, B} <= $random % 16;
initial begin
repeat(1000) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [1:0] A;
logic [1:0] B;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,A,B,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.A,
.B );
RefModule good1 (
.A,
.B,
.z(z_ref) );
TopModule top_module1 (
.A,
.B,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob021_mux256to1v |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (1024 bits)
- input sel ( 8 bits)
- output out ( 4 bits)
The module should implement a 4-bit wide, 256-to-1 multiplexer. The 256
4-bit inputs are all packed into a single 1024-bit input vector. sel=0
should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects
bits in[11:8], etc.
|
module RefModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [1023:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<32; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [1023:0] in;
logic [7:0] sel;
logic [3:0] out_ref;
logic [3:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.sel );
RefModule good1 (
.in,
.sel,
.out(out_ref) );
TopModule top_module1 (
.in,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob022_mux2to1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input sel
- output out
The module should implement a one-bit wide, 2-to-1 multiplexer. When
sel=0, choose a. When sel=1, choose b.
|
module RefModule (
input a,
input b,
input sel,
output out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b, sel} <= 3'b000;
@(negedge clk) wavedrom_start("<b>Sel</b> chooses between <b>a</b> and <b>b</b>");
@(posedge clk) {a, b, sel} <= 3'b000;
@(posedge clk) {a, b, sel} <= 3'b100;
@(posedge clk) {a, b, sel} <= 3'b110;
@(posedge clk) {a, b, sel} <= 3'b111;
@(posedge clk) {a, b, sel} <= 3'b011;
@(posedge clk) {a, b, sel} <= 3'b001;
@(posedge clk) {a, b, sel} <= 3'b100;
@(posedge clk) {a, b, sel} <= 3'b101;
@(posedge clk) {a, b, sel} <= 3'b110;
@(posedge clk) {a, b, sel} <= 3'b111;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic sel;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel );
RefModule good1 (
.a,
.b,
.sel,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob023_vector100r |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (100 bits)
- output out (100 bits)
The module should reverse the bit ordering of the input and write to the
output.
|
module RefModule (
input [99:0] in,
output reg [99:0] out
);
always_comb
for (int i=0;i<$bits(out);i++)
out[i] = in[$bits(out)-i-1];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [99:0] in
);
always @(posedge clk, negedge clk)
in <= {$random, $random, $random, $random};
initial begin
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] in;
logic [99:0] out_ref;
logic [99:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob024_hadd |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output sum
- output cout
The module should implement a half adder. A half adder adds two bits
(with no carry-in) and produces a sum and carry-out.
|
module RefModule (
input a,
input b,
output sum,
output cout
);
assign {cout, sum} = a+b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b
);
always @(posedge clk, negedge clk)
{a,b} <= $random;
initial begin
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_sum;
int errortime_sum;
int errors_cout;
int errortime_cout;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic sum_ref;
logic sum_dut;
logic cout_ref;
logic cout_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sum_ref,sum_dut,cout_ref,cout_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.sum(sum_ref),
.cout(cout_ref) );
TopModule top_module1 (
.a,
.b,
.sum(sum_dut),
.cout(cout_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_sum) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "sum", stats1.errors_sum, stats1.errortime_sum);
else $display("Hint: Output '%s' has no mismatches.", "sum");
if (stats1.errors_cout) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "cout", stats1.errors_cout, stats1.errortime_cout);
else $display("Hint: Output '%s' has no mismatches.", "cout");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { sum_ref, cout_ref } === ( { sum_ref, cout_ref } ^ { sum_dut, cout_dut } ^ { sum_ref, cout_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))
begin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;
stats1.errors_sum = stats1.errors_sum+1'b1; end
if (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))
begin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;
stats1.errors_cout = stats1.errors_cout+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob025_reduction |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output parity
Parity checking is often used as a simple method of detecting errors when
transmitting data through an imperfect channel. The module should compute
a parity bit for an 8-bit byte (which will add a 9th bit to the byte). We
will use "even" parity, where the parity bit is just the XOR of all 8
data bits.
|
module RefModule (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_parity;
int errortime_parity;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic parity_ref;
logic parity_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,parity_ref,parity_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.parity(parity_ref) );
TopModule top_module1 (
.in,
.parity(parity_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_parity) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "parity", stats1.errors_parity, stats1.errortime_parity);
else $display("Hint: Output '%s' has no mismatches.", "parity");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { parity_ref } === ( { parity_ref } ^ { parity_dut } ^ { parity_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (parity_ref !== ( parity_ref ^ parity_dut ^ parity_ref ))
begin if (stats1.errors_parity == 0) stats1.errortime_parity = $time;
stats1.errors_parity = stats1.errors_parity+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob026_alwaysblock1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out_assign
- output out_alwaysblock
The module should implement an AND gate using both an assign statement
and a combinational always block.
|
module RefModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("AND gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_alwaysblock;
int errortime_out_alwaysblock;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_assign_ref;
logic out_assign_dut;
logic out_alwaysblock_ref;
logic out_alwaysblock_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_assign_ref,out_assign_dut,out_alwaysblock_ref,out_alwaysblock_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out_assign(out_assign_ref),
.out_alwaysblock(out_alwaysblock_ref) );
TopModule top_module1 (
.a,
.b,
.out_assign(out_assign_dut),
.out_alwaysblock(out_alwaysblock_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_alwaysblock) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_alwaysblock", stats1.errors_out_alwaysblock, stats1.errortime_out_alwaysblock);
else $display("Hint: Output '%s' has no mismatches.", "out_alwaysblock");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_alwaysblock_ref } === ( { out_assign_ref, out_alwaysblock_ref } ^ { out_assign_dut, out_alwaysblock_dut } ^ { out_assign_ref, out_alwaysblock_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_alwaysblock_ref !== ( out_alwaysblock_ref ^ out_alwaysblock_dut ^ out_alwaysblock_ref ))
begin if (stats1.errors_out_alwaysblock == 0) stats1.errortime_out_alwaysblock = $time;
stats1.errors_out_alwaysblock = stats1.errors_out_alwaysblock+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob027_fadd |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input cin
- output cout
- output sum
The module should impement a full adder. A full adder adds three bits
(including carry-in) and produces a sum and carry-out.
|
module RefModule (
input a,
input b,
input cin,
output cout,
output sum
);
assign {cout, sum} = a+b+cin;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,cin,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start();
@(posedge clk) {a,b,cin} <= 3'b000;
@(posedge clk) {a,b,cin} <= 3'b010;
@(posedge clk) {a,b,cin} <= 3'b100;
@(posedge clk) {a,b,cin} <= 3'b110;
@(posedge clk) {a,b,cin} <= 3'b000;
@(posedge clk) {a,b,cin} <= 3'b001;
@(posedge clk) {a,b,cin} <= 3'b011;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{a,b,cin} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_cout;
int errortime_cout;
int errors_sum;
int errortime_sum;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic cin;
logic cout_ref;
logic cout_dut;
logic sum_ref;
logic sum_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,cin,cout_ref,cout_dut,sum_ref,sum_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.cin );
RefModule good1 (
.a,
.b,
.cin,
.cout(cout_ref),
.sum(sum_ref) );
TopModule top_module1 (
.a,
.b,
.cin,
.cout(cout_dut),
.sum(sum_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_cout) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "cout", stats1.errors_cout, stats1.errortime_cout);
else $display("Hint: Output '%s' has no mismatches.", "cout");
if (stats1.errors_sum) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "sum", stats1.errors_sum, stats1.errortime_sum);
else $display("Hint: Output '%s' has no mismatches.", "sum");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { cout_ref, sum_ref } === ( { cout_ref, sum_ref } ^ { cout_dut, sum_dut } ^ { cout_ref, sum_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))
begin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;
stats1.errors_cout = stats1.errors_cout+1'b1; end
if (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))
begin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;
stats1.errors_sum = stats1.errors_sum+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob028_m2014_q4a |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input d
- input ena
- output q
The module should impement a D latch using an always block.
|
module RefModule (
input d,
input ena,
output logic q
);
always@(*) begin
if (ena)
q = d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, ena
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,ena} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic ena;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,d,ena,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.ena );
RefModule good1 (
.d,
.ena,
.q(q_ref) );
TopModule top_module1 (
.d,
.ena,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob029_m2014_q4g |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- input in3
- output out
The module should impement the following circuit: A two-input XNOR
(connected to 'in1' and 'in2) has an output connected to the input of a
two-input XOR. The second input of the XOR is 'in3.' The output of the
XOR is 'out'.
|
module RefModule (
input in1,
input in2,
input in3,
output logic out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2, in3
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2, in3} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in1;
logic in2;
logic in3;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,in3,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in1,
.in2,
.in3 );
RefModule good1 (
.in1,
.in2,
.in3,
.out(out_ref) );
TopModule top_module1 (
.in1,
.in2,
.in3,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob030_popcount255 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (255 bits)
- output out ( 8 bits)
A "population count" circuit counts the number of '1's in an input
vector. The module should implement a population count circuit for a
255-bit input vector.
|
module RefModule (
input [254:0] in,
output reg [7:0] out
);
always_comb begin
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [254:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 255'h0;
wavedrom_start("");
@(posedge clk, negedge clk) in <= 255'h0;
@(posedge clk, negedge clk) in <= 255'h0;
@(posedge clk, negedge clk) in <= 255'h1;
@(posedge clk, negedge clk) in <= 255'h1;
@(posedge clk, negedge clk) in <= 255'h3;
@(posedge clk, negedge clk) in <= 255'h3;
@(posedge clk, negedge clk) in <= 255'h7;
@(posedge clk, negedge clk) in <= 255'haaaa;
@(posedge clk, negedge clk) in <= 255'hf00000;
@(posedge clk, negedge clk) in <= 255'h0;
wavedrom_stop();
repeat (200) @(posedge clk, negedge clk) begin
in <= {$random, $random, $random, $random, $random, $random, $random, $random};
end
@(posedge clk);
in <= '0;
@(posedge clk)
in <= '1;
@(posedge clk)
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [254:0] in;
logic [7:0] out_ref;
logic [7:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob031_dff |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- input q
The module should implement a single D flip-flop. Assume all sequential
logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input d,
output reg q
);
initial
q = 1'hx;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
d <= $urandom;
initial begin
@(posedge clk);
wavedrom_start("Positive-edge triggered DFF");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d );
RefModule good1 (
.clk,
.d,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob032_vector0 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input vec (3 bits)
- output outv (3 bits)
- output o2
- output o1
- output o0
The module has one 3-bit input, then outputs the same vector, and also
splits it into three separate 1-bit outputs. Connect output o0 to the
input vector's position 0, o1 to position 1, etc.
|
module RefModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] vec,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
vec <= 3'b0;
@(negedge clk);
wavedrom_start();
repeat(10) @(posedge clk)
vec <= count++;
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_outv;
int errortime_outv;
int errors_o2;
int errortime_o2;
int errors_o1;
int errortime_o1;
int errors_o0;
int errortime_o0;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] vec;
logic [2:0] outv_ref;
logic [2:0] outv_dut;
logic o2_ref;
logic o2_dut;
logic o1_ref;
logic o1_dut;
logic o0_ref;
logic o0_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,vec,outv_ref,outv_dut,o2_ref,o2_dut,o1_ref,o1_dut,o0_ref,o0_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.vec );
RefModule good1 (
.vec,
.outv(outv_ref),
.o2(o2_ref),
.o1(o1_ref),
.o0(o0_ref) );
TopModule top_module1 (
.vec,
.outv(outv_dut),
.o2(o2_dut),
.o1(o1_dut),
.o0(o0_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_outv) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "outv", stats1.errors_outv, stats1.errortime_outv);
else $display("Hint: Output '%s' has no mismatches.", "outv");
if (stats1.errors_o2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o2", stats1.errors_o2, stats1.errortime_o2);
else $display("Hint: Output '%s' has no mismatches.", "o2");
if (stats1.errors_o1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o1", stats1.errors_o1, stats1.errortime_o1);
else $display("Hint: Output '%s' has no mismatches.", "o1");
if (stats1.errors_o0) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o0", stats1.errors_o0, stats1.errortime_o0);
else $display("Hint: Output '%s' has no mismatches.", "o0");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { outv_ref, o2_ref, o1_ref, o0_ref } === ( { outv_ref, o2_ref, o1_ref, o0_ref } ^ { outv_dut, o2_dut, o1_dut, o0_dut } ^ { outv_ref, o2_ref, o1_ref, o0_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (outv_ref !== ( outv_ref ^ outv_dut ^ outv_ref ))
begin if (stats1.errors_outv == 0) stats1.errortime_outv = $time;
stats1.errors_outv = stats1.errors_outv+1'b1; end
if (o2_ref !== ( o2_ref ^ o2_dut ^ o2_ref ))
begin if (stats1.errors_o2 == 0) stats1.errortime_o2 = $time;
stats1.errors_o2 = stats1.errors_o2+1'b1; end
if (o1_ref !== ( o1_ref ^ o1_dut ^ o1_ref ))
begin if (stats1.errors_o1 == 0) stats1.errortime_o1 = $time;
stats1.errors_o1 = stats1.errors_o1+1'b1; end
if (o0_ref !== ( o0_ref ^ o0_dut ^ o0_ref ))
begin if (stats1.errors_o0 == 0) stats1.errortime_o0 = $time;
stats1.errors_o0 = stats1.errors_o0+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob033_ece241_2014_q1c |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (8 bits)
- input b (8 bits)
- output s (8 bits)
- output overflow
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0].
The module should add these numbers to produce s[7:0]. Also compute
whether a (signed) overflow has occurred.
|
module RefModule (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b} <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) {a, b} <= 16'h0;
@(posedge clk) {a, b} <= 16'h0070;
@(posedge clk) {a, b} <= 16'h7070;
@(posedge clk) {a, b} <= 16'h7090;
@(posedge clk) {a, b} <= 16'h9070;
@(posedge clk) {a, b} <= 16'h9090;
@(posedge clk) {a, b} <= 16'h90ff;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_s;
int errortime_s;
int errors_overflow;
int errortime_overflow;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] a;
logic [7:0] b;
logic [7:0] s_ref;
logic [7:0] s_dut;
logic overflow_ref;
logic overflow_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,s_ref,s_dut,overflow_ref,overflow_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.s(s_ref),
.overflow(overflow_ref) );
TopModule top_module1 (
.a,
.b,
.s(s_dut),
.overflow(overflow_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_s) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "s", stats1.errors_s, stats1.errortime_s);
else $display("Hint: Output '%s' has no mismatches.", "s");
if (stats1.errors_overflow) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "overflow", stats1.errors_overflow, stats1.errortime_overflow);
else $display("Hint: Output '%s' has no mismatches.", "overflow");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { s_ref, overflow_ref } === ( { s_ref, overflow_ref } ^ { s_dut, overflow_dut } ^ { s_ref, overflow_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (s_ref !== ( s_ref ^ s_dut ^ s_ref ))
begin if (stats1.errors_s == 0) stats1.errortime_s = $time;
stats1.errors_s = stats1.errors_s+1'b1; end
if (overflow_ref !== ( overflow_ref ^ overflow_dut ^ overflow_ref ))
begin if (stats1.errors_overflow == 0) stats1.errortime_overflow = $time;
stats1.errors_overflow = stats1.errors_overflow+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob034_dff8 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops. All DFFs should be triggered by
the positive edge of clock.
|
module RefModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
d <= $random % 256;
initial begin
@(posedge clk);
wavedrom_start("Positive-edge triggered DFF");
repeat(10) @(posedge clk);
wavedrom_stop();
#100;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d );
RefModule good1 (
.clk,
.d,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob035_count1to10 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a decade counter that counts 1 through 10,
inclusive. Assume all sequential logic is triggered on the positive edge
of the clock. The reset input is active high synchronous, and should
reset the counter to 1.
|
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 10)
q <= 1;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
wavedrom_start("Synchronous reset and counting.");
reset_test();
repeat(12) @(posedge clk);
wavedrom_stop();
@(posedge clk);
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob036_ringer |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input ring
- input vibrate_mode
- output ringer
- output motor
The module should implement a circuit to control a cellphone's ringer and
vibration motor. Whenever the phone needs to ring from an incoming call
(input ring), your circuit must either turn on the ringer (output ringer
= 1) or the motor (output motor = 1), but not both. If the phone is in
vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn
on the ringer.
|
module RefModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg ring, vibrate_mode,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{vibrate_mode,ring} <= 1'b0;
wavedrom_start();
repeat(10) @(posedge clk)
{vibrate_mode,ring} <= count++;
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_ringer;
int errortime_ringer;
int errors_motor;
int errortime_motor;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic ring;
logic vibrate_mode;
logic ringer_ref;
logic ringer_dut;
logic motor_ref;
logic motor_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,ring,vibrate_mode,ringer_ref,ringer_dut,motor_ref,motor_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.ring,
.vibrate_mode );
RefModule good1 (
.ring,
.vibrate_mode,
.ringer(ringer_ref),
.motor(motor_ref) );
TopModule top_module1 (
.ring,
.vibrate_mode,
.ringer(ringer_dut),
.motor(motor_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_ringer) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "ringer", stats1.errors_ringer, stats1.errortime_ringer);
else $display("Hint: Output '%s' has no mismatches.", "ringer");
if (stats1.errors_motor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "motor", stats1.errors_motor, stats1.errortime_motor);
else $display("Hint: Output '%s' has no mismatches.", "motor");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { ringer_ref, motor_ref } === ( { ringer_ref, motor_ref } ^ { ringer_dut, motor_dut } ^ { ringer_ref, motor_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (ringer_ref !== ( ringer_ref ^ ringer_dut ^ ringer_ref ))
begin if (stats1.errors_ringer == 0) stats1.errortime_ringer = $time;
stats1.errors_ringer = stats1.errors_ringer+1'b1; end
if (motor_ref !== ( motor_ref ^ motor_dut ^ motor_ref ))
begin if (stats1.errors_motor == 0) stats1.errortime_motor = $time;
stats1.errors_motor = stats1.errors_motor+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob037_review2015_count1k |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (10 bits)
The module should implement a counter that counts from 0 to 999,
inclusive, with a period of 1000 cycles. Assume all sequential logic is
triggered on the positive edge of the clock. The reset input is active
high synchronous, and should reset the counter to 0.
|
module RefModule (
input clk,
input reset,
output reg [9:0] q
);
always @(posedge clk)
if (reset || q == 999)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
wavedrom_start("Synchronous reset");
reset_test();
repeat(5) @(posedge clk);
wavedrom_stop();
reset <= 0;
repeat(989) @(negedge clk);
wavedrom_start("Wrap around behaviour");
repeat(14)@(posedge clk);
wavedrom_stop();
repeat(2000) @(posedge clk, negedge clk) begin
reset <= !($random & 127);
end
reset <= 0;
repeat(2000) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [9:0] q_ref;
logic [9:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob038_count15 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a 4-bit binary counter that counts from 0
through 15, inclusive, with a period of 16. Assume all sequential logic
is triggered on the positive edge of the clock. The reset input is active
high synchronous, and should reset the counter to 0.
|
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
input tb_match,
output reg wavedrom_enable,
output reg[511:0] wavedrom_title
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
@(negedge clk);
wavedrom_start("Reset and counting");
reset_test();
repeat(3) @(posedge clk);
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob039_always_if |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input sel_b1
- input sel_b2
- output out_assign
- output out_always
The module should implement a 2-to-1 mux that chooses between a and b.
Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the
same twice, once using assign statements and once using a procedural if
statement.
|
module RefModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) out_always = (sel_b1 & sel_b2) ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,sel_b1, sel_b2,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b, sel_b1, sel_b2} <= 4'b000;
@(negedge clk) wavedrom_start("");
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0100;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1000;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1101;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0001;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0110;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1010;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0111;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1011;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel_b1,sel_b2} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_always;
int errortime_out_always;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic sel_b1;
logic sel_b2;
logic out_assign_ref;
logic out_assign_dut;
logic out_always_ref;
logic out_always_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel_b1,sel_b2,out_assign_ref,out_assign_dut,out_always_ref,out_always_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel_b1,
.sel_b2 );
RefModule good1 (
.a,
.b,
.sel_b1,
.sel_b2,
.out_assign(out_assign_ref),
.out_always(out_always_ref) );
TopModule top_module1 (
.a,
.b,
.sel_b1,
.sel_b2,
.out_assign(out_assign_dut),
.out_always(out_always_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_always) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_always", stats1.errors_out_always, stats1.errortime_out_always);
else $display("Hint: Output '%s' has no mismatches.", "out_always");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_always_ref } === ( { out_assign_ref, out_always_ref } ^ { out_assign_dut, out_always_dut } ^ { out_assign_ref, out_always_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_always_ref !== ( out_always_ref ^ out_always_dut ^ out_always_ref ))
begin if (stats1.errors_out_always == 0) stats1.errortime_out_always = $time;
stats1.errors_out_always = stats1.errors_out_always+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob040_count10 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a decade counter that counts from 0 through
9, inclusive, with a period of 10. Assume all sequential logic is
triggered on the positive edge of the clock. The reset input is active
high synchronous, and should reset the counter to 0.
|
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 9)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
wavedrom_start("Synchronous reset and counting");
reset_test();
repeat(12) @(posedge clk);
wavedrom_stop();
@(posedge clk);
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob041_dff8r |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops with active high synchronous
reset setting the output to zero. All DFFs should be triggered by the
positive edge of clk.
|
module RefModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
d <= $random;
wavedrom_start("Synchronous active-high reset");
reset_test();
repeat(10) @(negedge clk)
d <= $random;
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 15);
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic reset;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.reset );
RefModule good1 (
.clk,
.d,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob042_vector4 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output out (32 bits)
One common place to see a replication operator is when sign-extending a
smaller number to a larger one, while preserving its signed value. This
is done by replicating the sign bit (the most significant bit) of the
smaller number to the left. For example, sign-extending 4'b0101 (5) to 8
bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8
bits results in 8'b11111101 (-3). Implement a module that sign-extends an
8-bit number to 32 bits. This requires a concatenation of 24 copies of
the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit
number itself.
|
module RefModule (
input [7:0] in,
output [31:0] out
);
assign out = { {24{in[7]}}, in };
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob043_vector5 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- input e
- output out (25 bits)
Implement a module that given five 1-bit signals (a, b, c, d, and e),
compute all 25 pairwise one-bit comparisons in the 25-bit output vector.
The output should be 1 if the two bits being compared are equal. Example:
out[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ...
out[ 1] = ~e ^ d; out[ 0] = ~e ^ e.
|
module RefModule (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a, b, c, d, e
);
initial begin
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d,e} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic e;
logic [24:0] out_ref;
logic [24:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d,
.e );
RefModule good1 (
.a,
.b,
.c,
.d,
.e,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.e,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob044_vectorgates |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (3 bits)
- input b (3 bits)
- output out_or_bitwise (3 bits)
- output out_or_logical
- output out_not (6 bits)
Implement a module with two 3-bit inputs that computes the bitwise-OR of
the two vectors, the logical-OR of the two vectors, and the inverse (NOT)
of both vectors. Place the inverse of b in the upper half of out_not
(i.e., bits [5:3]), and the inverse of a in the lower half.
|
module RefModule (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b,~a};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 6'h38;
{b, a} <= 6'b0;
@(negedge clk);
wavedrom_start();
repeat(30) @(posedge clk)
{b, a} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_or_bitwise;
int errortime_out_or_bitwise;
int errors_out_or_logical;
int errortime_out_or_logical;
int errors_out_not;
int errortime_out_not;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] a;
logic [2:0] b;
logic [2:0] out_or_bitwise_ref;
logic [2:0] out_or_bitwise_dut;
logic out_or_logical_ref;
logic out_or_logical_dut;
logic [5:0] out_not_ref;
logic [5:0] out_not_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_or_bitwise_ref,out_or_bitwise_dut,out_or_logical_ref,out_or_logical_dut,out_not_ref,out_not_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out_or_bitwise(out_or_bitwise_ref),
.out_or_logical(out_or_logical_ref),
.out_not(out_not_ref) );
TopModule top_module1 (
.a,
.b,
.out_or_bitwise(out_or_bitwise_dut),
.out_or_logical(out_or_logical_dut),
.out_not(out_not_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_or_bitwise) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or_bitwise", stats1.errors_out_or_bitwise, stats1.errortime_out_or_bitwise);
else $display("Hint: Output '%s' has no mismatches.", "out_or_bitwise");
if (stats1.errors_out_or_logical) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or_logical", stats1.errors_out_or_logical, stats1.errortime_out_or_logical);
else $display("Hint: Output '%s' has no mismatches.", "out_or_logical");
if (stats1.errors_out_not) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_not", stats1.errors_out_not, stats1.errortime_out_not);
else $display("Hint: Output '%s' has no mismatches.", "out_not");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } === ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ^ { out_or_bitwise_dut, out_or_logical_dut, out_not_dut } ^ { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_or_bitwise_ref !== ( out_or_bitwise_ref ^ out_or_bitwise_dut ^ out_or_bitwise_ref ))
begin if (stats1.errors_out_or_bitwise == 0) stats1.errortime_out_or_bitwise = $time;
stats1.errors_out_or_bitwise = stats1.errors_out_or_bitwise+1'b1; end
if (out_or_logical_ref !== ( out_or_logical_ref ^ out_or_logical_dut ^ out_or_logical_ref ))
begin if (stats1.errors_out_or_logical == 0) stats1.errortime_out_or_logical = $time;
stats1.errors_out_or_logical = stats1.errors_out_or_logical+1'b1; end
if (out_not_ref !== ( out_not_ref ^ out_not_dut ^ out_not_ref ))
begin if (stats1.errors_out_not == 0) stats1.errortime_out_not = $time;
stats1.errors_out_not = stats1.errors_out_not+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob045_edgedetect2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input in (8 bits)
- input anyedge (8 bits)
Implement a module that for each bit in an 8-bit input vector, detect
when the input signal changes from one clock cycle to the next (detect
any edge). The output bit should be set the cycle after a 0 to 1
transition occurs. Assume all sequential logic is triggered on the
positive edge of the clock.
|
module RefModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in;
anyedge <= in ^ d_last;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output reg [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
@(posedge clk);
@(negedge clk) wavedrom_start("");
repeat(2) @(posedge clk);
in <= 1;
repeat(4) @(posedge clk);
in <= 0;
repeat(4) @(negedge clk);
in <= 6;
repeat(2) @(negedge clk);
in <= 0;
repeat(2) @(posedge clk);
@(negedge clk) wavedrom_stop();
repeat(200)
@(posedge clk, negedge clk) in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_anyedge;
int errortime_anyedge;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [7:0] anyedge_ref;
logic [7:0] anyedge_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,anyedge_ref,anyedge_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.clk,
.in,
.anyedge(anyedge_ref) );
TopModule top_module1 (
.clk,
.in,
.anyedge(anyedge_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_anyedge) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "anyedge", stats1.errors_anyedge, stats1.errortime_anyedge);
else $display("Hint: Output '%s' has no mismatches.", "anyedge");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { anyedge_ref } === ( { anyedge_ref } ^ { anyedge_dut } ^ { anyedge_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (anyedge_ref !== ( anyedge_ref ^ anyedge_dut ^ anyedge_ref ))
begin if (stats1.errors_anyedge == 0) stats1.errortime_anyedge = $time;
stats1.errors_anyedge = stats1.errors_anyedge+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob046_dff8p |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input d (8 bits)
- output q (8 bits)
Implement a module that includes 8 D flip-flops with active high
synchronous reset. The flip-flops must be reset to 0x34 rather than zero.
All DFFs should be triggered by the negative edge of clk.
|
module RefModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
always @(negedge clk)
if (reset)
q <= 8'h34;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
d <= $random;
@(negedge clk);
@(negedge clk);
wavedrom_start("Synchronous active-high reset");
reset_test();
repeat(10) @(negedge clk)
d <= $random;
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 15);
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic reset;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.reset );
RefModule good1 (
.clk,
.d,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob047_dff8ar |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops with active high asynchronous
reset. The output should be reset to 0. All DFFs should be triggered by
the positive edge of clk.
|
module RefModule (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
always @(posedge clk, posedge areset)
if (areset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
d <= $random;
@(negedge clk);
@(negedge clk);
wavedrom_start("Asynchronous active-high reset");
reset_test(1);
repeat(7) @(negedge clk) d <= $random;
@(posedge clk) reset <= 1;
@(negedge clk) reset <= 0; d <= $random;
repeat(2) @(negedge clk) d <= $random;
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 15);
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic areset;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,areset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.areset );
RefModule good1 (
.clk,
.d,
.areset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.areset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob048_m2014_q4c |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- input r
- output q
The module should implement a simple D flip flop with active high
synchronous reset (reset output to 0).
|
module RefModule (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, r
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,r} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic r;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,r,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.r );
RefModule good1 (
.clk,
.d,
.r,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.r,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob049_m2014_q4b |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input ar
- input d
- output q
The module should implement a D flip flop, positive edge triggered, with
an asynchronous reset "ar".
|
module RefModule (
input clk,
input d,
input ar,
output logic q
);
always@(posedge clk or posedge ar) begin
if (ar)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, ar
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,ar} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic ar;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,ar,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.ar );
RefModule good1 (
.clk,
.d,
.ar,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.ar,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob050_kmap1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- output out
The module should implement the circuit described by the Karnaugh map
below.
a
bc 0 1
00 | 0 | 1 |
01 | 1 | 1 |
11 | 1 | 1 |
10 | 1 | 1 |
|
module RefModule (
input a,
input b,
input c,
output out
);
assign out = (a | b | c);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b, c,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b,c} <= 1'b0;
wavedrom_start();
repeat(10) @(posedge clk)
{a,b,c} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{c,b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c );
RefModule good1 (
.a,
.b,
.c,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
End of preview. Expand
in Dataset Viewer.
VerilogEvalv2 spec-to-rtl dataset from the VerilogEval paper. Paper: Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks Repo: https://github.com/NVlabs/verilog-eval).
Disclaimer: I am not the original author and uploaded this here only for convenience! Please refer to the original repo for any information.
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