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module axi_join_intf (
AXI_BUS.Slave in,
AXI_BUS.Master out
);
`AXI_ASSIGN(out, in)
// pragma translate_off
`ifndef VERILATOR
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
assert(in.AXI_ID_WIDTH <= out.AXI_ID_WIDTH );
assert(in.AXI_USER_WIDTH == out.AXI_USER_WIDTH);
end
`endif
// pragma translate_on
endmodule |
module axi_isolate #(
parameter int unsigned NumPending = 32'd16, // Number of pending requests per channel
parameter type req_t = logic, // AXI request struct definition
parameter type resp_t = logic // AXI response struct definition
) (
input logic clk_i, // clock
input logic rst_ni, // reset
input req_t slv_req_i, // slave port request struct
output resp_t slv_resp_o, // slave port response struct
output req_t mst_req_o, // master port request struct
input resp_t mst_resp_i, // master port response struct
input logic isolate_i, // isolate master port from slave port
output logic isolated_o // master port is isolated from slave port
);
// plus 1 in clog for accouning no open transaction, plus one bit for atomic injection
localparam int unsigned CounterWidth = $clog2(NumPending + 32'd1) + 32'd1;
typedef logic [CounterWidth-1:0] cnt_t;
typedef enum logic [1:0] {
Normal,
Hold,
Drain,
Isolate
} isolate_state_e;
isolate_state_e state_aw_d, state_aw_q, state_ar_d, state_ar_q;
logic update_aw_state, update_ar_state;
cnt_t pending_aw_d, pending_aw_q;
logic update_aw_cnt;
cnt_t pending_w_d, pending_w_q;
logic update_w_cnt, connect_w;
cnt_t pending_ar_d, pending_ar_q;
logic update_ar_cnt;
`FFLARN(pending_aw_q, pending_aw_d, update_aw_cnt, '0, clk_i, rst_ni)
`FFLARN(pending_w_q, pending_w_d, update_w_cnt, '0, clk_i, rst_ni)
`FFLARN(pending_ar_q, pending_ar_d, update_ar_cnt, '0, clk_i, rst_ni)
`FFLARN(state_aw_q, state_aw_d, update_aw_state, Isolate, clk_i, rst_ni)
`FFLARN(state_ar_q, state_ar_d, update_ar_state, Isolate, clk_i, rst_ni)
// Update counters.
always_comb begin
pending_aw_d = pending_aw_q;
update_aw_cnt = 1'b0;
pending_w_d = pending_w_q;
update_w_cnt = 1'b0;
connect_w = 1'b0;
pending_ar_d = pending_ar_q;
update_ar_cnt = 1'b0;
// write counters
if (mst_req_o.aw_valid && (state_aw_q == Normal)) begin
pending_aw_d++;
update_aw_cnt = 1'b1;
pending_w_d++;
update_w_cnt = 1'b1;
connect_w = 1'b1;
if (mst_req_o.aw.atop[axi_pkg::ATOP_R_RESP]) begin
pending_ar_d++; // handle atomic with read response by injecting a count in AR
update_ar_cnt = 1'b1;
end
end
if (mst_req_o.w_valid && mst_resp_i.w_ready && mst_req_o.w.last) begin
pending_w_d--;
update_w_cnt = 1'b1;
end
if (mst_resp_i.b_valid && mst_req_o.b_ready) begin
pending_aw_d--;
update_aw_cnt = 1'b1;
end
// read counters
if (mst_req_o.ar_valid && (state_ar_q == Normal)) begin
pending_ar_d++;
update_ar_cnt = 1'b1;
end
if (mst_resp_i.r_valid && mst_req_o.r_ready && mst_resp_i.r.last) begin
pending_ar_d--;
update_ar_cnt = 1'b1;
end
end
// Perform isolation.
always_comb begin
// Default assignments
state_aw_d = state_aw_q;
update_aw_state = 1'b0;
state_ar_d = state_ar_q;
update_ar_state = 1'b0;
// Connect channel per default
mst_req_o = slv_req_i;
slv_resp_o = mst_resp_i;
/////////////////////////////////////////////////////////////
// Write transaction
/////////////////////////////////////////////////////////////
unique case (state_aw_q)
Normal: begin // Normal operation
// Cut valid handshake if a counter capacity is reached. It has to check AR counter in case
// of atomics. Counters are wide enough to account for injected count in the read response
// counter.
if (pending_aw_q >= cnt_t'(NumPending) || pending_ar_q >= cnt_t'(2*NumPending)
|| (pending_w_q >= cnt_t'(NumPending))) begin
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
if (isolate_i) begin
state_aw_d = Drain;
update_aw_state = 1'b1;
end
end else begin
// here the AW handshake is connected normally
if (slv_req_i.aw_valid && !mst_resp_i.aw_ready) begin
state_aw_d = Hold;
update_aw_state = 1'b1;
end else begin
if (isolate_i) begin
state_aw_d = Drain;
update_aw_state = 1'b1;
end
end
end
end
Hold: begin // Hold the valid signal on 1'b1 if there was no transfer
mst_req_o.aw_valid = 1'b1;
// aw_ready normal connected
if (mst_resp_i.aw_ready) begin
update_aw_state = 1'b1;
state_aw_d = isolate_i ? Drain : Normal;
end
end
Drain: begin // cut the AW channel until counter is zero
mst_req_o.aw = '0;
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
if (pending_aw_q == '0) begin
state_aw_d = Isolate;
update_aw_state = 1'b1;
end
end
Isolate: begin // Cut the signals to the outputs
mst_req_o.aw = '0;
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
slv_resp_o.b = '0;
slv_resp_o.b_valid = 1'b0;
mst_req_o.b_ready = 1'b0;
if (!isolate_i) begin
state_aw_d = Normal;
update_aw_state = 1'b1;
end
end
default: /*do nothing*/;
endcase
// W channel is cut as long the counter is zero and not explicitly unlocked through an AW.
if ((pending_w_q == '0) && !connect_w ) begin
mst_req_o.w = '0;
mst_req_o.w_valid = 1'b0;
slv_resp_o.w_ready = 1'b0;
end
/////////////////////////////////////////////////////////////
// Read transaction
/////////////////////////////////////////////////////////////
unique case (state_ar_q)
Normal: begin
// cut handshake if counter capacity is reached
if (pending_ar_q >= NumPending) begin
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
if (isolate_i) begin
state_ar_d = Drain;
update_ar_state = 1'b1;
end
end else begin
// here the AR handshake is connected normally
if (slv_req_i.ar_valid && !mst_resp_i.ar_ready) begin
state_ar_d = Hold;
update_ar_state = 1'b1;
end else begin
if (isolate_i) begin
state_ar_d = Drain;
update_ar_state = 1'b1;
end
end
end
end
Hold: begin // Hold the valid signal on 1'b1 if there was no transfer
mst_req_o.ar_valid = 1'b1;
// ar_ready normal connected
if (mst_resp_i.ar_ready) begin
update_ar_state = 1'b1;
state_ar_d = isolate_i ? Drain : Normal;
end
end
Drain: begin
mst_req_o.ar = '0;
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
if (pending_ar_q == '0) begin
state_ar_d = Isolate;
update_ar_state = 1'b1;
end
end
Isolate: begin
mst_req_o.ar = '0;
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
slv_resp_o.r = '0;
slv_resp_o.r_valid = 1'b0;
mst_req_o.r_ready = 1'b0;
if (!isolate_i) begin
state_ar_d = Normal;
update_ar_state = 1'b1;
end
end
default: /*do nothing*/;
endcase
end
// the isolated output signal
assign isolated_o = (state_aw_q == Isolate && state_ar_q == Isolate);
// pragma translate_off
`ifndef VERILATOR
initial begin
assume (NumPending > 0) else $fatal(1, "At least one pending transaction required.");
end
default disable iff (!rst_ni);
aw_overflow: assert property (@(posedge clk_i)
(pending_aw_q == '1) |=> (pending_aw_q != '0)) else
$fatal(1, "pending_aw_q overflowed");
ar_overflow: assert property (@(posedge clk_i)
(pending_ar_q == '1) |=> (pending_ar_q != '0)) else
$fatal(1, "pending_ar_q overflowed");
aw_underflow: assert property (@(posedge clk_i)
(pending_aw_q == '0) |=> (pending_aw_q != '1)) else
$fatal(1, "pending_aw_q underflowed");
ar_underflow: assert property (@(posedge clk_i)
(pending_ar_q == '0) |=> (pending_ar_q != '1)) else
$fatal(1, "pending_ar_q underflowed");
`endif
// pragma translate_on
endmodule |
module axi_isolate_intf #(
parameter int unsigned NUM_PENDING = 32'd16, // Number of pending requests
parameter int unsigned AXI_ID_WIDTH = 32'd0, // AXI ID width
parameter int unsigned AXI_ADDR_WIDTH = 32'd0, // AXI address width
parameter int unsigned AXI_DATA_WIDTH = 32'd0, // AXI data width
parameter int unsigned AXI_USER_WIDTH = 32'd0 // AXI user width
) (
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low
AXI_BUS.Slave slv, // slave port
AXI_BUS.Master mst, // master port
input logic isolate_i, // isolate master port from slave port
output logic isolated_o // master port is isolated from slave port
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)
axi_isolate #(
.NumPending ( NUM_PENDING ), // Number of pending requests per channel
.req_t ( req_t ), // AXI request struct definition
.resp_t ( resp_t ) // AXI response struct definition
) i_axi_isolate (
.clk_i, // clock
.rst_ni, // reset
.slv_req_i ( slv_req ), // slave port request struct
.slv_resp_o ( slv_resp ), // slave port response struct
.mst_req_o ( mst_req ), // master port request struct
.mst_resp_i ( mst_resp ), // master port response struct
.isolate_i, // isolate master port from slave port
.isolated_o // master port is isolated from slave port
);
// pragma translate_off
`ifndef VERILATOR
initial begin
assume (AXI_ID_WIDTH > 0) else $fatal(1, "AXI_ID_WIDTH has to be > 0.");
assume (AXI_ADDR_WIDTH > 0) else $fatal(1, "AXI_ADDR_WIDTH has to be > 0.");
assume (AXI_DATA_WIDTH > 0) else $fatal(1, "AXI_DATA_WIDTH has to be > 0.");
assume (AXI_USER_WIDTH > 0) else $fatal(1, "AXI_USER_WIDTH has to be > 0.");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_join_intf (
AXI_LITE.Slave in,
AXI_LITE.Master out
);
`AXI_LITE_ASSIGN(out, in)
// pragma translate_off
`ifndef VERILATOR
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
end
`endif
// pragma translate_on
endmodule |
module axi_demux #(
parameter int unsigned AxiIdWidth = 32'd0,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type req_t = logic,
parameter type resp_t = logic,
parameter int unsigned NoMstPorts = 32'd0,
parameter int unsigned MaxTrans = 32'd8,
parameter int unsigned AxiLookBits = 32'd3,
parameter bit UniqueIds = 1'b0,
parameter bit FallThrough = 1'b0,
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0,
parameter int unsigned aw_chan_width = 32'd0,
parameter int unsigned ar_chan_width = 32'd0,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1,
parameter type select_t = logic [SelectWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
// Slave Port
input req_t slv_req_i,
input select_t slv_aw_select_i,
input select_t slv_ar_select_i,
output resp_t slv_resp_o,
// Master Ports
output req_t [NoMstPorts-1:0] mst_reqs_o,
input resp_t [NoMstPorts-1:0] mst_resps_i
);
localparam int unsigned IdCounterWidth = MaxTrans > 1 ? $clog2(MaxTrans) : 1;
//--------------------------------------
// Typedefs for the FIFOs / Queues
//--------------------------------------
typedef struct packed {
aw_chan_t aw_chan;
select_t aw_select;
} aw_chan_select_t;
typedef struct packed {
ar_chan_t ar_chan;
select_t ar_select;
} ar_chan_select_t;
// pass through if only one master port
if (NoMstPorts == 32'h1) begin : gen_no_demux
assign mst_reqs_o[0] = slv_req_i;
assign slv_resp_o = mst_resps_i;
// other non degenerate cases
end else begin : gen_demux
//--------------------------------------
//--------------------------------------
// Signal Declarations
//--------------------------------------
//--------------------------------------
//--------------------------------------
// Write Transaction
//--------------------------------------
// comes from spill register at input
aw_chan_select_t slv_aw_chan_select;
logic slv_aw_valid, slv_aw_ready;
// AW ID counter
select_t lookup_aw_select;
logic aw_select_occupied, aw_id_cnt_full;
logic aw_push;
// Upon an ATOP load, inject IDs from the AW into the AR channel
logic atop_inject;
// W FIFO: stores the decision to which master W beats should go
logic w_fifo_pop;
logic w_fifo_full, w_fifo_empty;
select_t w_select;
// Register which locks the AW valid signal
logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock;
logic aw_valid, aw_ready;
// W channel from spill reg
w_chan_t slv_w_chan;
logic slv_w_valid, slv_w_ready;
// B channles input into the arbitration
b_chan_t [NoMstPorts-1:0] mst_b_chans;
logic [NoMstPorts-1:0] mst_b_valids, mst_b_readies;
// B channel to spill register
b_chan_t slv_b_chan;
logic slv_b_valid, slv_b_ready;
//--------------------------------------
// Read Transaction
//--------------------------------------
// comes from spill register at input
ar_chan_select_t slv_ar_chan_select;
logic slv_ar_valid, slv_ar_ready;
// AR ID counter
select_t lookup_ar_select;
logic ar_select_occupied, ar_id_cnt_full;
logic ar_push;
// Register which locks the AR valid signel
logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock;
logic ar_valid, ar_ready;
// R channles input into the arbitration
r_chan_t [NoMstPorts-1:0] mst_r_chans;
logic [NoMstPorts-1:0] mst_r_valids, mst_r_readies;
// R channel to spill register
r_chan_t slv_r_chan;
logic slv_r_valid, slv_r_ready;
//--------------------------------------
//--------------------------------------
// Channel Control
//--------------------------------------
//--------------------------------------
//--------------------------------------
// AW Channel
//--------------------------------------
// spill register at the channel input
// Workaround for bug in Questa 2020.2 and 2021.1: Flatten the struct into a logic vector before
// instantiating `spill_register`.
//typedef logic [$bits(aw_chan_select_t)-1:0] aw_chan_select_flat_t;
typedef logic [aw_chan_width+SelectWidth-1:0] aw_chan_select_flat_t;
aw_chan_select_flat_t slv_aw_chan_select_in_flat,
slv_aw_chan_select_out_flat;
assign slv_aw_chan_select_in_flat = {slv_req_i.aw, slv_aw_select_i};
spill_register #(
.T ( aw_chan_select_flat_t ),
.Bypass ( ~SpillAw ) // because module param indicates if we want a spill reg
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.aw_valid ),
.ready_o ( slv_resp_o.aw_ready ),
.data_i ( slv_aw_chan_select_in_flat ),
.valid_o ( slv_aw_valid ),
.ready_i ( slv_aw_ready ),
.data_o ( slv_aw_chan_select_out_flat )
);
assign slv_aw_chan_select = slv_aw_chan_select_out_flat;
// Control of the AW handshake
always_comb begin
// AXI Handshakes
slv_aw_ready = 1'b0;
aw_valid = 1'b0;
// `lock_aw_valid`, used to be protocol conform as it is not allowed to deassert
// a valid if there was no corresponding ready. As this process has to be able to inject
// an AXI ID into the counter of the AR channel on an ATOP, there could be a case where
// this process waits on `aw_ready` but in the mean time on the AR channel the counter gets
// full.
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
// AW ID counter and W FIFO
aw_push = 1'b0;
// ATOP injection into ar counter
atop_inject = 1'b0;
// we had an arbitration decision, the valid is locked, wait for the transaction
if (lock_aw_valid_q) begin
aw_valid = 1'b1;
// transaction
if (aw_ready) begin
slv_aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
atop_inject = slv_aw_chan_select.aw_chan.atop[5]; // inject the ATOP if necessary
end
end else begin
// Process can start handling a transaction if its `i_aw_id_counter` and `w_fifo` have
// space in them. Further check if we could inject something on the AR channel.
if (!aw_id_cnt_full && !w_fifo_full && !ar_id_cnt_full) begin
// there is a valid AW vector make the id lookup and go further, if it passes
if (slv_aw_valid && (!aw_select_occupied ||
(slv_aw_chan_select.aw_select == lookup_aw_select))) begin
// connect the handshake
aw_valid = 1'b1;
// push arbitration to the W FIFO regardless, do not wait for the AW transaction
aw_push = 1'b1;
// on AW transaction
if (aw_ready) begin
slv_aw_ready = 1'b1;
atop_inject = slv_aw_chan_select.aw_chan.atop[5];
// no AW transaction this cycle, lock the decision
end else begin
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
end
// lock the valid signal, as the selection gets pushed into the W FIFO on first assertion,
// prevent further pushing
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
if (UniqueIds) begin : gen_unique_ids_aw
// If the `UniqueIds` parameter is set, each write transaction has an ID that is unique among
// all in-flight write transactions, or all write transactions with a given ID target the same
// master port as all write transactions with the same ID, or both. This means that the
// signals that are driven by the ID counters if this parameter is not set can instead be
// derived from existing signals. The ID counters can therefore be omitted.
assign lookup_aw_select = slv_aw_chan_select.aw_select;
assign aw_select_occupied = 1'b0;
assign aw_id_cnt_full = 1'b0;
end else begin : gen_aw_id_counter
axi_demux_id_counters #(
.AxiIdBits ( AxiLookBits ),
.CounterWidth ( IdCounterWidth ),
.mst_port_select_t ( select_t )
) i_aw_id_counter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.lookup_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ),
.lookup_mst_select_o ( lookup_aw_select ),
.lookup_mst_select_occupied_o ( aw_select_occupied ),
.full_o ( aw_id_cnt_full ),
.inject_axi_id_i ( '0 ),
.inject_i ( 1'b0 ),
.push_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ),
.push_mst_select_i ( slv_aw_chan_select.aw_select ),
.push_i ( aw_push ),
.pop_axi_id_i ( slv_b_chan.id[0+:AxiLookBits] ),
.pop_i ( slv_b_valid & slv_b_ready )
);
// pop from ID counter on outward transaction
end
// FIFO to save W selection
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( ),
.data_i ( slv_aw_chan_select.aw_select ),
.push_i ( aw_push ), // controlled from proc_aw_chan
.data_o ( w_select ), // where the w beat should go
.pop_i ( w_fifo_pop ) // controlled from proc_w_chan
);
//--------------------------------------
// W Channel
//--------------------------------------
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.w_valid ),
.ready_o ( slv_resp_o.w_ready ),
.data_i ( slv_req_i.w ),
.valid_o ( slv_w_valid ),
.ready_i ( slv_w_ready ),
.data_o ( slv_w_chan )
);
//--------------------------------------
// B Channel
//--------------------------------------
// optional spill register
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_b_valid ),
.ready_o ( slv_b_ready ),
.data_i ( slv_b_chan ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
// Arbitration of the different B responses
rr_arb_tree #(
.NumIn ( NoMstPorts ),
.DataType ( b_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_b_mux (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( mst_b_valids ),
.gnt_o ( mst_b_readies ),
.data_i ( mst_b_chans ),
.gnt_i ( slv_b_ready ),
.req_o ( slv_b_valid ),
.data_o ( slv_b_chan ),
.idx_o ( )
);
//--------------------------------------
// AR Channel
//--------------------------------------
// Workaround for bug in Questa 2020.2 and 2021.1: Flatten the struct into a logic vector before
// instantiating `spill_register`.
//typedef logic [$bits(ar_chan_select_t)-1:0] ar_chan_select_flat_t;
typedef logic [ar_chan_width+SelectWidth-1:0] ar_chan_select_flat_t;
ar_chan_select_flat_t slv_ar_chan_select_in_flat,
slv_ar_chan_select_out_flat;
assign slv_ar_chan_select_in_flat = {slv_req_i.ar, slv_ar_select_i};
spill_register #(
.T ( ar_chan_select_flat_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.ar_valid ),
.ready_o ( slv_resp_o.ar_ready ),
.data_i ( slv_ar_chan_select_in_flat ),
.valid_o ( slv_ar_valid ),
.ready_i ( slv_ar_ready ),
.data_o ( slv_ar_chan_select_out_flat )
);
assign slv_ar_chan_select = slv_ar_chan_select_out_flat;
// control of the AR handshake
always_comb begin
// AXI Handshakes
slv_ar_ready = 1'b0;
ar_valid = 1'b0;
// `lock_ar_valid`: Used to be protocol conform as it is not allowed to deassert `ar_valid`
// if there was no corresponding `ar_ready`. There is the possibility that an injection
// of a R response from an `atop` from the AW channel can change the occupied flag of the
// `i_ar_id_counter`, even if it was previously empty. This FF prevents the deassertion.
lock_ar_valid_d = lock_ar_valid_q;
load_ar_lock = 1'b0;
// AR id counter
ar_push = 1'b0;
// The process had an arbitration decision in a previous cycle, the valid is locked,
// wait for the AR transaction.
if (lock_ar_valid_q) begin
ar_valid = 1'b1;
// transaction
if (ar_ready) begin
slv_ar_ready = 1'b1;
ar_push = 1'b1;
lock_ar_valid_d = 1'b0;
load_ar_lock = 1'b1;
end
end else begin
// The process can start handling AR transaction if `i_ar_id_counter` has space.
if (!ar_id_cnt_full) begin
// There is a valid AR, so look the ID up.
if (slv_ar_valid && (!ar_select_occupied ||
(slv_ar_chan_select.ar_select == lookup_ar_select))) begin
// connect the AR handshake
ar_valid = 1'b1;
// on transaction
if (ar_ready) begin
slv_ar_ready = 1'b1;
ar_push = 1'b1;
// no transaction this cycle, lock the valid decision!
end else begin
lock_ar_valid_d = 1'b1;
load_ar_lock = 1'b1;
end
end
end
end
end
// this ff is needed so that ar does not get de-asserted if an atop gets injected
`FFLARN(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni)
if (UniqueIds) begin : gen_unique_ids_ar
// If the `UniqueIds` parameter is set, each read transaction has an ID that is unique among
// all in-flight read transactions, or all read transactions with a given ID target the same
// master port as all read transactions with the same ID, or both. This means that the
// signals that are driven by the ID counters if this parameter is not set can instead be
// derived from existing signals. The ID counters can therefore be omitted.
assign lookup_ar_select = slv_ar_chan_select.ar_select;
assign ar_select_occupied = 1'b0;
assign ar_id_cnt_full = 1'b0;
end else begin : gen_ar_id_counter
axi_demux_id_counters #(
.AxiIdBits ( AxiLookBits ),
.CounterWidth ( IdCounterWidth ),
.mst_port_select_t ( select_t )
) i_ar_id_counter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.lookup_axi_id_i ( slv_ar_chan_select.ar_chan.id[0+:AxiLookBits] ),
.lookup_mst_select_o ( lookup_ar_select ),
.lookup_mst_select_occupied_o ( ar_select_occupied ),
.full_o ( ar_id_cnt_full ),
.inject_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ),
.inject_i ( atop_inject ),
.push_axi_id_i ( slv_ar_chan_select.ar_chan.id[0+:AxiLookBits] ),
.push_mst_select_i ( slv_ar_chan_select.ar_select ),
.push_i ( ar_push ),
.pop_axi_id_i ( slv_r_chan.id[0+:AxiLookBits] ),
.pop_i ( slv_r_valid & slv_r_ready & slv_r_chan.last )
);
end
//--------------------------------------
// R Channel
//--------------------------------------
// optional spill register
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_r_valid ),
.ready_o ( slv_r_ready ),
.data_i ( slv_r_chan ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
// Arbitration of the different r responses
rr_arb_tree #(
.NumIn ( NoMstPorts ),
.DataType ( r_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_r_mux (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( mst_r_valids ),
.gnt_o ( mst_r_readies ),
.data_i ( mst_r_chans ),
.gnt_i ( slv_r_ready ),
.req_o ( slv_r_valid ),
.data_o ( slv_r_chan ),
.idx_o ( )
);
assign ar_ready = ar_valid & mst_resps_i[slv_ar_chan_select.ar_select].ar_ready;
assign aw_ready = aw_valid & mst_resps_i[slv_aw_chan_select.aw_select].aw_ready;
// process that defines the individual demuxes and assignments for the arbitration
// as mst_reqs_o has to be drivem from the same always comb block!
always_comb begin
// default assignments
mst_reqs_o = '0;
slv_w_ready = 1'b0;
w_fifo_pop = 1'b0;
for (int unsigned i = 0; i < NoMstPorts; i++) begin
// AW channel
mst_reqs_o[i].aw = slv_aw_chan_select.aw_chan;
mst_reqs_o[i].aw_valid = 1'b0;
if (aw_valid && (slv_aw_chan_select.aw_select == i)) begin
mst_reqs_o[i].aw_valid = 1'b1;
end
// W channel
mst_reqs_o[i].w = slv_w_chan;
mst_reqs_o[i].w_valid = 1'b0;
if (!w_fifo_empty && (w_select == i)) begin
mst_reqs_o[i].w_valid = slv_w_valid;
slv_w_ready = mst_resps_i[i].w_ready;
w_fifo_pop = slv_w_valid & mst_resps_i[i].w_ready & slv_w_chan.last;
end
// B channel
mst_reqs_o[i].b_ready = mst_b_readies[i];
// AR channel
mst_reqs_o[i].ar = slv_ar_chan_select.ar_chan;
mst_reqs_o[i].ar_valid = 1'b0;
if (ar_valid && (slv_ar_chan_select.ar_select == i)) begin
mst_reqs_o[i].ar_valid = 1'b1;
end
// R channel
mst_reqs_o[i].r_ready = mst_r_readies[i];
end
end
// unpack the response B and R channels for the arbitration
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_b_channels
assign mst_b_chans[i] = mst_resps_i[i].b;
assign mst_b_valids[i] = mst_resps_i[i].b_valid;
assign mst_r_chans[i] = mst_resps_i[i].r;
assign mst_r_valids[i] = mst_resps_i[i].r_valid;
end
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
initial begin: validate_params
no_mst_ports: assume (NoMstPorts > 0) else
$fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1");
AXI_ID_BITS: assume (AxiIdWidth >= AxiLookBits) else
$fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth.");
end
default disable iff (!rst_ni);
aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |->
(slv_aw_select_i < NoMstPorts))) else
$fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\
NoMstPorts: %d", slv_aw_select_i, NoMstPorts);
ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |->
(slv_ar_select_i < NoMstPorts))) else
$fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\
NoMstPorts: %d", slv_ar_select_i, NoMstPorts);
aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else
$fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle.");
ar_valid_stable: assert property( @(posedge clk_i)
(ar_valid && !ar_ready) |=> ar_valid) else
$fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle.");
aw_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready)
|=> $stable(slv_aw_chan_select)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
ar_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready)
|=> $stable(slv_ar_chan_select)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
internal_ar_select: assert property( @(posedge clk_i)
(ar_valid |-> slv_ar_chan_select.ar_select < NoMstPorts))
else $fatal(1, "slv_ar_chan_select.ar_select illegal while ar_valid.");
internal_aw_select: assert property( @(posedge clk_i)
(aw_valid |-> slv_aw_chan_select.aw_select < NoMstPorts))
else $fatal(1, "slv_aw_chan_select.aw_select illegal while aw_valid.");
`endif
`endif
// pragma translate_on
end
endmodule |
module axi_demux_id_counters #(
// the lower bits of the AXI ID that should be considered, results in 2**AXI_ID_BITS counters
parameter int unsigned AxiIdBits = 2,
parameter int unsigned CounterWidth = 4,
parameter type mst_port_select_t = logic
) (
input clk_i, // Clock
input rst_ni, // Asynchronous reset active low
// lookup
input logic [AxiIdBits-1:0] lookup_axi_id_i,
output mst_port_select_t lookup_mst_select_o,
output logic lookup_mst_select_occupied_o,
// push
output logic full_o,
input logic [AxiIdBits-1:0] push_axi_id_i,
input mst_port_select_t push_mst_select_i,
input logic push_i,
// inject ATOPs in AR channel
input logic [AxiIdBits-1:0] inject_axi_id_i,
input logic inject_i,
// pop
input logic [AxiIdBits-1:0] pop_axi_id_i,
input logic pop_i
);
localparam int unsigned NoCounters = 2**AxiIdBits;
typedef logic [CounterWidth-1:0] cnt_t;
// registers, each gets loaded when push_en[i]
mst_port_select_t [NoCounters-1:0] mst_select_q;
// counter signals
logic [NoCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full;
//-----------------------------------
// Lookup
//-----------------------------------
assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i];
assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i];
//-----------------------------------
// Push and Pop
//-----------------------------------
assign push_en = (push_i) ? (1 << push_axi_id_i) : '0;
assign inject_en = (inject_i) ? (1 << inject_axi_id_i) : '0;
assign pop_en = (pop_i) ? (1 << pop_axi_id_i) : '0;
assign full_o = |cnt_full;
// counters
for (genvar i = 0; i < NoCounters; i++) begin : gen_counters
logic cnt_en, cnt_down, overflow;
cnt_t cnt_delta, in_flight;
always_comb begin
unique case ({push_en[i], inject_en[i], pop_en[i]})
3'b001 : begin // pop_i = -1
cnt_en = 1'b1;
cnt_down = 1'b1;
cnt_delta = cnt_t'(1);
end
3'b010 : begin // inject_i = +1
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(1);
end
// 3'b011, inject_i & pop_i = 0 --> use default
3'b100 : begin // push_i = +1
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(1);
end
// 3'b101, push_i & pop_i = 0 --> use default
3'b110 : begin // push_i & inject_i = +2
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(2);
end
3'b111 : begin // push_i & inject_i & pop_i = +1
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(1);
end
default : begin // do nothing to the counters
cnt_en = 1'b0;
cnt_down = 1'b0;
cnt_delta = cnt_t'(0);
end
endcase
end
delta_counter #(
.WIDTH ( CounterWidth ),
.STICKY_OVERFLOW ( 1'b0 )
) i_in_flight_cnt (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clear_i ( 1'b0 ),
.en_i ( cnt_en ),
.load_i ( 1'b0 ),
.down_i ( cnt_down ),
.delta_i ( cnt_delta ),
.d_i ( '0 ),
.q_o ( in_flight ),
.overflow_o ( overflow )
);
assign occupied[i] = |in_flight;
assign cnt_full[i] = overflow | (&in_flight);
// holds the selection signal for this id
`FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni)
// pragma translate_off
//`ifndef VERILATOR
//`ifndef XSIM
// // Validate parameters.
// cnt_underflow: assert property(
// @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else
// $fatal(1, "axi_demux_id_counters > Counter: %0d underflowed.\
// The reason is probably a faulty AXI response.", i);
//`endif
//`endif
// pragma translate_on
end
endmodule |
module axi_demux_intf #(
parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
parameter int unsigned NO_MST_PORTS = 32'd3,
parameter int unsigned MAX_TRANS = 32'd8,
parameter int unsigned AXI_LOOK_BITS = 32'd3,
parameter bit UNIQUE_IDS = 1'b0,
parameter bit FALL_THROUGH = 1'b0,
parameter bit SPILL_AW = 1'b1,
parameter bit SPILL_W = 1'b0,
parameter bit SPILL_B = 1'b0,
parameter bit SPILL_AR = 1'b1,
parameter bit SPILL_R = 1'b0,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1,
parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
input select_t slv_aw_select_i, // has to be stable, when aw_valid
input select_t slv_ar_select_i, // has to be stable, when ar_valid
AXI_BUS.Slave slv, // slave port
AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req;
resp_t slv_resp;
req_t [NO_MST_PORTS-1:0] mst_req;
resp_t [NO_MST_PORTS-1:0] mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports
`AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i])
`AXI_ASSIGN_TO_RESP(mst_resp[i], mst[i])
end
axi_demux #(
.AxiIdWidth ( AXI_ID_WIDTH ), // ID Width
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoMstPorts ( NO_MST_PORTS ),
.MaxTrans ( MAX_TRANS ),
.AxiLookBits ( AXI_LOOK_BITS ),
.UniqueIds ( UNIQUE_IDS ),
.FallThrough ( FALL_THROUGH ),
.SpillAw ( SPILL_AW ),
.SpillW ( SPILL_W ),
.SpillB ( SPILL_B ),
.SpillAr ( SPILL_AR ),
.SpillR ( SPILL_R ),
.aw_chan_width ( 35+AXI_ID_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH),
.ar_chan_width ( 35+AXI_ID_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH)
) i_axi_demux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
// slave port
.slv_req_i ( slv_req ),
.slv_aw_select_i ( slv_aw_select_i ),
.slv_ar_select_i ( slv_ar_select_i ),
.slv_resp_o ( slv_resp ),
// master port
.mst_reqs_o ( mst_req ),
.mst_resps_i ( mst_resp )
);
endmodule |
module axi_lite_demux #(
parameter type aw_chan_t = logic, // AXI4-Lite AW channel
parameter type w_chan_t = logic, // AXI4-Lite W channel
parameter type b_chan_t = logic, // AXI4-Lite B channel
parameter type ar_chan_t = logic, // AXI4-Lite AR channel
parameter type r_chan_t = logic, // AXI4-Lite R channel
parameter type req_t = logic, // AXI4-Lite request struct
parameter type resp_t = logic, // AXI4-Lite response struct
parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports
parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel
parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode
parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW
parameter bit SpillW = 1'b0, // insert one cycle latency on slave W
parameter bit SpillB = 1'b0, // insert one cycle latency on slave B
parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR
parameter bit SpillR = 1'b0, // insert one cycle latency on slave R
// Dependent parameters, DO NOT OVERRIDE!
parameter type select_t = logic [$clog2(NoMstPorts)-1:0]
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
// slave port (AXI4-Lite input), connect master module here
input req_t slv_req_i,
input select_t slv_aw_select_i,
input select_t slv_ar_select_i,
output resp_t slv_resp_o,
// master ports (AXI4-Lite outputs), connect slave modules here
output req_t [NoMstPorts-1:0] mst_reqs_o,
input resp_t [NoMstPorts-1:0] mst_resps_i
);
//--------------------------------------
// Typedefs for the spill registers
//--------------------------------------
typedef struct packed {
aw_chan_t aw;
select_t select;
} aw_chan_select_t;
typedef struct packed {
ar_chan_t ar;
select_t select;
} ar_chan_select_t;
if (NoMstPorts == 32'd1) begin : gen_no_demux
// degenerate case, connect slave to master port
// AW channel
assign mst_reqs_o[0] = slv_req_i;
assign slv_resp_o = mst_resps_i[0];
end else begin : gen_demux
// normal non degenerate case
//--------------------------------------
//--------------------------------------
// Signal Declarations
//--------------------------------------
//--------------------------------------
//--------------------------------------
// Write Transaction
//--------------------------------------
aw_chan_select_t slv_aw_chan;
logic slv_aw_valid, slv_aw_ready;
logic [NoMstPorts-1:0] mst_aw_valids, mst_aw_readies;
logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock;
logic w_fifo_push, w_fifo_pop;
logic w_fifo_full, w_fifo_empty;
w_chan_t slv_w_chan;
select_t w_select;
logic slv_w_valid, slv_w_ready;
logic /*w_pop*/ b_fifo_pop;
logic b_fifo_full, b_fifo_empty;
b_chan_t slv_b_chan;
select_t b_select;
logic slv_b_valid, slv_b_ready;
//--------------------------------------
// Read Transaction
//--------------------------------------
ar_chan_select_t slv_ar_chan;
logic slv_ar_valid, slv_ar_ready;
logic r_fifo_push, r_fifo_pop;
logic r_fifo_full, r_fifo_empty;
r_chan_t slv_r_chan;
select_t r_select;
logic slv_r_valid, slv_r_ready;
//--------------------------------------
//--------------------------------------
// Channel control
//--------------------------------------
//--------------------------------------
//--------------------------------------
// AW Channel
//--------------------------------------
aw_chan_select_t slv_aw_inp;
assign slv_aw_inp.aw = slv_req_i.aw;
assign slv_aw_inp.select = slv_aw_select_i;
spill_register #(
.T ( aw_chan_select_t ),
.Bypass ( ~SpillAw )
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.aw_valid ),
.ready_o ( slv_resp_o.aw_ready ),
.data_i ( slv_aw_inp ),
.valid_o ( slv_aw_valid ),
.ready_i ( slv_aw_ready ),
.data_o ( slv_aw_chan )
);
// replicate AW channel to the request output
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_aw
assign mst_reqs_o[i].aw = slv_aw_chan.aw;
assign mst_reqs_o[i].aw_valid = mst_aw_valids[i];
assign mst_aw_readies[i] = mst_resps_i[i].aw_ready;
end
// AW channel handshake control
always_comb begin
// default assignments
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
// handshake
slv_aw_ready = 1'b0;
mst_aw_valids = '0;
// W FIFO input control
w_fifo_push = 1'b0;
// control
if (lock_aw_valid_q) begin
// AW channel is locked and has valid output, fifo was pushed, as the new request was issued
mst_aw_valids[slv_aw_chan.select] = 1'b1;
if (mst_aw_readies[slv_aw_chan.select]) begin
// transaction, go back to IDLE
slv_aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
end
end else begin
if (!w_fifo_full && slv_aw_valid) begin
// new transaction, push select in the FIFO and then look if transaction happened
w_fifo_push = 1'b1;
mst_aw_valids[slv_aw_chan.select] = 1'b1; // only set the valid when FIFO is not full
if (mst_aw_readies[slv_aw_chan.select]) begin
// transaction, notify slave port
slv_aw_ready = 1'b1;
end else begin
// no transaction, lock valid
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
// lock the valid signal, as the selection gets pushed into the W FIFO on first assertion,
// prevent further pushing
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
fifo_v3 #(
.FALL_THROUGH( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemtion rule
.testmode_i ( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( /*not used*/ ),
.data_i ( slv_aw_chan.select ),
.push_i ( w_fifo_push ),
.data_o ( w_select ),
.pop_i ( w_fifo_pop )
);
//--------------------------------------
// W Channel
//--------------------------------------
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.w_valid ),
.ready_o ( slv_resp_o.w_ready ),
.data_i ( slv_req_i.w ),
.valid_o ( slv_w_valid ),
.ready_i ( slv_w_ready ),
.data_o ( slv_w_chan )
);
// replicate W channel
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_w
assign mst_reqs_o[i].w = slv_w_chan;
assign mst_reqs_o[i].w_valid = ~w_fifo_empty & ~b_fifo_full &
slv_w_valid & (w_select == select_t'(i));
end
assign slv_w_ready = ~w_fifo_empty & ~b_fifo_full & mst_resps_i[w_select].w_ready;
assign w_fifo_pop = slv_w_valid & slv_w_ready;
fifo_v3 #(
.FALL_THROUGH( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_b_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption
.testmode_i ( test_i ),
.full_o ( b_fifo_full ),
.empty_o ( b_fifo_empty ),
.usage_o ( /*not used*/ ),
.data_i ( w_select ),
.push_i ( w_fifo_pop ), // w beat was transferred, push selection to b channel
.data_o ( b_select ),
.pop_i ( b_fifo_pop )
);
//--------------------------------------
// B Channel
//--------------------------------------
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_b_valid ),
.ready_o ( slv_b_ready ),
.data_i ( slv_b_chan ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
// connect the response if the FIFO has valid data in it
assign slv_b_chan = (!b_fifo_empty) ? mst_resps_i[b_select].b : '0;
assign slv_b_valid = ~b_fifo_empty & mst_resps_i[b_select].b_valid;
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_b
assign mst_reqs_o[i].b_ready = ~b_fifo_empty & slv_b_ready & (b_select == select_t'(i));
end
assign b_fifo_pop = slv_b_valid & slv_b_ready;
//--------------------------------------
// AR Channel
//--------------------------------------
ar_chan_select_t slv_ar_inp;
assign slv_ar_inp.ar = slv_req_i.ar;
assign slv_ar_inp.select = slv_ar_select_i;
spill_register #(
.T ( ar_chan_select_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.ar_valid ),
.ready_o ( slv_resp_o.ar_ready ),
.data_i ( slv_ar_inp ),
.valid_o ( slv_ar_valid ),
.ready_i ( slv_ar_ready ),
.data_o ( slv_ar_chan )
);
// replicate AR channel
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_ar
assign mst_reqs_o[i].ar = slv_ar_chan.ar;
assign mst_reqs_o[i].ar_valid = ~r_fifo_full & slv_ar_valid &
(slv_ar_chan.select == select_t'(i));
end
assign slv_ar_ready = ~r_fifo_full & mst_resps_i[slv_ar_chan.select].ar_ready;
assign r_fifo_push = slv_ar_valid & slv_ar_ready;
fifo_v3 #(
.FALL_THROUGH( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_r_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption rule
.testmode_i ( test_i ),
.full_o ( r_fifo_full ),
.empty_o ( r_fifo_empty ),
.usage_o ( /*not used*/ ),
.data_i ( slv_ar_chan.select ),
.push_i ( r_fifo_push ),
.data_o ( r_select ),
.pop_i ( r_fifo_pop )
);
//--------------------------------------
// R Channel
//--------------------------------------
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_r_valid ),
.ready_o ( slv_r_ready ),
.data_i ( slv_r_chan ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
// connect the response if the FIFO has valid data in it
assign slv_r_chan = (!r_fifo_empty) ? mst_resps_i[r_select].r : '0;
assign slv_r_valid = ~r_fifo_empty & mst_resps_i[r_select].r_valid;
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_r
assign mst_reqs_o[i].r_ready = ~r_fifo_empty & slv_r_ready & (r_select == select_t'(i));
end
assign r_fifo_pop = slv_r_valid & slv_r_ready;
// pragma translate_off
`ifndef VERILATOR
default disable iff (!rst_ni);
aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |->
(slv_aw_select_i < NoMstPorts))) else
$fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\
NoMstPorts: %d", slv_aw_select_i, NoMstPorts);
ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |->
(slv_ar_select_i < NoMstPorts))) else
$fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\
NoMstPorts: %d", slv_ar_select_i, NoMstPorts);
aw_valid_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready)
|=> slv_aw_valid) else
$fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle.");
ar_valid_stable: assert property( @(posedge clk_i) (slv_ar_valid && !slv_ar_ready)
|=> slv_ar_valid) else
$fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle.");
aw_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready)
|=> $stable(slv_aw_chan)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
ar_stable: assert property( @(posedge clk_i) (slv_ar_valid && !slv_ar_ready)
|=> $stable(slv_ar_chan)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
`endif
// pragma translate_on
end
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
NoPorts: assert (NoMstPorts > 0) else $fatal("Number of master ports must be at least 1!");
MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_demux_intf #(
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter int unsigned NoMstPorts = 32'd0,
parameter int unsigned MaxTrans = 32'd0,
parameter bit FallThrough = 1'b0,
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0,
// Dependent parameters, DO NOT OVERRIDE!
parameter type select_t = logic [$clog2(NoMstPorts)-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
input select_t slv_aw_select_i, // has to be stable, when aw_valid
input select_t slv_ar_select_i, // has to be stable, when ar_valid
AXI_LITE.Slave slv, // slave port
AXI_LITE.Master mst [NoMstPorts-1:0] // master ports
);
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiDataWidth/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req;
resp_t slv_resp;
req_t [NoMstPorts-1:0] mst_reqs;
resp_t [NoMstPorts-1:0] mst_resps;
`AXI_LITE_ASSIGN_TO_REQ(slv_req, slv)
`AXI_LITE_ASSIGN_FROM_RESP(slv, slv_resp)
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_assign_mst_ports
`AXI_LITE_ASSIGN_FROM_REQ(mst[i], mst_reqs[i])
`AXI_LITE_ASSIGN_TO_RESP(mst_resps[i], mst[i])
end
axi_lite_demux #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoMstPorts ( NoMstPorts ),
.MaxTrans ( MaxTrans ),
.FallThrough ( FallThrough ),
.SpillAw ( SpillAw ),
.SpillW ( SpillW ),
.SpillB ( SpillB ),
.SpillAr ( SpillAr ),
.SpillR ( SpillR )
) i_axi_demux (
.clk_i,
.rst_ni,
.test_i,
// slave Port
.slv_req_i ( slv_req ),
.slv_aw_select_i ( slv_aw_select_i ), // must be stable while slv_aw_valid_i
.slv_ar_select_i ( slv_ar_select_i ), // must be stable while slv_ar_valid_i
.slv_resp_o ( slv_resp ),
// mster ports
.mst_reqs_o ( mst_reqs ),
.mst_resps_i ( mst_resps )
);
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
AddrWidth: assert (AxiAddrWidth > 0) else $fatal("Axi Parmeter has to be > 0!");
DataWidth: assert (AxiDataWidth > 0) else $fatal("Axi Parmeter has to be > 0!");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mux #(
// AXI4-Lite parameter and channel types
parameter type aw_chan_t = logic, // AW LITE Channel Type
parameter type w_chan_t = logic, // W LITE Channel Type
parameter type b_chan_t = logic, // B LITE Channel Type
parameter type ar_chan_t = logic, // AR LITE Channel Type
parameter type r_chan_t = logic, // R LITE Channel Type
parameter type req_t = logic, // AXI4-Lite request type
parameter type resp_t = logic, // AXI4-Lite response type
parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write or read
parameter int unsigned MaxTrans = 32'd0,
// If enabled, this multiplexer is purely combinatorial
parameter bit FallThrough = 1'b0,
// add spill register on write master port, adds a cycle latency on write channels
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
// add spill register on read master port, adds a cycle latency on read channels
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Test Mode enable
// slave ports (AXI4-Lite inputs), connect master modules here
input req_t [NoSlvPorts-1:0] slv_reqs_i,
output resp_t [NoSlvPorts-1:0] slv_resps_o,
// master port (AXI4-Lite output), connect slave module here
output req_t mst_req_o,
input resp_t mst_resp_i
);
// pass through if only one slave port
if (NoSlvPorts == 32'h1) begin : gen_no_mux
assign mst_req_o = slv_reqs_i[0];
assign slv_resps_o[0] = mst_resp_i;
// other non degenerate cases
end else begin : gen_mux
// typedef for the FIFO types
typedef logic [$clog2(NoSlvPorts)-1:0] select_t;
// input to the AW arbitration tree, unpacked from request struct
aw_chan_t [NoSlvPorts-1:0] slv_aw_chans;
logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies;
// AW channel arb tree decision
select_t aw_select;
aw_chan_t mst_aw_chan;
logic mst_aw_valid, mst_aw_ready;
// AW master handshake internal, so that we are able to stall, if w_fifo is full
logic aw_valid, aw_ready;
// FF to lock the AW valid signal, when a new arbitration decision is made the decision
// gets pushed into the W FIFO, when it now stalls prevent subsequent pushing
// This FF removes AW to W dependency
logic lock_aw_valid_d, lock_aw_valid_q;
logic load_aw_lock;
// signals for the FIFO that holds the last switching decision of the AW channel
logic w_fifo_full, w_fifo_empty;
logic w_fifo_push, w_fifo_pop;
// W channel spill reg
select_t w_select;
w_chan_t mst_w_chan;
logic mst_w_valid, mst_w_ready;
// switching decision for the B response back routing
select_t b_select;
// signals for the FIFO that holds the last switching decision of the AW channel
logic b_fifo_full, b_fifo_empty;
logic /*w_fifo_pop*/b_fifo_pop;
// B channel spill reg
b_chan_t mst_b_chan;
logic mst_b_valid, mst_b_ready;
// input to the AR arbitration tree, unpacked from request struct
ar_chan_t [NoSlvPorts-1:0] slv_ar_chans;
logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies;
// AR channel for when spill is enabled
select_t ar_select;
ar_chan_t mst_ar_chan;
logic mst_ar_valid, mst_ar_ready;
// AR master handshake internal, so that we are able to stall, if R_fifo is full
logic ar_valid, ar_ready;
// master ID in the r_id
select_t r_select;
// signals for the FIFO that holds the last switching decision of the AR channel
logic r_fifo_full, r_fifo_empty;
logic r_fifo_push, r_fifo_pop;
// R channel spill reg
r_chan_t mst_r_chan;
logic mst_r_valid, mst_r_ready;
//--------------------------------------
// AW Channel
//--------------------------------------
// unpach AW channel from request/response array
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_aw_arb_input
assign slv_aw_chans[i] = slv_reqs_i[i].aw;
assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid;
assign slv_resps_o[i].aw_ready = slv_aw_readies[i];
end
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( aw_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_aw_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_aw_valids ),
.gnt_o ( slv_aw_readies ),
.data_i ( slv_aw_chans ),
.gnt_i ( aw_ready ),
.req_o ( aw_valid ),
.data_o ( mst_aw_chan ),
.idx_o ( aw_select )
);
// control of the AW channel
always_comb begin
// default assignments
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
w_fifo_push = 1'b0;
mst_aw_valid = 1'b0;
aw_ready = 1'b0;
// had a downstream stall, be valid and send the AW along
if (lock_aw_valid_q) begin
mst_aw_valid = 1'b1;
// transaction
if (mst_aw_ready) begin
aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
end
end else begin
if (!w_fifo_full && aw_valid) begin
mst_aw_valid = 1'b1;
w_fifo_push = 1'b1;
if (mst_aw_ready) begin
aw_ready = 1'b1;
end else begin
// go to lock if transaction not in this cycle
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( ),
.data_i ( aw_select ),
.push_i ( w_fifo_push ),
.data_o ( w_select ),
.pop_i ( w_fifo_pop )
);
spill_register #(
.T ( aw_chan_t ),
.Bypass ( ~SpillAw ) // Param indicated that we want a spill reg
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_aw_valid ),
.ready_o ( mst_aw_ready ),
.data_i ( mst_aw_chan ),
.valid_o ( mst_req_o.aw_valid ),
.ready_i ( mst_resp_i.aw_ready ),
.data_o ( mst_req_o.aw )
);
//--------------------------------------
// W Channel
//--------------------------------------
// multiplexer
assign mst_w_chan = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w : '0;
assign mst_w_valid = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w_valid : 1'b0;
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_w_ready
assign slv_resps_o[i].w_ready = mst_w_ready & ~w_fifo_empty &
~b_fifo_full & (w_select == select_t'(i));
end
assign w_fifo_pop = mst_w_valid & mst_w_ready;
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_b_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( b_fifo_full ),
.empty_o ( b_fifo_empty ),
.usage_o ( ),
.data_i ( w_select ),
.push_i ( w_fifo_pop ), // push the selection for the B channel on W transaction
.data_o ( b_select ),
.pop_i ( b_fifo_pop )
);
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_w_valid ),
.ready_o ( mst_w_ready ),
.data_i ( mst_w_chan ),
.valid_o ( mst_req_o.w_valid ),
.ready_i ( mst_resp_i.w_ready ),
.data_o ( mst_req_o.w )
);
//--------------------------------------
// B Channel
//--------------------------------------
// replicate B channels
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_resps_b
assign slv_resps_o[i].b = mst_b_chan;
assign slv_resps_o[i].b_valid = mst_b_valid & ~b_fifo_empty & (b_select == select_t'(i));
end
assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready;
assign b_fifo_pop = mst_b_valid & mst_b_ready;
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.b_valid ),
.ready_o ( mst_req_o.b_ready ),
.data_i ( mst_resp_i.b ),
.valid_o ( mst_b_valid ),
.ready_i ( mst_b_ready ),
.data_o ( mst_b_chan )
);
//--------------------------------------
// AR Channel
//--------------------------------------
// unpack AR channel from request/response struct
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_ar_arb_input
assign slv_ar_chans[i] = slv_reqs_i[i].ar;
assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid;
assign slv_resps_o[i].ar_ready = slv_ar_readies[i];
end
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( ar_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_ar_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_ar_valids ),
.gnt_o ( slv_ar_readies ),
.data_i ( slv_ar_chans ),
.gnt_i ( ar_ready ),
.req_o ( ar_valid ),
.data_o ( mst_ar_chan ),
.idx_o ( ar_select )
);
// connect the handshake if there is space in the FIFO, no need for valid locking
// as the R response is only allowed, when AR is transferred
assign mst_ar_valid = (!r_fifo_full) ? ar_valid : 1'b0;
assign ar_ready = (!r_fifo_full) ? mst_ar_ready : 1'b0;
assign r_fifo_push = mst_ar_valid & mst_ar_ready;
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_r_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( r_fifo_full ),
.empty_o ( r_fifo_empty ),
.usage_o ( ),
.data_i ( ar_select ),
.push_i ( r_fifo_push ), // push the selection when w transaction happens
.data_o ( r_select ),
.pop_i ( r_fifo_pop )
);
spill_register #(
.T ( ar_chan_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_ar_valid ),
.ready_o ( mst_ar_ready ),
.data_i ( mst_ar_chan ),
.valid_o ( mst_req_o.ar_valid ),
.ready_i ( mst_resp_i.ar_ready ),
.data_o ( mst_req_o.ar )
);
//--------------------------------------
// R Channel
//--------------------------------------
// replicate R channels
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_resps_r
assign slv_resps_o[i].r = mst_r_chan;
assign slv_resps_o[i].r_valid = mst_r_valid & ~r_fifo_empty & (r_select == select_t'(i));
end
assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready;
assign r_fifo_pop = mst_r_valid & mst_r_ready;
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.r_valid ),
.ready_o ( mst_req_o.r_ready ),
.data_i ( mst_resp_i.r ),
.valid_o ( mst_r_valid ),
.ready_i ( mst_r_ready ),
.data_o ( mst_r_chan )
);
end
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
NoPorts: assert (NoSlvPorts > 0) else $fatal("Number of slave ports must be at least 1!");
MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mux_intf #(
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write
parameter int unsigned MaxTrans = 32'd0,
// if enabled, this multiplexer is purely combinatorial
parameter bit FallThrough = 1'b0,
// add spill register on write master ports, adds a cycle latency on write channels
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
// add spill register on read master ports, adds a cycle latency on read channels
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
AXI_BUS.Slave slv [NoSlvPorts-1:0], // slave ports
AXI_BUS.Master mst // master port
);
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiDataWidth/8-1:0] strb_t;
// channels typedef
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t [NoSlvPorts-1:0] slv_reqs;
resp_t [NoSlvPorts-1:0] slv_resps;
req_t mst_req;
resp_t mst_resp;
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports
`AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
`AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
end
`AXI_LITE_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst)
axi_lite_mux #(
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.NoSlvPorts ( NoSlvPorts ), // Number of slave ports
.MaxTrans ( MaxTrans ),
.FallThrough ( FallThrough ),
.SpillAw ( SpillAw ),
.SpillW ( SpillW ),
.SpillB ( SpillB ),
.SpillAr ( SpillAr ),
.SpillR ( SpillR )
) i_axi_mux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Test Mode enable
.slv_reqs_i ( slv_reqs ),
.slv_resps_o ( slv_resps ),
.mst_req_o ( mst_req ),
.mst_resp_i ( mst_resp )
);
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
AddrWidth: assert (AxiAddrWidth > 0) else $fatal("Axi Parameter has to be > 0!");
DataWidth: assert (AxiDataWidth > 0) else $fatal("Axi Parameter has to be > 0!");
end
`endif
// pragma translate_on
endmodule |
module axi_mux #(
// AXI parameter and channel types
parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports
parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports
parameter type mst_aw_chan_t = logic, // AW Channel Type, master port
parameter type w_chan_t = logic, // W Channel Type, all ports
parameter type slv_b_chan_t = logic, // B Channel Type, slave ports
parameter type mst_b_chan_t = logic, // B Channel Type, master port
parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports
parameter type mst_ar_chan_t = logic, // AR Channel Type, master port
parameter type slv_r_chan_t = logic, // R Channel Type, slave ports
parameter type mst_r_chan_t = logic, // R Channel Type, master port
parameter type slv_req_t = logic, // Slave port request type
parameter type slv_resp_t = logic, // Slave port response type
parameter type mst_req_t = logic, // Master ports request type
parameter type mst_resp_t = logic, // Master ports response type
parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write
parameter int unsigned MaxWTrans = 32'd8,
// If enabled, this multiplexer is purely combinatorial
parameter bit FallThrough = 1'b0,
// add spill register on write master ports, adds a cycle latency on write channels
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
// add spill register on read master ports, adds a cycle latency on read channels
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Test Mode enable
// slave ports (AXI inputs), connect master modules here
input slv_req_t [NoSlvPorts-1:0] slv_reqs_i,
output slv_resp_t [NoSlvPorts-1:0] slv_resps_o,
// master port (AXI outputs), connect slave modules here
output mst_req_t mst_req_o,
input mst_resp_t mst_resp_i
);
localparam int unsigned MstIdxBits = $clog2(NoSlvPorts);
localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits;
// pass through if only one slave port
if (NoSlvPorts == 32'h1) begin : gen_no_mux
assign mst_req_o = slv_reqs_i[0];
assign slv_resps_o[0] = mst_resp_i;
// other non degenerate cases
end else begin : gen_mux
typedef logic [MstIdxBits-1:0] switch_id_t;
// AXI channels between the ID prepend unit and the rest of the multiplexer
mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans;
logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies;
w_chan_t [NoSlvPorts-1:0] slv_w_chans;
logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies;
mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans;
logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies;
mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans;
logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies;
mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans;
logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies;
// These signals are all ID prepended
// AW channel
mst_aw_chan_t mst_aw_chan;
logic mst_aw_valid, mst_aw_ready;
// AW master handshake internal, so that we are able to stall, if w_fifo is full
logic aw_valid, aw_ready;
// FF to lock the AW valid signal, when a new arbitration decision is made the decision
// gets pushed into the W FIFO, when it now stalls prevent subsequent pushing
// This FF removes AW to W dependency
logic lock_aw_valid_d, lock_aw_valid_q;
logic load_aw_lock;
// signals for the FIFO that holds the last switching decision of the AW channel
logic w_fifo_full, w_fifo_empty;
logic w_fifo_push, w_fifo_pop;
switch_id_t w_fifo_data;
// W channel spill reg
w_chan_t mst_w_chan;
logic mst_w_valid, mst_w_ready;
// master ID in the b_id
switch_id_t switch_b_id;
// B channel spill reg
mst_b_chan_t mst_b_chan;
logic mst_b_valid;
// AR channel for when spill is enabled
mst_ar_chan_t mst_ar_chan;
logic ar_valid, ar_ready;
// master ID in the r_id
switch_id_t switch_r_id;
// R channel spill reg
mst_r_chan_t mst_r_chan;
logic mst_r_valid;
//--------------------------------------
// ID prepend for all slave ports
//--------------------------------------
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend
axi_id_prepend #(
.NoBus ( 32'd1 ), // one AXI bus per slave port
.AxiIdWidthSlvPort( SlvAxiIDWidth ),
.AxiIdWidthMstPort( MstAxiIDWidth ),
.slv_aw_chan_t ( slv_aw_chan_t ),
.slv_w_chan_t ( w_chan_t ),
.slv_b_chan_t ( slv_b_chan_t ),
.slv_ar_chan_t ( slv_ar_chan_t ),
.slv_r_chan_t ( slv_r_chan_t ),
.mst_aw_chan_t ( mst_aw_chan_t ),
.mst_w_chan_t ( w_chan_t ),
.mst_b_chan_t ( mst_b_chan_t ),
.mst_ar_chan_t ( mst_ar_chan_t ),
.mst_r_chan_t ( mst_r_chan_t )
) i_id_prepend (
.pre_id_i ( switch_id_t'(i) ),
.slv_aw_chans_i ( slv_reqs_i[i].aw ),
.slv_aw_valids_i ( slv_reqs_i[i].aw_valid ),
.slv_aw_readies_o ( slv_resps_o[i].aw_ready ),
.slv_w_chans_i ( slv_reqs_i[i].w ),
.slv_w_valids_i ( slv_reqs_i[i].w_valid ),
.slv_w_readies_o ( slv_resps_o[i].w_ready ),
.slv_b_chans_o ( slv_resps_o[i].b ),
.slv_b_valids_o ( slv_resps_o[i].b_valid ),
.slv_b_readies_i ( slv_reqs_i[i].b_ready ),
.slv_ar_chans_i ( slv_reqs_i[i].ar ),
.slv_ar_valids_i ( slv_reqs_i[i].ar_valid ),
.slv_ar_readies_o ( slv_resps_o[i].ar_ready ),
.slv_r_chans_o ( slv_resps_o[i].r ),
.slv_r_valids_o ( slv_resps_o[i].r_valid ),
.slv_r_readies_i ( slv_reqs_i[i].r_ready ),
.mst_aw_chans_o ( slv_aw_chans[i] ),
.mst_aw_valids_o ( slv_aw_valids[i] ),
.mst_aw_readies_i ( slv_aw_readies[i] ),
.mst_w_chans_o ( slv_w_chans[i] ),
.mst_w_valids_o ( slv_w_valids[i] ),
.mst_w_readies_i ( slv_w_readies[i] ),
.mst_b_chans_i ( slv_b_chans[i] ),
.mst_b_valids_i ( slv_b_valids[i] ),
.mst_b_readies_o ( slv_b_readies[i] ),
.mst_ar_chans_o ( slv_ar_chans[i] ),
.mst_ar_valids_o ( slv_ar_valids[i] ),
.mst_ar_readies_i ( slv_ar_readies[i] ),
.mst_r_chans_i ( slv_r_chans[i] ),
.mst_r_valids_i ( slv_r_valids[i] ),
.mst_r_readies_o ( slv_r_readies[i] )
);
end
//--------------------------------------
// AW Channel
//--------------------------------------
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( mst_aw_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_aw_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_aw_valids ),
.gnt_o ( slv_aw_readies ),
.data_i ( slv_aw_chans ),
.gnt_i ( aw_ready ),
.req_o ( aw_valid ),
.data_o ( mst_aw_chan ),
.idx_o ( )
);
// control of the AW channel
always_comb begin
// default assignments
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
w_fifo_push = 1'b0;
mst_aw_valid = 1'b0;
aw_ready = 1'b0;
// had a downstream stall, be valid and send the AW along
if (lock_aw_valid_q) begin
mst_aw_valid = 1'b1;
// transaction
if (mst_aw_ready) begin
aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
end
end else begin
if (!w_fifo_full && aw_valid) begin
mst_aw_valid = 1'b1;
w_fifo_push = 1'b1;
if (mst_aw_ready) begin
aw_ready = 1'b1;
end else begin
// go to lock if transaction not in this cycle
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxWTrans ),
.dtype ( switch_id_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( ),
.data_i ( mst_aw_chan.id[SlvAxiIDWidth+:MstIdxBits] ),
.push_i ( w_fifo_push ),
.data_o ( w_fifo_data ),
.pop_i ( w_fifo_pop )
);
spill_register #(
.T ( mst_aw_chan_t ),
.Bypass ( ~SpillAw ) // Param indicated that we want a spill reg
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_aw_valid ),
.ready_o ( mst_aw_ready ),
.data_i ( mst_aw_chan ),
.valid_o ( mst_req_o.aw_valid ),
.ready_i ( mst_resp_i.aw_ready ),
.data_o ( mst_req_o.aw )
);
//--------------------------------------
// W Channel
//--------------------------------------
// multiplexer
assign mst_w_chan = slv_w_chans[w_fifo_data];
always_comb begin
// default assignments
mst_w_valid = 1'b0;
slv_w_readies = '0;
w_fifo_pop = 1'b0;
// control
if (!w_fifo_empty) begin
// connect the handshake
mst_w_valid = slv_w_valids[w_fifo_data];
slv_w_readies[w_fifo_data] = mst_w_ready;
// pop FIFO on a last transaction
w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last;
end
end
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_w_valid ),
.ready_o ( mst_w_ready ),
.data_i ( mst_w_chan ),
.valid_o ( mst_req_o.w_valid ),
.ready_i ( mst_resp_i.w_ready ),
.data_o ( mst_req_o.w )
);
//--------------------------------------
// B Channel
//--------------------------------------
// replicate B channels
assign slv_b_chans = {NoSlvPorts{mst_b_chan}};
// control B channel handshake
assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits];
assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0;
spill_register #(
.T ( mst_b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.b_valid ),
.ready_o ( mst_req_o.b_ready ),
.data_i ( mst_resp_i.b ),
.valid_o ( mst_b_valid ),
.ready_i ( slv_b_readies[switch_b_id] ),
.data_o ( mst_b_chan )
);
//--------------------------------------
// AR Channel
//--------------------------------------
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( mst_ar_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_ar_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_ar_valids ),
.gnt_o ( slv_ar_readies ),
.data_i ( slv_ar_chans ),
.gnt_i ( ar_ready ),
.req_o ( ar_valid ),
.data_o ( mst_ar_chan ),
.idx_o ( )
);
spill_register #(
.T ( mst_ar_chan_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( ar_valid ),
.ready_o ( ar_ready ),
.data_i ( mst_ar_chan ),
.valid_o ( mst_req_o.ar_valid ),
.ready_i ( mst_resp_i.ar_ready ),
.data_o ( mst_req_o.ar )
);
//--------------------------------------
// R Channel
//--------------------------------------
// replicate R channels
assign slv_r_chans = {NoSlvPorts{mst_r_chan}};
// R channel handshake control
assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits];
assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0;
spill_register #(
.T ( mst_r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.r_valid ),
.ready_o ( mst_req_o.r_ready ),
.data_i ( mst_resp_i.r ),
.valid_o ( mst_r_valid ),
.ready_i ( slv_r_readies[switch_r_id] ),
.data_o ( mst_r_chan )
);
end
// pragma translate_off
`ifndef VERILATOR
initial begin
assert (SlvAxiIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!");
assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!");
assert (MaxWTrans > 0)
else $fatal(1, "Maximum number of outstanding writes must be non-zero!");
assert (MstAxiIDWidth >= SlvAxiIDWidth + $clog2(NoSlvPorts))
else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!");
// Assert ID widths (one slave is sufficient since they all have the same type).
assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of AW channel of slave ports does not match parameter!");
assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of AR channel of slave ports does not match parameter!");
assert ($unsigned($bits(slv_resps_o[0].b.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of B channel of slave ports does not match parameter!");
assert ($unsigned($bits(slv_resps_o[0].r.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of R channel of slave ports does not match parameter!");
assert ($unsigned($bits(mst_req_o.aw.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of AW channel of master port is wrong!");
assert ($unsigned($bits(mst_req_o.ar.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of AR channel of master port is wrong!");
assert ($unsigned($bits(mst_resp_i.b.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of B channel of master port is wrong!");
assert ($unsigned($bits(mst_resp_i.r.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of R channel of master port is wrong!");
end
`endif
// pragma translate_on
endmodule |
module axi_mux_intf #(
parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params
parameter int unsigned MST_AXI_ID_WIDTH = 32'd0,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write
parameter int unsigned MAX_W_TRANS = 32'd8,
// if enabled, this multiplexer is purely combinatorial
parameter bit FALL_THROUGH = 1'b0,
// add spill register on write master ports, adds a cycle latency on write channels
parameter bit SPILL_AW = 1'b1,
parameter bit SPILL_W = 1'b0,
parameter bit SPILL_B = 1'b0,
// add spill register on read master ports, adds a cycle latency on read channels
parameter bit SPILL_AR = 1'b1,
parameter bit SPILL_R = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports
AXI_BUS.Master mst // master port
);
typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t;
typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t;
typedef logic [AXI_ADDR_WIDTH -1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
// channels typedef
`AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t)
`AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t)
`AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t)
`AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t)
`AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t)
`AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t)
slv_req_t [NO_SLV_PORTS-1:0] slv_reqs;
slv_resp_t [NO_SLV_PORTS-1:0] slv_resps;
mst_req_t mst_req;
mst_resp_t mst_resp;
for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports
`AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
`AXI_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
end
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)
axi_mux #(
.SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ),
.slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports
.mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port
.w_chan_t ( w_chan_t ), // W Channel Type, all ports
.slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports
.mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port
.slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports
.mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port
.slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports
.mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port
.slv_req_t ( slv_req_t ),
.slv_resp_t ( slv_resp_t ),
.mst_req_t ( mst_req_t ),
.mst_resp_t ( mst_resp_t ),
.NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports
.MaxWTrans ( MAX_W_TRANS ),
.FallThrough ( FALL_THROUGH ),
.SpillAw ( SPILL_AW ),
.SpillW ( SPILL_W ),
.SpillB ( SPILL_B ),
.SpillAr ( SPILL_AR ),
.SpillR ( SPILL_R )
) i_axi_mux (
.clk_i ( clk_i ), // Clock
.rst_ni ( rst_ni ), // Asynchronous reset active low
.test_i ( test_i ), // Test Mode enable
.slv_reqs_i ( slv_reqs ),
.slv_resps_o ( slv_resps ),
.mst_req_o ( mst_req ),
.mst_resp_i ( mst_resp )
);
endmodule |
module axi_lite_mailbox #(
parameter int unsigned MailboxDepth = 32'd0,
parameter bit unsigned IrqEdgeTrig = 1'b0,
parameter bit unsigned IrqActHigh = 1'b1,
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter type req_lite_t = logic,
parameter type resp_lite_t = logic,
// DEPENDENT PARAMETERS, DO NOT OVERRIDE!
parameter type addr_t = logic [AxiAddrWidth-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
// slave ports [1:0]
input req_lite_t [1:0] slv_reqs_i,
output resp_lite_t [1:0] slv_resps_o,
output logic [1:0] irq_o, // interrupt output for each port
input addr_t [1:0] base_addr_i // base address for each port
);
localparam int unsigned FifoUsageWidth = $clog2(MailboxDepth);
typedef logic [AxiDataWidth-1:0] data_t;
// usage type of the mailbox FIFO, also the type of the threshold comparison
// is one bit wider, MSB is the fifo_full flag of the respective fifo
typedef logic [FifoUsageWidth:0] usage_t;
// signal declaration for the mailbox FIFO's, signal index is the port
logic [1:0] mbox_full, mbox_empty; // index is the instantiated mailbox FIFO
logic [1:0] mbox_push, mbox_pop; // index is port
logic [1:0] w_mbox_flush, r_mbox_flush; // index is port
data_t [1:0] mbox_w_data, mbox_r_data; // index is port
usage_t [1:0] mbox_usage; // index is the instantiated mailbox FIFO
// interrupt request from this slave port, level triggered, active high --> convert
logic [1:0] slv_irq;
logic [1:0] clear_irq;
axi_lite_mailbox_slave #(
.MailboxDepth ( MailboxDepth ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t ),
.addr_t ( addr_t ),
.data_t ( data_t ),
.usage_t ( usage_t ) // fill pointer from MBOX FIFO
) i_slv_port_0 (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
// slave port
.slv_req_i ( slv_reqs_i[0] ),
.slv_resp_o ( slv_resps_o[0] ),
.base_addr_i ( base_addr_i[0] ), // base address for the slave port
// write FIFO port
.mbox_w_data_o ( mbox_w_data[0] ),
.mbox_w_full_i ( mbox_full[0] ),
.mbox_w_push_o ( mbox_push[0] ),
.mbox_w_flush_o ( w_mbox_flush[0] ),
.mbox_w_usage_i ( mbox_usage[0] ),
// read FIFO port
.mbox_r_data_i ( mbox_r_data[0] ),
.mbox_r_empty_i ( mbox_empty[1] ),
.mbox_r_pop_o ( mbox_pop[0] ),
.mbox_r_flush_o ( r_mbox_flush[0] ),
.mbox_r_usage_i ( mbox_usage[1] ),
// interrupt output, level triggered, active high, conversion in top
.irq_o ( slv_irq[0] ),
.clear_irq_o ( clear_irq[0] )
);
axi_lite_mailbox_slave #(
.MailboxDepth ( MailboxDepth ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t ),
.addr_t ( addr_t ),
.data_t ( data_t ),
.usage_t ( usage_t ) // fill pointer from MBOX FIFO
) i_slv_port_1 (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
// slave port
.slv_req_i ( slv_reqs_i[1] ),
.slv_resp_o ( slv_resps_o[1] ),
.base_addr_i ( base_addr_i[1] ), // base address for the slave port
// write FIFO port
.mbox_w_data_o ( mbox_w_data[1] ),
.mbox_w_full_i ( mbox_full[1] ),
.mbox_w_push_o ( mbox_push[1] ),
.mbox_w_flush_o ( w_mbox_flush[1] ),
.mbox_w_usage_i ( mbox_usage[1] ),
// read FIFO port
.mbox_r_data_i ( mbox_r_data[1] ),
.mbox_r_empty_i ( mbox_empty[0] ),
.mbox_r_pop_o ( mbox_pop[1] ),
.mbox_r_flush_o ( r_mbox_flush[1] ),
.mbox_r_usage_i ( mbox_usage[0] ),
// interrupt output, level triggered, active high, conversion in top
.irq_o ( slv_irq[1] ),
.clear_irq_o ( clear_irq[1] )
);
// the usage gets concatinated with the full flag to have consistent threshold detection
logic [FifoUsageWidth-1:0] mbox_0_to_1_usage, mbox_1_to_0_usage;
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MailboxDepth ),
.dtype ( data_t )
) i_mbox_0_to_1 (
.clk_i,
.rst_ni,
.testmode_i( test_i ),
.flush_i ( w_mbox_flush[0] | r_mbox_flush[1] ),
.full_o ( mbox_full[0] ),
.empty_o ( mbox_empty[0] ),
.usage_o ( mbox_0_to_1_usage ),
.data_i ( mbox_w_data[0] ),
.push_i ( mbox_push[0] ),
.data_o ( mbox_r_data[1] ),
.pop_i ( mbox_pop[1] )
);
// assign the MSB of the FIFO to the correct usage signal
assign mbox_usage[0] = {mbox_full[0], mbox_0_to_1_usage};
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MailboxDepth ),
.dtype ( data_t )
) i_mbox_1_to_0 (
.clk_i,
.rst_ni,
.testmode_i( test_i ),
.flush_i ( w_mbox_flush[1] | r_mbox_flush[0] ),
.full_o ( mbox_full[1] ),
.empty_o ( mbox_empty[1] ),
.usage_o ( mbox_1_to_0_usage ),
.data_i ( mbox_w_data[1] ),
.push_i ( mbox_push[1] ),
.data_o ( mbox_r_data[0] ),
.pop_i ( mbox_pop[0] )
);
assign mbox_usage[1] = {mbox_full[1], mbox_1_to_0_usage};
for (genvar i = 0; i < 2; i++) begin : gen_irq_conversion
if (IrqEdgeTrig) begin : gen_irq_edge
logic irq_q, irq_d, update_irq;
always_comb begin
// default assignments
irq_d = irq_q;
update_irq = 1'b0;
// init the irq and pulse only on update
irq_o[i] = ~IrqActHigh;
if (clear_irq[i]) begin
irq_d = 1'b0;
update_irq = 1'b1;
end else if (!irq_q && slv_irq[i]) begin
irq_d = 1'b1;
update_irq = 1'b1;
irq_o[i] = IrqActHigh; // on update of the register pulse the irq signal
end
end
`FFLARN(irq_q, irq_d, update_irq, '0, clk_i, rst_ni)
end else begin : gen_irq_level
assign irq_o[i] = (IrqActHigh) ? slv_irq[i] : ~slv_irq[i];
end
end
// pragma translate_off
`ifndef VERILATOR
initial begin : proc_check_params
mailbox_depth: assert (MailboxDepth > 1) else $fatal(1, "MailboxDepth has to be at least 2");
axi_addr_width: assert (AxiAddrWidth > 0) else $fatal(1, "AxiAddrWidth has to be > 0");
axi_data_width: assert (AxiDataWidth > 0) else $fatal(1, "AxiDataWidth has to be > 0");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mailbox_slave #(
parameter int unsigned MailboxDepth = 32'd16,
parameter int unsigned AxiAddrWidth = 32'd32,
parameter int unsigned AxiDataWidth = 32'd32,
parameter type req_lite_t = logic,
parameter type resp_lite_t = logic,
parameter type addr_t = logic [AxiAddrWidth-1:0],
parameter type data_t = logic [AxiDataWidth-1:0],
parameter type usage_t = logic // fill pointer from MBOX FIFO
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// slave port
input req_lite_t slv_req_i,
output resp_lite_t slv_resp_o,
input addr_t base_addr_i, // base address for the slave port
// write FIFO port
output data_t mbox_w_data_o,
input logic mbox_w_full_i,
output logic mbox_w_push_o,
output logic mbox_w_flush_o,
input usage_t mbox_w_usage_i,
// read FIFO port
input data_t mbox_r_data_i,
input logic mbox_r_empty_i,
output logic mbox_r_pop_o,
output logic mbox_r_flush_o,
input usage_t mbox_r_usage_i,
// interrupt output, level triggered, active high, conversion in top
output logic irq_o,
output logic clear_irq_o // clear the edge trigger irq register in `axi_lite_mailbox`
);
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
localparam int unsigned NoRegs = 32'd10;
typedef enum logic [3:0] {
MBOXW = 4'd0, // Mailbox write register
MBOXR = 4'd1, // Mailbox read register
STATUS = 4'd2, // Mailbox status register
ERROR = 4'd3, // Mailbox error register
WIRQT = 4'd4, // Write interrupt request threshold register
RIRQT = 4'd5, // Read interrupt request threshold register
IRQS = 4'd6, // Interrupt request status register
IRQEN = 4'd7, // Interrupt request enable register
IRQP = 4'd8, // Interrupt request pending register
CTRL = 4'd9 // Mailbox control register
} reg_e;
// address map rule struct, as required from `addr_decode` from `common_cells`
typedef struct packed {
int unsigned idx;
addr_t start_addr;
addr_t end_addr;
} rule_t;
// output type of the address decoders, to be casted onto the enum type `reg_e`
typedef logic [$clog2(NoRegs)-1:0] idx_t;
// LITE response signals, go into the output spill registers to prevent combinational response
logic b_valid, b_ready;
b_chan_lite_t b_chan;
logic r_valid, r_ready;
r_chan_lite_t r_chan;
// address map generation
rule_t [NoRegs-1:0] addr_map;
for (genvar i = 0; i < NoRegs; i++) begin : gen_addr_map
assign addr_map[i] = '{
idx: i,
start_addr: base_addr_i + i * (AxiDataWidth / 8),
end_addr: base_addr_i + (i + 1) * (AxiDataWidth / 8),
default: '0
};
end
// address decode flags
idx_t w_reg_idx, r_reg_idx;
logic dec_w_valid, dec_r_valid;
// mailbox register signal declarations, get extended when read, some of these regs
// are build combinationally, indicated by the absence of the `*_d` signal
logic [3:0] status_q; // mailbox status register (read only)
logic [1:0] error_q, error_d; // mailbox error register
data_t wirqt_q, wirqt_d; // write interrupt request threshold register
data_t rirqt_q, rirqt_d; // read interrupt request threshold register
logic [2:0] irqs_q, irqs_d; // interrupt request status register
logic [2:0] irqen_q, irqen_d; // interrupt request enable register
logic [2:0] irqp_q; // interrupt request pending register (read only)
logic [1:0] ctrl_q; // mailbox control register
logic update_regs; // register enable signal
// register instantiation
`FFLARN(error_q, error_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(wirqt_q, wirqt_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(rirqt_q, rirqt_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(irqs_q, irqs_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(irqen_q, irqen_d, update_regs, '0, clk_i, rst_ni)
// Mailbox FIFO data assignments
for (genvar i = 0; i < (AxiDataWidth/8); i++) begin : gen_w_mbox_data
assign mbox_w_data_o[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : '0;
end
// combinational mailbox register assignments, for the read only registers
assign status_q = { mbox_r_usage_i > usage_t'(rirqt_q),
mbox_w_usage_i > usage_t'(wirqt_q),
mbox_w_full_i,
mbox_r_empty_i };
assign irqp_q = irqs_q & irqen_q; // interrupt request pending is bit wise and
assign ctrl_q = {mbox_r_flush_o, mbox_w_flush_o}; // read ctrl_q is flush signals
assign irq_o = |irqp_q; // generate an active-high level irq
always_comb begin
// slave port channel outputs for the AW, W and R channel, other driven from spill register
slv_resp_o.aw_ready = 1'b0;
slv_resp_o.w_ready = 1'b0;
b_chan = '{resp: axi_pkg::RESP_SLVERR};
b_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
r_chan = '{data: '0, resp: axi_pkg::RESP_SLVERR};
r_valid = 1'b0;
// Default assignments for the internal registers
error_d = error_q; // mailbox error register
wirqt_d = wirqt_q; // write interrupt request threshold register
rirqt_d = rirqt_q; // read interrupt request threshold register
irqs_d = irqs_q; // interrupt request status register
irqen_d = irqen_q; // interrupt request enable register
update_regs = 1'b0; // register update enable signal
// MBOX FIFO control signals
mbox_w_push_o = 1'b0;
mbox_w_flush_o = 1'b0;
mbox_r_pop_o = 1'b0;
mbox_r_flush_o = 1'b0;
// clear the edge triggered irq register if it is instantiated
clear_irq_o = 1'b0;
// -------------------------------------------
// Set the read and write interrupt FF (irqs), when the threshold triggers
// -------------------------------------------
// strict threshold interrupt these fields get cleared by acknowledge on write onto the register
// read trigger, see status_q above
if (!irqs_q[1] && status_q[3]) begin
irqs_d[1] = 1'b1;
update_regs = 1'b1;
end
// write trigger, see status_q above
if (!irqs_q[0] && status_q[2]) begin
irqs_d[0] = 1'b1;
update_regs = 1'b1;
end
// -------------------------------------------
// Read registers
// -------------------------------------------
// The logic of the read and write channels have to be in the same `always_comb` block.
// The reason is that the error register could be cleared in the same cycle as a read from
// the mailbox FIFO generates a new error. In this case the error is NOT cleared. Instead
// it will generate a new irq when it is edge triggered, or the level will stay at its
// active state.
// Check if there is a pending read request on the slave port.
if (slv_req_i.ar_valid) begin
// set the right read channel output depending on the address decoding
if (dec_r_valid) begin
// when decode not valid, send the default slaveerror
// read the right register when the transfer happens and decode is valid
unique case (reg_e'(r_reg_idx))
MBOXW: r_chan = '{data: data_t'( 32'hFEEDC0DE ), resp: axi_pkg::RESP_OKAY};
MBOXR: begin
if (!mbox_r_empty_i) begin
r_chan = '{data: data_t'( mbox_r_data_i ), resp: axi_pkg::RESP_OKAY};
mbox_r_pop_o = 1'b1;
end else begin
// read mailbox is empty, set the read error Flip flop and respond with error
r_chan = '{data: data_t'( 32'hFEEDDEAD ), resp: axi_pkg::RESP_SLVERR};
error_d[0] = 1'b1;
irqs_d[2] = 1'b1;
update_regs = 1'b1;
end
end
STATUS: r_chan = '{data: data_t'( status_q ), resp: axi_pkg::RESP_OKAY};
ERROR: begin // clear the error register
r_chan = '{data: data_t'( error_q ), resp: axi_pkg::RESP_OKAY};
error_d = '0;
update_regs = 1'b1;
end
WIRQT: r_chan = '{data: data_t'( wirqt_q ), resp: axi_pkg::RESP_OKAY};
RIRQT: r_chan = '{data: data_t'( rirqt_q ), resp: axi_pkg::RESP_OKAY};
IRQS: r_chan = '{data: data_t'( irqs_q ), resp: axi_pkg::RESP_OKAY};
IRQEN: r_chan = '{data: data_t'( irqen_q ), resp: axi_pkg::RESP_OKAY};
IRQP: r_chan = '{data: data_t'( irqp_q ), resp: axi_pkg::RESP_OKAY};
CTRL: r_chan = '{data: data_t'( ctrl_q ), resp: axi_pkg::RESP_OKAY};
default: /*do nothing*/;
endcase
end
r_valid = 1'b1;
if (r_ready) begin
slv_resp_o.ar_ready = 1'b1;
end
end // read register
// -------------------------------------------
// Write registers
// -------------------------------------------
// Wait for control and write data to be valid.
if (slv_req_i.aw_valid && slv_req_i.w_valid) begin
// Can do the handshake here as the b response goes into a spill register with latency one.
// Without the B spill register, the B channel would violate the AXI stable requirement.
b_valid = 1'b1;
if (b_ready) begin
// write to the register if required
if (dec_w_valid) begin
unique case (reg_e'(w_reg_idx))
MBOXW: begin
if (!mbox_w_full_i) begin
mbox_w_push_o = 1'b1;
b_chan = '{resp: axi_pkg::RESP_OKAY};
end else begin
// response with default error and set the error FF
error_d[1] = 1'b1;
irqs_d[2] = 1'b1;
update_regs = 1'b1;
end
end
// MBOXR: read only
// STATUS: read only
// ERROR: read only
WIRQT: begin
for (int unsigned i = 0; i < AxiDataWidth/8; i++) begin
wirqt_d[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : 8'b0000_0000;
end
if (wirqt_d >= data_t'(MailboxDepth)) begin
// the `-1` is to have the interrupt fireing when the FIFO is comletely full
wirqt_d = data_t'(MailboxDepth) - data_t'(32'd1); // Threshold to maximal value
end
update_regs = 1'b1;
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
RIRQT: begin
for (int unsigned i = 0; i < AxiDataWidth/8; i++) begin
rirqt_d[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : 8'b0000_0000;
end
if (rirqt_d >= data_t'(MailboxDepth)) begin
// Threshold to maximal value, minus two to prevent overflow in usage
rirqt_d = data_t'(MailboxDepth) - data_t'(32'd1);
end
update_regs = 1'b1;
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
IRQS: begin
// Acknowledge and clear the register by asserting the respective one
if (slv_req_i.w.strb[0]) begin
// *_d signal is set in the beginning of this process, prevent accidental
// overwrite of not acknowledged irq
irqs_d[2] = slv_req_i.w.data[2] ? 1'b0 : irqs_d[2]; // Error irq status
irqs_d[1] = slv_req_i.w.data[1] ? 1'b0 : irqs_d[1]; // Read irq status
irqs_d[0] = slv_req_i.w.data[0] ? 1'b0 : irqs_d[0]; // Write irq status
clear_irq_o = 1'b1;
update_regs = 1'b1;
end
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
IRQEN: begin
if (slv_req_i.w.strb[0]) begin
irqen_d[2:0] = slv_req_i.w.data[2:0]; // set the irq enable bits
update_regs = 1'b1;
end
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
// IRQP: read only
CTRL: begin
if (slv_req_i.w.strb[0]) begin
mbox_r_flush_o = slv_req_i.w.data[1]; // Flush read FIFO
mbox_w_flush_o = slv_req_i.w.data[0]; // Flush write FIFO
end
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
default : /* use default b_chan */;
endcase
end
slv_resp_o.aw_ready = 1'b1;
slv_resp_o.w_ready = 1'b1;
end // if (b_ready): Does not violate AXI spec, because the ready comes from an internal
// spill register and does not propagate the ready from the b channel.
end // write register
end
// address decoder and response FIFOs for the LITE channel, the port can take a new transaction if
// these FIFOs are not full, not fall through to prevent combinational paths to the return path
addr_decode #(
.NoIndices( NoRegs ),
.NoRules ( NoRegs ),
.addr_t ( addr_t ),
.rule_t ( rule_t )
) i_waddr_decode (
.addr_i ( slv_req_i.aw.addr ),
.addr_map_i ( addr_map ),
.idx_o ( w_reg_idx ),
.dec_valid_o ( dec_w_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( 1'b0 ),
.default_idx_i ( '0 )
);
spill_register #(
.T ( b_chan_lite_t )
) i_b_chan_outp (
.clk_i,
.rst_ni,
.valid_i ( b_valid ),
.ready_o ( b_ready ),
.data_i ( b_chan ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
addr_decode #(
.NoIndices( NoRegs ),
.NoRules ( NoRegs ),
.addr_t ( addr_t ),
.rule_t ( rule_t )
) i_raddr_decode (
.addr_i ( slv_req_i.ar.addr ),
.addr_map_i ( addr_map ),
.idx_o ( r_reg_idx ),
.dec_valid_o ( dec_r_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( 1'b0 ),
.default_idx_i ( '0 )
);
spill_register #(
.T ( r_chan_lite_t )
) i_r_chan_outp (
.clk_i,
.rst_ni,
.valid_i ( r_valid ),
.ready_o ( r_ready ),
.data_i ( r_chan ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
// pragma translate_off
`ifndef VERILATOR
initial begin : proc_check_params
assert (AxiAddrWidth == $bits(slv_req_i.aw.addr)) else $fatal(1, "AW AxiAddrWidth mismatch");
assert (AxiDataWidth == $bits(slv_req_i.w.data)) else $fatal(1, " W AxiDataWidth mismatch");
assert (AxiAddrWidth == $bits(slv_req_i.ar.addr)) else $fatal(1, "AR AxiAddrWidth mismatch");
assert (AxiDataWidth == $bits(slv_resp_o.r.data)) else $fatal(1, " R AxiDataWidth mismatch");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mailbox_intf #(
parameter int unsigned MAILBOX_DEPTH = 32'd0,
parameter bit unsigned IRQ_EDGE_TRIG = 1'b0,
parameter bit unsigned IRQ_ACT_HIGH = 1'b1,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
// DEPENDENT PARAMETERS, DO NOT OVERRIDE!
parameter type addr_t = logic [AXI_ADDR_WIDTH-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
AXI_LITE.Slave slv [1:0], // slave ports [1:0]
output logic [1:0] irq_o, // interrupt output for each port
input addr_t [1:0] base_addr_i // base address for each port
);
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t)
req_lite_t [1:0] slv_reqs;
resp_lite_t [1:0] slv_resps;
for (genvar i = 0; i < 2; i++) begin : gen_port_assign
`AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
`AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
end
axi_lite_mailbox #(
.MailboxDepth ( MAILBOX_DEPTH ),
.IrqEdgeTrig ( IRQ_EDGE_TRIG ),
.IrqActHigh ( IRQ_ACT_HIGH ),
.AxiAddrWidth ( AXI_ADDR_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t )
) i_axi_lite_mailbox (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
// slave ports [1:0]
.slv_reqs_i ( slv_reqs ),
.slv_resps_o ( slv_resps ),
.irq_o, // interrupt output for each port
.base_addr_i // base address for each port
);
// pragma translate_off
`ifndef VERILATOR
initial begin
assert (slv[0].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH)
else $fatal(1, "LITE Interface [0] AXI_ADDR_WIDTH missmatch!");
assert (slv[1].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH)
else $fatal(1, "LITE Interface [1] AXI_ADDR_WIDTH missmatch!");
assert (slv[0].AXI_DATA_WIDTH == AXI_DATA_WIDTH)
else $fatal(1, "LITE Interface [0] AXI_DATA_WIDTH missmatch!");
assert (slv[1].AXI_DATA_WIDTH == AXI_DATA_WIDTH)
else $fatal(1, "LITE Interface [1] AXI_DATA_WIDTH missmatch!");
end
`endif
// pragma translate_on
endmodule |
module axi_cdc_src #(
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LogDepth = 1,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
) (
// synchronous slave port - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
input axi_req_t src_req_i,
output axi_resp_t src_resp_o,
// asynchronous master port
output aw_chan_t [2**LogDepth-1:0] async_data_master_aw_data_o,
output logic [LogDepth:0] async_data_master_aw_wptr_o,
input logic [LogDepth:0] async_data_master_aw_rptr_i,
output w_chan_t [2**LogDepth-1:0] async_data_master_w_data_o,
output logic [LogDepth:0] async_data_master_w_wptr_o,
input logic [LogDepth:0] async_data_master_w_rptr_i,
input b_chan_t [2**LogDepth-1:0] async_data_master_b_data_i,
input logic [LogDepth:0] async_data_master_b_wptr_i,
output logic [LogDepth:0] async_data_master_b_rptr_o,
output ar_chan_t [2**LogDepth-1:0] async_data_master_ar_data_o,
output logic [LogDepth:0] async_data_master_ar_wptr_o,
input logic [LogDepth:0] async_data_master_ar_rptr_i,
input r_chan_t [2**LogDepth-1:0] async_data_master_r_data_i,
input logic [LogDepth:0] async_data_master_r_wptr_i,
output logic [LogDepth:0] async_data_master_r_rptr_o
);
cdc_fifo_gray_src #(
.T ( logic [$bits(aw_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_aw (
.src_clk_i,
.src_rst_ni,
.src_data_i ( src_req_i.aw ),
.src_valid_i ( src_req_i.aw_valid ),
.src_ready_o ( src_resp_o.aw_ready ),
.async_data_o ( async_data_master_aw_data_o ),
.async_wptr_o ( async_data_master_aw_wptr_o ),
.async_rptr_i ( async_data_master_aw_rptr_i )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(w_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_w (
.src_clk_i,
.src_rst_ni,
.src_data_i ( src_req_i.w ),
.src_valid_i ( src_req_i.w_valid ),
.src_ready_o ( src_resp_o.w_ready ),
.async_data_o ( async_data_master_w_data_o ),
.async_wptr_o ( async_data_master_w_wptr_o ),
.async_rptr_i ( async_data_master_w_rptr_i )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(b_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_b (
.dst_clk_i ( src_clk_i ),
.dst_rst_ni ( src_rst_ni ),
.dst_data_o ( src_resp_o.b ),
.dst_valid_o ( src_resp_o.b_valid ),
.dst_ready_i ( src_req_i.b_ready ),
.async_data_i ( async_data_master_b_data_i ),
.async_wptr_i ( async_data_master_b_wptr_i ),
.async_rptr_o ( async_data_master_b_rptr_o )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(ar_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_ar (
.src_clk_i,
.src_rst_ni,
.src_data_i ( src_req_i.ar ),
.src_valid_i ( src_req_i.ar_valid ),
.src_ready_o ( src_resp_o.ar_ready ),
.async_data_o ( async_data_master_ar_data_o ),
.async_wptr_o ( async_data_master_ar_wptr_o ),
.async_rptr_i ( async_data_master_ar_rptr_i )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(r_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_r (
.dst_clk_i ( src_clk_i ),
.dst_rst_ni ( src_rst_ni ),
.dst_data_o ( src_resp_o.r ),
.dst_valid_o ( src_resp_o.r_valid ),
.dst_ready_i ( src_req_i.r_ready ),
.async_data_i ( async_data_master_r_data_i ),
.async_wptr_i ( async_data_master_r_wptr_i ),
.async_rptr_o ( async_data_master_r_rptr_o )
);
endmodule |
module axi_cdc_src_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// synchronous slave port - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_BUS.Slave src,
// asynchronous master port
AXI_BUS_ASYNC_GRAY.Master dst
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req;
resp_t src_resp;
`AXI_ASSIGN_TO_REQ(src_req, src)
`AXI_ASSIGN_FROM_RESP(src, src_resp)
axi_cdc_src #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_src (
.src_clk_i,
.src_rst_ni,
.src_req_i ( src_req ),
.src_resp_o ( src_resp ),
.async_data_master_aw_data_o ( dst.aw_data ),
.async_data_master_aw_wptr_o ( dst.aw_wptr ),
.async_data_master_aw_rptr_i ( dst.aw_rptr ),
.async_data_master_w_data_o ( dst.w_data ),
.async_data_master_w_wptr_o ( dst.w_wptr ),
.async_data_master_w_rptr_i ( dst.w_rptr ),
.async_data_master_b_data_i ( dst.b_data ),
.async_data_master_b_wptr_i ( dst.b_wptr ),
.async_data_master_b_rptr_o ( dst.b_rptr ),
.async_data_master_ar_data_o ( dst.ar_data ),
.async_data_master_ar_wptr_o ( dst.ar_wptr ),
.async_data_master_ar_rptr_i ( dst.ar_rptr ),
.async_data_master_r_data_i ( dst.r_data ),
.async_data_master_r_wptr_i ( dst.r_wptr ),
.async_data_master_r_rptr_o ( dst.r_rptr )
);
endmodule |
module axi_lite_cdc_src_intf #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// synchronous slave port - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_BUS.Slave src,
// asynchronous master port
AXI_LITE_ASYNC_GRAY.Master dst
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req;
resp_t src_resp;
`AXI_LITE_ASSIGN_TO_REQ(src_req, src)
`AXI_LITE_ASSIGN_FROM_RESP(src, src_resp)
axi_cdc_src #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_src (
.src_clk_i,
.src_rst_ni,
.src_req_o ( src_req ),
.src_resp_i ( src_resp ),
.async_data_master_aw_data_o ( dst.aw_data ),
.async_data_master_aw_wptr_o ( dst.aw_wptr ),
.async_data_master_aw_rptr_i ( dst.aw_rptr ),
.async_data_master_w_data_o ( dst.w_data ),
.async_data_master_w_wptr_o ( dst.w_wptr ),
.async_data_master_w_rptr_i ( dst.w_rptr ),
.async_data_master_b_data_i ( dst.b_data ),
.async_data_master_b_wptr_i ( dst.b_wptr ),
.async_data_master_b_rptr_o ( dst.b_rptr ),
.async_data_master_ar_data_o ( dst.ar_data ),
.async_data_master_ar_wptr_o ( dst.ar_wptr ),
.async_data_master_ar_rptr_i ( dst.ar_rptr ),
.async_data_master_r_data_i ( dst.r_data ),
.async_data_master_r_wptr_i ( dst.r_wptr ),
.async_data_master_r_rptr_o ( dst.r_rptr )
);
endmodule |
module axi_cdc_dst #(
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LogDepth = 1,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
) (
// asynchronous slave port
input aw_chan_t [2**LogDepth-1:0] async_data_slave_aw_data_i,
input logic [LogDepth:0] async_data_slave_aw_wptr_i,
output logic [LogDepth:0] async_data_slave_aw_rptr_o,
input w_chan_t [2**LogDepth-1:0] async_data_slave_w_data_i,
input logic [LogDepth:0] async_data_slave_w_wptr_i,
output logic [LogDepth:0] async_data_slave_w_rptr_o,
output b_chan_t [2**LogDepth-1:0] async_data_slave_b_data_o,
output logic [LogDepth:0] async_data_slave_b_wptr_o,
input logic [LogDepth:0] async_data_slave_b_rptr_i,
input ar_chan_t [2**LogDepth-1:0] async_data_slave_ar_data_i,
input logic [LogDepth:0] async_data_slave_ar_wptr_i,
output logic [LogDepth:0] async_data_slave_ar_rptr_o,
output r_chan_t [2**LogDepth-1:0] async_data_slave_r_data_o,
output logic [LogDepth:0] async_data_slave_r_wptr_o,
input logic [LogDepth:0] async_data_slave_r_rptr_i,
// synchronous master port - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
output axi_req_t dst_req_o,
input axi_resp_t dst_resp_i
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(aw_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_aw (
.async_data_i ( async_data_slave_aw_data_i ),
.async_wptr_i ( async_data_slave_aw_wptr_i ),
.async_rptr_o ( async_data_slave_aw_rptr_o ),
.dst_clk_i,
.dst_rst_ni,
.dst_data_o ( dst_req_o.aw ),
.dst_valid_o ( dst_req_o.aw_valid ),
.dst_ready_i ( dst_resp_i.aw_ready )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(w_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_w (
.async_data_i ( async_data_slave_w_data_i ),
.async_wptr_i ( async_data_slave_w_wptr_i ),
.async_rptr_o ( async_data_slave_w_rptr_o ),
.dst_clk_i,
.dst_rst_ni,
.dst_data_o ( dst_req_o.w ),
.dst_valid_o ( dst_req_o.w_valid ),
.dst_ready_i ( dst_resp_i.w_ready )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(b_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_b (
.src_clk_i ( dst_clk_i ),
.src_rst_ni ( dst_rst_ni ),
.src_data_i ( dst_resp_i.b ),
.src_valid_i ( dst_resp_i.b_valid ),
.src_ready_o ( dst_req_o.b_ready ),
.async_data_o ( async_data_slave_b_data_o ),
.async_wptr_o ( async_data_slave_b_wptr_o ),
.async_rptr_i ( async_data_slave_b_rptr_i )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(ar_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_ar (
.dst_clk_i,
.dst_rst_ni,
.dst_data_o ( dst_req_o.ar ),
.dst_valid_o ( dst_req_o.ar_valid ),
.dst_ready_i ( dst_resp_i.ar_ready ),
.async_data_i ( async_data_slave_ar_data_i ),
.async_wptr_i ( async_data_slave_ar_wptr_i ),
.async_rptr_o ( async_data_slave_ar_rptr_o )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(r_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_r (
.src_clk_i ( dst_clk_i ),
.src_rst_ni ( dst_rst_ni ),
.src_data_i ( dst_resp_i.r ),
.src_valid_i ( dst_resp_i.r_valid ),
.src_ready_o ( dst_req_o.r_ready ),
.async_data_o ( async_data_slave_r_data_o ),
.async_wptr_o ( async_data_slave_r_wptr_o ),
.async_rptr_i ( async_data_slave_r_rptr_i )
);
endmodule |
module axi_cdc_dst_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// asynchronous slave port
AXI_BUS_ASYNC_GRAY.Slave src,
// synchronous master port - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_BUS.Master dst
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t dst_req;
resp_t dst_resp;
axi_cdc_dst #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_dst (
.async_data_slave_aw_data_i ( src.aw_data ),
.async_data_slave_aw_wptr_i ( src.aw_wptr ),
.async_data_slave_aw_rptr_o ( src.aw_rptr ),
.async_data_slave_w_data_i ( src.w_data ),
.async_data_slave_w_wptr_i ( src.w_wptr ),
.async_data_slave_w_rptr_o ( src.w_rptr ),
.async_data_slave_b_data_o ( src.b_data ),
.async_data_slave_b_wptr_o ( src.b_wptr ),
.async_data_slave_b_rptr_i ( src.b_rptr ),
.async_data_slave_ar_data_i ( src.ar_data ),
.async_data_slave_ar_wptr_i ( src.ar_wptr ),
.async_data_slave_ar_rptr_o ( src.ar_rptr ),
.async_data_slave_r_data_o ( src.r_data ),
.async_data_slave_r_wptr_o ( src.r_wptr ),
.async_data_slave_r_rptr_i ( src.r_rptr ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
`AXI_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_ASSIGN_TO_RESP(dst_resp, dst)
endmodule |
module axi_lite_cdc_dst_intf #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// asynchronous slave port
AXI_LITE_ASYNC_GRAY.Slave src,
// synchronous master port - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_LITE.Master dst
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t dst_req;
resp_t dst_resp;
axi_cdc_dst #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_dst (
.async_data_slave_aw_data_i ( src.aw_data ),
.async_data_slave_aw_wptr_i ( src.aw_wptr ),
.async_data_slave_aw_rptr_o ( src.aw_rptr ),
.async_data_slave_w_data_i ( src.w_data ),
.async_data_slave_w_wptr_i ( src.w_wptr ),
.async_data_slave_w_rptr_o ( src.w_rptr ),
.async_data_slave_b_data_o ( src.b_data ),
.async_data_slave_b_wptr_o ( src.b_wptr ),
.async_data_slave_b_rptr_i ( src.b_rptr ),
.async_data_slave_ar_data_i ( src.ar_data ),
.async_data_slave_ar_wptr_i ( src.ar_wptr ),
.async_data_slave_ar_rptr_o ( src.ar_rptr ),
.async_data_slave_r_data_o ( src.r_data ),
.async_data_slave_r_wptr_o ( src.r_wptr ),
.async_data_slave_r_rptr_i ( src.r_rptr ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
`AXI_LITE_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst)
endmodule |
module axi_serializer #(
/// Maximum number of in flight read transactions.
parameter int unsigned MaxReadTxns = 32'd0,
/// Maximum number of in flight write transactions.
parameter int unsigned MaxWriteTxns = 32'd0,
/// AXI4+ATOP ID width.
parameter int unsigned AxiIdWidth = 32'd0,
/// AXI4+ATOP request struct definition.
parameter type req_t = logic,
/// AXI4+ATOP response struct definition.
parameter type resp_t = logic
) (
/// Clock
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// Slave port request
input req_t slv_req_i,
/// Slave port response
output resp_t slv_resp_o,
/// Master port request
output req_t mst_req_o,
/// Master port response
input resp_t mst_resp_i
);
typedef logic [AxiIdWidth-1:0] id_t;
typedef enum logic [1:0] {
AtopIdle = 2'b00,
AtopDrain = 2'b01,
AtopExecute = 2'b10
} state_e;
logic rd_fifo_full, rd_fifo_empty, rd_fifo_push, rd_fifo_pop,
wr_fifo_full, wr_fifo_empty, wr_fifo_push, wr_fifo_pop;
id_t b_id,
r_id, ar_id;
state_e state_q, state_d;
always_comb begin
// Default assignments
state_d = state_q;
rd_fifo_push = 1'b0;
wr_fifo_push = 1'b0;
// Default, connect the channels
mst_req_o = slv_req_i;
slv_resp_o = mst_resp_i;
// Serialize transactions -> tie downstream IDs to zero.
mst_req_o.aw.id = '0;
mst_req_o.ar.id = '0;
// Reflect upstream ID in response.
ar_id = slv_req_i.ar.id;
slv_resp_o.b.id = b_id;
slv_resp_o.r.id = r_id;
// Default, cut the AW/AR handshaking
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
unique case (state_q)
AtopIdle, AtopExecute: begin
// Wait until the ATOP response(s) have been sent back upstream.
if (state_q == AtopExecute) begin
if ((wr_fifo_empty && rd_fifo_empty) || (wr_fifo_pop && rd_fifo_pop) ||
(wr_fifo_empty && rd_fifo_pop) || (wr_fifo_pop && rd_fifo_empty)) begin
state_d = AtopIdle;
end
end
// This part lets new Transactions through, if no ATOP is underway or the last ATOP
// response has been transmitted.
if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin
// Gate AR handshake with ready output of Read FIFO.
mst_req_o.ar_valid = slv_req_i.ar_valid & ~rd_fifo_full;
slv_resp_o.ar_ready = mst_resp_i.ar_ready & ~rd_fifo_full;
rd_fifo_push = mst_req_o.ar_valid & mst_resp_i.ar_ready;
if (slv_req_i.aw_valid) begin
if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin
// Normal operation
// Gate AW handshake with ready output of Write FIFO.
mst_req_o.aw_valid = ~wr_fifo_full;
slv_resp_o.aw_ready = mst_resp_i.aw_ready & ~wr_fifo_full;
wr_fifo_push = mst_req_o.aw_valid & mst_resp_i.aw_ready;
end else begin
// Atomic Operation received, go to drain state, when both channels are ready
// Wait for finished or no AR beat
if (!mst_req_o.ar_valid || (mst_req_o.ar_valid && mst_resp_i.ar_ready)) begin
state_d = AtopDrain;
end
end
end
end
end
AtopDrain: begin
// Send the ATOP AW when the last open transaction terminates
if (wr_fifo_empty && rd_fifo_empty) begin
mst_req_o.aw_valid = 1'b1;
slv_resp_o.aw_ready = mst_resp_i.aw_ready;
wr_fifo_push = mst_resp_i.aw_ready;
if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
// Overwrite the read ID with the one from AW
ar_id = slv_req_i.aw.id;
rd_fifo_push = mst_resp_i.aw_ready;
end
if (mst_resp_i.aw_ready) begin
state_d = AtopExecute;
end
end
end
default : /* do nothing */;
endcase
// Gate B handshake with empty flag output of Write FIFO.
slv_resp_o.b_valid = mst_resp_i.b_valid & ~wr_fifo_empty;
mst_req_o.b_ready = slv_req_i.b_ready & ~wr_fifo_empty;
// Gate R handshake with empty flag output of Read FIFO.
slv_resp_o.r_valid = mst_resp_i.r_valid & ~rd_fifo_empty;
mst_req_o.r_ready = slv_req_i.r_ready & ~rd_fifo_empty;
end
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ), // No fall-through as response has to come a cycle later anyway
.DEPTH ( MaxReadTxns ),
.dtype ( id_t )
) i_rd_id_fifo (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ( ar_id ),
.push_i ( rd_fifo_push ),
.full_o ( rd_fifo_full ),
.data_o ( r_id ),
.empty_o ( rd_fifo_empty ),
.pop_i ( rd_fifo_pop ),
.usage_o ( /*not used*/ )
);
// Assign as this condition is needed in FSM
assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last;
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MaxWriteTxns ),
.dtype ( id_t )
) i_wr_id_fifo (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ( slv_req_i.aw.id ),
.push_i ( wr_fifo_push ),
.full_o ( wr_fifo_full ),
.data_o ( b_id ),
.empty_o ( wr_fifo_empty ),
.pop_i ( wr_fifo_pop ),
.usage_o ( /*not used*/ )
);
// Assign as this condition is needed in FSM
assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready;
`FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (AxiIdWidth >= 1) else $fatal(1, "AXI ID width must be at least 1!");
assert (MaxReadTxns >= 1)
else $fatal(1, "Maximum number of read transactions must be >= 1!");
assert (MaxWriteTxns >= 1)
else $fatal(1, "Maximum number of write transactions must be >= 1!");
end
default disable iff (~rst_ni);
aw_lost : assert property( @(posedge clk_i)
(slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready))
else $error("AW beat lost.");
w_lost : assert property( @(posedge clk_i)
(slv_req_i.w_valid & slv_resp_o.w_ready |-> mst_req_o.w_valid & mst_resp_i.w_ready))
else $error("W beat lost.");
b_lost : assert property( @(posedge clk_i)
(mst_resp_i.b_valid & mst_req_o.b_ready |-> slv_resp_o.b_valid & slv_req_i.b_ready))
else $error("B beat lost.");
ar_lost : assert property( @(posedge clk_i)
(slv_req_i.ar_valid & slv_resp_o.ar_ready |-> mst_req_o.ar_valid & mst_resp_i.ar_ready))
else $error("AR beat lost.");
r_lost : assert property( @(posedge clk_i)
(mst_resp_i.r_valid & mst_req_o.r_ready |-> slv_resp_o.r_valid & slv_req_i.r_ready))
else $error("R beat lost.");
`endif
// pragma translate_on
endmodule |
module axi_serializer_intf #(
/// AXI4+ATOP ID width.
parameter int unsigned AXI_ID_WIDTH = 32'd0,
/// AXI4+ATOP address width.
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
/// AXI4+ATOP data width.
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
/// AXI4+ATOP user width.
parameter int unsigned AXI_USER_WIDTH = 32'd0,
/// Maximum number of in flight read transactions.
parameter int unsigned MAX_READ_TXNS = 32'd0,
/// Maximum number of in flight write transactions.
parameter int unsigned MAX_WRITE_TXNS = 32'd0
) (
/// Clock
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// AXI4+ATOP Slave modport
AXI_BUS.Slave slv,
/// AXI4+ATOP Master modport
AXI_BUS.Master mst
);
typedef logic [AXI_ID_WIDTH -1:0] id_t;
typedef logic [AXI_ADDR_WIDTH -1:0] addr_t;
typedef logic [AXI_DATA_WIDTH -1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH -1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)
axi_serializer #(
.MaxReadTxns ( MAX_READ_TXNS ),
.MaxWriteTxns ( MAX_WRITE_TXNS ),
.AxiIdWidth ( AXI_ID_WIDTH ),
.req_t ( req_t ),
.resp_t ( resp_t )
) i_axi_serializer (
.clk_i,
.rst_ni,
.slv_req_i ( slv_req ),
.slv_resp_o ( slv_resp ),
.mst_req_o ( mst_req ),
.mst_resp_i ( mst_resp )
);
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI address width must be at least 1!");
assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI data width must be at least 1!");
assert (AXI_ID_WIDTH >= 1) else $fatal(1, "AXI ID width must be at least 1!");
assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!");
assert (MAX_READ_TXNS >= 1)
else $fatal(1, "Maximum number of read transactions must be >= 1!");
assert (MAX_WRITE_TXNS >= 1)
else $fatal(1, "Maximum number of write transactions must be >= 1!");
end
`endif
// pragma translate_on
endmodule |
module axi_cdc #(
parameter type aw_chan_t = logic, // AW Channel Type
parameter type w_chan_t = logic, // W Channel Type
parameter type b_chan_t = logic, // B Channel Type
parameter type ar_chan_t = logic, // AR Channel Type
parameter type r_chan_t = logic, // R Channel Type
parameter type axi_req_t = logic, // encapsulates request channels
parameter type axi_resp_t = logic, // encapsulates request channels
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LogDepth = 1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
input axi_req_t src_req_i,
output axi_resp_t src_resp_o,
// master side - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
output axi_req_t dst_req_o,
input axi_resp_t dst_resp_i
);
aw_chan_t [2**LogDepth-1:0] async_data_aw_data;
w_chan_t [2**LogDepth-1:0] async_data_w_data;
b_chan_t [2**LogDepth-1:0] async_data_b_data;
ar_chan_t [2**LogDepth-1:0] async_data_ar_data;
r_chan_t [2**LogDepth-1:0] async_data_r_data;
logic [LogDepth:0] async_data_aw_wptr, async_data_aw_rptr,
async_data_w_wptr, async_data_w_rptr,
async_data_b_wptr, async_data_b_rptr,
async_data_ar_wptr, async_data_ar_rptr,
async_data_r_wptr, async_data_r_rptr;
axi_cdc_src #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.LogDepth ( LogDepth )
) i_axi_cdc_src (
.src_clk_i,
.src_rst_ni,
.src_req_i,
.src_resp_o,
(* async *) .async_data_master_aw_data_o ( async_data_aw_data ),
(* async *) .async_data_master_aw_wptr_o ( async_data_aw_wptr ),
(* async *) .async_data_master_aw_rptr_i ( async_data_aw_rptr ),
(* async *) .async_data_master_w_data_o ( async_data_w_data ),
(* async *) .async_data_master_w_wptr_o ( async_data_w_wptr ),
(* async *) .async_data_master_w_rptr_i ( async_data_w_rptr ),
(* async *) .async_data_master_b_data_i ( async_data_b_data ),
(* async *) .async_data_master_b_wptr_i ( async_data_b_wptr ),
(* async *) .async_data_master_b_rptr_o ( async_data_b_rptr ),
(* async *) .async_data_master_ar_data_o ( async_data_ar_data ),
(* async *) .async_data_master_ar_wptr_o ( async_data_ar_wptr ),
(* async *) .async_data_master_ar_rptr_i ( async_data_ar_rptr ),
(* async *) .async_data_master_r_data_i ( async_data_r_data ),
(* async *) .async_data_master_r_wptr_i ( async_data_r_wptr ),
(* async *) .async_data_master_r_rptr_o ( async_data_r_rptr )
);
axi_cdc_dst #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.LogDepth ( LogDepth )
) i_axi_cdc_dst (
.dst_clk_i,
.dst_rst_ni,
.dst_req_o,
.dst_resp_i,
(* async *) .async_data_slave_aw_wptr_i ( async_data_aw_wptr ),
(* async *) .async_data_slave_aw_rptr_o ( async_data_aw_rptr ),
(* async *) .async_data_slave_aw_data_i ( async_data_aw_data ),
(* async *) .async_data_slave_w_wptr_i ( async_data_w_wptr ),
(* async *) .async_data_slave_w_rptr_o ( async_data_w_rptr ),
(* async *) .async_data_slave_w_data_i ( async_data_w_data ),
(* async *) .async_data_slave_b_wptr_o ( async_data_b_wptr ),
(* async *) .async_data_slave_b_rptr_i ( async_data_b_rptr ),
(* async *) .async_data_slave_b_data_o ( async_data_b_data ),
(* async *) .async_data_slave_ar_wptr_i ( async_data_ar_wptr ),
(* async *) .async_data_slave_ar_rptr_o ( async_data_ar_rptr ),
(* async *) .async_data_slave_ar_data_i ( async_data_ar_data ),
(* async *) .async_data_slave_r_wptr_o ( async_data_r_wptr ),
(* async *) .async_data_slave_r_rptr_i ( async_data_r_rptr ),
(* async *) .async_data_slave_r_data_o ( async_data_r_data )
);
endmodule |
module axi_cdc_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_BUS.Slave src,
// master side - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_BUS.Master dst
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req, dst_req;
resp_t src_resp, dst_resp;
`AXI_ASSIGN_TO_REQ(src_req, src)
`AXI_ASSIGN_FROM_RESP(src, src_resp)
`AXI_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_ASSIGN_TO_RESP(dst_resp, dst)
axi_cdc #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc (
.src_clk_i,
.src_rst_ni,
.src_req_i ( src_req ),
.src_resp_o ( src_resp ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
endmodule |
module axi_lite_cdc_intf #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_LITE.Slave src,
// master side - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_LITE.Master dst
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req, dst_req;
resp_t src_resp, dst_resp;
`AXI_LITE_ASSIGN_TO_REQ(src_req, src)
`AXI_LITE_ASSIGN_FROM_RESP(src, src_resp)
`AXI_LITE_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst)
axi_cdc #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc (
.src_clk_i,
.src_rst_ni,
.src_req_i ( src_req ),
.src_resp_o ( src_resp ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
endmodule |
module axi_lite_regs #(
/// The size of the register field in bytes.
parameter int unsigned RegNumBytes = 32'd0,
/// Address width of the AXI4-Lite port.
///
/// The minimum value of this parameter is `$clog2(RegNumBytes)`.
parameter int unsigned AxiAddrWidth = 32'd0,
/// Data width of the AXI4-Lite port.
parameter int unsigned AxiDataWidth = 32'd0,
/// Only allow *privileged* accesses on the AXI4-Lite port.
///
/// If this parameter is set to `1`, this module only allows reads and writes that have the
/// `AxProt[0]` bit set. If a transaction does not have the `AxProt[0]` bit set, this module
/// replies with `SLVERR` and does not read or write register data.
parameter bit PrivProtOnly = 1'b0,
/// Only allow *secure* accesses on the AXI4-Lite port.
///
/// If this parameter is set to `1`, this module only allows reads and writes that have the
/// `AxProt[1]` bit set. If a transaction does not have the `AxProt[1]` bit set, this module
/// replies with `SLVERR` and does not read or write register data.
parameter bit SecuProtOnly = 1'b0,
/// Define individual bytes as *read-only from the AXI4-Lite port*.
///
/// This parameter is an array with one bit for each byte. If that bit is `0`, the byte can be
/// read and written on the AXI4-Lite port; if that bit is `1`, the byte can only be read on the
/// AXI4-Lite port.
parameter logic [RegNumBytes-1:0] AxiReadOnly = {RegNumBytes{1'b0}},
/// Constant (=**do not overwrite!**); type of a byte is 8 bit.
parameter type byte_t = logic [7:0],
/// Reset value for the whole register array.
///
/// This parameter is an array with one byte value for each byte. At reset, each byte is
/// assigned its value from this array.
parameter byte_t [RegNumBytes-1:0] RegRstVal = {RegNumBytes{8'h00}},
/// Request struct of the AXI4-Lite port.
parameter type req_lite_t = logic,
/// Response struct of the AXI4-Lite port.
parameter type resp_lite_t = logic
) (
/// Rising-edge clock of all ports
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// AXI4-Lite slave request
input req_lite_t axi_req_i,
/// AXI4-Lite slave response
output resp_lite_t axi_resp_o,
/// Signals that a byte is being written from the AXI4-Lite port in the current clock cycle. This
/// signal is asserted regardless of the value of `AxiReadOnly` and can therefore be used by
/// surrounding logic to react to write-on-read-only-byte errors.
output logic [RegNumBytes-1:0] wr_active_o,
/// Signals that a byte is being read from the AXI4-Lite port in the current clock cycle.
output logic [RegNumBytes-1:0] rd_active_o,
/// Input value of each byte. If `reg_load_i` is `1` for a byte in the current clock cycle, the
/// byte register in this module is set to the value of the byte in `reg_d_i` at the next clock
/// edge.
input byte_t [RegNumBytes-1:0] reg_d_i,
/// Load enable of each byte.
///
/// If `reg_load_i` is `1` for a byte defined as non-read-only in a clock cycle, an AXI4-Lite
/// write transaction is stalled when it tries to write the same byte. That is, a write
/// transaction is stalled if all of the following conditions are true for the byte at index `i`:
/// - `AxiReadOnly[i]` is `0`,
/// - `reg_load_i[i]` is `1`,
/// - the bit in `axi_req_i.w.strb` that affects the byte is `1`.
///
/// If unused, set this input to `'0`.
input logic [RegNumBytes-1:0] reg_load_i,
/// The registered value of each byte.
output byte_t [RegNumBytes-1:0] reg_q_o
);
// Define the number of register chunks needed to map all `RegNumBytes` to the AXI channel.
// Eg: `AxiDataWidth == 32'd32`
// AXI strb: 3 2 1 0
// | | | |
// *---------*---------* | | |
// | *-------|-*-------|-* | |
// | | *-----|-|-*-----|-|-* |
// | | | *---|-|-|-*---|-|-|-*
// | | | | | | | | | | | |
// Reg byte: B A 9 8 7 6 5 4 3 2 1 0
// | chunk_2 | chunk_1 | chunk_0 |
localparam int unsigned AxiStrbWidth = AxiDataWidth / 32'd8;
localparam int unsigned NumChunks = cf_math_pkg::ceil_div(RegNumBytes, AxiStrbWidth);
localparam int unsigned ChunkIdxWidth = (NumChunks > 32'd1) ? $clog2(NumChunks) : 32'd1;
// Type of the index to identify a specific register chunk.
typedef logic [ChunkIdxWidth-1:0] chunk_idx_t;
// Find out how many bits of the address are applicable for this module.
// Look at the `AddrWidth` number of LSBs to calculate the multiplexer index of the AXI.
localparam int unsigned AddrWidth = (RegNumBytes > 32'd1) ? ($clog2(RegNumBytes)+1) : 32'd2;
typedef logic [AddrWidth-1:0] addr_t;
// Define the address map which maps each register chunk onto an AXI address.
typedef struct packed {
int unsigned idx;
addr_t start_addr;
addr_t end_addr;
} axi_rule_t;
axi_rule_t [NumChunks-1:0] addr_map;
for (genvar i = 0; i < NumChunks; i++) begin : gen_addr_map
assign addr_map[i] = axi_rule_t'{
idx: i,
start_addr: addr_t'( i * AxiStrbWidth),
end_addr: addr_t'((i+1)* AxiStrbWidth)
};
end
// Channel definitions for spill register
typedef logic [AxiDataWidth-1:0] axi_data_t;
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, axi_data_t)
// Register array declarations
byte_t [RegNumBytes-1:0] reg_q, reg_d;
logic [RegNumBytes-1:0] reg_update;
// Write logic
chunk_idx_t aw_chunk_idx;
logic aw_dec_valid;
b_chan_lite_t b_chan;
logic b_valid, b_ready;
logic aw_prot_ok;
logic chunk_loaded, chunk_ro;
// Flag for telling that the protection level is the right one.
assign aw_prot_ok = (PrivProtOnly ? axi_req_i.aw.prot[0] : 1'b1) &
(SecuProtOnly ? axi_req_i.aw.prot[1] : 1'b1);
// Have a flag which is true if any of the bytes inside a chunk are directly loaded.
logic [AxiStrbWidth-1:0] load;
logic [AxiStrbWidth-1:0] read_only;
// Address of the lowest byte byte of a chunk accessed by an AXI write transaction.
addr_t byte_w_addr;
assign byte_w_addr = addr_t'(aw_chunk_idx * AxiStrbWidth);
for (genvar i = 0; i < AxiStrbWidth; i++) begin : gen_load_assign
// Indexed byte address
addr_t reg_w_idx;
assign reg_w_idx = byte_w_addr + addr_t'(i);
// Only assert load flag for non read only bytes.
assign load[i] = (reg_w_idx < RegNumBytes) ?
(reg_load_i[reg_w_idx] && !AxiReadOnly[reg_w_idx]) : 1'b0;
// Flag to find out that all bytes of the chunk are read only.
assign read_only[i] = (reg_w_idx < RegNumBytes) ? AxiReadOnly[reg_w_idx] : 1'b1;
end
// Only assert the loaded flag if there could be a load conflict between a strobe and load
// signal.
assign chunk_loaded = |(load & axi_req_i.w.strb);
assign chunk_ro = &read_only;
// Register write logic.
always_comb begin
automatic addr_t reg_byte_idx = '0;
// default assignments
reg_d = reg_q;
reg_update = '0;
// Channel handshake
axi_resp_o.aw_ready = 1'b0;
axi_resp_o.w_ready = 1'b0;
// Response
b_chan = b_chan_lite_t'{resp: axi_pkg::RESP_SLVERR, default: '0};
b_valid = 1'b0;
// write active flag
wr_active_o = '0;
// Control
// Handle all non AXI register loads.
for (int unsigned i = 0; i < RegNumBytes; i++) begin
if (reg_load_i[i]) begin
reg_d[i] = reg_d_i[i];
reg_update[i] = 1'b1;
end
end
// Handle load from AXI write.
// `b_ready` is allowed to be a condition as it comes from a spill register.
if (axi_req_i.aw_valid && axi_req_i.w_valid && b_ready) begin
// The write can be performed when these conditions are true:
// - AW decode is valid.
// - `axi_req_i.aw.prot` has the right value.
if (aw_dec_valid && aw_prot_ok) begin
// Stall write as long as any direct load is going on in the current chunk.
// Read-only bytes within a chunk have no influence on stalling.
if (!chunk_loaded) begin
// Go through all bytes on the W channel.
for (int unsigned i = 0; i < AxiStrbWidth; i++) begin
reg_byte_idx = byte_w_addr + addr_t'(i);
// Only execute if the byte is mapped onto the register array.
if (reg_byte_idx < RegNumBytes) begin
// Only update the reg from an AXI write if it is not `ReadOnly`.
// Only connect the data and load to the reg, if the byte is written from AXI.
// This allows for simultaneous direct load onto unwritten bytes.
if (!AxiReadOnly[reg_byte_idx] && axi_req_i.w.strb[i]) begin
reg_d[reg_byte_idx] = axi_req_i.w.data[8*i+:8];
reg_update[reg_byte_idx] = 1'b1;
end
wr_active_o[reg_byte_idx] = axi_req_i.w.strb[i];
end
end
b_chan.resp = chunk_ro ? axi_pkg::RESP_SLVERR : axi_pkg::RESP_OKAY;
b_valid = 1'b1;
axi_resp_o.aw_ready = 1'b1;
axi_resp_o.w_ready = 1'b1;
end
end else begin
// Send default B error response on each not allowed write transaction.
b_valid = 1'b1;
axi_resp_o.aw_ready = 1'b1;
axi_resp_o.w_ready = 1'b1;
end
end
end
// Read logic
chunk_idx_t ar_chunk_idx;
logic ar_dec_valid;
r_chan_lite_t r_chan;
logic r_valid, r_ready;
logic ar_prot_ok;
assign ar_prot_ok = (PrivProtOnly ? axi_req_i.ar.prot[0] : 1'b1) &
(SecuProtOnly ? axi_req_i.ar.prot[1] : 1'b1);
// Multiplexer to determine R channel
always_comb begin
automatic int unsigned reg_byte_idx = '0;
// Default R channel throws an error.
r_chan = r_chan_lite_t'{
data: axi_data_t'(32'hBA5E1E55),
resp: axi_pkg::RESP_SLVERR,
default: '0
};
// Default nothing is reading the registers
rd_active_o = '0;
// Read is valid on a chunk
if (ar_dec_valid && ar_prot_ok) begin
// Calculate the corresponding byte index from `ar_chunk_idx`.
for (int unsigned i = 0; i < AxiStrbWidth; i++) begin
reg_byte_idx = unsigned'(ar_chunk_idx) * AxiStrbWidth + i;
// Guard to not index outside the `reg_q_o` array.
if (reg_byte_idx < RegNumBytes) begin
r_chan.data[8*i+:8] = reg_q_o[reg_byte_idx];
rd_active_o[reg_byte_idx] = r_valid & r_ready;
end else begin
r_chan.data[8*i+:8] = 8'h00;
end
end
r_chan.resp = axi_pkg::RESP_OKAY;
end
end
assign r_valid = axi_req_i.ar_valid; // to spill register
assign axi_resp_o.ar_ready = r_ready; // from spill register
// Register array mapping, even read only register can be loaded over `reg_load_i`.
for (genvar i = 0; i < RegNumBytes; i++) begin : gen_rw_regs
`FFLARN(reg_q[i], reg_d[i], reg_update[i], RegRstVal[i], clk_i, rst_ni)
assign reg_q_o[i] = reg_q[i];
end
addr_decode #(
.NoIndices ( NumChunks ),
.NoRules ( NumChunks ),
.addr_t ( addr_t ),
.rule_t ( axi_rule_t )
) i_aw_decode (
.addr_i ( addr_t'(axi_req_i.aw.addr) ), // Only look at the `AddrWidth` LSBs.
.addr_map_i ( addr_map ),
.idx_o ( aw_chunk_idx ),
.dec_valid_o ( aw_dec_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( '0 ),
.default_idx_i ( '0 )
);
addr_decode #(
.NoIndices ( NumChunks ),
.NoRules ( NumChunks ),
.addr_t ( addr_t ),
.rule_t ( axi_rule_t )
) i_ar_decode (
.addr_i ( addr_t'(axi_req_i.ar.addr) ), // Only look at the `AddrWidth` LSBs.
.addr_map_i ( addr_map ),
.idx_o ( ar_chunk_idx ),
.dec_valid_o ( ar_dec_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( '0 ),
.default_idx_i ( '0 )
);
// Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs.
spill_register #(
.T ( b_chan_lite_t ),
.Bypass ( 1'b0 )
) i_b_spill_register (
.clk_i,
.rst_ni,
.valid_i ( b_valid ),
.ready_o ( b_ready ),
.data_i ( b_chan ),
.valid_o ( axi_resp_o.b_valid ),
.ready_i ( axi_req_i.b_ready ),
.data_o ( axi_resp_o.b )
);
// Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs.
spill_register #(
.T ( r_chan_lite_t ),
.Bypass ( 1'b0 )
) i_r_spill_register (
.clk_i,
.rst_ni,
.valid_i ( r_valid ),
.ready_o ( r_ready ),
.data_i ( r_chan ),
.valid_o ( axi_resp_o.r_valid ),
.ready_i ( axi_req_i.r_ready ),
.data_o ( axi_resp_o.r )
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (RegNumBytes > 32'd0) else
$fatal(1, "The number of bytes must be at least 1!");
assert (AxiAddrWidth >= AddrWidth) else
$fatal(1, "AxiAddrWidth is not wide enough, has to be at least %0d-bit wide!", AddrWidth);
assert ($bits(axi_req_i.aw.addr) == AxiAddrWidth) else
$fatal(1, "AddrWidth does not match req_i.aw.addr!");
assert ($bits(axi_req_i.ar.addr) == AxiAddrWidth) else
$fatal(1, "AddrWidth does not match req_i.ar.addr!");
assert (AxiDataWidth == $bits(axi_req_i.w.data)) else
$fatal(1, "AxiDataWidth has to be: AxiDataWidth == $bits(axi_req_i.w.data)!");
assert (AxiDataWidth == $bits(axi_resp_o.r.data)) else
$fatal(1, "AxiDataWidth has to be: AxiDataWidth == $bits(axi_resp_o.r.data)!");
assert (RegNumBytes == $bits(AxiReadOnly)) else
$fatal(1, "Each register needs a `ReadOnly` flag!");
end
default disable iff (~rst_ni);
for (genvar i = 0; i < RegNumBytes; i++) begin
assert property (@(posedge clk_i) (!reg_load_i[i] && AxiReadOnly[i] |=> $stable(reg_q_o[i])))
else $fatal(1, "Read-only register at `byte_index: %0d` was changed by AXI!", i);
end
`endif
// pragma translate_on
endmodule |
module axi_lite_regs_intf #(
parameter type byte_t = logic [7:0],
parameter int unsigned REG_NUM_BYTES = 32'd0,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter bit PRIV_PROT_ONLY = 1'd0,
parameter bit SECU_PROT_ONLY = 1'd0,
parameter logic [REG_NUM_BYTES-1:0] AXI_READ_ONLY = {REG_NUM_BYTES{1'b0}},
parameter byte_t [REG_NUM_BYTES-1:0] REG_RST_VAL = {REG_NUM_BYTES{8'h00}}
) (
input logic clk_i,
input logic rst_ni,
AXI_LITE.Slave slv,
output logic [REG_NUM_BYTES-1:0] wr_active_o,
output logic [REG_NUM_BYTES-1:0] rd_active_o,
input byte_t [REG_NUM_BYTES-1:0] reg_d_i,
input logic [REG_NUM_BYTES-1:0] reg_load_i,
output byte_t [REG_NUM_BYTES-1:0] reg_q_o
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t)
req_lite_t axi_lite_req;
resp_lite_t axi_lite_resp;
`AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, slv)
`AXI_LITE_ASSIGN_FROM_RESP(slv, axi_lite_resp)
axi_lite_regs #(
.RegNumBytes ( REG_NUM_BYTES ),
.AxiAddrWidth ( AXI_ADDR_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.PrivProtOnly ( PRIV_PROT_ONLY ),
.SecuProtOnly ( SECU_PROT_ONLY ),
.AxiReadOnly ( AXI_READ_ONLY ),
.RegRstVal ( REG_RST_VAL ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t )
) i_axi_lite_regs (
.clk_i,
.rst_ni,
.axi_req_i ( axi_lite_req ),
.axi_resp_o ( axi_lite_resp ),
.wr_active_o,
.rd_active_o,
.reg_d_i,
.reg_load_i,
.reg_q_o
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (AXI_ADDR_WIDTH == $bits(slv.aw_addr))
else $fatal(1, "AXI_ADDR_WIDTH does not match slv interface!");
assert (AXI_DATA_WIDTH == $bits(slv.w_data))
else $fatal(1, "AXI_DATA_WIDTH does not match slv interface!");
end
`endif
// pragma translate_on
endmodule |
module main_scu_bac_address_decoder
#(
parameter p_bus_address_width = 24,
parameter p_response_width = 3 ,
parameter p_bac_reg_offset_address_width = 10,
parameter p_kernel_reg_offset_address_width = 10
)
(
//clock & reset
input clk_i ,
input resetn_i ,
//Bus access interface
input bus_csb_i ,
input bus_wr_i ,
input[p_bus_address_width-1:0] bus_address_i ,
input[31:0] bus_write_data_i,
input[3:0] bus_byte_en_i ,
output reg [31:0] bus_read_data_o ,
output reg bus_ready_o ,
output reg [p_response_width-1:0] bus_response_o ,
//to BAC register
output bac_csb_o ,
output bac_wr_o ,
output[p_bac_reg_offset_address_width-1:0] bac_address_o ,
output[31:0] bac_write_data_o,
output[3:0] bac_byte_en_o ,
input [31:0] bac_read_data_i ,
input bac_ready_i ,
input[p_response_width-1:0] bac_response_i ,
//to register bank
output reg_csb_o ,
output reg_wr_o ,
output[p_kernel_reg_offset_address_width-1:0] reg_address_o ,
output[31:0] reg_write_data_o,
output[3:0] reg_byte_en_o ,
input [31:0] reg_read_data_i ,
input reg_ready_i ,
input [p_response_width-1:0] reg_response_i
);
//TODO address distribution
//BAC Reg 24'h00_0000
// 24'h00_03FF
//TX fifo 24'h00_0400
// 24'h00_07FC
//RX fifo 24'h00_0800
// 24'h00_0BFC
//BAC Reserved 24'h00_0C00
// 24'h00_0FFF
//Kernel Reg 24'h00_1000
// 24'h01_FFFF
//Memory IF 24'h02_0000
// 24'hFF_FFFF
logic bac_sel_s;
logic reg_sel_s;
logic bac_sel_r;
logic reg_sel_r;
//decoder
always@(*)begin
bac_sel_s=1'b0;
reg_sel_s=1'b0;
if(bus_address_i[23:0] < 24'h00_0040) begin
bac_sel_s= 1'b1;
end
else if(bus_address_i[23:0] >= 24'h00_0040 && bus_address_i[23:0] < 24'hc10 + 24'h00_0040 + 24'h4 ) begin
//TODO Extract the .csv max user offset address
reg_sel_s= 1'b1;
end
end
always@(posedge clk_i or negedge resetn_i)
begin
if(!resetn_i) begin
bac_sel_r<=1'b0;
reg_sel_r<=1'b0;
end
else begin
if(!bus_csb_i && bus_ready_o) begin
bac_sel_r<=bac_sel_s;
reg_sel_r<=reg_sel_s;
end
end
end
//BAC Reg
assign bac_csb_o =(bac_sel_s == 1)? bus_csb_i : 1'b1 ;
assign bac_wr_o =(bac_sel_s == 1)? bus_wr_i : 1'b0 ;
assign bac_address_o =(bac_sel_s == 1)? bus_address_i[p_bac_reg_offset_address_width-1:0] : {p_bac_reg_offset_address_width{1'b0} };
assign bac_write_data_o=(bac_sel_s == 1)? bus_write_data_i : 32'h0 ;
assign bac_byte_en_o =(bac_sel_s == 1)? bus_byte_en_i : 4'h0 ;
//Kernel Reg
////TODO?? need to make the kernel base address auto generated!!!
assign reg_csb_o =(reg_sel_s == 1)? bus_csb_i : 1'b1 ;
assign reg_wr_o =(reg_sel_s == 1)? bus_wr_i : 1'b0 ;
assign reg_address_o =(reg_sel_s == 1)? bus_address_i[p_bus_address_width-8:0]-17'h0040 : {p_kernel_reg_offset_address_width{1'b0} };
assign reg_write_data_o=(reg_sel_s == 1)? bus_write_data_i : 32'h0 ;
assign reg_byte_en_o =(reg_sel_s == 1)? bus_byte_en_i : 4'h0 ;
always@(*)
begin
bus_read_data_o = 'hdead_dead;
bus_response_o = 'h0;
if(bac_sel_r) begin
bus_read_data_o = bac_read_data_i ;
bus_response_o = bac_response_i ;
end
else if(reg_sel_r) begin //TODO Add else to the always block
bus_read_data_o = reg_read_data_i ;
bus_response_o = reg_response_i ;
end
end
always@(*)
begin
bus_ready_o = 'h1;
if(bac_sel_s) begin
bus_ready_o = bac_ready_i ;
end
else if(reg_sel_s) begin //TODO Add else to the alwyas block
bus_ready_o = reg_ready_i ;
end
end
//TODO??
//
//need to verify the request_ready, response_ready behavior ,
//currently for BAC, kernel register, it is tied to "1"
//But in the future, when there is memory, it will need these two ready with
//correct backpressure on request and response
endmodule |
module main_scu_bus_access_control_top
#(
parameter p_num_of_bac_register =16,
parameter p_bus_address_width = 24,
parameter p_response_width = 3,
parameter p_memory_address_width = 24, // memory will give full 24 bits address
parameter p_bac_reg_offset_address_width = 6,
parameter p_kernel_reg_offset_address_width = 12,
parameter p_client_num = 1,
parameter p_func_int0_num = 32,
parameter p_func_int1_num = 32,
parameter p_error_int_num = 32,
parameter p_tx_fifo_common_int_num = 8,
parameter p_rx_fifo_common_int_num = 8
)
(
//clock & reset
input clk_i ,
input resetn_i ,
//DFT port
input dft_scan_en_i , //It will be used to control the clock gate cell
input jtag_rst_sync_bypass_i , //It will be used to control the Reset sync cell
input bus_clk_i , // in case it is async bridge
//synced reset for AHB2ESRAM Async Bridge
output synced_hclk_reset_o ,
//SRAM Bus access interface
input bus_csb_i ,
input bus_wr_i ,
input[p_bus_address_width-1:0] bus_address_i ,
input[31:0] bus_write_data_i ,
input[3:0] bus_byte_en_i ,
output reg [31:0] bus_read_data_o ,
output reg bus_ready_o ,
output reg [p_response_width-1:0] bus_response_o ,
//to register bank
output reg_csb_o ,
output reg_wr_o ,
output[p_kernel_reg_offset_address_width-1:0] reg_address_o ,
output[31:0] reg_write_data_o ,
output[3:0] reg_byte_en_o ,
input [31:0] reg_read_data_i ,
input reg_ready_i ,
input[p_response_width-1:0] reg_response_i ,
//interrupt HW set from Kernel side
input [p_func_int0_num-1 :0] func_int0_hw_set_i ,
output func_int0_interrupt_o ,
//gated clocks
output gated_kernel_clk_o ,
output gated_regbank_clk_o ,
//synced kernel reset
output synced_kernel_reset_o
);
//in this top level, only Wiring(signals & parameters) is allowed!!!!!
//logic definition
//SRAM access interface
logic bac_csb_s ;
logic bac_wr_s ;
logic[p_bac_reg_offset_address_width-1:0] bac_address_s ;
logic[31:0] bac_write_data_s ;
logic[3:0] bac_byte_en_s ;
logic[31:0] bac_read_data_s ;
logic bac_ready_s ;
logic[p_response_width-1:0] bac_response_s ;
//TODO p_chipid_val p_checksum_val p_register_if_version_val p_module_versionid_val p_moduleid_val
logic [31:0] p_chipid_val_s ;
logic [31:0] p_checksum_val_s ;
logic [15:0] p_register_if_version_val_s;
logic [7:0] p_module_versionid_val_s ;
logic [7:0] p_moduleid_val_s ;
//common interrupts
logic [p_func_int0_num-1 :0] func_int0_enable_set_s ;
logic [p_func_int0_num-1 :0] func_int0_enable_clr_s ;
logic [p_func_int0_num-1 :0] func_int0_sw_set_s ;
logic [p_func_int0_num-1 :0] func_int0_sw_clr_s ;
logic [p_func_int0_num-1 :0] func_int0_enable_status_s ;
logic [p_func_int0_num-1 :0] func_int0_enabled_int_status_s ;
logic [p_func_int0_num-1 :0] func_int0_int_status_s ;
//--
logic[p_client_num-1:0] reg_bank_clk_i_en_set_wo_s ;
logic[p_client_num-1:0] reg_bank_clk_i_en_clr_wo_s ;
logic[p_client_num-1:0] reg_bank_clk_i_en_sta_ro_s ;
logic[p_client_num-1:0] kernel_clk_i_en_set_wo_s ;
logic[p_client_num-1:0] kernel_clk_i_en_clr_wo_s ;
logic[p_client_num-1:0] kernel_clk_i_en_sta_ro_s ;
//TODO because delete these ports---
//logic first_access_error_clear_wo_o ;
//logic last_access_error_clear_wo_o ;
//logic[31:0] first_access_error_ro_i ;
//logic[31:0] last_access_error_ro_i ;
//--
logic synced_kernel_reset_s;
//---
main_scu_bac_address_decoder
#(
.p_bus_address_width (p_bus_address_width ),
.p_response_width (p_response_width ),
.p_bac_reg_offset_address_width (p_bac_reg_offset_address_width ),
.p_kernel_reg_offset_address_width(p_kernel_reg_offset_address_width)
) main_scu_bac_address_decoder_inst
(
.clk_i (clk_i ),
.resetn_i (synced_kernel_reset_s ),
.bus_csb_i (bus_csb_i ),
.bus_wr_i (bus_wr_i ),
.bus_address_i (bus_address_i ),
.bus_write_data_i (bus_write_data_i),
.bus_byte_en_i (bus_byte_en_i ),
.bus_read_data_o (bus_read_data_o ),
.bus_ready_o (bus_ready_o ),
.bus_response_o (bus_response_o ),
.bac_csb_o (bac_csb_s ),
.bac_wr_o (bac_wr_s ),
.bac_address_o (bac_address_s ),
.bac_write_data_o (bac_write_data_s),
.bac_byte_en_o (bac_byte_en_s ),
.bac_read_data_i (bac_read_data_s ),
.bac_ready_i (bac_ready_s ),
.bac_response_i (bac_response_s ),
.reg_csb_o (reg_csb_o ),
.reg_wr_o (reg_wr_o ),
.reg_address_o (reg_address_o ),
.reg_write_data_o (reg_write_data_o),
.reg_byte_en_o (reg_byte_en_o ),
.reg_read_data_i (reg_read_data_i ),
.reg_ready_i (reg_ready_i ),
.reg_response_i (reg_response_i )
);
//TODO main_scu_bac_register_block --> main_scu_bac_register_block_wrapper---
main_scu_bac_register_wrapper
#(
.p_bac_reg_offset_address_width(p_bac_reg_offset_address_width),
.p_response_width (p_response_width ),
.p_num_of_bac_register (p_num_of_bac_register ), // 4 TX/RX FIFO is not consider here
.p_tx_fifo_common_int_num (p_tx_fifo_common_int_num ),
.p_rx_fifo_common_int_num (p_rx_fifo_common_int_num )
) main_scu_bac_register_wrapper_inst
(
.clk_i (clk_i ),
.rst_n_i (synced_kernel_reset_s ),
.bac_csb_i (bac_csb_s ),
.bac_wr_i (bac_wr_s ),
.bac_address_i (bac_address_s ),
.bac_write_data_i (bac_write_data_s ),
.bac_byte_en_i (bac_byte_en_s ),
.bac_read_data_o (bac_read_data_s ),
.bac_ready_o (bac_ready_s ),
.bac_response_o (bac_response_s ),
//TODO?? need to connect for real function ..
.register_bank_clock_enable_set_wo_set_o (reg_bank_clk_i_en_set_wo_s ),
.register_bank_clock_enable_clr_wo_clr_o (reg_bank_clk_i_en_clr_wo_s ),
.register_bank_clock_enable_status_ro_status_i (reg_bank_clk_i_en_sta_ro_s ),
.kernel_clock_enable_set_wo_set_o (kernel_clk_i_en_set_wo_s ),
.kernel_clock_enable_clr_wo_clr_o (kernel_clk_i_en_clr_wo_s ),
.kernel_clock_enable_status_ro_status_i (kernel_clk_i_en_sta_ro_s ),
.func_int_0_enable_set_wo_set_o (func_int0_enable_set_s ),
.func_int_0_enable_clear_wo_clear_o (func_int0_enable_clr_s ),
.func_int_0_set_wo_set_o (func_int0_sw_set_s ),
.func_int_0_clr_wo_clear_o (func_int0_sw_clr_s ),
.func_int_0_enable_status_ro_status_i (func_int0_enable_status_s ),
.func_int_0_status_enabled_ro_status_i (func_int0_enabled_int_status_s ),
.func_int_0_status_ro_status_i (func_int0_int_status_s ),
.chipid_ro_chipid_i (p_chipid_val_s ),
.moduleid_ro_module_id_i (p_moduleid_val_s ),
.moduleid_ro_module_version_i (p_module_versionid_val_s ),
.moduleid_ro_reg_if_version_i (p_register_if_version_val_s ),
.checksum_ro_checksum_i (p_checksum_val_s )
);
//---
main_scu_bac_common_interrupt_handle
#(
.p_func_int0_num (p_func_int0_num ),
.p_func_int1_num (p_func_int1_num ),
.p_error_int_num (p_error_int_num ),
.p_tx_fifo_common_int_num (p_tx_fifo_common_int_num ),
.p_rx_fifo_common_int_num (p_rx_fifo_common_int_num )
) main_scu_bac_common_interrupt_handle_inst
(
.func_int0_enable_set_i (func_int0_enable_set_s ),
.func_int0_enable_clr_i (func_int0_enable_clr_s ),
.func_int0_hw_set_i (func_int0_hw_set_i ),
.func_int0_sw_set_i (func_int0_sw_set_s ),
.func_int0_sw_clr_i (func_int0_sw_clr_s ),
.func_int0_enable_status_o (func_int0_enable_status_s ),
.func_int0_enabled_int_status_o (func_int0_enabled_int_status_s ),
.func_int0_int_status_o (func_int0_int_status_s ),
.func_int0_interrupt_o (func_int0_interrupt_o ),
.clk_i (clk_i ),
.resetn_i (synced_kernel_reset_s )
);
//---
main_scu_bac_misc
#(
.p_client_num(p_client_num)
) main_scu_bac_misc_inst
(
.kernel_clk_i (clk_i ),
.resetn_i (resetn_i ),
.dft_scan_en_i (dft_scan_en_i ) ,
.jtag_rst_sync_bypass_i (jtag_rst_sync_bypass_i ) ,
//---
.reg_bank_clk_en_set_i (reg_bank_clk_i_en_set_wo_s ),
.reg_bank_clk_en_clr_i (reg_bank_clk_i_en_clr_wo_s ),
.reg_bank_clk_en_sta_o (reg_bank_clk_i_en_sta_ro_s ),
.kernel_clk_en_set_i (kernel_clk_i_en_set_wo_s ),
.kernel_clk_en_clr_i (kernel_clk_i_en_clr_wo_s ),
.kernel_clk_en_sta_o (kernel_clk_i_en_sta_ro_s ),
//TODO p_chipid_val p_checksum_val p_register_if_version_val p_moduleid_val p_moduleid_val
.p_chipid_val_o (p_chipid_val_s ),
.p_checksum_val_o (p_checksum_val_s ),
.p_register_if_version_val_o (p_register_if_version_val_s ),
.p_module_versionid_val_o (p_module_versionid_val_s ),
.p_moduleid_val_o (p_moduleid_val_s ),
.gated_kernel_clk_o (gated_kernel_clk_o ),
.gated_regbank_clk_o (gated_regbank_clk_o ),
.hclk_i (bus_clk_i ),
.synced_hclk_reset_o (synced_hclk_reset_o ),
.synced_kernel_reset_o (synced_kernel_reset_s )
);
assign synced_kernel_reset_o = synced_kernel_reset_s;
endmodule |
module TestBench ();
parameter CLOCK_FREQ = 100_000_000;
parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
// setup clock and reset
reg clk, rst;
initial clk = 'b0;
always #(CLOCK_PERIOD/2) clk = ~clk;
Tile dut (
.clock(clk),
.reset(rst),
.io_led()
);
reg clock;
initial begin
// set up logging
// $dumpfile("out.vcd");
// $dumpvars(0, top);
$fsdbDumpfile("out.fsdb");
$fsdbDumpvars("+all");
#0;
rst = 1;
$display("[TEST]\tRESET pulled HIGH.");
repeat(2) @(posedge clk);
@(negedge clk);
rst = 0;
$display("[TEST]\tRESET pulled LOW.");
@(posedge clk);
repeat(100) @(posedge clk);
$display("[TEST]\tDONE.");
$finish;
end
endmodule |
module TB_Tile();
parameter CLOCK_FREQ = 100_000_000;
parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
// setup clock and reset
reg clk, rst;
initial clk = 'b0;
always #(CLOCK_PERIOD/2) clk = ~clk;
Tile dut (
.clk(clk),
.rst(rst),
.led()
);
initial begin
#0;
rst = 1;
$display("[TEST]\tRESET pulled HIGH.");
repeat(2) @(posedge clk);
@(negedge clk);
rst = 0;
$display("[TEST]\tRESET pulled LOW.");
@(posedge clk);
repeat(10000) @(posedge clk);
$finish();
end
endmodule |
module nvme_buffer_ram
#(
parameter ADDR_BITS = 8,
parameter DEPTH = 2**8
) (
input wire wclk,
input wire [3:0] we,
input wire [ADDR_BITS-1:0] waddr,
input wire [127:0] din,
input wire rclk,
input wire re,
input wire [ADDR_BITS-1:0] raddr,
output logic [127:0] dout
);
reg [31:0] ram0 [0:DEPTH-1];
reg [31:0] ram1 [0:DEPTH-1];
reg [31:0] ram2 [0:DEPTH-1];
reg [31:0] ram3 [0:DEPTH-1];
always @(posedge rclk)
begin : READ_P
if (re) begin
dout <= {ram3[raddr], ram2[raddr], ram1[raddr], ram0[raddr]};
end
end
always @(posedge wclk)
begin : WRITE_P
if (we[0]) begin
ram0[waddr] <= din[31:0];
end
if (we[1]) begin
ram1[waddr] <= din[63:32];
end
if (we[2]) begin
ram2[waddr] <= din[95:64];
end
if (we[3]) begin
ram3[waddr] <= din[127:96];
end
end
endmodule |
module nvme_host
(
input wire axi_aclk,
input wire axi_aresetn,
// Action/MMIO to NMVE Host Slave AXI Lite IF
input wire [`HOST_ADDR_BITS - 1:0] host_s_axi_awaddr,
input wire host_s_axi_awvalid,
output logic host_s_axi_awready,
input wire [31:0] host_s_axi_wdata,
input wire [3:0] host_s_axi_wstrb,
input wire host_s_axi_wvalid,
output logic host_s_axi_wready,
output logic [1:0] host_s_axi_bresp,
output logic host_s_axi_bvalid,
input wire host_s_axi_bready,
input wire [`HOST_ADDR_BITS - 1:0] host_s_axi_araddr,
input wire host_s_axi_arvalid,
output logic host_s_axi_arready,
output logic [31:0] host_s_axi_rdata,
output logic [1:0] host_s_axi_rresp,
output logic host_s_axi_rvalid,
input wire host_s_axi_rready,
// NVMe Host to PCIE Master AXI Lite IF
output logic [`PCIE_M_ADDR_BITS-1:0] pcie_m_axi_awaddr,
output logic [2:0] pcie_m_axi_awprot,
output logic pcie_m_axi_awvalid,
input wire pcie_m_axi_awready,
output logic [31:0] pcie_m_axi_wdata,
output logic [3:0] pcie_m_axi_wstrb,
output logic pcie_m_axi_wvalid,
input wire pcie_m_axi_wready,
input wire [1:0] pcie_m_axi_bresp,
input wire pcie_m_axi_bvalid,
output logic pcie_m_axi_bready,
output logic [`PCIE_M_ADDR_BITS-1:0] pcie_m_axi_araddr,
output logic [2:0] pcie_m_axi_arprot,
output logic pcie_m_axi_arvalid,
input wire pcie_m_axi_arready,
input wire [31:0] pcie_m_axi_rdata,
input wire [1:0] pcie_m_axi_rresp,
input wire pcie_m_axi_rvalid,
output logic pcie_m_axi_rready,
// NVMe Host to PCIE Slave AXI MM IF
input wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_awid,
input wire [`PCIE_S_ADDR_BITS-1:0] pcie_s_axi_awaddr,
input wire [7:0] pcie_s_axi_awlen,
input wire [2:0] pcie_s_axi_awsize,
input wire [1:0] pcie_s_axi_awburst,
input wire pcie_s_axi_awvalid,
output logic pcie_s_axi_awready,
input wire [127:0] pcie_s_axi_wdata,
input wire [15:0] pcie_s_axi_wstrb,
input wire pcie_s_axi_wlast,
input wire pcie_s_axi_wvalid,
output logic pcie_s_axi_wready,
output logic [`PCIE_S_ID_BITS-1:0] pcie_s_axi_bid,
output logic [1:0] pcie_s_axi_bresp,
output logic pcie_s_axi_bvalid,
input wire pcie_s_axi_bready,
input wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_arid,
input wire [`PCIE_S_ADDR_BITS-1:0] pcie_s_axi_araddr,
input wire [7:0] pcie_s_axi_arlen,
input wire [2:0] pcie_s_axi_arsize,
input wire [1:0] pcie_s_axi_arburst,
input wire pcie_s_axi_arvalid,
output logic pcie_s_axi_arready,
output logic [`PCIE_S_ID_BITS-1:0] pcie_s_axi_rid,
output logic [127:0] pcie_s_axi_rdata,
output logic [1:0] pcie_s_axi_rresp,
output logic pcie_s_axi_rlast,
output logic pcie_s_axi_rvalid,
input wire pcie_s_axi_rready
);
// Each submission queue entry is 64 bytes, buffer width is 16 bytes
// Each completion queue entry is 16 bytes, buffer width is 16 bytes
// There is a separate Admin and IO queue for each SSD drive
localparam integer TX_DEPTH = (`ADM_SQ_NUM * 2 + `IO_SQ_NUM * 2 + `DATA_SQ_NUM) * 4;
localparam integer RX_DEPTH = (`ADM_CQ_NUM * 2 + `IO_CQ_NUM * 2 + `DATA_CQ_NUM) * 1;
// Buffer initialization done
logic init_done;
// Tx Buffer Signals
localparam TX_ADDR_BITS = $clog2(TX_DEPTH);
logic [3:0] tx_write;
logic [TX_ADDR_BITS-1:0] tx_waddr;
logic [127:0] tx_wdata;
logic tx_read;
logic [TX_ADDR_BITS-1:0] tx_raddr;
logic [127:0] tx_rdata;
// Rx Buffer Signals
localparam RX_ADDR_BITS = $clog2(RX_DEPTH);
logic rx_write_valid;
logic [3:0] rx_write;
logic [RX_ADDR_BITS-1:0] rx_waddr;
logic [127:0] rx_wdata;
logic rx_read;
logic [RX_ADDR_BITS-1:0] rx_raddr;
logic [127:0] rx_rdata;
// PCIE Master Write IF
logic pcie_write;
logic [31:0] pcie_waddr;
logic [31:0] pcie_wdata;
logic pcie_wdone;
logic pcie_werror;
// PCIE Master Read IF
logic pcie_read;
logic [31:0] pcie_raddr;
logic [31:0] pcie_rdata;
logic pcie_rdone;
logic pcie_rerror;
// Action/MMIO AXI Lite Slave
nvme_host_slave #(.TX_ADDR_BITS(TX_ADDR_BITS), .RX_ADDR_BITS(RX_ADDR_BITS)) host_slave_i
(
.*
);
// PCIE AXI Lite Master
nvme_pcie_master pcie_master_i
(
.*
);
// PCIE AXI MM Slave
nvme_pcie_slave #(.TX_ADDR_BITS(TX_ADDR_BITS), .RX_ADDR_BITS(RX_ADDR_BITS)) pcie_slave_i
(
.*
);
// Tx Buffer Instantiation
nvme_buffer_ram #(.ADDR_BITS(TX_ADDR_BITS), .DEPTH(TX_DEPTH)) tx_ram_i
(
.wclk(axi_aclk),
.we(tx_write),
.waddr(tx_waddr),
.din(tx_wdata),
.rclk(axi_aclk),
.re(tx_read),
.raddr(tx_raddr),
.dout(tx_rdata)
);
// Rx Buffer Instantiation
nvme_buffer_ram #(.ADDR_BITS(RX_ADDR_BITS), .DEPTH(RX_DEPTH)) rx_ram_i
(
.wclk(axi_aclk),
.we(rx_write),
.waddr(rx_waddr),
.din(rx_wdata),
.rclk(axi_aclk),
.re(rx_read),
.raddr(rx_raddr),
.dout(rx_rdata)
);
endmodule |
module nvme_top (
/* Action AXI Bus: Here we should see the register reads/writes */
input wire ACT_NVME_ACLK,
input wire ACT_NVME_ARESETN,
input wire [31:0]ACT_NVME_AXI_araddr,
input wire [1:0]ACT_NVME_AXI_arburst,
input wire [3:0]ACT_NVME_AXI_arcache,
input wire [7:0]ACT_NVME_AXI_arlen,
input wire [0:0]ACT_NVME_AXI_arlock,
input wire [2:0]ACT_NVME_AXI_arprot,
input wire [3:0]ACT_NVME_AXI_arqos,
output wire ACT_NVME_AXI_arready,
input wire [3:0]ACT_NVME_AXI_arregion,
input wire [2:0]ACT_NVME_AXI_arsize,
input wire ACT_NVME_AXI_arvalid,
input wire [31:0]ACT_NVME_AXI_awaddr,
input wire [1:0]ACT_NVME_AXI_awburst,
input wire [3:0]ACT_NVME_AXI_awcache,
input wire [7:0]ACT_NVME_AXI_awlen,
input wire [0:0]ACT_NVME_AXI_awlock,
input wire [2:0]ACT_NVME_AXI_awprot,
input wire [3:0]ACT_NVME_AXI_awqos,
output wire ACT_NVME_AXI_awready,
input wire [3:0]ACT_NVME_AXI_awregion,
input wire [2:0]ACT_NVME_AXI_awsize,
input wire ACT_NVME_AXI_awvalid,
input wire ACT_NVME_AXI_bready,
output wire [1:0]ACT_NVME_AXI_bresp,
output wire ACT_NVME_AXI_bvalid,
output wire [31:0]ACT_NVME_AXI_rdata,
output wire ACT_NVME_AXI_rlast,
input wire ACT_NVME_AXI_rready,
output wire [1:0]ACT_NVME_AXI_rresp,
output wire ACT_NVME_AXI_rvalid,
input wire [31:0]ACT_NVME_AXI_wdata,
input wire ACT_NVME_AXI_wlast,
output wire ACT_NVME_AXI_wready,
input wire [3:0]ACT_NVME_AXI_wstrb,
input wire ACT_NVME_AXI_wvalid,
/* SDRAM Access AXI Bus: Here we need to copy data to or from */
output wire [`DDR_M_ADDRBWIDTH-1:0]DDR_M_AXI_araddr,
output wire [1:0]DDR_M_AXI_arburst,
output wire [3:0]DDR_M_AXI_arcache,
output wire [3:0]DDR_M_AXI_arid,
output wire [7:0]DDR_M_AXI_arlen,
output wire [0:0]DDR_M_AXI_arlock,
output wire [2:0]DDR_M_AXI_arprot,
output wire [3:0]DDR_M_AXI_arqos,
input wire [0:0]DDR_M_AXI_arready,
output wire [3:0]DDR_M_AXI_arregion,
output wire [2:0]DDR_M_AXI_arsize,
output wire [0:0]DDR_M_AXI_arvalid,
output wire [`DDR_M_ADDRBWIDTH-1:0]DDR_M_AXI_awaddr,
output wire [1:0]DDR_M_AXI_awburst,
output wire [3:0]DDR_M_AXI_awcache,
output wire [3:0]DDR_M_AXI_awid,
output wire [7:0]DDR_M_AXI_awlen,
output wire [0:0]DDR_M_AXI_awlock,
output wire [2:0]DDR_M_AXI_awprot,
output wire [3:0]DDR_M_AXI_awqos,
input wire [0:0]DDR_M_AXI_awready,
output wire [3:0]DDR_M_AXI_awregion,
output wire [2:0]DDR_M_AXI_awsize,
output wire [0:0]DDR_M_AXI_awvalid,
input wire [3:0]DDR_M_AXI_bid,
output wire [0:0]DDR_M_AXI_bready,
input wire [1:0]DDR_M_AXI_bresp,
input wire [0:0]DDR_M_AXI_bvalid,
input wire [127:0]DDR_M_AXI_rdata,
input wire [3:0]DDR_M_AXI_rid,
input wire [0:0]DDR_M_AXI_rlast,
output wire [0:0]DDR_M_AXI_rready,
input wire [1:0]DDR_M_AXI_rresp,
input wire [15:0]DDR_M_AXI_ruser,
input wire [0:0]DDR_M_AXI_rvalid,
output wire [127:0]DDR_M_AXI_wdata,
output wire [0:0]DDR_M_AXI_wlast,
input wire [0:0]DDR_M_AXI_wready,
output wire [15:0]DDR_M_AXI_wstrb,
output wire [15:0]DDR_M_AXI_wuser,
output wire [0:0]DDR_M_AXI_wvalid,
/* Yet another AXI Bus */
input wire NVME_S_ACLK,
input wire NVME_S_ARESETN,
input wire [31:0]NVME_S_AXI_araddr,
input wire [2:0]NVME_S_AXI_arprot,
output wire [0:0]NVME_S_AXI_arready,
input wire [0:0]NVME_S_AXI_arvalid,
input wire [31:0]NVME_S_AXI_awaddr,
input wire [2:0]NVME_S_AXI_awprot,
output wire [0:0]NVME_S_AXI_awready,
input wire [0:0]NVME_S_AXI_awvalid,
input wire [0:0]NVME_S_AXI_bready,
output wire [1:0]NVME_S_AXI_bresp,
output wire [0:0]NVME_S_AXI_bvalid,
output wire [31:0]NVME_S_AXI_rdata,
input wire [0:0]NVME_S_AXI_rready,
output wire [1:0]NVME_S_AXI_rresp,
output wire [0:0]NVME_S_AXI_rvalid,
input wire [31:0]NVME_S_AXI_wdata,
output wire [0:0]NVME_S_AXI_wready,
input wire [3:0]NVME_S_AXI_wstrb,
input wire [0:0]NVME_S_AXI_wvalid,
/* And some other signals to control the PCIe root complexes in the orignal design */
output wire ddr_aclk,
output wire ddr_aresetn,
input wire nvme_reset_n,
input wire [3:0]pcie_rc0_rxn,
input wire [3:0]pcie_rc0_rxp,
output wire [3:0]pcie_rc0_txn,
output wire [3:0]pcie_rc0_txp,
input wire [3:0]pcie_rc1_rxn,
input wire [3:0]pcie_rc1_rxp,
output wire [3:0]pcie_rc1_txn,
output wire [3:0]pcie_rc1_txp,
input wire refclk_nvme_ch0_n,
input wire refclk_nvme_ch0_p,
input wire refclk_nvme_ch1_n,
input wire refclk_nvme_ch1_p
);
`define CONFIG_DDR_READWRITE_TEST 0 /* Enable test for DDR, write some data, read it back and compare */
/* Local hardware instances go here */
reg ACT_arready;
reg [31:0] ACT_araddr;
reg [31:0] ACT_rdata;
reg [0:0] ACT_awready;
reg [31:0] ACT_awaddr;
reg [31:0] ACT_wdata;
reg [0:0] ACT_wready;
reg [0:0] ACT_bvalid;
reg [1:0] ACT_bresp;
reg [0:0] ACT_rvalid;
reg [0:0] ACT_rlast;
reg [1:0] ACT_rresp;
/* DDR AXI Bus control signals */
reg DDR_aclk;
reg DDR_aresetn;
reg [3:0] DDR_arid;
reg [7:0] DDR_awlen;
reg [2:0] DDR_awsize;
reg [1:0] DDR_awburst;
reg [`DDR_M_ADDRBWIDTH-1:0] DDR_awaddr;
reg [0:0] DDR_arvalid;
reg [0:0] DDR_awvalid;
reg [127:0] DDR_wdata;
reg [15:0] DDR_wstrb;
reg [0:0] DDR_wvalid;
reg [3:0] DDR_awid;
reg [7:0] DDR_arlen;
reg [2:0] DDR_arsize;
reg [`DDR_M_ADDRBWIDTH-1:0] DDR_araddr;
reg [0:0] DDR_rready;
reg [0:0] DDR_arlock;
reg [0:0] DDR_wlast;
reg [0:0] DDR_bready;
reg [0:0] DDR_arburst;
reg [0:0] DDR_awlock;
reg [2:0] DDR_awprot;
reg [2:0] DDR_arprot;
reg [3:0] DDR_awqos;
reg [3:0] DDR_arqos;
reg [3:0] DDR_awcache;
reg [3:0] DDR_arcache;
reg [15:0] DDR_wuser;
reg [3:0] DDR_awregion;
reg [3:0] DDR_arregion;
/* SNAP Action AXI Interface */
assign ACT_NVME_AXI_arready = ACT_arready;
assign ACT_NVME_AXI_rdata = ACT_rdata;
assign ACT_NVME_AXI_awready = ACT_awready;
assign ACT_NVME_AXI_wready = ACT_wready;
assign ACT_NVME_AXI_bvalid = ACT_bvalid;
assign ACT_NVME_AXI_bresp = ACT_bresp;
assign ACT_NVME_AXI_rvalid = ACT_rvalid;
assign ACT_NVME_AXI_rresp = ACT_rresp;
assign ACT_NVME_AXI_rlast = ACT_rlast;
/* Access to Card DDR AXI Interface */
assign ddr_aclk = DDR_aclk;
assign ddr_aresetn = DDR_aresetn;
assign DDR_M_AXI_awid = DDR_awid;
assign DDR_M_AXI_arid = DDR_arid;
assign DDR_M_AXI_awlen = DDR_awlen;
assign DDR_M_AXI_awsize = DDR_awsize;
assign DDR_M_AXI_awburst = DDR_awburst;
assign DDR_M_AXI_awaddr = DDR_awaddr[`DDR_M_ADDRBWIDTH-1:0];
assign DDR_M_AXI_awvalid = DDR_awvalid;
assign DDR_M_AXI_wdata = DDR_wdata;
assign DDR_M_AXI_wstrb = DDR_wstrb;
assign DDR_M_AXI_wvalid = DDR_wvalid;
assign DDR_M_AXI_wlast = DDR_wlast;
assign DDR_M_AXI_arvalid = DDR_arvalid;
assign DDR_M_AXI_arlen = DDR_arlen;
assign DDR_M_AXI_arsize = DDR_arsize;
assign DDR_M_AXI_araddr = DDR_araddr[`DDR_M_ADDRBWIDTH-1:0];
assign DDR_M_AXI_rready = DDR_rready;
assign DDR_M_AXI_bready = DDR_bready;
assign DDR_M_AXI_arburst = DDR_arburst;
assign DDR_M_AXI_awlock = DDR_awlock;
assign DDR_M_AXI_arlock = DDR_arlock;
assign DDR_M_AXI_awprot = DDR_awprot;
assign DDR_M_AXI_arprot = DDR_arprot;
assign DDR_M_AXI_awqos = DDR_awqos;
assign DDR_M_AXI_arqos = DDR_arqos;
assign DDR_M_AXI_awcache = DDR_awcache;
assign DDR_M_AXI_arcache = DDR_arcache;
assign DDR_M_AXI_wuser = DDR_wuser;
assign DDR_M_AXI_awregion = DDR_awregion;
assign DDR_M_AXI_arregion = DDR_arregion;
/* SNAP NVME AXI Interface: FIXME Figure out for what this is really used */
localparam ACTION_W_BITS = $clog2(`ACTION_W_NUM_REGS);
localparam ACTION_R_BITS = $clog2(`ACTION_R_NUM_REGS);
localparam SQ_INDEX_BITS = $clog2(`TOTAL_NUM_QUEUES);
logic [31:0] action_w_regs[`ACTION_W_NUM_REGS];
logic [31:0] action_r_regs[`ACTION_R_NUM_REGS];
logic [ACTION_R_BITS - 1: 0] action_r_index;
assign action_r_index = ACT_araddr[ACTION_R_BITS + 1: 2];
logic [ACTION_W_BITS - 1: 0] action_w_index;
assign action_w_index = ACT_awaddr[ACTION_W_BITS + 1: 2];
/* Tie status information to TRACK_n register bits */
assign action_r_regs[`ACTION_R_STATUS][16] = action_r_regs[`ACTION_R_TRACK_0][0];
assign action_r_regs[`ACTION_R_STATUS][17] = action_r_regs[`ACTION_R_TRACK_0 + 1][0];
assign action_r_regs[`ACTION_R_STATUS][18] = action_r_regs[`ACTION_R_TRACK_0 + 2][0];
assign action_r_regs[`ACTION_R_STATUS][19] = action_r_regs[`ACTION_R_TRACK_0 + 3][0];
assign action_r_regs[`ACTION_R_STATUS][20] = action_r_regs[`ACTION_R_TRACK_0 + 4][0];
assign action_r_regs[`ACTION_R_STATUS][21] = action_r_regs[`ACTION_R_TRACK_0 + 5][0];
assign action_r_regs[`ACTION_R_STATUS][22] = action_r_regs[`ACTION_R_TRACK_0 + 6][0];
assign action_r_regs[`ACTION_R_STATUS][23] = action_r_regs[`ACTION_R_TRACK_0 + 7][0];
assign action_r_regs[`ACTION_R_STATUS][24] = action_r_regs[`ACTION_R_TRACK_0 + 8][0];
assign action_r_regs[`ACTION_R_STATUS][25] = action_r_regs[`ACTION_R_TRACK_0 + 9][0];
assign action_r_regs[`ACTION_R_STATUS][26] = action_r_regs[`ACTION_R_TRACK_0 + 10][0];
assign action_r_regs[`ACTION_R_STATUS][27] = action_r_regs[`ACTION_R_TRACK_0 + 11][0];
assign action_r_regs[`ACTION_R_STATUS][28] = action_r_regs[`ACTION_R_TRACK_0 + 12][0];
assign action_r_regs[`ACTION_R_STATUS][29] = action_r_regs[`ACTION_R_TRACK_0 + 13][0];
assign action_r_regs[`ACTION_R_STATUS][30] = action_r_regs[`ACTION_R_TRACK_0 + 14][0];
assign action_r_regs[`ACTION_R_STATUS][31] = action_r_regs[`ACTION_R_TRACK_15][0];
localparam DDR_AWLEN = 4; /* AXI write burst length on the DDR bus (substract 1 to get awlen) */
localparam DDR_ARLEN = 4; /* AXI read burst length on the DDR bus (substract 1 to get arlen) */
localparam ACTION_ID_MAX = 16;
localparam ACTION_ID_BITS = $clog2(ACTION_ID_MAX);
/* NVME Device STATEMACHINE */
enum { NVME_IDLE, NVME_WRITING, NVME_READING, NVME_COMPLETED } activity_state;
/* Verification helper */
enum { VERIFY_OK, VERIFY_ERROR } verify_state;
initial begin
// Complete reset driving ddr_aresetn
axi_ddr_reset();
// Small reset, just set our output to defined values
//axi_ddr_wreset();
//axi_ddr_rreset();
if (`CONFIG_DDR_READWRITE_TEST) begin
axi_ddr_test();
end
end
/* ACTION REGISTER READ STATEMACHINE */
enum { READ_IDLE, READ_DECODE, READ_BUFFER, READ_ACTION_REGS } read_state;
always @(posedge ACT_NVME_ACLK, negedge ACT_NVME_ARESETN)
begin
if (!ACT_NVME_ARESETN) begin
ACT_arready <= 1'b0;
ACT_araddr <= 'hx;
ACT_rdata <= 'hx; /* data to see if read might work ok */
ACT_rresp <= 2'hx;
ACT_rlast <= 1'b0;
ACT_rvalid <= 1'b0;
action_r_regs[`ACTION_R_STATUS] = 32'h0000fff0;
for (int i = `ACTION_R_TRACK_0; i < `ACTION_R_SQ_LEVEL; i++) begin
action_r_regs[i][31:16] <= 16'h0000;
action_r_regs[i][15:8] <= i;
action_r_regs[i][7:0] <= 8'h0;
end
for (int i = `ACTION_R_SQ_LEVEL; i < `ACTION_R_NUM_REGS; i++) begin
action_r_regs[i] <= 32'haabbcc00 + i;
end
read_state <= READ_IDLE;
end else begin
case (read_state)
READ_IDLE: begin /* Capture read address */
ACT_rvalid <= 1'b0; /* No data available yet */
ACT_arready <= 1'b1; /* Ready to accept next read address */
if (ACT_arready && ACT_NVME_AXI_arvalid) begin
ACT_araddr <= ACT_NVME_AXI_araddr;
ACT_arready <= 1'b0; /* address is not needed anymore */
read_state <= READ_DECODE;
end
end
READ_DECODE: begin
ACT_rresp <= 2'h0; /* read status is OK */
ACT_rdata <= action_r_regs[action_r_index]; /* provide data */
ACT_rvalid <= 1'b1; /* signal that data is valid */
ACT_rlast <= 1'b1; /* last transfer for the given address, no burst read yet */
/* Implement read-clear behavior */
if ((ACT_NVME_AXI_araddr >= `ACTION_R_TRACK_0) &&
(ACT_NVME_AXI_araddr <= `ACTION_R_TRACK_15) &&
(activity_state == NVME_COMPLETED)) begin
action_r_regs[action_r_index][31:30] <= 2'b11; /* Mark ACTION_TRACK_n debug */
action_r_regs[action_r_index][0] <= 0; /* Clear ACTION_TRACK_n[0] */
end
read_state <= READ_BUFFER;
end
READ_BUFFER: begin
if (ACT_rvalid && ACT_NVME_AXI_rready) begin
//ACT_rdata <= 32'hX; /* Mark invalid for debugging */
ACT_rvalid <= 1'b0;
ACT_rlast <= 1'b0;
read_state <= READ_IDLE;
end
end
default: begin
end
endcase
end
end
/* ACTION REGISTER WRITE STATEMACHINE */
enum { WRITE_IDLE, WRITE_DECODE, WRITE_BUFFER, WRITE_BURST } write_state;
logic start_nvme_operation;
always @(posedge ACT_NVME_ACLK, negedge ACT_NVME_ARESETN)
begin
if (!ACT_NVME_ARESETN) begin
ACT_awready <= 1'b0; /* Ready to accept next write address */
ACT_bvalid <= 1'b0; /* write not finished */
ACT_bresp <= 2'hx;
ACT_awaddr <= 'hx;
ACT_wdata <= 'hx;
ACT_wready <= 1'b0; /* must be 0 to indicate that we are not ready for data yet, must not let be undefined */
for (int i = 0; i < `ACTION_W_NUM_REGS; i++) begin
action_w_regs[i] <= 'd0;
end
write_state <= WRITE_IDLE;
end else begin
case (write_state)
WRITE_IDLE: begin /* Capture write address */
ACT_awready <= 1'b1;
ACT_wready <= 1'b0;
start_nvme_operation <= 0;
if (ACT_NVME_AXI_awvalid == 1 && ACT_NVME_AXI_awready == 1) begin
ACT_awaddr <= ACT_NVME_AXI_awaddr; // Save away the desired address
ACT_awready <= 1'b0; // Wait for data now, no addresses anymore
ACT_wready <= 1'b1; // Now we captured the address and can receive the data
//action_w_index = 0;
write_state <= WRITE_DECODE;
end
end
WRITE_DECODE: begin /* Capture write data */
if (ACT_NVME_AXI_wvalid == 1 && ACT_wready == 1) begin
/* Save away the data for the address AXI_awaddr */
/* Addresses are 0x0, 0x4, 0x8, 0xC, ... */
ACT_wdata <= ACT_NVME_AXI_wdata;
action_w_regs[ACT_awaddr[ACTION_W_BITS + 1: 2]] <= ACT_NVME_AXI_wdata;
if (ACT_NVME_AXI_awburst == 2'b01) begin
ACT_awaddr <= ACT_awaddr + 4;
write_state <= WRITE_BURST;
end else begin
write_state <= WRITE_BUFFER;
end
end
end
/* AXI Single Write */
WRITE_BUFFER: begin /* Check if command register was written and try to trigger actity based on that */
if ((ACT_NVME_AXI_wvalid == 1'b1) && (ACT_wready == 1'b1) && (ACT_bvalid == 1'b0)) begin
if (ACT_awaddr[ACTION_W_BITS + 1: 2] == `ACTION_W_COMMAND) begin
void' (nvme_operation());
end
end
ACT_bresp <= 2'h0;
ACT_bvalid <= 1'b1; /* Write transfer completed */
if (ACT_bvalid && ACT_NVME_AXI_bready) begin
ACT_bvalid <= 1'b0; /* Accept next write request */
write_state <= WRITE_IDLE;
end
end
/* AXI Burst Read */
WRITE_BURST: begin
ACT_wready <= 1'b1;
if ((ACT_NVME_AXI_wvalid == 1'b1) && (ACT_wready == 1'b1) && (ACT_bvalid == 1'b0)) begin
if (ACT_awaddr[ACTION_W_BITS + 1: 2] == `ACTION_W_COMMAND) begin
start_nvme_operation <= 1;
end
/* store register content */
action_w_regs[ACT_awaddr[ACTION_W_BITS + 1: 2]] <= ACT_NVME_AXI_wdata;
ACT_wdata <= ACT_NVME_AXI_wdata; /* Take write data every clock */
ACT_awaddr <= ACT_awaddr + 4;
end
/* We need to ack the last transfer with bvalid = 1 if wlast was set to 1,
when the partner has set bready, we can start all over again */
if (ACT_NVME_AXI_wvalid == 1'b1 && ACT_wready == 1'b1 && ACT_NVME_AXI_wlast == 1'b1) begin
ACT_bresp <= 2'b00;
ACT_bvalid <= 1'b1;
end
if (ACT_bvalid && ACT_NVME_AXI_bready) begin
if (start_nvme_operation) begin
void '(nvme_operation());
start_nvme_operation <= 0;
end
ACT_bvalid <= 1'b0;
write_state <= WRITE_IDLE;
end
end
endcase
end
end
function nvme_operation();
logic [63:0] ddr_addr;
logic [63:0] lba_addr;
logic [31:0] lba_num;
logic [63:0] axi_addr;
logic [`CMD_TYPE_BITS-1:0] cmd_type;
logic [`CMD_ACTION_ID_BITS-1:0] cmd_action_id;
//#1; /* Ensure that all required registers are latched */
assign cmd_type = action_w_regs[`ACTION_W_COMMAND][`CMD_TYPE_BITS-1:0];
assign cmd_action_id = action_w_regs[`ACTION_W_COMMAND][11:8];
assign ddr_addr = { action_w_regs[`ACTION_W_DPTR_HIGH], action_w_regs[`ACTION_W_DPTR_LOW] };
assign lba_addr = { action_w_regs[`ACTION_W_LBA_HIGH], action_w_regs[`ACTION_W_LBA_LOW] };
assign lba_num = action_w_regs[`ACTION_W_LBA_NUM] + 1;
$display("nvme_operation: ddr=%h lba=%h num=%h cmd_type=%h cmd_action_id=%h",
ddr_addr, lba_addr, lba_num, cmd_type, cmd_action_id);
if (cmd_type == `CMD_READ) begin
fork
nvme_cmd_read(ddr_addr, lba_addr, lba_num, cmd_action_id);
join_none
end
if (cmd_type == `CMD_WRITE) begin
fork
nvme_cmd_write(ddr_addr, lba_addr, lba_num, cmd_action_id);
join_none
end
return 0;
endfunction
task nvme_cmd_read(input logic [63:0] ddr_addr,
input logic [63:0] lba_addr,
input logic [31:0] lba_num,
input logic [`CMD_ACTION_ID_BITS-1:0] cmd_action_id);
logic [63:0] axi_addr;
logic [15:0] i, j;
logic [127:0] axi_data[512/16]; /* size of one LBA */
//int fd;
activity_state = NVME_READING;
if (action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] == 1) begin
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][1] = 1; /* error, results not read */
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b00; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 0; /* Mark ACTION_TRACK_n busy */
verify_state = VERIFY_OK;
#1;
// read stuff: 128bit DDR access => 16 bytes
$display("nvme_read: ddr=%h lba=%h num=%h", ddr_addr, lba_addr, lba_num);
i = 0;
for (axi_addr = ddr_addr; axi_addr < ddr_addr + lba_num * 512; axi_addr += 16 * DDR_AWLEN) begin
/* Read a block once buffer is empty */
if (i == 0) begin
/* Circumvention for simulator problems we have seen. Xilinx change request was filed */
`ifdef SIM_XSIM
static logic [7:0] fname[128]; /* works only for xsim */
`else
static string fname; /* works for ncsim but not for xsim */
`endif
$sformat(fname, "SNAP_LBA_%h.bin", lba_addr);
$readmemh(fname, axi_data);
// FIXME Bug in xsim sformat, the fname version has problems, the fixed filename seems working OK.
// $readmemh("SNAP_LBA_0000000000000000.bin", axi_data);
lba_addr += 1;
end
/* FIXME ... well well not really generic regarding DDR_AWLEN ... HOWTO FIX THAT? */
axi_ddr_write(axi_addr, { axi_data[i], axi_data[i+1], axi_data[i+2],axi_data[i+3] });
$display(" write: axi_addr=%h axi_data=%h%h%h%h", axi_addr,
axi_data[i], axi_data[i+1], axi_data[i+2], axi_data[i+3]);
i = (i + DDR_AWLEN) % (512/16);
//#1;
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b10; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 1; /* Mark ACTION_TRACK_n ready */
activity_state = NVME_COMPLETED;
#1;
endtask
task nvme_cmd_write(input logic [63:0] ddr_addr,
input logic [63:0] lba_addr,
input logic [31:0] lba_num,
input logic [`CMD_ACTION_ID_BITS-1:0] cmd_action_id);
logic [63:0] axi_addr;
logic [15:0] i, j;
logic [127:0] axi_rdata[DDR_ARLEN];
logic [127:0] axi_data[512/16]; /* size of one LBA */
activity_state = NVME_WRITING;
if (action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] == 1) begin
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][1] = 1; /* error, results not read */
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b00; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 0; /* Mark ACTION_TRACK_n busy */
verify_state = VERIFY_OK; /* No real verification done here, but set to OK such that it looks nice */
#1;
// write stuff: 128bit DDR access => 16 bytes
i = 0;
$display("nvme_write: ddr=%h lba=%h num=%h", ddr_addr, lba_addr, lba_num);
for (axi_addr = ddr_addr; axi_addr < ddr_addr + lba_num * 512; axi_addr += 16 * DDR_ARLEN) begin
axi_ddr_read(axi_addr, axi_rdata);
for (j = 0; j < DDR_ARLEN; j++) begin
axi_data[i + j] = axi_rdata[j];
end
$display(" read: axi_addr=%h axi_data=%h%h%h%h", axi_addr,
axi_data[i], axi_data[i+1], axi_data[i+2], axi_data[i+3]);
i = (i + DDR_ARLEN) % (512/16);
/* Write a block once buffer is full */
if (i == 0) begin
static string fname;
$sformat(fname, "SNAP_LBA_%h.bin", lba_addr);
$display("Writing %s\n", fname);
$writememh(fname, axi_data);
lba_addr += 1;
end
//#1;
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b01; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 1; /* Mark ACTION_TRACK_n ready */
activity_state = NVME_COMPLETED;
#1;
endtask
/* AXI RAM Clock */
always begin : AXI_DDR_CLOCK
#1 DDR_aclk = 0;
#1 DDR_aclk = 1;
end
enum { DDR_WIDLE, DDR_WRESET, DDR_WADDR, DDR_WDATA, DDR_WACK, DDR_WERROR } ddr_write_state;
enum { DDR_RIDLE, DDR_RRESET, DDR_RADDR, DDR_RDATA, DDR_RERROR } ddr_read_state;
task axi_ddr_reset();
DDR_aclk = 0;
DDR_aresetn = 0;
ddr_write_state = DDR_WRESET;
ddr_read_state = DDR_RRESET;
#5;
DDR_aresetn = 1;
#1;
endtask
// Test AXI DDR access
// NOTE Development only, did not execute that once it started working in the
// larger context. Try out yourself or throw away if it is not useful.
task axi_ddr_test();
int i;
logic [`DDR_M_ADDRBWIDTH-1:0] axi_addr;
logic [127:0] axi_data[DDR_AWLEN];
logic [127:0] cmp_data[DDR_AWLEN];
// AXI Memory Transfers
/* axi_ddr_reset(); */
for (axi_addr = 0; axi_addr < 4 * 1024; axi_addr += 16 * DDR_AWLEN) begin
for (i = 0; i < DDR_AWLEN; i++) begin
axi_data[i] = 128'h0011223344556677_8899aa00000000 + axi_addr + i;
$display("write: axi_addr=%h axi_data=%h", axi_addr + 16 * i, axi_data[i]);
end
axi_ddr_write(axi_addr, axi_data);
end
/* Read back the data and check for correctness. Result is visible in
ddr_state. */
for (axi_addr = 0; axi_addr < 4 * 1024; axi_addr += 16 * DDR_AWLEN) begin
for (i = 0; i < DDR_AWLEN; i++) begin
cmp_data[i] = 128'h0011223344556677_8899aa00000000 + axi_addr + i;
end
axi_ddr_read(axi_addr, axi_data);
if (axi_data != cmp_data) begin
ddr_read_state = DDR_RERROR;
end
$display("read: axi_addr=%h cmp_data=%h%h%h%h axi_data=%h%h%h%h", axi_addr,
cmp_data[i], cmp_data[i+1], cmp_data[i+2], cmp_data[i+3],
axi_data[i], axi_data[i+1], axi_data[i+2], axi_data[i+3]);
end
endtask
/* task or function, what is more appropriate? How to wait best for completion? */
logic [`DDR_M_ADDRBWIDTH-1:0] ddr_write_addr; /* FIXME need one per slot */
logic [7:0] ddr_widx; /* Index into ddr_write_data[] */
logic [127:0] ddr_write_data[DDR_AWLEN]; /* FIXME need one per slot */
/* task or function, what is more appropriate? How to wait best for completion? */
logic [`DDR_M_ADDRBWIDTH-1:0] ddr_read_addr; /* FIXME need one per slot */
logic [7:0] ddr_ridx; /* Index into ddr_read_data[] */
logic [127:0] ddr_read_data[DDR_ARLEN]; /* FIXME need one per slot */
task axi_ddr_write(input logic [`DDR_M_ADDRBWIDTH-1:0] addr, input logic [127:0] data[DDR_AWLEN]);
while (ddr_write_state != DDR_WIDLE) begin
#1;
end
ddr_write_addr = addr;
ddr_write_data = data;
ddr_write_state = DDR_WADDR;
#1;
while (ddr_write_state != DDR_WIDLE) begin
#1;
end
endtask
function axi_ddr_wreset();
DDR_awid <= 0;
DDR_awlen <= 0;
DDR_awsize <= 0;
DDR_wstrb <= 0;
DDR_awburst <= 0;
DDR_awvalid <= 0;
DDR_wstrb <= 0;
DDR_wlast <= 0;
DDR_wvalid <= 0;
DDR_bready <= 0; // 1: Master is ready
DDR_awlock <= 0;
DDR_awprot <= 0;
DDR_awqos <= 0;
DDR_awcache <= 0;
DDR_wuser <= 0;
DDR_awregion <= 0;
ddr_widx <= 0;
ddr_write_state <= DDR_WIDLE;
return 0;
endfunction
/* DDR WRITE Statemachine */
always @(posedge DDR_aclk, negedge ddr_aresetn) begin
if (!ddr_aresetn) begin
void' (axi_ddr_wreset());
end else begin
case (ddr_write_state)
DDR_WADDR: begin
DDR_awburst <= 2'b01; /* 00 FIXED, 01 INCR burst mode */
ddr_widx <= 0;
DDR_awlen <= DDR_AWLEN - 1;
DDR_awcache <= 4'b0011; /* allow merging / bufferable */
DDR_awprot <= 4'b0000; /* no protection bits */
DDR_awsize <= 3'b100; /* 16 bytes */
DDR_wstrb <= 16'hffff; /* all bytes enabled */
DDR_bready <= 1'b0;
DDR_wvalid <= 1'b0;
DDR_awaddr <= ddr_write_addr;
DDR_awvalid <= 1'b1; /* put address on bus */
if (DDR_M_AXI_awready && DDR_M_AXI_awvalid) begin /* address is on bus and slave saw it */
DDR_wdata <= ddr_write_data[ddr_widx]; /* put data on bus */
ddr_widx <= ddr_widx + 1;
DDR_wvalid <= 1'b1; /* and mark it valid */
DDR_awvalid <= 1'b0;
if (ddr_widx == DDR_AWLEN - 1) begin
DDR_wlast <= 1'b1;
end
ddr_write_state <= DDR_WDATA;
end
end
DDR_WDATA: begin
/* not the last one, put new data on the bus */
if (!DDR_wlast && DDR_M_AXI_wvalid && DDR_M_AXI_wready) begin
DDR_wdata <= ddr_write_data[ddr_widx]; /* put data on bus */
ddr_widx <= ddr_widx + 1;
DDR_wvalid <= 1'b1; /* and mark it valid */
if (ddr_widx == DDR_AWLEN - 1) begin
DDR_wlast <= 1'b1;
end
end
/* last one, end transfer and change back to WACK */
if (DDR_wlast && DDR_M_AXI_wvalid && DDR_M_AXI_wready) begin
DDR_wvalid <= 1'b0;
DDR_wlast <= 1'b0;
DDR_bready <= 1'b1; /* Ready to accept answer */
ddr_write_state <= DDR_WACK;
end
end
DDR_WACK: begin
if (DDR_M_AXI_bready && DDR_M_AXI_bvalid) begin
DDR_bready <= 1'b0;
ddr_write_state <= DDR_WIDLE;
end
end
default begin
end
endcase
end
end
task axi_ddr_read(input logic [`DDR_M_ADDRBWIDTH-1:0] addr, output logic [127:0] data[DDR_ARLEN]);
while (ddr_read_state != DDR_RIDLE) begin
#1;
end
ddr_read_addr = addr;
ddr_read_state = DDR_RADDR;
#1;
while (ddr_read_state != DDR_RIDLE) begin
#1;
end
data = ddr_read_data;
#1;
endtask
function axi_ddr_rreset();
DDR_arid <= 0;
DDR_arlock <= 0;
DDR_arlen <= 0;
DDR_arsize <= 0;
DDR_arburst <= 0;
DDR_arcache <= 0;
DDR_arvalid <= 0;
DDR_rready <= 0; // master is ready to receive data
DDR_rready <= 0;
DDR_arqos <= 0;
DDR_arregion <= 0;
ddr_ridx <= 0;
ddr_read_state <= DDR_RIDLE;
return 0;
endfunction
/* DDR READ Statemachine */
always @(posedge DDR_aclk, negedge ddr_aresetn) begin
if (!ddr_aresetn) begin
void' (axi_ddr_rreset());
end else begin
case (ddr_read_state)
DDR_RADDR: begin
DDR_arburst <= 2'b01; /* 00 FIXED, 01 INCR burst mode */
DDR_arlen <= DDR_ARLEN - 1;
ddr_ridx <= 0;
DDR_arcache <= 4'b0011; /* allow merging, bufferable */
DDR_arprot <= 4'b0000; /* no protection bits */
DDR_arsize <= 3'b100; /* 16 bytes */
DDR_araddr <= ddr_read_addr;
DDR_arvalid <= 1'b1; /* put read address on bus */
if (DDR_M_AXI_arready && DDR_arvalid) begin
DDR_arvalid <= 1'b0; /* no address required anymore */
DDR_rready <= 1'b1; /* ready to receive data */
ddr_read_state <= DDR_RDATA;
end
end
DDR_RDATA: begin
if (DDR_M_AXI_rvalid && DDR_rready) begin
ddr_read_data[ddr_ridx] <= DDR_M_AXI_rdata; /* get the data */
ddr_ridx <= ddr_ridx + 1;
if (DDR_M_AXI_rlast == 1'b1) begin
DDR_rready <= 1'b0; /* have all the data now */
ddr_read_state <= DDR_RIDLE;
end
end
end
default begin
end
endcase
end
end
endmodule |
module rvfi_bus_util_fifo_stage #(
parameter WIDTH = 8
) (
input clock,
input reset,
input in_valid,
output in_ready,
input [WIDTH-1:0] in_data,
output out_valid,
input out_ready,
output [WIDTH-1:0] out_data
);
reg [WIDTH-1:0] buffered;
reg buffer_valid;
wire in_txn = in_valid && in_ready;
wire out_txn = out_valid && out_ready;
assign out_data = buffer_valid ? buffered : in_data;
assign in_ready = out_ready || !buffer_valid;
assign out_valid = in_valid || buffer_valid;
always @(posedge clock) begin
if (reset) begin
buffer_valid <= 0;
end else begin
if (in_txn != out_txn)
buffer_valid <= in_txn;
end
if (in_txn)
buffered <= in_data;
end
endmodule |
module rvfi_bus_util_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 3
) (
input clock,
input reset,
input in_valid,
output in_ready,
input [WIDTH-1:0] in_data,
output out_valid,
input out_ready,
output [WIDTH-1:0] out_data
);
wire [WIDTH-1:0] stage_data [0:DEPTH];
wire [DEPTH:0] stage_valid;
wire [DEPTH:0] stage_ready;
genvar i;
generate for (i = 0; i < DEPTH; i = i + 1) begin
rvfi_bus_util_fifo_stage #(.WIDTH(WIDTH)) stage (
.clock(clock),
.reset(reset),
.in_data(stage_data[i]),
.out_data(stage_data[i+1]),
.in_valid(stage_valid[i]),
.out_valid(stage_valid[i+1]),
.in_ready(stage_ready[i]),
.out_ready(stage_ready[i+1])
);
end endgenerate
assign stage_valid[0] = in_valid;
assign stage_data[0] = in_data;
assign in_ready = stage_ready[0];
assign out_valid = stage_valid[DEPTH];
assign stage_ready[DEPTH] = out_ready;
assign out_data = stage_data[DEPTH];
endmodule |
module testbench (
input clk
);
reg reset = 1;
always @(posedge clk)
reset <= 0;
(* keep *) wire iBus_cmd_valid;
(* keep *) wire [31:0] iBus_cmd_payload_pc;
(* keep *) `rvformal_rand_reg iBus_cmd_ready;
(* keep *) `rvformal_rand_reg iBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;
(* keep *) wire dBus_cmd_valid;
(* keep *) wire dBus_cmd_payload_wr;
(* keep *) wire [31:0] dBus_cmd_payload_address;
(* keep *) wire [31:0] dBus_cmd_payload_data;
(* keep *) wire [1:0] dBus_cmd_payload_size;
(* keep *) `rvformal_rand_reg dBus_cmd_ready;
(* keep *) `rvformal_rand_reg dBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data;
`RVFI_WIRES
(* keep *) wire [31:0] dmem_addr;
(* keep *) reg [31:0] dmem_data;
rvfi_dmem_check checker_inst (
.clock (clk ),
.reset (reset ),
.enable (1'b1 ),
.dmem_addr (dmem_addr),
`RVFI_CONN
);
(* keep *) reg dmem_last_valid;
(* keep *) wire [3:0] dBus_cmd_payload_mask;
assign dBus_cmd_payload_mask = ((1 << (1 << dBus_cmd_payload_size))-1) << dBus_cmd_payload_address[1:0];
always @(posedge clk) begin
if (reset) begin
dmem_last_valid <= 0;
end else begin
if(dmem_last_valid) begin
assume(dBus_rsp_data == dmem_data);
end
if(dBus_rsp_ready) begin
dmem_last_valid <= 0;
end
if(dBus_cmd_valid && dBus_cmd_ready) begin
if((dBus_cmd_payload_address >> 2) == (dmem_addr >> 2)) begin
if(!dBus_cmd_payload_wr) begin
dmem_last_valid <= 1;
end else begin
if (dBus_cmd_payload_mask[0]) dmem_data[ 7: 0] <= dBus_cmd_payload_data[ 7: 0];
if (dBus_cmd_payload_mask[1]) dmem_data[15: 8] <= dBus_cmd_payload_data[15: 8];
if (dBus_cmd_payload_mask[2]) dmem_data[23:16] <= dBus_cmd_payload_data[23:16];
if (dBus_cmd_payload_mask[3]) dmem_data[31:24] <= dBus_cmd_payload_data[31:24];
end
end
end
end
end
VexRiscv uut (
.clk (clk ),
.reset (reset ),
.iBus_cmd_valid (iBus_cmd_valid),
.iBus_cmd_ready (iBus_cmd_ready),
.iBus_cmd_payload_pc (iBus_cmd_payload_pc ),
.iBus_rsp_ready(iBus_rsp_ready),
.iBus_rsp_inst (iBus_rsp_inst),
.iBus_rsp_error(1'b0),
.dBus_cmd_valid(dBus_cmd_valid),
.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
.dBus_cmd_payload_address(dBus_cmd_payload_address),
.dBus_cmd_payload_data(dBus_cmd_payload_data),
.dBus_cmd_payload_size(dBus_cmd_payload_size),
.dBus_cmd_ready(dBus_cmd_ready),
.dBus_rsp_ready(dBus_rsp_ready),
.dBus_rsp_data(dBus_rsp_data),
.dBus_rsp_error(1'b0),
`RVFI_CONN
);
endmodule |
module testbench (
input clk
);
reg reset = 1;
always @(posedge clk)
reset <= 0;
(* keep *) wire iBus_cmd_valid;
(* keep *) wire [31:0] iBus_cmd_payload_pc;
(* keep *) `rvformal_rand_reg iBus_cmd_ready;
(* keep *) `rvformal_rand_reg iBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;
(* keep *) wire dBus_cmd_valid;
(* keep *) wire dBus_cmd_payload_wr;
(* keep *) wire [31:0] dBus_cmd_payload_address;
(* keep *) wire [31:0] dBus_cmd_payload_data;
(* keep *) wire [1:0] dBus_cmd_payload_size;
(* keep *) `rvformal_rand_reg dBus_cmd_ready;
(* keep *) `rvformal_rand_reg dBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data;
`RVFI_WIRES
(* keep *) wire [31:0] imem_addr;
(* keep *) wire [15:0] imem_data;
rvfi_imem_check checker_inst (
.clock (clk ),
.reset (reset ),
.enable (1'b1 ),
.imem_addr (imem_addr),
.imem_data (imem_data),
`RVFI_CONN
);
(* keep *) wire imem_last_valid;
(* keep *) wire [31:0] imem_last_addr;
always @(posedge clk) begin
if (reset) begin
imem_last_valid <= 0;
end else begin
if(imem_last_valid) begin
if (imem_last_addr == imem_addr)
assume(iBus_rsp_inst[15:0] == imem_data);
if (imem_last_addr+2 == imem_addr)
assume(iBus_rsp_inst[31:16] == imem_data);
end
if(iBus_rsp_ready) begin
imem_last_valid <= 0;
end
if(iBus_cmd_valid && iBus_cmd_ready) begin
imem_last_valid <= 1;
imem_last_addr <= iBus_cmd_payload_pc;
end
end
end
VexRiscv uut (
.clk (clk ),
.reset (reset ),
.iBus_cmd_valid (iBus_cmd_valid),
.iBus_cmd_ready (iBus_cmd_ready),
.iBus_cmd_payload_pc (iBus_cmd_payload_pc ),
.iBus_rsp_ready(iBus_rsp_ready),
.iBus_rsp_inst (iBus_rsp_inst),
.iBus_rsp_error(1'b0),
.dBus_cmd_valid(dBus_cmd_valid),
.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
.dBus_cmd_payload_address(dBus_cmd_payload_address),
.dBus_cmd_payload_data(dBus_cmd_payload_data),
.dBus_cmd_payload_size(dBus_cmd_payload_size),
.dBus_cmd_ready(dBus_cmd_ready),
.dBus_rsp_ready(dBus_rsp_ready),
.dBus_rsp_data(dBus_rsp_data),
.dBus_rsp_error(1'b0),
`RVFI_CONN
);
endmodule |
module SB_RAM40_4K (
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
// MODE 0: 256 x 16
// MODE 1: 512 x 8
// MODE 2: 1024 x 4
// MODE 3: 2048 x 2
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
`ifndef BLACKBOX
wire [15:0] WMASK_I;
wire [15:0] RMASK_I;
reg [15:0] RDATA_I;
wire [15:0] WDATA_I;
generate
case (WRITE_MODE)
0: assign WMASK_I = MASK;
1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (READ_MODE)
0: assign RMASK_I = 16'b 0000_0000_0000_0000;
1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (WRITE_MODE)
0: assign WDATA_I = WDATA;
1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
endcase
case (READ_MODE)
0: assign RDATA = RDATA_I;
1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
endcase
endgenerate
integer i;
reg [15:0] memory [0:255];
initial begin
for (i=0; i<16; i=i+1) begin
memory[ 0*16 + i] <= INIT_0[16*i +: 16];
memory[ 1*16 + i] <= INIT_1[16*i +: 16];
memory[ 2*16 + i] <= INIT_2[16*i +: 16];
memory[ 3*16 + i] <= INIT_3[16*i +: 16];
memory[ 4*16 + i] <= INIT_4[16*i +: 16];
memory[ 5*16 + i] <= INIT_5[16*i +: 16];
memory[ 6*16 + i] <= INIT_6[16*i +: 16];
memory[ 7*16 + i] <= INIT_7[16*i +: 16];
memory[ 8*16 + i] <= INIT_8[16*i +: 16];
memory[ 9*16 + i] <= INIT_9[16*i +: 16];
memory[10*16 + i] <= INIT_A[16*i +: 16];
memory[11*16 + i] <= INIT_B[16*i +: 16];
memory[12*16 + i] <= INIT_C[16*i +: 16];
memory[13*16 + i] <= INIT_D[16*i +: 16];
memory[14*16 + i] <= INIT_E[16*i +: 16];
memory[15*16 + i] <= INIT_F[16*i +: 16];
end
end
always @(posedge WCLK) begin
if (WE && WCLKE) begin
if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
end
end
always @(posedge RCLK) begin
if (RE && RCLKE) begin
RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
end
end
`endif
endmodule |
module SB_RAM40_4KNR (
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule |
module SB_RAM40_4KNW (
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (~WCLKN),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule |
module SB_RAM40_4KNRNW (
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (~WCLKN),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule |
module nervsoc (
input clock,
input reset,
output reg [31:0] leds
);
reg [31:0] imem [0:1023];
reg [31:0] dmem [0:1023];
wire stall = 0;
wire trap;
wire [31:0] imem_addr;
reg [31:0] imem_data;
wire dmem_valid;
wire [31:0] dmem_addr;
wire [3:0] dmem_wstrb;
wire [31:0] dmem_wdata;
reg [31:0] dmem_rdata;
initial begin
$readmemh("firmware.hex", imem);
end
always @(posedge clock)
imem_data <= imem[imem_addr[31:2]];
always @(posedge clock) begin
if (dmem_valid) begin
if (dmem_addr == 32'h 0100_0000) begin
if (dmem_wstrb[0]) leds[ 7: 0] <= dmem_wdata[ 7: 0];
if (dmem_wstrb[1]) leds[15: 8] <= dmem_wdata[15: 8];
if (dmem_wstrb[2]) leds[23:16] <= dmem_wdata[23:16];
if (dmem_wstrb[3]) leds[31:24] <= dmem_wdata[31:24];
end else begin
if (dmem_wstrb[0]) dmem[dmem_addr[31:2]][ 7: 0] <= dmem_wdata[ 7: 0];
if (dmem_wstrb[1]) dmem[dmem_addr[31:2]][15: 8] <= dmem_wdata[15: 8];
if (dmem_wstrb[2]) dmem[dmem_addr[31:2]][23:16] <= dmem_wdata[23:16];
if (dmem_wstrb[3]) dmem[dmem_addr[31:2]][31:24] <= dmem_wdata[31:24];
end
dmem_rdata <= dmem[dmem_addr[31:2]];
end
end
nerv cpu (
.clock (clock ),
.reset (reset ),
.stall (stall ),
.trap (trap ),
.imem_addr (imem_addr ),
.imem_data (imem_data ),
.dmem_valid(dmem_valid),
.dmem_addr (dmem_addr ),
.dmem_wstrb(dmem_wstrb),
.dmem_wdata(dmem_wdata),
.dmem_rdata(dmem_rdata)
);
endmodule |
module testbench;
localparam MEM_ADDR_WIDTH = 16;
localparam TIMEOUT = (1<<10);
reg clock;
reg reset = 1'b1;
reg stall = 1'b0;
wire trap;
wire [31:0] imem_addr;
reg [31:0] imem_data;
wire dmem_valid;
wire [31:0] dmem_addr;
wire [ 3:0] dmem_wstrb;
wire [31:0] dmem_wdata;
reg [31:0] dmem_rdata;
reg [31:0] irq = 'b0;
always #5 clock = clock === 1'b0;
always @(posedge clock) reset <= 0;
reg [7:0] mem [0:(1<<MEM_ADDR_WIDTH)-1];
wire wr_in_mem_range = (dmem_addr[31:2] < (1<<MEM_ADDR_WIDTH));
wire wr_in_output = (dmem_addr == 32'h 02000000);
reg [31:0] out;
reg out_valid;
always @(posedge clock) begin
if (out_valid) begin
$write("%c", out[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
end
`ifdef STALL
always @(posedge clock) begin
stall <= $random;
end
`endif
always @(posedge clock) begin
if (imem_addr >= (1<<MEM_ADDR_WIDTH)) begin
$display("Memory access out of range: imem_addr = 0x%08x", imem_addr);
end
if (dmem_valid && !(wr_in_mem_range || wr_in_output)) begin
$display("Memory access out of range: dmem_addr = 0x%08x", dmem_addr);
end
end
integer i;
always @(posedge clock) begin
out <= 32'h 0;
out_valid <= 1'b0;
if (!stall && !reset) begin
imem_data <= {
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]
};
if (dmem_valid) begin
dmem_rdata <= {
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]
};
for (i=0;i<4;i=i+1) begin
if (dmem_wstrb[i]) begin
if (wr_in_mem_range) begin
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], i[1:0]}] <= dmem_wdata[(i*8)+: 8];
end
if (wr_in_output) begin
out[(i*8)+: 8] <= dmem_wdata[(i*8)+: 8];
out_valid <= 1'b1;
end
dmem_rdata <= 'hx;
end
end
end else begin
dmem_rdata <= 32'h XXXX_XXXX;
end
end
end
initial begin
$readmemh("firmware.hex", mem);
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
end
nerv dut (
.clock(clock),
.reset(reset),
.stall(stall),
.trap(trap),
.imem_addr(imem_addr),
.imem_data(stall ? 32'bx : imem_data),
.dmem_valid(dmem_valid),
.dmem_addr(dmem_addr),
.dmem_wstrb(dmem_wstrb),
.dmem_wdata(dmem_wdata),
.dmem_rdata(stall ? 32'bx : dmem_rdata),
`ifdef NERV_FAULT
.imem_fault(1'b0),
.dmem_fault(1'b0),
`endif
.irq(irq)
);
reg [31:0] cycles = 0;
always @(posedge clock) begin
cycles <= cycles + 32'h1;
if (trap || (cycles >= TIMEOUT)) begin
$display("Simulated %0d cycles", cycles);
$finish;
end
end
endmodule |
module testbench;
localparam TIMEOUT = (1<<10);
reg clock;
wire LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5;
always #5 clock = clock === 1'b0;
top dut (
.CLK(clock),
.LEDR_N(LEDR_N),
.LEDG_N(LEDG_N),
.LED1(LED1),
.LED2(LED2),
.LED3(LED3),
.LED4(LED4),
.LED5(LED5)
);
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
end
reg [31:0] cycles = 0;
always @(posedge clock) begin
cycles <= cycles + 32'h1;
if (cycles >= TIMEOUT) begin
$display("Simulated %0d cycles", cycles);
$finish;
end
end
endmodule |
module emib_ch (
inout s_aib95,
inout aib95,
inout s_aib94,
inout aib94,
inout s_aib93,
inout aib93,
inout s_aib92,
inout aib92,
inout s_aib91,
inout aib91,
inout s_aib90,
inout aib90,
inout s_aib89,
inout aib89,
inout s_aib88,
inout aib88,
inout s_aib87,
inout aib87,
inout s_aib86,
inout aib86,
inout s_aib85,
inout aib85,
inout s_aib84,
inout aib84,
inout s_aib83,
inout aib83,
inout s_aib82,
inout aib82,
inout s_aib81,
inout aib81,
inout s_aib80,
inout aib80,
inout s_aib79,
inout aib79,
inout s_aib78,
inout aib78,
inout s_aib77,
inout aib77,
inout s_aib76,
inout aib76,
inout s_aib75,
inout aib75,
inout s_aib74,
inout aib74,
inout s_aib73,
inout aib73,
inout s_aib72,
inout aib72,
inout s_aib71,
inout aib71,
inout s_aib70,
inout aib70,
inout s_aib69,
inout aib69,
inout s_aib68,
inout aib68,
inout s_aib67,
inout aib67,
inout s_aib66,
inout aib66,
inout s_aib65,
inout aib65,
inout s_aib64,
inout aib64,
inout s_aib63,
inout aib63,
inout s_aib62,
inout aib62,
inout s_aib61,
inout aib61,
inout s_aib60,
inout aib60,
inout s_aib59,
inout aib59,
inout s_aib58,
inout aib58,
inout s_aib57,
inout aib57,
inout s_aib56,
inout aib56,
inout s_aib55,
inout aib55,
inout s_aib54,
inout aib54,
inout s_aib53,
inout aib53,
inout s_aib52,
inout aib52,
inout s_aib51,
inout aib51,
inout s_aib50,
inout aib50,
inout s_aib49,
inout aib49,
inout s_aib48,
inout aib48,
inout s_aib47,
inout aib47,
inout s_aib46,
inout aib46,
inout s_aib45,
inout aib45,
inout s_aib44,
inout aib44,
inout s_aib43,
inout aib43,
inout s_aib42,
inout aib42,
inout s_aib41,
inout aib41,
inout s_aib40,
inout aib40,
inout s_aib39,
inout aib39,
inout s_aib38,
inout aib38,
inout s_aib37,
inout aib37,
inout s_aib36,
inout aib36,
inout s_aib35,
inout aib35,
inout s_aib34,
inout aib34,
inout s_aib33,
inout aib33,
inout s_aib32,
inout aib32,
inout s_aib31,
inout aib31,
inout s_aib30,
inout aib30,
inout s_aib29,
inout aib29,
inout s_aib28,
inout aib28,
inout s_aib27,
inout aib27,
inout s_aib26,
inout aib26,
inout s_aib25,
inout aib25,
inout s_aib24,
inout aib24,
inout s_aib23,
inout aib23,
inout s_aib22,
inout aib22,
inout s_aib21,
inout aib21,
inout s_aib20,
inout aib20,
inout s_aib19,
inout aib19,
inout s_aib18,
inout aib18,
inout s_aib17,
inout aib17,
inout s_aib16,
inout aib16,
inout s_aib15,
inout aib15,
inout s_aib14,
inout aib14,
inout s_aib13,
inout aib13,
inout s_aib12,
inout aib12,
inout s_aib11,
inout aib11,
inout s_aib10,
inout aib10,
inout s_aib9,
inout aib9,
inout s_aib8,
inout aib8,
inout s_aib7,
inout aib7,
inout s_aib6,
inout aib6,
inout s_aib5,
inout aib5,
inout s_aib4,
inout aib4,
inout s_aib3,
inout aib3,
inout s_aib2,
inout aib2,
inout s_aib1,
inout aib1,
inout s_aib0,
inout aib0
);
aliasv xaliasv95 (
.PLUS(s_aib95),
.MINUS(aib95)
);
aliasv xaliasv94 (
.PLUS(s_aib94),
.MINUS(aib94)
);
aliasv xaliasv93 (
.PLUS(s_aib93),
.MINUS(aib93)
);
aliasv xaliasv92 (
.PLUS(s_aib92),
.MINUS(aib92)
);
aliasv xaliasv91 (
.PLUS(s_aib91),
.MINUS(aib91)
);
aliasv xaliasv90 (
.PLUS(s_aib90),
.MINUS(aib90)
);
aliasv xaliasv89 (
.PLUS(s_aib89),
.MINUS(aib89)
);
aliasv xaliasv88 (
.PLUS(s_aib88),
.MINUS(aib88)
);
aliasv xaliasv87 (
.PLUS(s_aib87),
.MINUS(aib87)
);
aliasv xaliasv86 (
.PLUS(s_aib86),
.MINUS(aib86)
);
aliasv xaliasv85 (
.PLUS(s_aib85),
.MINUS(aib85)
);
aliasv xaliasv84 (
.PLUS(s_aib84),
.MINUS(aib84)
);
aliasv xaliasv83 (
.PLUS(s_aib83),
.MINUS(aib83)
);
aliasv xaliasv82 (
.PLUS(s_aib82),
.MINUS(aib82)
);
aliasv xaliasv81 (
.PLUS(s_aib81),
.MINUS(aib81)
);
aliasv xaliasv80 (
.PLUS(s_aib80),
.MINUS(aib80)
);
aliasv xaliasv79 (
.PLUS(s_aib79),
.MINUS(aib79)
);
aliasv xaliasv78 (
.PLUS(s_aib78),
.MINUS(aib78)
);
aliasv xaliasv77 (
.PLUS(s_aib77),
.MINUS(aib77)
);
aliasv xaliasv76 (
.PLUS(s_aib76),
.MINUS(aib76)
);
aliasv xaliasv75 (
.PLUS(s_aib75),
.MINUS(aib75)
);
aliasv xaliasv74 (
.PLUS(s_aib74),
.MINUS(aib74)
);
aliasv xaliasv73 (
.PLUS(s_aib73),
.MINUS(aib73)
);
aliasv xaliasv72 (
.PLUS(s_aib72),
.MINUS(aib72)
);
aliasv xaliasv71 (
.PLUS(s_aib71),
.MINUS(aib71)
);
aliasv xaliasv70 (
.PLUS(s_aib70),
.MINUS(aib70)
);
aliasv xaliasv69 (
.PLUS(s_aib69),
.MINUS(aib69)
);
aliasv xaliasv68 (
.PLUS(s_aib68),
.MINUS(aib68)
);
aliasv xaliasv67 (
.PLUS(s_aib67),
.MINUS(aib67)
);
aliasv xaliasv66 (
.PLUS(s_aib66),
.MINUS(aib66)
);
aliasv xaliasv65 (
.PLUS(s_aib65),
.MINUS(aib65)
);
aliasv xaliasv64 (
.PLUS(s_aib64),
.MINUS(aib64)
);
aliasv xaliasv63 (
.PLUS(s_aib63),
.MINUS(aib63)
);
aliasv xaliasv62 (
.PLUS(s_aib62),
.MINUS(aib62)
);
aliasv xaliasv61 (
.PLUS(s_aib61),
.MINUS(aib61)
);
aliasv xaliasv60 (
.PLUS(s_aib60),
.MINUS(aib60)
);
aliasv xaliasv59 (
.PLUS(s_aib59),
.MINUS(aib59)
);
aliasv xaliasv58 (
.PLUS(s_aib58),
.MINUS(aib58)
);
aliasv xaliasv57 (
.PLUS(s_aib57),
.MINUS(aib57)
);
aliasv xaliasv56 (
.PLUS(s_aib56),
.MINUS(aib56)
);
aliasv xaliasv55 (
.PLUS(s_aib55),
.MINUS(aib55)
);
aliasv xaliasv54 (
.PLUS(s_aib54),
.MINUS(aib54)
);
aliasv xaliasv53 (
.PLUS(s_aib53),
.MINUS(aib53)
);
aliasv xaliasv52 (
.PLUS(s_aib52),
.MINUS(aib52)
);
aliasv xaliasv51 (
.PLUS(s_aib51),
.MINUS(aib51)
);
aliasv xaliasv50 (
.PLUS(s_aib50),
.MINUS(aib50)
);
aliasv xaliasv49 (
.PLUS(s_aib49),
.MINUS(aib49)
);
aliasv xaliasv48 (
.PLUS(s_aib48),
.MINUS(aib48)
);
aliasv xaliasv47 (
.PLUS(s_aib47),
.MINUS(aib47)
);
aliasv xaliasv46 (
.PLUS(s_aib46),
.MINUS(aib46)
);
aliasv xaliasv45 (
.PLUS(s_aib45),
.MINUS(aib45)
);
aliasv xaliasv44 (
.PLUS(s_aib44),
.MINUS(aib44)
);
aliasv xaliasv43 (
.PLUS(s_aib43),
.MINUS(aib43)
);
aliasv xaliasv42 (
.PLUS(s_aib42),
.MINUS(aib42)
);
aliasv xaliasv41 (
.PLUS(s_aib41),
.MINUS(aib41)
);
aliasv xaliasv40 (
.PLUS(s_aib40),
.MINUS(aib40)
);
aliasv xaliasv39 (
.PLUS(s_aib39),
.MINUS(aib39)
);
aliasv xaliasv38 (
.PLUS(s_aib38),
.MINUS(aib38)
);
aliasv xaliasv37 (
.PLUS(s_aib37),
.MINUS(aib37)
);
aliasv xaliasv36 (
.PLUS(s_aib36),
.MINUS(aib36)
);
aliasv xaliasv35 (
.PLUS(s_aib35),
.MINUS(aib35)
);
aliasv xaliasv34 (
.PLUS(s_aib34),
.MINUS(aib34)
);
aliasv xaliasv33 (
.PLUS(s_aib33),
.MINUS(aib33)
);
aliasv xaliasv32 (
.PLUS(s_aib32),
.MINUS(aib32)
);
aliasv xaliasv31 (
.PLUS(s_aib31),
.MINUS(aib31)
);
aliasv xaliasv30 (
.PLUS(s_aib30),
.MINUS(aib30)
);
aliasv xaliasv29 (
.PLUS(s_aib29),
.MINUS(aib29)
);
aliasv xaliasv28 (
.PLUS(s_aib28),
.MINUS(aib28)
);
aliasv xaliasv27 (
.PLUS(s_aib27),
.MINUS(aib27)
);
aliasv xaliasv26 (
.PLUS(s_aib26),
.MINUS(aib26)
);
aliasv xaliasv25 (
.PLUS(s_aib25),
.MINUS(aib25)
);
aliasv xaliasv24 (
.PLUS(s_aib24),
.MINUS(aib24)
);
aliasv xaliasv23 (
.PLUS(s_aib23),
.MINUS(aib23)
);
aliasv xaliasv22 (
.PLUS(s_aib22),
.MINUS(aib22)
);
aliasv xaliasv21 (
.PLUS(s_aib21),
.MINUS(aib21)
);
aliasv xaliasv20 (
.PLUS(s_aib20),
.MINUS(aib20)
);
aliasv xaliasv19 (
.PLUS(s_aib19),
.MINUS(aib19)
);
aliasv xaliasv18 (
.PLUS(s_aib18),
.MINUS(aib18)
);
aliasv xaliasv17 (
.PLUS(s_aib17),
.MINUS(aib17)
);
aliasv xaliasv16 (
.PLUS(s_aib16),
.MINUS(aib16)
);
aliasv xaliasv15 (
.PLUS(s_aib15),
.MINUS(aib15)
);
aliasv xaliasv14 (
.PLUS(s_aib14),
.MINUS(aib14)
);
aliasv xaliasv13 (
.PLUS(s_aib13),
.MINUS(aib13)
);
aliasv xaliasv12 (
.PLUS(s_aib12),
.MINUS(aib12)
);
aliasv xaliasv11 (
.PLUS(s_aib11),
.MINUS(aib11)
);
aliasv xaliasv10 (
.PLUS(s_aib10),
.MINUS(aib10)
);
aliasv xaliasv9 (
.PLUS(s_aib9),
.MINUS(aib9)
);
aliasv xaliasv8 (
.PLUS(s_aib8),
.MINUS(aib8)
);
aliasv xaliasv7 (
.PLUS(s_aib7),
.MINUS(aib7)
);
aliasv xaliasv6 (
.PLUS(s_aib6),
.MINUS(aib6)
);
aliasv xaliasv5 (
.PLUS(s_aib5),
.MINUS(aib5)
);
aliasv xaliasv4 (
.PLUS(s_aib4),
.MINUS(aib4)
);
aliasv xaliasv3 (
.PLUS(s_aib3),
.MINUS(aib3)
);
aliasv xaliasv2 (
.PLUS(s_aib2),
.MINUS(aib2)
);
aliasv xaliasv1 (
.PLUS(s_aib1),
.MINUS(aib1)
);
aliasv xaliasv0 (
.PLUS(s_aib0),
.MINUS(aib0)
);
endmodule |
module aliasv ( .PLUS(w), .MINUS(w) );
inout w;
wire w;
endmodule |
module aliasv_16 ( .PLUS(w), .MINUS(w) );
inout [15:0] w;
wire [15:0] w;
endmodule |
module aib_top_wrapper_v2s
# (
parameter DATA_WIDTH = 78,
parameter TOTAL_CHNL_NUM = 24
)
(
//================================================================================================
// Reset Inteface
input i_conf_done, // AIB adaptor hard reset
input dual_mode_select,
// reset for XCVRIF
output [TOTAL_CHNL_NUM-1:0] fs_mac_rdy, //o_rx_xcvrif_rst_n, receiving path reset
//===============================================================================================
// Configuration Interface which includes two paths
// Path directly from chip programming controller
input i_cfg_avmm_clk,
input i_cfg_avmm_rst_n,
input [16:0] i_cfg_avmm_addr, // address to be programmed
input [3:0] i_cfg_avmm_byte_en, // byte enable
input i_cfg_avmm_read, // Asserted to indicate the Cfg read access
input i_cfg_avmm_write, // Asserted to indicate the Cfg write access
input [31:0] i_cfg_avmm_wdata, // data to be programmed
output o_cfg_avmm_rdatavld,// Assert to indicate data available for Cfg read access
output [31:0] o_cfg_avmm_rdata, // data returned for Cfg read access
output o_cfg_avmm_waitreq, // asserted to indicate not ready for Cfg access
//===============================================================================================
// Data Path
// Rx Path clocks/data, from master (current chiplet) to slave (FPGA)
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_clk, // i_rx_pma_clk.Rx path clk for data receiving,
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_div2_clk, // i_rx_pma_div2_clk, Divided by 2 clock on Rx pathinput
input [TOTAL_CHNL_NUM*DATA_WIDTH-1:0] data_in , // i_rx_pma_data, Directed bump rx data sync path
input [TOTAL_CHNL_NUM-1:0] m_wr_clk, //Clock for phase compensation fifo
// Tx Path clocks/data, from slave (FPGA) to master (current chiplet)
input [TOTAL_CHNL_NUM-1:0] m_ns_rcv_clk, //i_tx_pma_clk, sent over to the other chiplet to be used for the clock
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_clk, //o_tx_transfer_clk, clock used for tx data transmission
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_div2_clk, // o_tx_transfer_div2_clk, half rate of tx data transmission clock
output [TOTAL_CHNL_NUM-1:0] m_fs_rcv_clk,
output [TOTAL_CHNL_NUM-1:0] m_fs_rcv_div2_clk,
output [TOTAL_CHNL_NUM*78-1:0] data_out, //o_tx_pma_data, Directed bump tx data sync path
input [TOTAL_CHNL_NUM-1:0] m_rd_clk, //Clock for phase compensation fifo
//=================================================================================================
// AIB open source IP enhancement. The following ports are added to
// be compliance with AIB specification 1.1
input [TOTAL_CHNL_NUM-1:0] ns_mac_rdy, //From Mac. To indicate MAC is ready to send and receive // data. use aibio49
input [TOTAL_CHNL_NUM-1:0] ns_adapter_rstn, //From Mac. To reset near site adapt reset state machine and far site sm. Not implemented currently.
output [TOTAL_CHNL_NUM*81-1:0] ms_sideband, //Status of serial shifting bit from this master chiplet to slave chiplet
output [TOTAL_CHNL_NUM*73-1:0] sl_sideband, //Status of serial shifting bit from slave chiplet to master chiplet.
output [TOTAL_CHNL_NUM-1:0] m_rxfifo_align_done,
output [TOTAL_CHNL_NUM-1:0] ms_tx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] ms_rx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] sl_tx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] sl_rx_transfer_en,
input [TOTAL_CHNL_NUM-1:0] sl_tx_dcc_dll_lock_req,
input [TOTAL_CHNL_NUM-1:0] sl_rx_dcc_dll_lock_req,
//=================================================================================================
// Inout signals for AIB ubump
inout [TOTAL_CHNL_NUM*20-1:0] iopad_tx,
inout [TOTAL_CHNL_NUM*20-1:0] iopad_rx,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_mac_rdy,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_mac_rdy,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_adapter_rstn,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_adapter_rstn,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_load,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_data,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_load,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_data,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib45,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib46,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib47,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib50,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib51,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib52,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib58,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib60,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib61,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib62,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib63,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib64,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib66,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib67,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib68,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib69,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib70,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib71,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib72,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib73,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib74,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib75,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib76,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib77,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib78,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib79,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib80,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib81,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib88,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib89,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib90,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib91,
inout por, //iopad_aib_aux[85] power on from slave.
inout device_detect, //iopad_aib_aux[74] device detect to slave
//======================================================================================
// Interface with AIB control block
input m_power_on_reset,
output m_device_detect,
input m_device_detect_ovrd,
// from control block register file
// input [31:0] i_aibaux_ctrl_bus0, //1st set of register bits from register file
// input [31:0] i_aibaux_ctrl_bus1, //2nd set of register bits from register file
// input [31:0] i_aibaux_ctrl_bus2, //3rd set of register bits from register file
// input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from User
//
input i_osc_clk, // test clock from c4 bump, may tie low for User if not used
output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator
//======================================================================================
// DFT signals
input scan_clk,
input scan_enable,
input [19:0] scan_in_ch0,
input [19:0] scan_in_ch1,
input [19:0] scan_in_ch2,
input [19:0] scan_in_ch3,
input [19:0] scan_in_ch4,
input [19:0] scan_in_ch5,
input [19:0] scan_in_ch6,
input [19:0] scan_in_ch7,
input [19:0] scan_in_ch8,
input [19:0] scan_in_ch9,
input [19:0] scan_in_ch10,
input [19:0] scan_in_ch11,
input [19:0] scan_in_ch12,
input [19:0] scan_in_ch13,
input [19:0] scan_in_ch14,
input [19:0] scan_in_ch15,
input [19:0] scan_in_ch16,
input [19:0] scan_in_ch17,
input [19:0] scan_in_ch18,
input [19:0] scan_in_ch19,
input [19:0] scan_in_ch20,
input [19:0] scan_in_ch21,
input [19:0] scan_in_ch22,
input [19:0] scan_in_ch23,
// output [TOTAL_CHNL_NUM-1:0] [19:0] scan_out,
output [19:0] scan_out_ch0,
output [19:0] scan_out_ch1,
output [19:0] scan_out_ch2,
output [19:0] scan_out_ch3,
output [19:0] scan_out_ch4,
output [19:0] scan_out_ch5,
output [19:0] scan_out_ch6,
output [19:0] scan_out_ch7,
output [19:0] scan_out_ch8,
output [19:0] scan_out_ch9,
output [19:0] scan_out_ch10,
output [19:0] scan_out_ch11,
output [19:0] scan_out_ch12,
output [19:0] scan_out_ch13,
output [19:0] scan_out_ch14,
output [19:0] scan_out_ch15,
output [19:0] scan_out_ch16,
output [19:0] scan_out_ch17,
output [19:0] scan_out_ch18,
output [19:0] scan_out_ch19,
output [19:0] scan_out_ch20,
output [19:0] scan_out_ch21,
output [19:0] scan_out_ch22,
output [19:0] scan_out_ch23,
input i_scan_clk, //ATPG Scan shifting clock from Test Pad.
input i_test_scan_en,
input i_test_scan_mode,
// input i_test_clk_1g, //1GHz free running direct accessed ATPG at speed clock.
// input i_test_clk_125m,//Divided down from i_test_clk_1g.
// input i_test_clk_250m,//Divided down from i_test_clk_1g.
// input i_test_clk_500m,//Divided down from i_test_clk_1g.
// input i_test_clk_62m, //Divided down from i_test_clk_1g.
//The divided down clock is for different clock domain at
//speed test.
//Channel ATPG signals from/to CODEC
// input [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] i_test_c3adapt_scan_in, //scan in hook from Codec
// output [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] o_test_c3adapt_scan_out, //scan out hook to Codec
//Inputs from TCB (JTAG signals)
input i_jtag_clkdr, // (from dbg_test_bscan block)Enable AIB IO boundary scan clock (clock gate control)
input i_jtag_clksel, // (from dbg_test_bscan block)Select between i_jtag_clkdr_in and functional clk
input i_jtag_intest, // (from dbg_test_bscan block)Enable in test operation
input i_jtag_mode, // (from dbg_test_bscan block)Selects between AIB BSR register or functional path
input i_jtag_rstb, // (from dbg_test_bscan block)JTAG controlleable reset the AIB IO circuitry
input i_jtag_rstb_en, // (from dbg_test_bscan block)JTAG controlleable override to reset the AIB IO circuitry
input i_jtag_tdi, // (from dbg_test_bscan block)TDI
input i_jtag_tx_scanen,// (from dbg_test_bscan block)Drives AIB IO jtag_tx_scanen_in or BSR shift control
input i_jtag_weakpdn, //(from dbg_test_bscan block)Enable AIB global pull down test.
input i_jtag_weakpu, //(from dbg_test_bscan block)Enable AIB global pull up test.
// input [2:0] i_aibdft2osc, //To AIB osc.[2] force reset [1] force enable [0] 33 MHz JTAG
// output [12:0] o_aibdft2osc, //Observability of osc and DLL/DCC status
//this signal go through C4 bump, User may muxed it out with their test signals
//output TCB
output o_jtag_tdo //last boundary scan chain output, TDO
);
wire [TOTAL_CHNL_NUM-1:0] i_rx_pma_clk;
wire [TOTAL_CHNL_NUM-1:0] i_rx_pma_div2_clk;
wire [TOTAL_CHNL_NUM*40-1:0] i_rx_pma_data;
wire [TOTAL_CHNL_NUM-1:0] i_tx_pma_clk;
wire [TOTAL_CHNL_NUM-1:0] o_tx_transfer_clk;
wire [TOTAL_CHNL_NUM-1:0] o_tx_transfer_div2_clk;
wire [TOTAL_CHNL_NUM*40-1:0] o_tx_pma_data;
wire [TOTAL_CHNL_NUM-1:0] o_rx_xcvrif_rst_n;
wire HI, LO;
assign HI = 1'b1;
assign LO = 1'b0;
//assign i_rx_pma_clk = m_ns_fwd_clk;
//assign i_rx_pma_div2_clk = m_ns_fwd_div2_clk;
//assign i_rx_pma_data = data_in;
//assign i_tx_pma_clk = m_ns_rcv_clk;
//assign m_fs_fwd_clk = o_tx_transfer_clk;
//assign m_fs_fwd_div2_clk = o_tx_transfer_div2_clk;
//assign data_out = o_tx_pma_data;
//assign fs_mac_rdy = o_rx_xcvrif_rst_n;
aib_top_v2s u_aib_top
(
.i_conf_done (i_conf_done),
.dual_mode_select (dual_mode_select),
.fs_mac_rdy (fs_mac_rdy),
.i_cfg_avmm_clk (i_cfg_avmm_clk),
.i_cfg_avmm_rst_n (i_cfg_avmm_rst_n),
.i_cfg_avmm_addr (i_cfg_avmm_addr[16:0]),
.i_cfg_avmm_byte_en (i_cfg_avmm_byte_en[3:0]),
.i_cfg_avmm_read (i_cfg_avmm_read),
.i_cfg_avmm_write (i_cfg_avmm_write),
.i_cfg_avmm_wdata (i_cfg_avmm_wdata[31:0]),
.o_cfg_avmm_rdatavld (o_cfg_avmm_rdatavld),
.o_cfg_avmm_rdata (o_cfg_avmm_rdata),
.o_cfg_avmm_waitreq (o_cfg_avmm_waitreq),
.m_ns_fwd_clk (m_ns_fwd_clk),
.m_ns_fwd_div2_clk (m_ns_fwd_div2_clk),
.m_wr_clk (m_wr_clk),
.data_in (data_in),
// .i_rx_pma_data ('0),
.m_ns_rcv_clk (m_ns_rcv_clk),
.m_fs_fwd_clk (m_fs_fwd_clk),
.m_fs_fwd_div2_clk (m_fs_fwd_div2_clk), // Not used
.m_fs_rcv_clk (m_fs_rcv_clk),
.m_fs_rcv_div2_clk (m_fs_rcv_div2_clk),
.m_rd_clk (m_rd_clk),
.data_out (data_out),
.ns_mac_rdy (ns_mac_rdy),
.ns_adapter_rstn (ns_adapter_rstn),
.ms_sideband (ms_sideband),
.sl_sideband (sl_sideband),
.m_rxfifo_align_done (m_rxfifo_align_done),
.m_power_on_reset (m_power_on_reset),
.m_device_detect (m_device_detect),
.m_device_detect_ovrd (m_device_detect_ovrd),
.ms_tx_transfer_en (ms_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.ms_rx_transfer_en (ms_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_tx_transfer_en (sl_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_rx_transfer_en (sl_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_tx_dcc_dll_lock_req (sl_tx_dcc_dll_lock_req[TOTAL_CHNL_NUM-1:0]),
.sl_rx_dcc_dll_lock_req (sl_rx_dcc_dll_lock_req[TOTAL_CHNL_NUM-1:0]),
.s0_ch0_aib( { iopad_fs_sr_data[0], iopad_fs_sr_load[0], iopad_ns_sr_data[0], iopad_ns_sr_load[0],
iopad_unused_aib91[0], iopad_unused_aib90[0], iopad_unused_aib89[0], iopad_unused_aib88[0],
iopad_fs_rcv_clk[0], iopad_fs_rcv_clkb[0], iopad_fs_sr_clk[0], iopad_fs_sr_clkb[0],
iopad_ns_sr_clk[0], iopad_ns_sr_clkb[0], iopad_unused_aib81[0], iopad_unused_aib80[0],
iopad_unused_aib79[0], iopad_unused_aib78[0], iopad_unused_aib77[0], iopad_unused_aib76[0],
iopad_unused_aib75[0], iopad_unused_aib74[0], iopad_unused_aib73[0], iopad_unused_aib72[0],
iopad_unused_aib71[0], iopad_unused_aib70[0], iopad_unused_aib69[0], iopad_unused_aib68[0],
iopad_unused_aib67[0], iopad_unused_aib66[0], iopad_ns_adapter_rstn[0], iopad_unused_aib64[0],
iopad_unused_aib63[0], iopad_unused_aib62[0], iopad_unused_aib61[0], iopad_unused_aib60[0],
iopad_ns_rcv_clkb[0], iopad_unused_aib58[0], iopad_ns_rcv_clk[0], iopad_fs_adapter_rstn[0],
iopad_fs_rcv_div2_clkb[0], iopad_fs_fwd_div2_clkb[0], iopad_fs_fwd_div2_clk[0], iopad_unused_aib52[0],
iopad_unused_aib51[0], iopad_unused_aib50[0], iopad_fs_mac_rdy[0], iopad_fs_rcv_div2_clk[0],
iopad_unused_aib47[0], iopad_unused_aib46[0], iopad_unused_aib45[0], iopad_ns_mac_rdy[0],
iopad_ns_fwd_clk[0], iopad_ns_fwd_clkb[0], iopad_fs_fwd_clk[0], iopad_fs_fwd_clkb[0],
iopad_tx[19:0], iopad_rx[19:0]}),
.s0_ch1_aib( { iopad_fs_sr_data[1], iopad_fs_sr_load[1], iopad_ns_sr_data[1], iopad_ns_sr_load[1],
iopad_unused_aib91[1], iopad_unused_aib90[1], iopad_unused_aib89[1], iopad_unused_aib88[1],
iopad_fs_rcv_clk[1], iopad_fs_rcv_clkb[1], iopad_fs_sr_clk[1], iopad_fs_sr_clkb[1],
iopad_ns_sr_clk[1], iopad_ns_sr_clkb[1], iopad_unused_aib81[1], iopad_unused_aib80[1],
iopad_unused_aib79[1], iopad_unused_aib78[1], iopad_unused_aib77[1], iopad_unused_aib76[1],
iopad_unused_aib75[1], iopad_unused_aib74[1], iopad_unused_aib73[1], iopad_unused_aib72[1],
iopad_unused_aib71[1], iopad_unused_aib70[1], iopad_unused_aib69[1], iopad_unused_aib68[1],
iopad_unused_aib67[1], iopad_unused_aib66[1], iopad_ns_adapter_rstn[1], iopad_unused_aib64[1],
iopad_unused_aib63[1], iopad_unused_aib62[1], iopad_unused_aib61[1], iopad_unused_aib60[1],
iopad_ns_rcv_clkb[1], iopad_unused_aib58[1], iopad_ns_rcv_clk[1], iopad_fs_adapter_rstn[1],
iopad_fs_rcv_div2_clkb[1], iopad_fs_fwd_div2_clkb[1], iopad_fs_fwd_div2_clk[1], iopad_unused_aib52[1],
iopad_unused_aib51[1], iopad_unused_aib50[1], iopad_fs_mac_rdy[1], iopad_fs_rcv_div2_clk[1],
iopad_unused_aib47[1], iopad_unused_aib46[1], iopad_unused_aib45[1], iopad_ns_mac_rdy[1],
iopad_ns_fwd_clk[1], iopad_ns_fwd_clkb[1], iopad_fs_fwd_clk[1], iopad_fs_fwd_clkb[1],
iopad_tx[39:20], iopad_rx[39:20]}),
.s0_ch2_aib( { iopad_fs_sr_data[2], iopad_fs_sr_load[2], iopad_ns_sr_data[2], iopad_ns_sr_load[2],
iopad_unused_aib91[2], iopad_unused_aib90[2], iopad_unused_aib89[2], iopad_unused_aib88[2],
iopad_fs_rcv_clk[2], iopad_fs_rcv_clkb[2], iopad_fs_sr_clk[2], iopad_fs_sr_clkb[2],
iopad_ns_sr_clk[2], iopad_ns_sr_clkb[2], iopad_unused_aib81[2], iopad_unused_aib80[2],
iopad_unused_aib79[2], iopad_unused_aib78[2], iopad_unused_aib77[2], iopad_unused_aib76[2],
iopad_unused_aib75[2], iopad_unused_aib74[2], iopad_unused_aib73[2], iopad_unused_aib72[2],
iopad_unused_aib71[2], iopad_unused_aib70[2], iopad_unused_aib69[2], iopad_unused_aib68[2],
iopad_unused_aib67[2], iopad_unused_aib66[2], iopad_ns_adapter_rstn[2], iopad_unused_aib64[2],
iopad_unused_aib63[2], iopad_unused_aib62[2], iopad_unused_aib61[2], iopad_unused_aib60[2],
iopad_ns_rcv_clkb[2], iopad_unused_aib58[2], iopad_ns_rcv_clk[2], iopad_fs_adapter_rstn[2],
iopad_fs_rcv_div2_clkb[2], iopad_fs_fwd_div2_clkb[2], iopad_fs_fwd_div2_clk[2], iopad_unused_aib52[2],
iopad_unused_aib51[2], iopad_unused_aib50[2], iopad_fs_mac_rdy[2], iopad_fs_rcv_div2_clk[2],
iopad_unused_aib47[2], iopad_unused_aib46[2], iopad_unused_aib45[2], iopad_ns_mac_rdy[2],
iopad_ns_fwd_clk[2], iopad_ns_fwd_clkb[2], iopad_fs_fwd_clk[2], iopad_fs_fwd_clkb[2],
iopad_tx[59:40], iopad_rx[59:40]}),
.s0_ch3_aib( { iopad_fs_sr_data[3], iopad_fs_sr_load[3], iopad_ns_sr_data[3], iopad_ns_sr_load[3],
iopad_unused_aib91[3], iopad_unused_aib90[3], iopad_unused_aib89[3], iopad_unused_aib88[3],
iopad_fs_rcv_clk[3], iopad_fs_rcv_clkb[3], iopad_fs_sr_clk[3], iopad_fs_sr_clkb[3],
iopad_ns_sr_clk[3], iopad_ns_sr_clkb[3], iopad_unused_aib81[3], iopad_unused_aib80[3],
iopad_unused_aib79[3], iopad_unused_aib78[3], iopad_unused_aib77[3], iopad_unused_aib76[3],
iopad_unused_aib75[3], iopad_unused_aib74[3], iopad_unused_aib73[3], iopad_unused_aib72[3],
iopad_unused_aib71[3], iopad_unused_aib70[3], iopad_unused_aib69[3], iopad_unused_aib68[3],
iopad_unused_aib67[3], iopad_unused_aib66[3], iopad_ns_adapter_rstn[3], iopad_unused_aib64[3],
iopad_unused_aib63[3], iopad_unused_aib62[3], iopad_unused_aib61[3], iopad_unused_aib60[3],
iopad_ns_rcv_clkb[3], iopad_unused_aib58[3], iopad_ns_rcv_clk[3], iopad_fs_adapter_rstn[3],
iopad_fs_rcv_div2_clkb[3], iopad_fs_fwd_div2_clkb[3], iopad_fs_fwd_div2_clk[3], iopad_unused_aib52[3],
iopad_unused_aib51[3], iopad_unused_aib50[3], iopad_fs_mac_rdy[3], iopad_fs_rcv_div2_clk[3],
iopad_unused_aib47[3], iopad_unused_aib46[3], iopad_unused_aib45[3], iopad_ns_mac_rdy[3],
iopad_ns_fwd_clk[3], iopad_ns_fwd_clkb[3], iopad_fs_fwd_clk[3], iopad_fs_fwd_clkb[3],
iopad_tx[79:60], iopad_rx[79:60]}),
.s0_ch4_aib( { iopad_fs_sr_data[4], iopad_fs_sr_load[4], iopad_ns_sr_data[4], iopad_ns_sr_load[4],
iopad_unused_aib91[4], iopad_unused_aib90[4], iopad_unused_aib89[4], iopad_unused_aib88[4],
iopad_fs_rcv_clk[4], iopad_fs_rcv_clkb[4], iopad_fs_sr_clk[4], iopad_fs_sr_clkb[4],
iopad_ns_sr_clk[4], iopad_ns_sr_clkb[4], iopad_unused_aib81[4], iopad_unused_aib80[4],
iopad_unused_aib79[4], iopad_unused_aib78[4], iopad_unused_aib77[4], iopad_unused_aib76[4],
iopad_unused_aib75[4], iopad_unused_aib74[4], iopad_unused_aib73[4], iopad_unused_aib72[4],
iopad_unused_aib71[4], iopad_unused_aib70[4], iopad_unused_aib69[4], iopad_unused_aib68[4],
iopad_unused_aib67[4], iopad_unused_aib66[4], iopad_ns_adapter_rstn[4], iopad_unused_aib64[4],
iopad_unused_aib63[4], iopad_unused_aib62[4], iopad_unused_aib61[4], iopad_unused_aib60[4],
iopad_ns_rcv_clkb[4], iopad_unused_aib58[4], iopad_ns_rcv_clk[4], iopad_fs_adapter_rstn[4],
iopad_fs_rcv_div2_clkb[4], iopad_fs_fwd_div2_clkb[4], iopad_fs_fwd_div2_clk[4], iopad_unused_aib52[4],
iopad_unused_aib51[4], iopad_unused_aib50[4], iopad_fs_mac_rdy[4], iopad_fs_rcv_div2_clk[4],
iopad_unused_aib47[4], iopad_unused_aib46[4], iopad_unused_aib45[4], iopad_ns_mac_rdy[4],
iopad_ns_fwd_clk[4], iopad_ns_fwd_clkb[4], iopad_fs_fwd_clk[4], iopad_fs_fwd_clkb[4],
iopad_tx[99:80], iopad_rx[99:80]}),
.s0_ch5_aib( { iopad_fs_sr_data[5], iopad_fs_sr_load[5], iopad_ns_sr_data[5], iopad_ns_sr_load[5],
iopad_unused_aib91[5], iopad_unused_aib90[5], iopad_unused_aib89[5], iopad_unused_aib88[5],
iopad_fs_rcv_clk[5], iopad_fs_rcv_clkb[5], iopad_fs_sr_clk[5], iopad_fs_sr_clkb[5],
iopad_ns_sr_clk[5], iopad_ns_sr_clkb[5], iopad_unused_aib81[5], iopad_unused_aib80[5],
iopad_unused_aib79[5], iopad_unused_aib78[5], iopad_unused_aib77[5], iopad_unused_aib76[5],
iopad_unused_aib75[5], iopad_unused_aib74[5], iopad_unused_aib73[5], iopad_unused_aib72[5],
iopad_unused_aib71[5], iopad_unused_aib70[5], iopad_unused_aib69[5], iopad_unused_aib68[5],
iopad_unused_aib67[5], iopad_unused_aib66[5], iopad_ns_adapter_rstn[5], iopad_unused_aib64[5],
iopad_unused_aib63[5], iopad_unused_aib62[5], iopad_unused_aib61[5], iopad_unused_aib60[5],
iopad_ns_rcv_clkb[5], iopad_unused_aib58[5], iopad_ns_rcv_clk[5], iopad_fs_adapter_rstn[5],
iopad_fs_rcv_div2_clkb[5], iopad_fs_fwd_div2_clkb[5], iopad_fs_fwd_div2_clk[5], iopad_unused_aib52[5],
iopad_unused_aib51[5], iopad_unused_aib50[5], iopad_fs_mac_rdy[5], iopad_fs_rcv_div2_clk[5],
iopad_unused_aib47[5], iopad_unused_aib46[5], iopad_unused_aib45[5], iopad_ns_mac_rdy[5],
iopad_ns_fwd_clk[5], iopad_ns_fwd_clkb[5], iopad_fs_fwd_clk[5], iopad_fs_fwd_clkb[5],
iopad_tx[119:100], iopad_rx[119:100]}),
.s1_ch0_aib( { iopad_fs_sr_data[6], iopad_fs_sr_load[6], iopad_ns_sr_data[6], iopad_ns_sr_load[6],
iopad_unused_aib91[6], iopad_unused_aib90[6], iopad_unused_aib89[6], iopad_unused_aib88[6],
iopad_fs_rcv_clk[6], iopad_fs_rcv_clkb[6], iopad_fs_sr_clk[6], iopad_fs_sr_clkb[6],
iopad_ns_sr_clk[6], iopad_ns_sr_clkb[6], iopad_unused_aib81[6], iopad_unused_aib80[6],
iopad_unused_aib79[6], iopad_unused_aib78[6], iopad_unused_aib77[6], iopad_unused_aib76[6],
iopad_unused_aib75[6], iopad_unused_aib74[6], iopad_unused_aib73[6], iopad_unused_aib72[6],
iopad_unused_aib71[6], iopad_unused_aib70[6], iopad_unused_aib69[6], iopad_unused_aib68[6],
iopad_unused_aib67[6], iopad_unused_aib66[6], iopad_ns_adapter_rstn[6], iopad_unused_aib64[6],
iopad_unused_aib63[6], iopad_unused_aib62[6], iopad_unused_aib61[6], iopad_unused_aib60[6],
iopad_ns_rcv_clkb[6], iopad_unused_aib58[6], iopad_ns_rcv_clk[6], iopad_fs_adapter_rstn[6],
iopad_fs_rcv_div2_clkb[6], iopad_fs_fwd_div2_clkb[6], iopad_fs_fwd_div2_clk[6], iopad_unused_aib52[6],
iopad_unused_aib51[6], iopad_unused_aib50[6], iopad_fs_mac_rdy[6], iopad_fs_rcv_div2_clk[6],
iopad_unused_aib47[6], iopad_unused_aib46[6], iopad_unused_aib45[6], iopad_ns_mac_rdy[6],
iopad_ns_fwd_clk[6], iopad_ns_fwd_clkb[6], iopad_fs_fwd_clk[6], iopad_fs_fwd_clkb[6],
iopad_tx[139:120], iopad_rx[139:120]}),
.s1_ch1_aib( { iopad_fs_sr_data[7], iopad_fs_sr_load[7], iopad_ns_sr_data[7], iopad_ns_sr_load[7],
iopad_unused_aib91[7], iopad_unused_aib90[7], iopad_unused_aib89[7], iopad_unused_aib88[7],
iopad_fs_rcv_clk[7], iopad_fs_rcv_clkb[7], iopad_fs_sr_clk[7], iopad_fs_sr_clkb[7],
iopad_ns_sr_clk[7], iopad_ns_sr_clkb[7], iopad_unused_aib81[7], iopad_unused_aib80[7],
iopad_unused_aib79[7], iopad_unused_aib78[7], iopad_unused_aib77[7], iopad_unused_aib76[7],
iopad_unused_aib75[7], iopad_unused_aib74[7], iopad_unused_aib73[7], iopad_unused_aib72[7],
iopad_unused_aib71[7], iopad_unused_aib70[7], iopad_unused_aib69[7], iopad_unused_aib68[7],
iopad_unused_aib67[7], iopad_unused_aib66[7], iopad_ns_adapter_rstn[7], iopad_unused_aib64[7],
iopad_unused_aib63[7], iopad_unused_aib62[7], iopad_unused_aib61[7], iopad_unused_aib60[7],
iopad_ns_rcv_clkb[7], iopad_unused_aib58[7], iopad_ns_rcv_clk[7], iopad_fs_adapter_rstn[7],
iopad_fs_rcv_div2_clkb[7], iopad_fs_fwd_div2_clkb[7], iopad_fs_fwd_div2_clk[7], iopad_unused_aib52[7],
iopad_unused_aib51[7], iopad_unused_aib50[7], iopad_fs_mac_rdy[7], iopad_fs_rcv_div2_clk[7],
iopad_unused_aib47[7], iopad_unused_aib46[7], iopad_unused_aib45[7], iopad_ns_mac_rdy[7],
iopad_ns_fwd_clk[7], iopad_ns_fwd_clkb[7], iopad_fs_fwd_clk[7], iopad_fs_fwd_clkb[7],
iopad_tx[159:140], iopad_rx[159:140]}),
.s1_ch2_aib( { iopad_fs_sr_data[8], iopad_fs_sr_load[8], iopad_ns_sr_data[8], iopad_ns_sr_load[8],
iopad_unused_aib91[8], iopad_unused_aib90[8], iopad_unused_aib89[8], iopad_unused_aib88[8],
iopad_fs_rcv_clk[8], iopad_fs_rcv_clkb[8], iopad_fs_sr_clk[8], iopad_fs_sr_clkb[8],
iopad_ns_sr_clk[8], iopad_ns_sr_clkb[8], iopad_unused_aib81[8], iopad_unused_aib80[8],
iopad_unused_aib79[8], iopad_unused_aib78[8], iopad_unused_aib77[8], iopad_unused_aib76[8],
iopad_unused_aib75[8], iopad_unused_aib74[8], iopad_unused_aib73[8], iopad_unused_aib72[8],
iopad_unused_aib71[8], iopad_unused_aib70[8], iopad_unused_aib69[8], iopad_unused_aib68[8],
iopad_unused_aib67[8], iopad_unused_aib66[8], iopad_ns_adapter_rstn[8], iopad_unused_aib64[8],
iopad_unused_aib63[8], iopad_unused_aib62[8], iopad_unused_aib61[8], iopad_unused_aib60[8],
iopad_ns_rcv_clkb[8], iopad_unused_aib58[8], iopad_ns_rcv_clk[8], iopad_fs_adapter_rstn[8],
iopad_fs_rcv_div2_clkb[8], iopad_fs_fwd_div2_clkb[8], iopad_fs_fwd_div2_clk[8], iopad_unused_aib52[8],
iopad_unused_aib51[8], iopad_unused_aib50[8], iopad_fs_mac_rdy[8], iopad_fs_rcv_div2_clk[8],
iopad_unused_aib47[8], iopad_unused_aib46[8], iopad_unused_aib45[8], iopad_ns_mac_rdy[8],
iopad_ns_fwd_clk[8], iopad_ns_fwd_clkb[8], iopad_fs_fwd_clk[8], iopad_fs_fwd_clkb[8],
iopad_tx[179:160], iopad_rx[179:160]}),
.s1_ch3_aib( { iopad_fs_sr_data[9], iopad_fs_sr_load[9], iopad_ns_sr_data[9], iopad_ns_sr_load[9],
iopad_unused_aib91[9], iopad_unused_aib90[9], iopad_unused_aib89[9], iopad_unused_aib88[9],
iopad_fs_rcv_clk[9], iopad_fs_rcv_clkb[9], iopad_fs_sr_clk[9], iopad_fs_sr_clkb[9],
iopad_ns_sr_clk[9], iopad_ns_sr_clkb[9], iopad_unused_aib81[9], iopad_unused_aib80[9],
iopad_unused_aib79[9], iopad_unused_aib78[9], iopad_unused_aib77[9], iopad_unused_aib76[9],
iopad_unused_aib75[9], iopad_unused_aib74[9], iopad_unused_aib73[9], iopad_unused_aib72[9],
iopad_unused_aib71[9], iopad_unused_aib70[9], iopad_unused_aib69[9], iopad_unused_aib68[9],
iopad_unused_aib67[9], iopad_unused_aib66[9], iopad_ns_adapter_rstn[9], iopad_unused_aib64[9],
iopad_unused_aib63[9], iopad_unused_aib62[9], iopad_unused_aib61[9], iopad_unused_aib60[9],
iopad_ns_rcv_clkb[9], iopad_unused_aib58[9], iopad_ns_rcv_clk[9], iopad_fs_adapter_rstn[9],
iopad_fs_rcv_div2_clkb[9], iopad_fs_fwd_div2_clkb[9], iopad_fs_fwd_div2_clk[9], iopad_unused_aib52[9],
iopad_unused_aib51[9], iopad_unused_aib50[9], iopad_fs_mac_rdy[9], iopad_fs_rcv_div2_clk[9],
iopad_unused_aib47[9], iopad_unused_aib46[9], iopad_unused_aib45[9], iopad_ns_mac_rdy[9],
iopad_ns_fwd_clk[9], iopad_ns_fwd_clkb[9], iopad_fs_fwd_clk[9], iopad_fs_fwd_clkb[9],
iopad_tx[199:180], iopad_rx[199:180]}),
.s1_ch4_aib( { iopad_fs_sr_data[10], iopad_fs_sr_load[10], iopad_ns_sr_data[10], iopad_ns_sr_load[10],
iopad_unused_aib91[10], iopad_unused_aib90[10], iopad_unused_aib89[10], iopad_unused_aib88[10],
iopad_fs_rcv_clk[10], iopad_fs_rcv_clkb[10], iopad_fs_sr_clk[10], iopad_fs_sr_clkb[10],
iopad_ns_sr_clk[10], iopad_ns_sr_clkb[10], iopad_unused_aib81[10], iopad_unused_aib80[10],
iopad_unused_aib79[10], iopad_unused_aib78[10], iopad_unused_aib77[10], iopad_unused_aib76[10],
iopad_unused_aib75[10], iopad_unused_aib74[10], iopad_unused_aib73[10], iopad_unused_aib72[10],
iopad_unused_aib71[10], iopad_unused_aib70[10], iopad_unused_aib69[10], iopad_unused_aib68[10],
iopad_unused_aib67[10], iopad_unused_aib66[10], iopad_ns_adapter_rstn[10], iopad_unused_aib64[10],
iopad_unused_aib63[10], iopad_unused_aib62[10], iopad_unused_aib61[10], iopad_unused_aib60[10],
iopad_ns_rcv_clkb[10], iopad_unused_aib58[10], iopad_ns_rcv_clk[10], iopad_fs_adapter_rstn[10],
iopad_fs_rcv_div2_clkb[10], iopad_fs_fwd_div2_clkb[10], iopad_fs_fwd_div2_clk[10], iopad_unused_aib52[10],
iopad_unused_aib51[10], iopad_unused_aib50[10], iopad_fs_mac_rdy[10], iopad_fs_rcv_div2_clk[10],
iopad_unused_aib47[10], iopad_unused_aib46[10], iopad_unused_aib45[10], iopad_ns_mac_rdy[10],
iopad_ns_fwd_clk[10], iopad_ns_fwd_clkb[10], iopad_fs_fwd_clk[10], iopad_fs_fwd_clkb[10],
iopad_tx[219:200], iopad_rx[219:200]}),
.s1_ch5_aib( { iopad_fs_sr_data[11], iopad_fs_sr_load[11], iopad_ns_sr_data[11], iopad_ns_sr_load[11],
iopad_unused_aib91[11], iopad_unused_aib90[11], iopad_unused_aib89[11], iopad_unused_aib88[11],
iopad_fs_rcv_clk[11], iopad_fs_rcv_clkb[11], iopad_fs_sr_clk[11], iopad_fs_sr_clkb[11],
iopad_ns_sr_clk[11], iopad_ns_sr_clkb[11], iopad_unused_aib81[11], iopad_unused_aib80[11],
iopad_unused_aib79[11], iopad_unused_aib78[11], iopad_unused_aib77[11], iopad_unused_aib76[11],
iopad_unused_aib75[11], iopad_unused_aib74[11], iopad_unused_aib73[11], iopad_unused_aib72[11],
iopad_unused_aib71[11], iopad_unused_aib70[11], iopad_unused_aib69[11], iopad_unused_aib68[11],
iopad_unused_aib67[11], iopad_unused_aib66[11], iopad_ns_adapter_rstn[11], iopad_unused_aib64[11],
iopad_unused_aib63[11], iopad_unused_aib62[11], iopad_unused_aib61[11], iopad_unused_aib60[11],
iopad_ns_rcv_clkb[11], iopad_unused_aib58[11], iopad_ns_rcv_clk[11], iopad_fs_adapter_rstn[11],
iopad_fs_rcv_div2_clkb[11], iopad_fs_fwd_div2_clkb[11], iopad_fs_fwd_div2_clk[11], iopad_unused_aib52[11],
iopad_unused_aib51[11], iopad_unused_aib50[11], iopad_fs_mac_rdy[11], iopad_fs_rcv_div2_clk[11],
iopad_unused_aib47[11], iopad_unused_aib46[11], iopad_unused_aib45[11], iopad_ns_mac_rdy[11],
iopad_ns_fwd_clk[11], iopad_ns_fwd_clkb[11], iopad_fs_fwd_clk[11], iopad_fs_fwd_clkb[11],
iopad_tx[239:220], iopad_rx[239:220]}),
.s2_ch0_aib( { iopad_fs_sr_data[12], iopad_fs_sr_load[12], iopad_ns_sr_data[12], iopad_ns_sr_load[12],
iopad_unused_aib91[12], iopad_unused_aib90[12], iopad_unused_aib89[12], iopad_unused_aib88[12],
iopad_fs_rcv_clk[12], iopad_fs_rcv_clkb[12], iopad_fs_sr_clk[12], iopad_fs_sr_clkb[12],
iopad_ns_sr_clk[12], iopad_ns_sr_clkb[12], iopad_unused_aib81[12], iopad_unused_aib80[12],
iopad_unused_aib79[12], iopad_unused_aib78[12], iopad_unused_aib77[12], iopad_unused_aib76[12],
iopad_unused_aib75[12], iopad_unused_aib74[12], iopad_unused_aib73[12], iopad_unused_aib72[12],
iopad_unused_aib71[12], iopad_unused_aib70[12], iopad_unused_aib69[12], iopad_unused_aib68[12],
iopad_unused_aib67[12], iopad_unused_aib66[12], iopad_ns_adapter_rstn[12], iopad_unused_aib64[12],
iopad_unused_aib63[12], iopad_unused_aib62[12], iopad_unused_aib61[12], iopad_unused_aib60[12],
iopad_ns_rcv_clkb[12], iopad_unused_aib58[12], iopad_ns_rcv_clk[12], iopad_fs_adapter_rstn[12],
iopad_fs_rcv_div2_clkb[12], iopad_fs_fwd_div2_clkb[12], iopad_fs_fwd_div2_clk[12], iopad_unused_aib52[12],
iopad_unused_aib51[12], iopad_unused_aib50[12], iopad_fs_mac_rdy[12], iopad_fs_rcv_div2_clk[12],
iopad_unused_aib47[12], iopad_unused_aib46[12], iopad_unused_aib45[12], iopad_ns_mac_rdy[12],
iopad_ns_fwd_clk[12], iopad_ns_fwd_clkb[12], iopad_fs_fwd_clk[12], iopad_fs_fwd_clkb[12],
iopad_tx[259:240], iopad_rx[259:240]}),
.s2_ch1_aib( { iopad_fs_sr_data[13], iopad_fs_sr_load[13], iopad_ns_sr_data[13], iopad_ns_sr_load[13],
iopad_unused_aib91[13], iopad_unused_aib90[13], iopad_unused_aib89[13], iopad_unused_aib88[13],
iopad_fs_rcv_clk[13], iopad_fs_rcv_clkb[13], iopad_fs_sr_clk[13], iopad_fs_sr_clkb[13],
iopad_ns_sr_clk[13], iopad_ns_sr_clkb[13], iopad_unused_aib81[13], iopad_unused_aib80[13],
iopad_unused_aib79[13], iopad_unused_aib78[13], iopad_unused_aib77[13], iopad_unused_aib76[13],
iopad_unused_aib75[13], iopad_unused_aib74[13], iopad_unused_aib73[13], iopad_unused_aib72[13],
iopad_unused_aib71[13], iopad_unused_aib70[13], iopad_unused_aib69[13], iopad_unused_aib68[13],
iopad_unused_aib67[13], iopad_unused_aib66[13], iopad_ns_adapter_rstn[13], iopad_unused_aib64[13],
iopad_unused_aib63[13], iopad_unused_aib62[13], iopad_unused_aib61[13], iopad_unused_aib60[13],
iopad_ns_rcv_clkb[13], iopad_unused_aib58[13], iopad_ns_rcv_clk[13], iopad_fs_adapter_rstn[13],
iopad_fs_rcv_div2_clkb[13], iopad_fs_fwd_div2_clkb[13], iopad_fs_fwd_div2_clk[13], iopad_unused_aib52[13],
iopad_unused_aib51[13], iopad_unused_aib50[13], iopad_fs_mac_rdy[13], iopad_fs_rcv_div2_clk[13],
iopad_unused_aib47[13], iopad_unused_aib46[13], iopad_unused_aib45[13], iopad_ns_mac_rdy[13],
iopad_ns_fwd_clk[13], iopad_ns_fwd_clkb[13], iopad_fs_fwd_clk[13], iopad_fs_fwd_clkb[13],
iopad_tx[279:260], iopad_rx[279:260]}),
.s2_ch2_aib( { iopad_fs_sr_data[14], iopad_fs_sr_load[14], iopad_ns_sr_data[14], iopad_ns_sr_load[14],
iopad_unused_aib91[14], iopad_unused_aib90[14], iopad_unused_aib89[14], iopad_unused_aib88[14],
iopad_fs_rcv_clk[14], iopad_fs_rcv_clkb[14], iopad_fs_sr_clk[14], iopad_fs_sr_clkb[14],
iopad_ns_sr_clk[14], iopad_ns_sr_clkb[14], iopad_unused_aib81[14], iopad_unused_aib80[14],
iopad_unused_aib79[14], iopad_unused_aib78[14], iopad_unused_aib77[14], iopad_unused_aib76[14],
iopad_unused_aib75[14], iopad_unused_aib74[14], iopad_unused_aib73[14], iopad_unused_aib72[14],
iopad_unused_aib71[14], iopad_unused_aib70[14], iopad_unused_aib69[14], iopad_unused_aib68[14],
iopad_unused_aib67[14], iopad_unused_aib66[14], iopad_ns_adapter_rstn[14], iopad_unused_aib64[14],
iopad_unused_aib63[14], iopad_unused_aib62[14], iopad_unused_aib61[14], iopad_unused_aib60[14],
iopad_ns_rcv_clkb[14], iopad_unused_aib58[14], iopad_ns_rcv_clk[14], iopad_fs_adapter_rstn[14],
iopad_fs_rcv_div2_clkb[14], iopad_fs_fwd_div2_clkb[14], iopad_fs_fwd_div2_clk[14], iopad_unused_aib52[14],
iopad_unused_aib51[14], iopad_unused_aib50[14], iopad_fs_mac_rdy[14], iopad_fs_rcv_div2_clk[14],
iopad_unused_aib47[14], iopad_unused_aib46[14], iopad_unused_aib45[14], iopad_ns_mac_rdy[14],
iopad_ns_fwd_clk[14], iopad_ns_fwd_clkb[14], iopad_fs_fwd_clk[14], iopad_fs_fwd_clkb[14],
iopad_tx[299:280], iopad_rx[299:280]}),
.s2_ch3_aib( { iopad_fs_sr_data[15], iopad_fs_sr_load[15], iopad_ns_sr_data[15], iopad_ns_sr_load[15],
iopad_unused_aib91[15], iopad_unused_aib90[15], iopad_unused_aib89[15], iopad_unused_aib88[15],
iopad_fs_rcv_clk[15], iopad_fs_rcv_clkb[15], iopad_fs_sr_clk[15], iopad_fs_sr_clkb[15],
iopad_ns_sr_clk[15], iopad_ns_sr_clkb[15], iopad_unused_aib81[15], iopad_unused_aib80[15],
iopad_unused_aib79[15], iopad_unused_aib78[15], iopad_unused_aib77[15], iopad_unused_aib76[15],
iopad_unused_aib75[15], iopad_unused_aib74[15], iopad_unused_aib73[15], iopad_unused_aib72[15],
iopad_unused_aib71[15], iopad_unused_aib70[15], iopad_unused_aib69[15], iopad_unused_aib68[15],
iopad_unused_aib67[15], iopad_unused_aib66[15], iopad_ns_adapter_rstn[15], iopad_unused_aib64[15],
iopad_unused_aib63[15], iopad_unused_aib62[15], iopad_unused_aib61[15], iopad_unused_aib60[15],
iopad_ns_rcv_clkb[15], iopad_unused_aib58[15], iopad_ns_rcv_clk[15], iopad_fs_adapter_rstn[15],
iopad_fs_rcv_div2_clkb[15], iopad_fs_fwd_div2_clkb[15], iopad_fs_fwd_div2_clk[15], iopad_unused_aib52[15],
iopad_unused_aib51[15], iopad_unused_aib50[15], iopad_fs_mac_rdy[15], iopad_fs_rcv_div2_clk[15],
iopad_unused_aib47[15], iopad_unused_aib46[15], iopad_unused_aib45[15], iopad_ns_mac_rdy[15],
iopad_ns_fwd_clk[15], iopad_ns_fwd_clkb[15], iopad_fs_fwd_clk[15], iopad_fs_fwd_clkb[15],
iopad_tx[319:300], iopad_rx[319:300]}),
.s2_ch4_aib( { iopad_fs_sr_data[16], iopad_fs_sr_load[16], iopad_ns_sr_data[16], iopad_ns_sr_load[16],
iopad_unused_aib91[16], iopad_unused_aib90[16], iopad_unused_aib89[16], iopad_unused_aib88[16],
iopad_fs_rcv_clk[16], iopad_fs_rcv_clkb[16], iopad_fs_sr_clk[16], iopad_fs_sr_clkb[16],
iopad_ns_sr_clk[16], iopad_ns_sr_clkb[16], iopad_unused_aib81[16], iopad_unused_aib80[16],
iopad_unused_aib79[16], iopad_unused_aib78[16], iopad_unused_aib77[16], iopad_unused_aib76[16],
iopad_unused_aib75[16], iopad_unused_aib74[16], iopad_unused_aib73[16], iopad_unused_aib72[16],
iopad_unused_aib71[16], iopad_unused_aib70[16], iopad_unused_aib69[16], iopad_unused_aib68[16],
iopad_unused_aib67[16], iopad_unused_aib66[16], iopad_ns_adapter_rstn[16], iopad_unused_aib64[16],
iopad_unused_aib63[16], iopad_unused_aib62[16], iopad_unused_aib61[16], iopad_unused_aib60[16],
iopad_ns_rcv_clkb[16], iopad_unused_aib58[16], iopad_ns_rcv_clk[16], iopad_fs_adapter_rstn[16],
iopad_fs_rcv_div2_clkb[16], iopad_fs_fwd_div2_clkb[16], iopad_fs_fwd_div2_clk[16], iopad_unused_aib52[16],
iopad_unused_aib51[16], iopad_unused_aib50[16], iopad_fs_mac_rdy[16], iopad_fs_rcv_div2_clk[16],
iopad_unused_aib47[16], iopad_unused_aib46[16], iopad_unused_aib45[16], iopad_ns_mac_rdy[16],
iopad_ns_fwd_clk[16], iopad_ns_fwd_clkb[16], iopad_fs_fwd_clk[16], iopad_fs_fwd_clkb[16],
iopad_tx[339:320], iopad_rx[339:320]}),
.s2_ch5_aib( { iopad_fs_sr_data[17], iopad_fs_sr_load[17], iopad_ns_sr_data[17], iopad_ns_sr_load[17],
iopad_unused_aib91[17], iopad_unused_aib90[17], iopad_unused_aib89[17], iopad_unused_aib88[17],
iopad_fs_rcv_clk[17], iopad_fs_rcv_clkb[17], iopad_fs_sr_clk[17], iopad_fs_sr_clkb[17],
iopad_ns_sr_clk[17], iopad_ns_sr_clkb[17], iopad_unused_aib81[17], iopad_unused_aib80[17],
iopad_unused_aib79[17], iopad_unused_aib78[17], iopad_unused_aib77[17], iopad_unused_aib76[17],
iopad_unused_aib75[17], iopad_unused_aib74[17], iopad_unused_aib73[17], iopad_unused_aib72[17],
iopad_unused_aib71[17], iopad_unused_aib70[17], iopad_unused_aib69[17], iopad_unused_aib68[17],
iopad_unused_aib67[17], iopad_unused_aib66[17], iopad_ns_adapter_rstn[17], iopad_unused_aib64[17],
iopad_unused_aib63[17], iopad_unused_aib62[17], iopad_unused_aib61[17], iopad_unused_aib60[17],
iopad_ns_rcv_clkb[17], iopad_unused_aib58[17], iopad_ns_rcv_clk[17], iopad_fs_adapter_rstn[17],
iopad_fs_rcv_div2_clkb[17], iopad_fs_fwd_div2_clkb[17], iopad_fs_fwd_div2_clk[17], iopad_unused_aib52[17],
iopad_unused_aib51[17], iopad_unused_aib50[17], iopad_fs_mac_rdy[17], iopad_fs_rcv_div2_clk[17],
iopad_unused_aib47[17], iopad_unused_aib46[17], iopad_unused_aib45[17], iopad_ns_mac_rdy[17],
iopad_ns_fwd_clk[17], iopad_ns_fwd_clkb[17], iopad_fs_fwd_clk[17], iopad_fs_fwd_clkb[17],
iopad_tx[359:340], iopad_rx[359:340]}),
.s3_ch0_aib( { iopad_fs_sr_data[18], iopad_fs_sr_load[18], iopad_ns_sr_data[18], iopad_ns_sr_load[18],
iopad_unused_aib91[18], iopad_unused_aib90[18], iopad_unused_aib89[18], iopad_unused_aib88[18],
iopad_fs_rcv_clk[18], iopad_fs_rcv_clkb[18], iopad_fs_sr_clk[18], iopad_fs_sr_clkb[18],
iopad_ns_sr_clk[18], iopad_ns_sr_clkb[18], iopad_unused_aib81[18], iopad_unused_aib80[18],
iopad_unused_aib79[18], iopad_unused_aib78[18], iopad_unused_aib77[18], iopad_unused_aib76[18],
iopad_unused_aib75[18], iopad_unused_aib74[18], iopad_unused_aib73[18], iopad_unused_aib72[18],
iopad_unused_aib71[18], iopad_unused_aib70[18], iopad_unused_aib69[18], iopad_unused_aib68[18],
iopad_unused_aib67[18], iopad_unused_aib66[18], iopad_ns_adapter_rstn[18], iopad_unused_aib64[18],
iopad_unused_aib63[18], iopad_unused_aib62[18], iopad_unused_aib61[18], iopad_unused_aib60[18],
iopad_ns_rcv_clkb[18], iopad_unused_aib58[18], iopad_ns_rcv_clk[18], iopad_fs_adapter_rstn[18],
iopad_fs_rcv_div2_clkb[18], iopad_fs_fwd_div2_clkb[18], iopad_fs_fwd_div2_clk[18], iopad_unused_aib52[18],
iopad_unused_aib51[18], iopad_unused_aib50[18], iopad_fs_mac_rdy[18], iopad_fs_rcv_div2_clk[18],
iopad_unused_aib47[18], iopad_unused_aib46[18], iopad_unused_aib45[18], iopad_ns_mac_rdy[18],
iopad_ns_fwd_clk[18], iopad_ns_fwd_clkb[18], iopad_fs_fwd_clk[18], iopad_fs_fwd_clkb[18],
iopad_tx[379:360], iopad_rx[379:360]}),
.s3_ch1_aib( { iopad_fs_sr_data[19], iopad_fs_sr_load[19], iopad_ns_sr_data[19], iopad_ns_sr_load[19],
iopad_unused_aib91[19], iopad_unused_aib90[19], iopad_unused_aib89[19], iopad_unused_aib88[19],
iopad_fs_rcv_clk[19], iopad_fs_rcv_clkb[19], iopad_fs_sr_clk[19], iopad_fs_sr_clkb[19],
iopad_ns_sr_clk[19], iopad_ns_sr_clkb[19], iopad_unused_aib81[19], iopad_unused_aib80[19],
iopad_unused_aib79[19], iopad_unused_aib78[19], iopad_unused_aib77[19], iopad_unused_aib76[19],
iopad_unused_aib75[19], iopad_unused_aib74[19], iopad_unused_aib73[19], iopad_unused_aib72[19],
iopad_unused_aib71[19], iopad_unused_aib70[19], iopad_unused_aib69[19], iopad_unused_aib68[19],
iopad_unused_aib67[19], iopad_unused_aib66[19], iopad_ns_adapter_rstn[19], iopad_unused_aib64[19],
iopad_unused_aib63[19], iopad_unused_aib62[19], iopad_unused_aib61[19], iopad_unused_aib60[19],
iopad_ns_rcv_clkb[19], iopad_unused_aib58[19], iopad_ns_rcv_clk[19], iopad_fs_adapter_rstn[19],
iopad_fs_rcv_div2_clkb[19], iopad_fs_fwd_div2_clkb[19], iopad_fs_fwd_div2_clk[19], iopad_unused_aib52[19],
iopad_unused_aib51[19], iopad_unused_aib50[19], iopad_fs_mac_rdy[19], iopad_fs_rcv_div2_clk[19],
iopad_unused_aib47[19], iopad_unused_aib46[19], iopad_unused_aib45[19], iopad_ns_mac_rdy[19],
iopad_ns_fwd_clk[19], iopad_ns_fwd_clkb[19], iopad_fs_fwd_clk[19], iopad_fs_fwd_clkb[19],
iopad_tx[399:380], iopad_rx[399:380]}),
.s3_ch2_aib( { iopad_fs_sr_data[20], iopad_fs_sr_load[20], iopad_ns_sr_data[20], iopad_ns_sr_load[20],
iopad_unused_aib91[20], iopad_unused_aib90[20], iopad_unused_aib89[20], iopad_unused_aib88[20],
iopad_fs_rcv_clk[20], iopad_fs_rcv_clkb[20], iopad_fs_sr_clk[20], iopad_fs_sr_clkb[20],
iopad_ns_sr_clk[20], iopad_ns_sr_clkb[20], iopad_unused_aib81[20], iopad_unused_aib80[20],
iopad_unused_aib79[20], iopad_unused_aib78[20], iopad_unused_aib77[20], iopad_unused_aib76[20],
iopad_unused_aib75[20], iopad_unused_aib74[20], iopad_unused_aib73[20], iopad_unused_aib72[20],
iopad_unused_aib71[20], iopad_unused_aib70[20], iopad_unused_aib69[20], iopad_unused_aib68[20],
iopad_unused_aib67[20], iopad_unused_aib66[20], iopad_ns_adapter_rstn[20], iopad_unused_aib64[20],
iopad_unused_aib63[20], iopad_unused_aib62[20], iopad_unused_aib61[20], iopad_unused_aib60[20],
iopad_ns_rcv_clkb[20], iopad_unused_aib58[20], iopad_ns_rcv_clk[20], iopad_fs_adapter_rstn[20],
iopad_fs_rcv_div2_clkb[20], iopad_fs_fwd_div2_clkb[20], iopad_fs_fwd_div2_clk[20], iopad_unused_aib52[20],
iopad_unused_aib51[20], iopad_unused_aib50[20], iopad_fs_mac_rdy[20], iopad_fs_rcv_div2_clk[20],
iopad_unused_aib47[20], iopad_unused_aib46[20], iopad_unused_aib45[20], iopad_ns_mac_rdy[20],
iopad_ns_fwd_clk[20], iopad_ns_fwd_clkb[20], iopad_fs_fwd_clk[20], iopad_fs_fwd_clkb[20],
iopad_tx[419:400], iopad_rx[419:400]}),
.s3_ch3_aib( { iopad_fs_sr_data[21], iopad_fs_sr_load[21], iopad_ns_sr_data[21], iopad_ns_sr_load[21],
iopad_unused_aib91[21], iopad_unused_aib90[21], iopad_unused_aib89[21], iopad_unused_aib88[21],
iopad_fs_rcv_clk[21], iopad_fs_rcv_clkb[21], iopad_fs_sr_clk[21], iopad_fs_sr_clkb[21],
iopad_ns_sr_clk[21], iopad_ns_sr_clkb[21], iopad_unused_aib81[21], iopad_unused_aib80[21],
iopad_unused_aib79[21], iopad_unused_aib78[21], iopad_unused_aib77[21], iopad_unused_aib76[21],
iopad_unused_aib75[21], iopad_unused_aib74[21], iopad_unused_aib73[21], iopad_unused_aib72[21],
iopad_unused_aib71[21], iopad_unused_aib70[21], iopad_unused_aib69[21], iopad_unused_aib68[21],
iopad_unused_aib67[21], iopad_unused_aib66[21], iopad_ns_adapter_rstn[21], iopad_unused_aib64[21],
iopad_unused_aib63[21], iopad_unused_aib62[21], iopad_unused_aib61[21], iopad_unused_aib60[21],
iopad_ns_rcv_clkb[21], iopad_unused_aib58[21], iopad_ns_rcv_clk[21], iopad_fs_adapter_rstn[21],
iopad_fs_rcv_div2_clkb[21], iopad_fs_fwd_div2_clkb[21], iopad_fs_fwd_div2_clk[21], iopad_unused_aib52[21],
iopad_unused_aib51[21], iopad_unused_aib50[21], iopad_fs_mac_rdy[21], iopad_fs_rcv_div2_clk[21],
iopad_unused_aib47[21], iopad_unused_aib46[21], iopad_unused_aib45[21], iopad_ns_mac_rdy[21],
iopad_ns_fwd_clk[21], iopad_ns_fwd_clkb[21], iopad_fs_fwd_clk[21], iopad_fs_fwd_clkb[21],
iopad_tx[439:420], iopad_rx[439:420]}),
.s3_ch4_aib( { iopad_fs_sr_data[22], iopad_fs_sr_load[22], iopad_ns_sr_data[22], iopad_ns_sr_load[22],
iopad_unused_aib91[22], iopad_unused_aib90[22], iopad_unused_aib89[22], iopad_unused_aib88[22],
iopad_fs_rcv_clk[22], iopad_fs_rcv_clkb[22], iopad_fs_sr_clk[22], iopad_fs_sr_clkb[22],
iopad_ns_sr_clk[22], iopad_ns_sr_clkb[22], iopad_unused_aib81[22], iopad_unused_aib80[22],
iopad_unused_aib79[22], iopad_unused_aib78[22], iopad_unused_aib77[22], iopad_unused_aib76[22],
iopad_unused_aib75[22], iopad_unused_aib74[22], iopad_unused_aib73[22], iopad_unused_aib72[22],
iopad_unused_aib71[22], iopad_unused_aib70[22], iopad_unused_aib69[22], iopad_unused_aib68[22],
iopad_unused_aib67[22], iopad_unused_aib66[22], iopad_ns_adapter_rstn[22], iopad_unused_aib64[22],
iopad_unused_aib63[22], iopad_unused_aib62[22], iopad_unused_aib61[22], iopad_unused_aib60[22],
iopad_ns_rcv_clkb[22], iopad_unused_aib58[22], iopad_ns_rcv_clk[22], iopad_fs_adapter_rstn[22],
iopad_fs_rcv_div2_clkb[22], iopad_fs_fwd_div2_clkb[22], iopad_fs_fwd_div2_clk[22], iopad_unused_aib52[22],
iopad_unused_aib51[22], iopad_unused_aib50[22], iopad_fs_mac_rdy[22], iopad_fs_rcv_div2_clk[22],
iopad_unused_aib47[22], iopad_unused_aib46[22], iopad_unused_aib45[22], iopad_ns_mac_rdy[22],
iopad_ns_fwd_clk[22], iopad_ns_fwd_clkb[22], iopad_fs_fwd_clk[22], iopad_fs_fwd_clkb[22],
iopad_tx[459:440], iopad_rx[459:440]}),
.s3_ch5_aib( { iopad_fs_sr_data[23], iopad_fs_sr_load[23], iopad_ns_sr_data[23], iopad_ns_sr_load[23],
iopad_unused_aib91[23], iopad_unused_aib90[23], iopad_unused_aib89[23], iopad_unused_aib88[23],
iopad_fs_rcv_clk[23], iopad_fs_rcv_clkb[23], iopad_fs_sr_clk[23], iopad_fs_sr_clkb[23],
iopad_ns_sr_clk[23], iopad_ns_sr_clkb[23], iopad_unused_aib81[23], iopad_unused_aib80[23],
iopad_unused_aib79[23], iopad_unused_aib78[23], iopad_unused_aib77[23], iopad_unused_aib76[23],
iopad_unused_aib75[23], iopad_unused_aib74[23], iopad_unused_aib73[23], iopad_unused_aib72[23],
iopad_unused_aib71[23], iopad_unused_aib70[23], iopad_unused_aib69[23], iopad_unused_aib68[23],
iopad_unused_aib67[23], iopad_unused_aib66[23], iopad_ns_adapter_rstn[23], iopad_unused_aib64[23],
iopad_unused_aib63[23], iopad_unused_aib62[23], iopad_unused_aib61[23], iopad_unused_aib60[23],
iopad_ns_rcv_clkb[23], iopad_unused_aib58[23], iopad_ns_rcv_clk[23], iopad_fs_adapter_rstn[23],
iopad_fs_rcv_div2_clkb[23], iopad_fs_fwd_div2_clkb[23], iopad_fs_fwd_div2_clk[23], iopad_unused_aib52[23],
iopad_unused_aib51[23], iopad_unused_aib50[23], iopad_fs_mac_rdy[23], iopad_fs_rcv_div2_clk[23],
iopad_unused_aib47[23], iopad_unused_aib46[23], iopad_unused_aib45[23], iopad_ns_mac_rdy[23],
iopad_ns_fwd_clk[23], iopad_ns_fwd_clkb[23], iopad_fs_fwd_clk[23], iopad_fs_fwd_clkb[23],
iopad_tx[479:460], iopad_rx[479:460]}),
.device_detect (device_detect),
.por (por),
.i_osc_clk (i_osc_clk),
// .o_aibaux_osc_clk (o_aibaux_osc_clk),
.scan_clk (scan_clk),
.scan_enable (scan_enable),
// .scan_in (scan_in),
.scan_in_ch0 (scan_in_ch0),
.scan_in_ch1 (scan_in_ch1),
.scan_in_ch2 (scan_in_ch2),
.scan_in_ch3 (scan_in_ch3),
.scan_in_ch4 (scan_in_ch4),
.scan_in_ch5 (scan_in_ch5),
.scan_in_ch6 (scan_in_ch6),
.scan_in_ch7 (scan_in_ch7),
.scan_in_ch8 (scan_in_ch8),
.scan_in_ch9 (scan_in_ch9),
.scan_in_ch10 (scan_in_ch10),
.scan_in_ch11 (scan_in_ch11),
.scan_in_ch12 (scan_in_ch12),
.scan_in_ch13 (scan_in_ch13),
.scan_in_ch14 (scan_in_ch14),
.scan_in_ch15 (scan_in_ch15),
.scan_in_ch16 (scan_in_ch16),
.scan_in_ch17 (scan_in_ch17),
.scan_in_ch18 (scan_in_ch18),
.scan_in_ch19 (scan_in_ch19),
.scan_in_ch20 (scan_in_ch20),
.scan_in_ch21 (scan_in_ch21),
.scan_in_ch22 (scan_in_ch22),
.scan_in_ch23 (scan_in_ch23),
// .scan_out (scan_out),
.scan_out_ch0 (scan_out_ch0),
.scan_out_ch1 (scan_out_ch1),
.scan_out_ch2 (scan_out_ch2),
.scan_out_ch3 (scan_out_ch3),
.scan_out_ch4 (scan_out_ch4),
.scan_out_ch5 (scan_out_ch5),
.scan_out_ch6 (scan_out_ch6),
.scan_out_ch7 (scan_out_ch7),
.scan_out_ch8 (scan_out_ch8),
.scan_out_ch9 (scan_out_ch9),
.scan_out_ch10 (scan_out_ch10),
.scan_out_ch11 (scan_out_ch11),
.scan_out_ch12 (scan_out_ch12),
.scan_out_ch13 (scan_out_ch13),
.scan_out_ch14 (scan_out_ch14),
.scan_out_ch15 (scan_out_ch15),
.scan_out_ch16 (scan_out_ch16),
.scan_out_ch17 (scan_out_ch17),
.scan_out_ch18 (scan_out_ch18),
.scan_out_ch19 (scan_out_ch19),
.scan_out_ch20 (scan_out_ch20),
.scan_out_ch21 (scan_out_ch21),
.scan_out_ch22 (scan_out_ch22),
.scan_out_ch23 (scan_out_ch23),
.i_scan_clk (i_scan_clk),
.i_test_scan_en (i_test_scan_en),
.i_test_scan_mode (i_test_scan_mode),
// .i_test_clk_125m (i_test_clk_125m),
// .i_test_clk_1g (i_test_clk_1g),
// .i_test_clk_250m (i_test_clk_250m),
// .i_test_clk_500m (i_test_clk_500m),
// .i_test_clk_62m (i_test_clk_62m),
// .i_test_c3adapt_scan_in (i_test_c3adapt_scan_in),
// .o_test_c3adapt_scan_out (o_test_c3adapt_scan_out),
.i_jtag_clkdr (i_jtag_clkdr),
.i_jtag_clksel (i_jtag_clksel),
.i_jtag_intest (i_jtag_intest),
.i_jtag_mode (i_jtag_mode),
.i_jtag_rstb_en (i_jtag_rstb_en),
.i_jtag_rstb (i_jtag_rstb),
.i_jtag_weakpdn (i_jtag_weakpdn),
.i_jtag_weakpu (i_jtag_weakpu),
.i_jtag_tdi (i_jtag_tdi),
.i_jtag_tx_scanen (i_jtag_tx_scanen),
.o_jtag_tdo (o_jtag_tdo)
);
endmodule |
module c3lib_sync3_reset_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ),
// .SYNC_STAGES( 3 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b0),
.SyncRegWidth(3)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in (rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_set_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow (1),
.ResetVal (1'b1),
.SyncRegWidth (2)
) u_c3lib_sync2_reset_ulvt_gate (
.clk ( clk ),
.rst_in ( rst_n ),
.data_in (data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_set_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b1),
.SyncRegWidth(2)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in ( rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_reset_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// AYAR RESET SYNC VERSION WITH 2 deep synchronizer to mimic the behavioral model below Chandru Ramamurthy!!
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b0),
.SyncRegWidth(2)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in (rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_reset_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// AYAR RESET SYNC VERSION WITH 2 deep synchronizer to mimic the behavioral model below Chandru Ramamurthy!!
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
//);
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b0),
.SyncRegWidth(2)
) u_c3lib_sync2_reset_ulvt_gate (
.clk ( clk ),
.rst_in ( rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync3_set_ulvt_gate (
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 3 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b1),
.SyncRegWidth(3)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in (rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_ckg_lvt_8x(
tst_en,
clk_en,
clk,
gated_clk
);
input wire tst_en;
input wire clk_en;
input wire clk;
output wire gated_clk;
`ifdef BEHAVIORAL
var logic latch_d;
var logic latch_q;
// Formulate control signal
assign latch_d = clk_en | tst_en;
// Latch control signal
always_latch if (~clk) latch_q <= latch_d;
// Actual clk gating gate
assign gated_clk = clk & latch_q;
`else
b15cilb01ah1n08x5 icg_cell (.clkout(gated_clk), .en(clk_en), .te(tst_en), .clk(clk));
`endif
endmodule |
module c3lib_ckinv_svt_8x(
in,
out
);
input in;
output out;
`ifdef BEHAVIORAL
assign out = ~in;
`else
clock_inv u_clock_inv (.out(out), .in(in));
`endif
endmodule |
module aibio_clkdist_inv1_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input clkp,
input clkn,
//------Output pins------//
output clkp_b,
output clkn_b
);
wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;
`ifdef POST_WORST
localparam delay_1 = 100;
localparam delay_2 = 49.55;
`else
localparam delay_1 = 0.0;
localparam delay_2 = 0.0;
`endif
assign #(delay_1) clkp_b_1 = ~clkp;
assign #(delay_2) clkp_b_2 = ~clkp_b_1;
assign #(delay_2) clkp_b = ~clkp_b_2;
assign #(delay_1) clkn_b_1 = ~clkn;
assign #(delay_2) clkn_b_2 = ~clkn_b_1;
assign #(delay_2) clkn_b = ~clkn_b_2;
/*
assign #(delay_clkp_b)clkp_b = ~clkp;
assign #(delay_clkn_b)clkn_b = ~clkn;
*/
endmodule |
module aibio_rxclk_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input [4:0] dcc_p_pdsel,
input [4:0] dcc_p_pusel,
input [4:0] dcc_n_pdsel,
input [4:0] dcc_n_pusel,
input rxclkp,
input rxclkn,
input rxclk_en,
input rxclk_localbias_en,
input ipbias,
input [2:0] ibias_ctrl,
input gen1mode_en,
//------Output pins------//
output rxclkp_out,
output rxclkn_out,
//------Spare pins------//
input [3:0] i_rxclk_spare,
output [3:0] o_rxclk_spare
);
wire rxclkp_out_1;
wire rxclkp_out_2;
wire rxclkp_out_3;
wire rxclkn_out_1;
wire rxclkn_out_2;
wire rxclkn_out_3;
`ifdef POST_WORST
localparam delay_rxclkp_out_1 = 150;
localparam delay_rxclkp_out_2 = 5;
localparam delay_rxclkn_out_1 = 150;
localparam delay_rxclkn_out_2 = 3;
`else
localparam delay_rxclkp_out_1 = 0.0;
localparam delay_rxclkp_out_2 = 0.0;
localparam delay_rxclkn_out_1 = 0.0;
localparam delay_rxclkn_out_2 = 0.0;
`endif
assign #(delay_rxclkp_out_1)rxclkp_out_1 = rxclk_en ? rxclkp : 1'b0;
assign #(delay_rxclkp_out_1)rxclkp_out_2 = rxclk_en ? rxclkp_out_1 : 1'b0;
assign #(delay_rxclkp_out_1)rxclkp_out_3 = rxclk_en ? rxclkp_out_2 : 1'b0;
assign #(delay_rxclkp_out_2)rxclkp_out = rxclk_en ? rxclkp_out_3 : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_1 = rxclk_en ? rxclkn : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_2 = rxclk_en ? rxclkn_out_1 : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_3 = rxclk_en ? rxclkn_out_2 : 1'b0;
assign #(delay_rxclkn_out_2)rxclkn_out = rxclk_en ? rxclkn_out_3 : 1'b0;
endmodule |
module aibio_clkdist_inv2_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input clkp,
input clkn,
//------Output pins------//
output clkp_b,
output clkn_b
);
wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;
`ifdef POST_WORST
localparam delay_1 = 100;
localparam delay_2 = 16.5;
`else
localparam delay_1 = 0.0;
localparam delay_2 = 0.0;
`endif
assign #(delay_1) clkp_b_1 = ~clkp;
assign #(delay_2) clkp_b_2 = ~clkp_b_1;
assign #(delay_2) clkp_b = ~clkp_b_2;
assign #(delay_1) clkn_b_1 = ~clkn;
assign #(delay_2) clkn_b_2 = ~clkn_b_1;
assign #(delay_2) clkn_b = ~clkn_b_2;
/*
assign #(delay_clkp_b)clkp_b = ~clkp;
assign #(delay_clkn_b)clkn_b = ~clkn;
*/
endmodule |
module aibio_outclk_select
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkphb,
input [3:0]i_adapter_code,
input [3:0]i_soc_code,
//--------Output pins---------//
output o_clk_adapter,
output o_clk_soc
);
assign o_clk_adapter = ~ i_clkphb[i_adapter_code];
assign o_clk_soc = ~ i_clkphb[i_soc_code];
endmodule |
module aibio_txdll_cbb
(
//------Supply pins------//
input vddcq,
input vddc,
input vss,
//------Input pins------//
input ck_in,
input ck_loopback,
input ck_sys,
input ck_jtag,
input [1:0] inp_clksel,
input dll_en,
input dll_reset,
input [3:0] dll_biasctrl,
input [4:0] dll_capctrl,
input [3:0] dll_cksoc_code,
input [3:0] dll_ckadapter_code,
input [3:0] dll_even_phase1_sel,
input [3:0] dll_odd_phase1_sel,
input [3:0] dll_even_phase2_sel,
input [3:0] dll_odd_phase2_sel,
input [3:0] dll_lockthresh,
input [1:0] dll_lockctrl,
input pwrgood_in,
input dll_dfx_en,
input [4:0] dll_digview_sel,
input [4:0] dll_anaview_sel,
//------Output pins------//
output dll_lock,
output clk_odd,
output clk_even,
output clk_soc,
output clk_adapter,
output pulseclk_odd,
output pulseclk_even,
output inbias,
output ipbias,
output [1:0] dll_digviewout,
output dll_anaviewout,
//------Spare pins------//
input [7:0] i_dll_spare,
output [7:0] o_dll_spare
);
wire clkp,clkn;
wire up,dn,upb,dnb;
wire [15:0]clkphb;
wire dll_enb;
assign dll_enb= ~dll_en;
aibio_inpclk_select_txdll inpclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clk_in(ck_in),
.i_clk_loopback(ck_loopback),
.i_clk_sys(ck_sys),
.i_clk_jtag(ck_jtag),
.i_clksel(inp_clksel),
.o_clkp(clkp),
.o_clkn(clkn)
);
aibio_dll_top dll_top
(
.vddcq(vddcq),
.vss(vss),
.i_clkp(clkp),
.i_clkn(clkn),
.i_clkp_cdr(),
.i_clkn_cdr(),
.i_dll_biasctrl(dll_biasctrl),
.i_dll_capctrl(dll_capctrl),
.i_dll_en(dll_en),
.i_dll_enb(dll_enb),
.o_up(up),
.o_dn(dn),
.o_upb(upb),
.o_dnb(dnb),
.o_dll_clkphb(clkphb),
.o_piclk_180(),
.o_piclk_90(),
.o_cdr_clk(),
.o_pbias(),
.o_nbias()
);
aibio_lock_detector lock_detector
(
.vddcq(vddcq),
.vss(vss),
.i_clkin(ck_sys),
.i_en(dll_en),
.i_up(up),
.i_dn(dn),
.i_upb(upb),
.i_dnb(dnb),
.i_lockthresh(dll_lockthresh[1:0]),
.i_lockctrl(dll_lockctrl),
.lock(dll_lock)
);
aibio_pulsegen_top pulsegen
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(clkphb),
.i_dll_even_phase1_sel(dll_even_phase1_sel),
.i_dll_odd_phase1_sel(dll_odd_phase1_sel),
.i_dll_even_phase2_sel(dll_even_phase2_sel),
.i_dll_odd_phase2_sel(dll_odd_phase2_sel),
.o_clk_even(clk_even),
.o_clk_odd(clk_odd),
.o_pulseclk_even(pulseclk_even),
.o_pulseclk_odd(pulseclk_odd)
);
aibio_outclk_select outclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clkphb(clkphb),
.i_adapter_code(dll_ckadapter_code),
.i_soc_code(dll_cksoc_code),
.o_clk_adapter(clk_adapter),
.o_clk_soc(clk_soc)
);
endmodule |
module aibio_inpclk_select_txdll
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_in,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn
);
wire i_clk_inp;
wire i_clk_inn;
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;
assign i_clk_loopbackp = i_clk_loopback;
assign i_clk_loopbackn = ~i_clk_loopback;
assign i_clk_sysp = i_clk_sys;
assign i_clk_sysn = ~i_clk_sys;
assign i_clk_inp = i_clk_in;
assign i_clk_inn = ~i_clk_in;
assign i_clk_jtagp = i_clk_jtag;
assign i_clk_jtagn = ~i_clk_jtag;
assign o_clkp = (i_clksel == 2'b00) ? i_clk_inp :
(i_clksel == 2'b01) ? i_clk_loopbackp :
(i_clksel == 2'b10) ? i_clk_sysp :
(i_clksel == 2'b11) ? i_clk_jtagp :
1'b0;
assign o_clkn = (i_clksel == 2'b00) ? i_clk_inn :
(i_clksel == 2'b01) ? i_clk_loopbackn :
(i_clksel == 2'b10) ? i_clk_sysn :
(i_clksel == 2'b11) ? i_clk_jtagn :
1'b0;
endmodule |
module aibio_pulsegen_top
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [15:0] i_clkph,
input [3:0] i_dll_even_phase1_sel,
input [3:0] i_dll_odd_phase1_sel,
input [3:0] i_dll_even_phase2_sel,
input [3:0] i_dll_odd_phase2_sel,
//--------Output pins-----------//
output o_clk_even,
output o_clk_odd,
output o_pulseclk_even,
output o_pulseclk_odd
);
wire [3:0]dll_even_phase2_sel_int;
wire [3:0]dll_odd_phase2_sel_int;
wire dll_even_phase2_selb_3;
wire dll_odd_phase2_selb_3;
assign dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign dll_even_phase2_sel_int = {dll_even_phase2_selb_3,i_dll_even_phase2_sel[2:0]};
assign dll_odd_phase2_sel_int = {dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[2:0]};
assign o_clk_even = ~i_clkph[i_dll_even_phase1_sel];
assign o_clk_odd = ~i_clkph[i_dll_odd_phase1_sel];
assign o_pulseclk_even = o_clk_even && (i_clkph[dll_even_phase2_sel_int]);
assign o_pulseclk_odd = o_clk_odd && (i_clkph[dll_odd_phase2_sel_int]);
endmodule |
module aibio_vref_cbb
(
//------Supply pins------//
input vddc,
input vddtx,
inout vss,
//------Input pins------//
input vref_en,
input calvref_en,
input [6:0] vref_bin_0,
input [6:0] vref_bin_1,
input [6:0] vref_bin_2,
input [6:0] vref_bin_3,
input [4:0] calvref_bin,
input gen1mode_en,
input pwrgood_in,
//------Output pins------//
output [3:0] vref,
output calvref,
//------Spare pins------//
input [3:0] i_vref_spare,
output [3:0] o_vref_spare
);
endmodule |
module en_logic_xxpad
(
input data,
input pwrgoodtx,
input pwrgood,
input rst_strap,
input wk_pu_en,
input wk_pd_en,
input compen_n,
input compen_p,
input tx_en,
input sdr_mode_en,
input tx_async_en,
input gen1_en,
output reg pu_en_gen1,
output reg pd_en_gen1,
output reg pu_en_gen2,
output reg pd_en_gen2,
output reg wkpd_en,
output reg wkpu_en
);
wire pg;
wire compen;
wire wk_en;
assign pg = (pwrgoodtx && pwrgood);
assign compen = (compen_p ^ compen_n);
assign wk_en = (wk_pu_en ^ wk_pd_en);
always @(rst_strap,pg,wk_en,compen,tx_en,sdr_mode_en,tx_async_en,gen1_en,data)
begin
if(rst_strap) //reset
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b1;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(!pg) //pwrgoodtx and pwrgood invalid
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(wk_en)
begin
if(wk_pu_en) //Weak PULL-UP
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b1;
end
else if(wk_pd_en) //Weak PULL-DOWN
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b1;
wkpu_en = 1'b0;
end
end
else if(compen)
begin
if(compen_n) //rcomp_n
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b1;
pd_en_gen2 = 1'b1;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(compen_p) //rcomp_p
begin
pu_en_gen1 = 1'b1;
pd_en_gen1 = 1'b1;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
end
else if(tx_async_en) //Async mode(Assumption ---> gen1_en is high): data here is async data
begin
pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(!tx_en) //No Mode: Both tx_async_en & tx_en is low
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(tx_en) //tx_en : high
begin
if(sdr_mode_en) //SDR Mode(Assumption ---> gen1_en is high) : Here data is even data
begin
pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else
begin
if(gen1_en) //GEN1 Mode : Here data is serialised data
begin
pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else //GEN2 Mode : Here data is serialised data
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen2 = (data == 1'b0) ? 1'b1 : 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
end
end
end
endmodule |
module pad_out_logic
(
input rst,
input pu_gen1,
input pd_gen1,
input pu_gen2,
input pd_gen2,
input wkpu,
input wkpd,
output reg data_out
);
always @(rst,wkpu,wkpd,pu_gen1,pd_gen1,pu_gen2,pd_gen2)
begin
if(rst)
begin
data_out = 1'b0;
end
else if(wkpu)
begin
data_out = 1'b1;
end
else if(wkpd)
begin
data_out = 1'b0;
end
else if(pu_gen1 && pd_gen1)
begin
data_out = 1'bx;
end
else if(pu_gen2 && pd_gen2)
begin
data_out = 1'bx;
end
else if(pu_gen1 ^ pd_gen1)
begin
data_out = pu_gen1;
end
else if(pu_gen2 ^ pd_gen2)
begin
data_out = pu_gen2;
end
else
begin
data_out = 1'bz;
end
end
endmodule |
module aibio_pvtmon_3to8dec(
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic [2:0]sel,
//----Output pins----//
output logic [7:0]out
);
always @(sel)
begin
case(sel)
3'b000 : out=8'b0000_0001;
3'b001 : out=8'b0000_0010;
3'b010 : out=8'b0000_0100;
3'b011 : out=8'b0000_1000;
3'b100 : out=8'b0001_0000;
3'b101 : out=8'b0010_0000;
3'b110 : out=8'b0100_0000;
3'b111 : out=8'b1000_0000;
default : out = 8'b0000_0000;
endcase
end
endmodule |
module mux2x1 (
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic [1:0]in,
input logic s,
//----Output pins----//
output logic out
);
always @(in or s)
begin
if(s)
out= in[1];
else
out=in[0];
end
endmodule |
module DFF(
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic clk,
input logic rb,
input logic d,
//----Output pins----//
output logic o
);
initial o <= 0;
always @(posedge clk or negedge rb )
begin
if(rb == 1'b0)
begin
o = 'd0;
end
else
begin
o = d;
end
end
endmodule |
module aibio_decoder3x8
(
//---------Supply pins---------//
input vddcq,
input vss,
//--------Input pins----------//
input [2:0] i,
//--------Output pins---------//
output reg [7:0] o
);
always @(i)
case(i)
3'b000 : o = 8'b0000_0001;
3'b001 : o = 8'b0000_0010;
3'b010 : o = 8'b0000_0100;
3'b011 : o = 8'b0000_1000;
3'b100 : o = 8'b0001_0000;
3'b101 : o = 8'b0010_0000;
3'b110 : o = 8'b0100_0000;
3'b111 : o = 8'b1000_0000;
default : o = 8'b0000_0000;
endcase
endmodule |
module aibio_decoder2x4
(
//----------Supply pins------------//
input vddcq,
input vss,
//----------Input pins------------//
input [1:0] i,
//----------Output pins----------//
output reg [3:0] o
);
always @(i)
case(i)
2'b00 : o = 4'b0001;
2'b01 : o = 4'b0010;
2'b10 : o = 4'b0100;
2'b11 : o = 4'b1000;
default : o = 4'b0000;
endcase
endmodule |
module aibio_outclk_mux16x1
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkph,
input [3:0]i_clksel,
//--------Output pins---------//
output o_clk
);
wire [3:0] clk_sel_stg1;
wire [3:0] clk_sel_stg2;
wire [3:0] clkphsel_stg2;
aibio_decoder2x4 I4
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel[1:0]),
.o(clk_sel_stg1)
);
aibio_decoder2x4 I3
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel[3:2]),
.o(clk_sel_stg2)
);
aibio_pimux4x1 MUX0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[3:0]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[0])
);
aibio_pimux4x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[7:4]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[1])
);
aibio_pimux4x1 I2
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[11:8]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[2])
);
aibio_pimux4x1 I1
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[15:12]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[3])
);
aibio_pimux4x1 I5
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(clkphsel_stg2),
.i_clkph_sel(clk_sel_stg2),
.o_clkph(o_clk)
);
endmodule |
module aibio_pimux4x1
(
//----------Supply pins----------//
input vddcq,
input vss,
//---------Input pins-----------//
input [3:0]i_clkph,
input [3:0]i_clkph_sel,
//---------Output pins----------//
output o_clkph
);
assign o_clkph = (i_clkph_sel == 4'b0001) ? i_clkph[0] :
(i_clkph_sel == 4'b0010) ? i_clkph[1] :
(i_clkph_sel == 4'b0100) ? i_clkph[2] :
(i_clkph_sel == 4'b1000) ? i_clkph[3] :
1'b0;
endmodule |
module aibio_clock_dist
(
//---------Supply pins------------//
input vddcq,
input vss,
//---------Input pins------------//
input i_piclk_even_in,
input i_piclk_odd_in,
input i_loopback_en,
//---------Output pins----------//
output o_piclk_even_loopback,
output o_piclk_odd_loopback
);
assign o_piclk_even_loopback = i_loopback_en ? i_piclk_even_in : 1'b0;
assign o_piclk_odd_loopback = i_loopback_en ? i_piclk_odd_in : 1'b0;
endmodule |
module aibio_outclk_select
(
//----------Supply pins-----------//
input vddcq,
input vss,
//----------Input pins-----------//
input [3:0] i_adapter_code,
input [3:0] i_soc_code,
input [15:0] i_clkphb,
//----------Output pins-----------//
output o_clk_adapter,
output o_clk_soc
);
wire clk_adapter_b;
wire clk_soc_b;
aibio_outclk_mux16x1 Adapater_MUX
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb),
.i_clksel(i_adapter_code),
.o_clk(clk_adapter_b)
);
aibio_outclk_mux16x1 SOC_MUX
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb),
.i_clksel(i_soc_code),
.o_clk(clk_soc_b)
);
assign o_clk_adapter = ~clk_adapter_b;
assign o_clk_soc = ~clk_soc_b;
endmodule |
module aibio_se_to_diff
(
input vddcq,
input vss,
input i,
output o,
output o_b
);
assign o = i;
assign o_b = ~i;
endmodule |
module aibio_auxch_Schmit_trigger
(
//-------Supply pins----------//
input vddc,
input vss,
//-------Input pin-----------//
input vin,
//-------Output pin---------//
output vout
);
assign vout=vin;
endmodule |
module aibio_auxch_cbb
(
//----supply pins----//
input vddc,
input vss,
//-----input pins-------------//
input dual_mode_sel,
input i_m_power_on_reset,
input m_por_ovrd,
input m_device_detect_ovrd,
input [2:0]rxbuf_cfg,
input powergood,
input gen1mode_en,
//-----inout pins-----------------//
inout xx_power_on_reset,
inout xx_device_detect,
//-------output pins--------------//
output o_m_power_on_reset,
output m_device_detect,
//--------spare pins---------------//
input [3:0]i_aux_spare,
output [3:0]o_aux_spare
);
wire net016;
wire net017;
wire net09;
wire net028;
wire net023;
wire net013;
wire vin1;
wire vin2;
assign net013 = ~i_m_power_on_reset;
assign net09 = ~ dual_mode_sel;
assign net028 = ~net09;
assign net023 = ~vddc;
assign o_m_power_on_reset = (m_por_ovrd & net016);
assign m_device_detect = (net017 | m_device_detect_ovrd);
assign xx_power_on_reset = (net09)? ~net013 : 1'hz;
assign xx_device_detect = (net028) ? ~net023 :1'hz;
assign vin1 = xx_power_on_reset;
assign vin2 = xx_device_detect;
aibio_auxch_Schmit_trigger schmit_trigger1
(
.vddc(vddc),
.vss(vss),
.vin(vin1),
.vout(net016)
);
aibio_auxch_Schmit_trigger schmit_trigger2
(
.vddc(vddc),
.vss(vss),
.vin(vin2),
.vout(net017)
);
endmodule |
module aibio_pulsegen_phsel_halfside
(
//---------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [7:0]i_clkph,
input [2:0]i_ph1sel,
input [2:0]i_ph2sel,
//--------Output pins---------//
output o_clkph1,
output o_clkph2
);
aibio_pulsegen_mux8x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_clksel(i_ph1sel),
.o_clkph(o_clkph1)
);
aibio_pulsegen_mux8x1 I1
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_clksel(i_ph2sel),
.o_clkph(o_clkph2)
);
endmodule |
module aibio_inpclk_select_txdll
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_in,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn
);
/*
wire i_clk_inp;
wire i_clk_inn;
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;
assign i_clk_loopbackp = i_clk_loopback;
assign i_clk_loopbackn = ~i_clk_loopback;
assign i_clk_sysp = i_clk_sys;
assign i_clk_sysn = ~i_clk_sys;
assign i_clk_inp = i_clk_in;
assign i_clk_inn = ~i_clk_in;
assign i_clk_jtagp = i_clk_jtag;
assign i_clk_jtagn = ~i_clk_jtag;
assign o_clkp = (i_clksel == 2'b00) ? i_clk_inp :
(i_clksel == 2'b01) ? i_clk_loopbackp :
(i_clksel == 2'b10) ? i_clk_sysp :
(i_clksel == 2'b11) ? i_clk_jtagp :
1'b0;
assign o_clkn = (i_clksel == 2'b00) ? i_clk_inn :
(i_clksel == 2'b01) ? i_clk_loopbackn :
(i_clksel == 2'b10) ? i_clk_sysn :
(i_clksel == 2'b11) ? i_clk_jtagn :
1'b0;
*/
wire o_clk;
wire [3:0]clksel_decoded;
aibio_decoder2x4 I5
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel),
.o(clksel_decoded)
);
aibio_pimux4x1 MUX_clkp
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(clksel_decoded),
.i_clkph({i_clk_jtag,i_clk_sys,i_clk_loopback,i_clk_in}),
.o_clkph(o_clk)
);
aibio_se_to_diff se_diff_1
(
.vddcq(vddcq),
.vss(vss),
.i(o_clk),
.o(o_clkp),
.o_b(o_clkn)
);
endmodule |
module aibio_pulsegen_muxfinal
(
//-------Supply pins--------//
input vddcq,
input vss,
//-------Input pins--------//
input [1:0]i_clkph1_even,
input [1:0]i_clkph1_odd,
input [1:0]i_clkph1_sel_even,
input [1:0]i_clkph1_sel_odd,
input [1:0]i_clkph2_even,
input [1:0]i_clkph2_odd,
input [1:0]i_clkph2_sel_even,
input [1:0]i_clkph2_sel_odd,
//-------Output pins---------//
output clk_out_even,
output clk_out_odd,
output pulse_out_even,
output pulse_out_odd
);
wire clkph1b_even;
wire clkph2b_even;
wire clkph1b_odd;
wire clkph2b_odd;
wire clkph2_odd;
wire clkph2_even;
aibio_pulsegen_mux2x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph1_even),
.i_clkph_sel(i_clkph1_sel_even),
.o_clkph(clkph1b_even)
);
aibio_pulsegen_mux2x1 I1
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph2_even),
.i_clkph_sel(i_clkph2_sel_even),
.o_clkph(clkph2b_even)
);
aibio_pulsegen_mux2x1 I3
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph2_odd),
.i_clkph_sel(i_clkph2_sel_odd),
.o_clkph(clkph2b_odd)
);
aibio_pulsegen_mux2x1 I4
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph1_odd),
.i_clkph_sel(i_clkph1_sel_odd),
.o_clkph(clkph1b_odd)
);
assign clk_out_even = ~clkph1b_even;
assign clk_out_odd = ~clkph1b_odd;
assign clkph2_odd = ~clkph2b_odd;
assign clkph2_even = ~clkph2b_even;
assign pulse_out_even = clk_out_even && clkph2_even;
assign pulse_out_odd = clk_out_odd && clkph2_odd;
endmodule |
module aibio_pulsegen_oddevn_halfside
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [7:0]i_clkph,
input [2:0]i_evn_ph1_sel,
input [2:0]i_evn_ph2_sel,
input [2:0]i_odd_ph1_sel,
input [2:0]i_odd_ph2_sel,
//--------Output pins-----------//
output o_clkph1_evn,
output o_clkph1_odd,
output o_clkph2_evn,
output o_clkph2_odd
);
aibio_pulsegen_phsel_halfside odd_ph1ph2
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_ph1sel(i_odd_ph1_sel),
.i_ph2sel(i_odd_ph2_sel),
.o_clkph1(o_clkph1_odd),
.o_clkph2(o_clkph2_odd)
);
aibio_pulsegen_phsel_halfside evn_ph1ph2
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_ph1sel(i_evn_ph1_sel),
.i_ph2sel(i_evn_ph2_sel),
.o_clkph1(o_clkph1_evn),
.o_clkph2(o_clkph2_evn)
);
endmodule |
module aibio_pulsegen_mux8x1
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [7:0] i_clkph,
input [2:0] i_clksel,
//-------Output pins---------//
output wor o_clkph
// output o_clkph //For LEC comment above line and uncomment this line
);
wire [7:0] clk_sel;
//wor o_clkph; //For LEC comment this line
aibio_decoder3x8 I1
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel),
.o(clk_sel)
);
aibio_pimux4x1 MUX0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph({i_clkph[3],i_clkph[2],i_clkph[1],i_clkph[0]}),
.i_clkph_sel({clk_sel[3],clk_sel[2],clk_sel[1],clk_sel[0]}),
.o_clkph(o_clkph)
);
aibio_pimux4x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph({i_clkph[7],i_clkph[6],i_clkph[5],i_clkph[4]}),
.i_clkph_sel({clk_sel[7],clk_sel[6],clk_sel[5],clk_sel[4]}),
.o_clkph(o_clkph)
);
//assign o_clkph = o_clkph_int1 || o_clkph_int2 ;
endmodule |
module aibio_pulsegen_mux2x1
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [1:0] i_clkph,
input [1:0] i_clkph_sel,
//-------Output pins--------//
output o_clkph
);
assign o_clkph = (i_clkph_sel == 2'b01) ? i_clkph[0] :
(i_clkph_sel == 2'b10) ? i_clkph[1] :
1'b0;
endmodule |
module aibio_txdll_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input ck_in,
input ck_loopback,
input ck_sys,
input ck_jtag,
input [1:0] inp_cksel,
input dll_en,
input dll_reset,
input [3:0] dll_biasctrl,
input [4:0] dll_capctrl,
input [3:0] dll_cksoc_code,
input [3:0] dll_ckadapter_code,
input [3:0] dll_even_phase1_sel,
input [3:0] dll_odd_phase1_sel,
input [3:0] dll_even_phase2_sel,
input [3:0] dll_odd_phase2_sel,
input [3:0] dll_lockthresh,
input [1:0] dll_lockctrl,
input loopback_en,
input pwrgood_in,
input dll_dfx_en,
input [4:0] dll_digview_sel,
input [4:0] dll_anaview_sel,
//------Output pins------//
output dll_lock,
output clk_odd,
output clk_even,
output clk_soc,
output clk_adapter,
output pulseclk_odd,
output pulseclk_even,
output pulseclk_odd_loopback,
output pulseclk_even_loopback,
output inbias,
output [3:0] ipbias,
output [1:0] dll_digviewout,
output dll_anaviewout,
//------Spare pins------//
input [7:0] i_dll_spare,
output [7:0] o_dll_spare
);
wire clkp,clkn;
wire up,dn,upb,dnb;
wire [15:0]clkphb;
wire dll_lock_en;
wire jtag_en;
wire dll_en_int;
wire dll_enb_int;
wire dll_clk_inp;
wire dll_clk_inn;
wire pulseclk_odd_int;
wire pulseclk_even_int;
wire clk_adapter_int;
wire clk_soc_int;
assign dll_en_int = dll_en & pwrgood_in;
assign dll_enb_int= ~dll_en_int;
`ifdef POST_WORST
localparam delay_inpclk_select = 80.73;
localparam delay_pulsegen = 132;
localparam delay_outclk_select = 114.96;
`else
localparam delay_inpclk_select = 0.0;
localparam delay_pulsegen = 0.0;
localparam delay_outclk_select = 0.0;
`endif
aibio_inpclk_select_txdll inpclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clk_in(ck_in),
.i_clk_loopback(ck_loopback),
.i_clk_sys(ck_sys),
.i_clk_jtag(ck_jtag),
.i_clksel(inp_cksel),
.o_clkp(clkp),
.o_clkn(clkn)
);
assign #(delay_inpclk_select) dll_clk_inp = clkp;
assign #(delay_inpclk_select) dll_clk_inn = clkn;
aibio_dll_top dll_top
(
.vddcq(vddcq),
.vss(vss),
.i_clkp(dll_clk_inp),
.i_clkn(dll_clk_inn),
.i_clkp_cdr(),
.i_clkn_cdr(),
.i_dll_biasctrl(dll_biasctrl),
.i_dll_capctrl(dll_capctrl),
.i_dll_en(dll_en_int),
.i_dll_enb(dll_enb_int),
.i_reset(dll_reset),
.i_jtag_en(jtag_en),
.o_up(up),
.o_dn(dn),
.o_upb(upb),
.o_dnb(dnb),
.o_dll_clkphb(clkphb),
.o_piclk_180(),
.o_piclk_90(),
.o_cdr_clk(),
.o_pbias(),
.o_nbias(),
.ph_diff()
);
aibio_lock_detector lock_detector
(
.vddcq(vddcq),
.vss(vss),
.i_clkin(ck_sys),
.i_up(up),
.i_dn(dn),
.i_upb(upb),
.i_dnb(dnb),
.i_reset(dll_reset),
.i_lockthresh(dll_lockthresh[1:0]),
.i_lockctrl(dll_lockctrl),
.o_dll_lock(dll_lock)
);
aibio_pulsegen_top pulsegen
(
.vddcq(vddcq),
.vss(vss),
.i_clkphb(clkphb),
.i_dll_even_phase1_sel(dll_even_phase1_sel),
.i_dll_odd_phase1_sel(dll_odd_phase1_sel),
.i_dll_even_phase2_sel(dll_even_phase2_sel),
.i_dll_odd_phase2_sel(dll_odd_phase2_sel),
.o_clk_even(),
.o_clk_odd(),
.o_pulseclk_even(pulseclk_even_int),
.o_pulseclk_odd(pulseclk_odd_int)
);
aibio_clock_dist piclk_dist
(
.vddcq(vddcq),
.vss(vss),
.i_piclk_even_in(pulseclk_even),
.i_piclk_odd_in(pulseclk_odd),
.i_loopback_en(loopback_en),
.o_piclk_even_loopback(pulseclk_even_loopback),
.o_piclk_odd_loopback(pulseclk_odd_loopback)
);
aibio_outclk_select outclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clkphb(clkphb),
.i_adapter_code(dll_ckadapter_code),
.i_soc_code(dll_cksoc_code),
.o_clk_adapter(clk_adapter_int),
.o_clk_soc(clk_soc_int)
);
assign jtag_en = inp_cksel[1] && inp_cksel[0] ;
assign #(delay_pulsegen) pulseclk_even = pulseclk_even_int;
assign #(delay_pulsegen) pulseclk_odd = pulseclk_odd_int;
assign #(delay_outclk_select) clk_soc = clk_soc_int;
assign #(delay_outclk_select) clk_adapter = clk_adapter_int;
endmodule |
module aibio_pulsegen_top
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [15:0] i_clkphb,
input [3:0] i_dll_even_phase1_sel,
input [3:0] i_dll_odd_phase1_sel,
input [3:0] i_dll_even_phase2_sel,
input [3:0] i_dll_odd_phase2_sel,
//--------Output pins-----------//
output o_clk_even,
output o_clk_odd,
output o_pulseclk_even,
output o_pulseclk_odd
);
wire [1:0]clkph1_even;
wire [1:0]clkph2_even;
wire [1:0]clkph1_odd;
wire [1:0]clkph2_odd;
wire i_dll_odd_phase1_selb_3;
wire i_dll_even_phase1_selb_3;
wire i_dll_odd_phase2_selb_3;
wire i_dll_even_phase2_selb_3;
assign i_dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign i_dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign i_dll_odd_phase1_selb_3 = ~i_dll_odd_phase1_sel[3];
assign i_dll_even_phase1_selb_3 = ~i_dll_even_phase1_sel[3];
aibio_pulsegen_oddevn_halfside phsel_LSB
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb[7:0]),
.i_evn_ph1_sel(i_dll_even_phase1_sel[2:0]),
.i_evn_ph2_sel(i_dll_even_phase2_sel[2:0]),
.i_odd_ph1_sel(i_dll_odd_phase1_sel[2:0]),
.i_odd_ph2_sel(i_dll_odd_phase2_sel[2:0]),
.o_clkph1_evn(clkph1_even[0]),
.o_clkph1_odd(clkph1_odd[0]),
.o_clkph2_evn(clkph2_even[0]),
.o_clkph2_odd(clkph2_odd[0])
);
aibio_pulsegen_oddevn_halfside phsel_MSB
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb[15:8]),
.i_evn_ph1_sel(i_dll_even_phase1_sel[2:0]),
.i_evn_ph2_sel(i_dll_even_phase2_sel[2:0]),
.i_odd_ph1_sel(i_dll_odd_phase1_sel[2:0]),
.i_odd_ph2_sel(i_dll_odd_phase2_sel[2:0]),
.o_clkph1_evn(clkph1_even[1]),
.o_clkph1_odd(clkph1_odd[1]),
.o_clkph2_evn(clkph2_even[1]),
.o_clkph2_odd(clkph2_odd[1])
);
aibio_pulsegen_muxfinal muxfinal
(
.vddcq(vddcq),
.vss(vss),
.i_clkph1_even(clkph1_even),
.i_clkph1_odd(clkph1_odd),
.i_clkph1_sel_even({i_dll_even_phase1_sel[3],i_dll_even_phase1_selb_3}),
.i_clkph1_sel_odd({i_dll_odd_phase1_sel[3],i_dll_odd_phase1_selb_3}),
.i_clkph2_even(clkph2_even),
.i_clkph2_odd(clkph2_odd),
.i_clkph2_sel_even({i_dll_even_phase2_selb_3,i_dll_even_phase2_sel[3]}),
.i_clkph2_sel_odd({i_dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[3]}),
.clk_out_even(o_clk_even),
.clk_out_odd(o_clk_odd),
.pulse_out_even(o_pulseclk_even),
.pulse_out_odd(o_pulseclk_odd)
);
endmodule |
module aibio_pioddevn_top
(
//--------Supply pins-----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkphb,
input [7:0]i_picode_evn,
input [7:0]i_picode_odd,
input i_pbias,
input i_nbias,
input [2:0]i_bias_trim,
input [1:0]i_capsel,
input [1:0]i_capselb,
input i_clken,
input i_pien,
input i_reset,
input i_update,
input real ph_diff,
//-------Output pins-----------//
output o_clkpi_evn,
output o_clkpi_odd
);
//--------Internal signals----------//
wire [2:0]pbias_trim;
wire [2:0]nbias_trim;
wire clkph_0;
wire clkph_1;
wire clkph_2;
wire clkph_3;
wire clkph_4;
wire clkph_5;
wire clkph_6;
wire clkph_7;
wire clkph_8;
wire clkph_9;
wire clkph_10;
wire clkph_11;
wire clkph_12;
wire clkph_13;
wire clkph_14;
wire clkph_15;
wire [7:0]clkphsel_stg1_odd;
wire [7:0]clkphsel_stg1_evn;
wire [1:0]clkphsel_stg2_odd;
wire [1:0]clkphsel_stg2_evn;
wire [7:0]pixer_odd;
wire [7:0]pixer_evn;
wire [1:0]phsel_stg2_b_odd;
wire [1:0]phsel_stg2_b_evn;
wire [1:0]phsel_stg2_bb_odd;
wire [1:0]phsel_stg2_bb_evn;
wire clkevn_evn;
wire clkevn_odd;
wire clkodd_evn;
wire clkodd_odd;
assign clkph_0 = ~i_clkphb[0];
assign clkph_1 = ~i_clkphb[1];
assign clkph_2 = ~i_clkphb[2];
assign clkph_3 = ~i_clkphb[3];
assign clkph_4 = ~i_clkphb[4];
assign clkph_5 = ~i_clkphb[5];
assign clkph_6 = ~i_clkphb[6];
assign clkph_7 = ~i_clkphb[7];
assign clkph_8 = ~i_clkphb[8];
assign clkph_9 = ~i_clkphb[9];
assign clkph_10 = ~i_clkphb[10];
assign clkph_11 = ~i_clkphb[11];
assign clkph_12 = ~i_clkphb[12];
assign clkph_13 = ~i_clkphb[13];
assign clkph_14 = ~i_clkphb[14];
assign clkph_15 = ~i_clkphb[15];
assign phsel_stg2_b_odd[0] = ~(clkphsel_stg2_odd[0] && i_pien);
assign phsel_stg2_b_odd[1] = ~(clkphsel_stg2_odd[1] && i_pien);
assign phsel_stg2_bb_odd[0] = ~phsel_stg2_b_odd[0];
assign phsel_stg2_bb_odd[1] = ~phsel_stg2_b_odd[1];
assign phsel_stg2_b_evn[0] = ~(clkphsel_stg2_evn[0] && i_pien);
assign phsel_stg2_b_evn[1] = ~(clkphsel_stg2_evn[1] && i_pien);
assign phsel_stg2_bb_evn[0] = ~phsel_stg2_b_evn[0];
assign phsel_stg2_bb_evn[1] = ~phsel_stg2_b_evn[1];
aibio_bias_trim I2
(
.vddcq(vddcq),
.vss(vss),
.i_bias_trim(i_bias_trim),
.i_pbias(i_pbias),
.i_nbias(i_nbias),
.o_pbias_trim(pbias_trim),
.o_nbias_trim(nbias_trim)
);
aibio_pi_decode_sync odd_decode_sync
(
.vddcq(vddcq),
.vss(vss),
.i_clk_en(i_clken),
.i_clk_sync(o_clkpi_odd),
.i_picode(i_picode_odd),
.i_reset(i_reset),
.i_update(i_update),
.o_clkphsel_stg1_synced(clkphsel_stg1_odd),
.o_clkphsel_stg2_synced(clkphsel_stg2_odd),
.o_pimixer_synced(pixer_odd)
);
aibio_pi_decode_sync evn_decode_sync
(
.vddcq(vddcq),
.vss(vss),
.i_clk_en(i_clken),
.i_clk_sync(o_clkpi_evn),
.i_picode(i_picode_evn),
.i_reset(i_reset),
.i_update(i_update),
.o_clkphsel_stg1_synced(clkphsel_stg1_evn),
.o_clkphsel_stg2_synced(clkphsel_stg2_evn),
.o_pimixer_synced(pixer_evn)
);
aibio_pioddevn_phsel_half phsel_oddevn_LSB
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_capsel),
.i_cap_selb(i_capselb),
.i_clk_evnph({clkph_6,clkph_4,clkph_2,clkph_0}),
.i_clk_evnphsel_stg1_evn({clkphsel_stg1_evn[6],clkphsel_stg1_evn[4],clkphsel_stg1_evn[2],clkphsel_stg1_evn[0]}),
.i_clk_evnphsel_stg1_odd({clkphsel_stg1_odd[6],clkphsel_stg1_odd[4],clkphsel_stg1_odd[2],clkphsel_stg1_odd[0]}),
.i_clk_evnphsel_stg2_evn(phsel_stg2_b_evn[0]),
.i_clk_evnphsel_stg2_odd(phsel_stg2_b_odd[0]),
.i_clk_oddph({clkph_7,clkph_5,clkph_3,clkph_1}),
.i_clk_oddphsel_stg1_evn({clkphsel_stg1_evn[7],clkphsel_stg1_evn[5],clkphsel_stg1_evn[3],clkphsel_stg1_evn[1]}),
.i_clk_oddphsel_stg1_odd({clkphsel_stg1_odd[7],clkphsel_stg1_odd[5],clkphsel_stg1_odd[3],clkphsel_stg1_odd[1]}),
.i_clk_oddphsel_stg2_evn(phsel_stg2_b_evn[1]),
.i_clk_oddphsel_stg2_odd(phsel_stg2_b_odd[1]),
.i_nbias(i_nbias),
.i_nbias_trim(nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(pbias_trim),
.o_clk_evnph_evn(clkevn_evn),
.o_clk_evnph_odd(clkevn_odd),
.o_clk_oddph_evn(clkodd_evn),
.o_clk_oddph_odd(clkodd_odd)
);
aibio_pioddevn_phsel_half phsel_oddevn_MSB
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_capsel),
.i_cap_selb(i_capselb),
.i_clk_evnph({clkph_14,clkph_12,clkph_10,clkph_8}),
.i_clk_evnphsel_stg1_evn({clkphsel_stg1_evn[6],clkphsel_stg1_evn[4],clkphsel_stg1_evn[2],clkphsel_stg1_evn[0]}),
.i_clk_evnphsel_stg1_odd({clkphsel_stg1_odd[6],clkphsel_stg1_odd[4],clkphsel_stg1_odd[2],clkphsel_stg1_odd[0]}),
.i_clk_evnphsel_stg2_evn(phsel_stg2_bb_evn[0]),
.i_clk_evnphsel_stg2_odd(phsel_stg2_bb_odd[0]),
.i_clk_oddph({clkph_15,clkph_13,clkph_11,clkph_9}),
.i_clk_oddphsel_stg1_evn({clkphsel_stg1_evn[7],clkphsel_stg1_evn[5],clkphsel_stg1_evn[3],clkphsel_stg1_evn[1]}),
.i_clk_oddphsel_stg1_odd({clkphsel_stg1_odd[7],clkphsel_stg1_odd[5],clkphsel_stg1_odd[3],clkphsel_stg1_odd[1]}),
.i_clk_oddphsel_stg2_evn(phsel_stg2_bb_evn[1]),
.i_clk_oddphsel_stg2_odd(phsel_stg2_bb_odd[1]),
.i_nbias(i_nbias),
.i_nbias_trim(nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(pbias_trim),
.o_clk_evnph_evn(clkevn_evn),
.o_clk_evnph_odd(clkevn_odd),
.o_clk_oddph_evn(clkodd_evn),
.o_clk_oddph_odd(clkodd_odd)
);
aibio_pioddevn_mixer_top oddevn_mixer
(
.vddcq(vddcq),
.vss(vss),
.i_clkevn_evn(clkevn_evn),
.i_clkevn_odd(clkevn_odd),
.i_clkodd_evn(clkodd_evn),
.i_clkodd_odd(clkodd_odd),
.i_pien(i_pien),
.i_pimixer_evn(pixer_evn),
.i_pimixer_odd(pixer_odd),
.i_clkph({clkph_15,clkph_14,clkph_13,clkph_12,clkph_11,clkph_10,clkph_9,clkph_8,clkph_7,clkph_6,clkph_5,clkph_4,clkph_3,clkph_2,clkph_1,clkph_0}),
.i_pievn_code(i_picode_evn),
.i_piodd_code(i_picode_odd),
.ph_diff(ph_diff),
.o_clk_evn(o_clkpi_evn),
.o_clk_odd(o_clkpi_odd)
);
endmodule |
module aibio_pi_decode_sync
(
//---------Supply pins--------//
input vddcq,
input vss,
//---------Input pins----------//
input i_clk_en,
input i_clk_sync,
input [7:0] i_picode,
input i_reset,
input i_update,
//---------Output pins---------//
output [7:0] o_clkphsel_stg1_synced,
output [1:0] o_clkphsel_stg2_synced,
output [7:0] o_pimixer_synced
);
wire [7:0] clkphsel_stg1;
wire [1:0] clkphsel_stg2;
wire [7:0] pimixer;
aibio_pi_decode I1
(
.vddcq(vddcq),
.vss(vss),
.i_picode(i_picode),
.o_clkphsel_stg1(clkphsel_stg1),
.o_clkphsel_stg2(clkphsel_stg2),
.o_pimixer(pimixer)
);
aibio_pi_codeupdate I2
(
.vddcq(vddcq),
.vss(vss),
.i_clk(i_clk_sync),
.i_clk_en(i_clk_en),
.i_clkphsel_stg1(clkphsel_stg1),
.i_clkphsel_stg2(clkphsel_stg2),
.i_pimixer(pimixer),
.i_update(i_update),
.i_reset(i_reset),
.o_clkphsel_stg1(o_clkphsel_stg1_synced),
.o_clkphsel_stg2(o_clkphsel_stg2_synced),
.o_pimixer(o_pimixer_synced)
);
endmodule |
module aibio_pi_decode
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [7:0] i_picode,
//--------Output pins----------//
output [7:0]o_clkphsel_stg1,
output [1:0]o_clkphsel_stg2,
output [7:0]o_pimixer
);
wire [3:0] picode_plus1;
wire mix_on;
wire [7:0] curr_code;
wire [7:0] next_code;
wire [7:1] therm;
wire [7:1] therm_b;
wire next_odd_en;
wire next_evn_en;
wire i_picode_b_3;
aibio_decoder3x8 I7
(
.vddcq(vddcq),
.vss(vss),
.i(i_picode[5:3]),
.o(curr_code)
);
aibio_decoder3x8 I6
(
.vddcq(vddcq),
.vss(vss),
.i(picode_plus1[2:0]),
.o(next_code)
);
aibio_3bit_bin_to_therm I3
(
.vddcq(vddcq),
.vss(vss),
.b(i_picode[2:0]),
.t(therm)
);
aibio_4bit_plus1 I4
(
.vddcq(vddcq),
.vss(vss),
.i_code(i_picode[6:3]),
.o_code(picode_plus1)
);
assign therm_b[7] = ~therm[7];
assign therm_b[6] = ~therm[6];
assign therm_b[5] = ~therm[5];
assign therm_b[4] = ~therm[4];
assign therm_b[3] = ~therm[3];
assign therm_b[2] = ~therm[2];
assign therm_b[1] = ~therm[1];
//assign mix_on = i_picode[2] || i_picode[1] || i_picode[0];
//assign next_evn_en = i_picode[3] && mix_on ;
assign next_evn_en = i_picode[3];
assign i_picode_b_3 = ~i_picode[3];
//assign next_odd_en = i_picode_b_3 && mix_on;
assign next_odd_en = i_picode_b_3;
assign o_clkphsel_stg2[0] = next_evn_en ? picode_plus1[3] : i_picode[6];
assign o_clkphsel_stg2[1] = next_odd_en ? picode_plus1[3] : i_picode[6];
assign o_clkphsel_stg1[6] = next_evn_en ? next_code[6] : curr_code[6];
assign o_clkphsel_stg1[4] = next_evn_en ? next_code[4] : curr_code[4];
assign o_clkphsel_stg1[2] = next_evn_en ? next_code[2] : curr_code[2];
assign o_clkphsel_stg1[0] = next_evn_en ? next_code[0] : curr_code[0];
assign o_clkphsel_stg1[7] = next_odd_en ? next_code[7] : curr_code[7];
assign o_clkphsel_stg1[5] = next_odd_en ? next_code[5] : curr_code[5];
assign o_clkphsel_stg1[3] = next_odd_en ? next_code[3] : curr_code[3];
assign o_clkphsel_stg1[1] = next_odd_en ? next_code[1] : curr_code[1];
assign o_pimixer[7] = i_picode[3] ? therm_b[7] : therm[7];
assign o_pimixer[6] = i_picode[3] ? therm_b[6] : therm[6];
assign o_pimixer[5] = i_picode[3] ? therm_b[5] : therm[5];
assign o_pimixer[4] = i_picode[3] ? therm_b[4] : therm[4];
assign o_pimixer[3] = i_picode[3] ? therm_b[3] : therm[3];
assign o_pimixer[2] = i_picode[3] ? therm_b[2] : therm[2];
assign o_pimixer[1] = i_picode[3] ? therm_b[1] : therm[1];
assign o_pimixer[0] = i_picode[3];
endmodule |
module aibio_pioddevn_mixer_top
(
//--------Supply pins--------//
input vddcq,
input vss,
//--------Input pins---------//
input i_clkevn_evn,
input i_clkevn_odd,
input i_clkodd_evn,
input i_clkodd_odd,
input i_pien,
input [7:0]i_pimixer_evn,
input [7:0]i_pimixer_odd,
input [15:0]i_clkph,
input [7:0]i_pievn_code,
input [7:0]i_piodd_code,
input real ph_diff,
//--------Output pins---------//
output o_clk_evn,
output o_clk_odd
);
wire odd_clk_mixer;
wire evn_clk_mixer;
wire odd_clk_mixerb;
wire evn_clk_mixerb;
wire out_ph_0_flag_evn;
wire out_ph_0_flag_odd;
wire out_ph_0_flag;
wire odd_clk_mixer_int;
wire evn_clk_mixer_int;
aibio_pi_mixer_top mixer_odd
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_evn(i_clkevn_odd),
.i_clkph_odd(i_clkodd_odd),
.i_oddph_en(i_pimixer_odd),
.i_pien(i_pien),
.i_clkph(i_clkph),
.i_picode(i_piodd_code),
.ph_diff(ph_diff),
.o_clkmix_out(odd_clk_mixer)
);
aibio_pi_mixer_top mixer_evn
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_evn(i_clkevn_evn),
.i_clkph_odd(i_clkodd_evn),
.i_oddph_en(i_pimixer_evn),
.i_pien(i_pien),
.i_clkph(i_clkph),
.i_picode(i_pievn_code),
.ph_diff(ph_diff),
.o_clkmix_out(evn_clk_mixer)
);
assign evn_clk_mixerb = ~evn_clk_mixer;
assign o_clk_evn = ~evn_clk_mixerb;
assign odd_clk_mixerb = ~odd_clk_mixer;
assign o_clk_odd = ~odd_clk_mixerb;
endmodule |
module aibio_half_adder
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input a,
input b,
//------Output pins---------//
output c,
output s
);
assign s = a^b;
assign c = a&&b;
endmodule |
module aibio_pi_phsel_halfside
(
//---------Supply pins--------//
input vddcq,
input vss,
//--------Input pins---------//
input [1:0]i_cap_sel,
input [1:0]i_cap_selb,
input [3:0]i_clk_evnph,
input [3:0]i_clk_evnphsel_stg1,
input i_clk_evnphsel_stg2,
input [3:0]i_clk_oddph,
input [3:0]i_clk_oddphsel_stg1,
input i_clk_oddphsel_stg2,
input i_nbias,
input [2:0]i_nbias_trim,
input i_pbias,
input [2:0]i_pbias_trim,
//--------Output pins----------//
output o_clk_evnph,
output o_clk_oddph
);
aibio_pi_phsel_quarter phsel_mux_odd
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clk_oddph),
.i_clkphsel_stg1(i_clk_oddphsel_stg1),
.i_clkphsel_stg2(i_clk_oddphsel_stg2),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.o_clkph(o_clk_oddph)
);
aibio_pi_phsel_quarter phsel_mux_evn
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clk_evnph),
.i_clkphsel_stg1(i_clk_evnphsel_stg1),
.i_clkphsel_stg2(i_clk_evnphsel_stg2),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.o_clkph(o_clk_evnph)
);
endmodule |
module aibio_4bit_plus1
(
//-------Supply pins------//
input vddcq,
input vss,
//-------Input pins--------//
input [3:0] i_code,
//-------Output pins-------//
output [3:0] o_code
);
wire net13;
wire net14;
wire net15;
wire net27;
aibio_half_adder I0
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[0]),
.b(1'b1),
.c(net13),
.s(o_code[0])
);
aibio_half_adder I1
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[1]),
.b(net13),
.c(net14),
.s(o_code[1])
);
aibio_half_adder I2
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[2]),
.b(net14),
.c(net15),
.s(o_code[2])
);
aibio_half_adder I3
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[3]),
.b(net15),
.c(net27),
.s(o_code[3])
);
endmodule |
module aibio_inpclk_select
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_inp,
input i_clk_inn,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input i_clk_cdr_inp,
input i_clk_cdr_inn,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn,
output o_cdr_clkp,
output o_cdr_clkn
);
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;
wire [3:0] clksel_decoded;
wire net016,net017,net018,net019;
aibio_se_to_diff se_diff_1
(
.vddcq(vddcq),
.vss(vss),
.i(i_clk_loopback),
.o(i_clk_loopbackp),
.o_b(i_clk_loopbackn)
);
aibio_se_to_diff I7
(
.vddcq(vddcq),
.vss(vss),
.i(i_clk_jtag),
.o(i_clk_jtagp),
.o_b(i_clk_jtagn)
);
aibio_se_to_diff se_diff_2
(
.vddcq(vddcq),
.vss(vss),
.i(i_clk_sys),
.o(i_clk_sysp),
.o_b(i_clk_sysn)
);
aibio_pimux4x1 MUX_dummy_p
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel({1'b0,1'b0,1'b0,1'b1}), //TBD
.i_clkph({1'b0,1'b0,1'b0,i_clk_cdr_inp}),
.o_clkph(net017)
);
aibio_pimux4x1 MUX_dummy_n
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel({1'b0,1'b0,1'b0,1'b1}),
.i_clkph({1'b0,1'b0,1'b0,i_clk_cdr_inn}),
.o_clkph(net016)
);
aibio_decoder2x4 I5
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel),
.o(clksel_decoded)
);
aibio_pimux4x1 MUX_clkp
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(clksel_decoded),
.i_clkph({i_clk_jtagp,i_clk_sysp,i_clk_loopbackp,i_clk_inp}),
.o_clkph(net019)
);
aibio_pimux4x1 MUX_clkn
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(clksel_decoded),
.i_clkph({i_clk_jtagn,i_clk_sysn,i_clk_loopbackn,i_clk_inn}),
.o_clkph(net018)
);
/*
assign o_cdr_clkp = ~net017;
assign o_cdr_clkn = ~net016;
assign o_clkp = ~net019;
assign o_clkn = ~net018;
*/
assign o_cdr_clkp = net017;
assign o_cdr_clkn = net016;
assign o_clkp = net019;
assign o_clkn = net018;
endmodule |
module aibio_pi_phsel_quarter
(
//--------Supply pins-------------//
input vddcq,
input vss,
//--------Input pins-------------//
input [3:0] i_clkph,
input [3:0] i_clkphsel_stg1,
input i_clkphsel_stg2,
input i_pbias,
input [2:0] i_pbias_trim,
input i_nbias,
input [2:0] i_nbias_trim,
input [1:0] i_cap_sel,
input [1:0] i_cap_selb,
//---------Output pins------------//
output o_clkph
);
wire ph_MUX_out;
aibio_pimux4x1 MUX0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(i_clkphsel_stg1),
.i_clkph(i_clkph),
.o_clkph(ph_MUX_out)
);
assign o_clkph = (i_clkphsel_stg2 == 1'b1) ? ph_MUX_out : 1'bz;
endmodule |
module aibio_pioddevn_phsel_half
(
//--------Supply pins---------//
input vddcq,
input vss,
//--------Input pins----------//
input [1:0]i_cap_sel,
input [1:0]i_cap_selb,
input [3:0]i_clk_evnph,
input [3:0]i_clk_evnphsel_stg1_evn,
input [3:0]i_clk_evnphsel_stg1_odd,
input i_clk_evnphsel_stg2_evn,
input i_clk_evnphsel_stg2_odd,
input [3:0]i_clk_oddph,
input [3:0]i_clk_oddphsel_stg1_evn,
input [3:0]i_clk_oddphsel_stg1_odd,
input i_clk_oddphsel_stg2_evn,
input i_clk_oddphsel_stg2_odd,
input i_nbias,
input [2:0] i_nbias_trim,
input i_pbias,
input [2:0]i_pbias_trim,
//---------Output pins-----------//
output o_clk_evnph_evn,
output o_clk_evnph_odd,
output o_clk_oddph_evn,
output o_clk_oddph_odd
);
aibio_pi_phsel_halfside oddclk_phselhalf
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.i_clk_evnph(i_clk_evnph),
.i_clk_evnphsel_stg1(i_clk_evnphsel_stg1_odd),
.i_clk_evnphsel_stg2(i_clk_evnphsel_stg2_odd),
.i_clk_oddph(i_clk_oddph),
.i_clk_oddphsel_stg1(i_clk_oddphsel_stg1_odd),
.i_clk_oddphsel_stg2(i_clk_oddphsel_stg2_odd),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.o_clk_evnph(o_clk_evnph_odd),
.o_clk_oddph(o_clk_oddph_odd)
);
aibio_pi_phsel_halfside evnclk_phselhalf
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.i_clk_evnph(i_clk_evnph),
.i_clk_evnphsel_stg1(i_clk_evnphsel_stg1_evn),
.i_clk_evnphsel_stg2(i_clk_evnphsel_stg2_evn),
.i_clk_oddph(i_clk_oddph),
.i_clk_oddphsel_stg1(i_clk_oddphsel_stg1_evn),
.i_clk_oddphsel_stg2(i_clk_oddphsel_stg2_evn),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.o_clk_evnph(o_clk_evnph_evn),
.o_clk_oddph(o_clk_oddph_evn)
);
endmodule |
module aibio_cdr_detect
(
//----------Supply pins------------//
input vddcq,
input vss,
//---------Input pins--------------//
input i_cdr_clk,
input i_piclk_90,
input i_piclk_180,
input i_sdr_mode,
input i_reset,
//---------Output pins-------------//
output reg o_cdr_phdet
);
wire clk_int;
wire rstb;
assign rstb = ~i_reset;
assign clk_int = (i_sdr_mode) ? i_piclk_180 : i_piclk_90;
`ifdef POST_WORST
localparam t_setup = 0.0;
localparam t_hold = 0.0;
localparam t_clk2q = 0.0;
`else
localparam t_setup = 0.0;
localparam t_hold = 0.0;
localparam t_clk2q = 0.0;
`endif
sampler #(t_setup,t_hold,t_clk2q)
i_cdr_phdet
(
.data_in(i_cdr_clk),
.clk(clk_int),
.rst(rstb),
.data_out(o_cdr_phdet)
);
/*
always @(posedge clk_int or negedge rstb)
begin
if(!rstb)
begin
o_cdr_phdet <= 1'b0;
end
else
begin
o_cdr_phdet <= i_cdr_clk;
end
end
*/
endmodule |
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