-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2019.1.3
-- Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity effect_delay is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    inData_l : IN STD_LOGIC_VECTOR (31 downto 0);
    inData_r : IN STD_LOGIC_VECTOR (31 downto 0);
    config_r_address0 : OUT STD_LOGIC_VECTOR (7 downto 0);
    config_r_ce0 : OUT STD_LOGIC;
    config_r_we0 : OUT STD_LOGIC;
    config_r_d0 : OUT STD_LOGIC_VECTOR (31 downto 0);
    config_r_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
    config_offset : IN STD_LOGIC_VECTOR (4 downto 0);
    m_axi_extMemPtr_V_AWVALID : OUT STD_LOGIC;
    m_axi_extMemPtr_V_AWREADY : IN STD_LOGIC;
    m_axi_extMemPtr_V_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_extMemPtr_V_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_extMemPtr_V_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_extMemPtr_V_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_extMemPtr_V_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_extMemPtr_V_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_extMemPtr_V_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_WVALID : OUT STD_LOGIC;
    m_axi_extMemPtr_V_WREADY : IN STD_LOGIC;
    m_axi_extMemPtr_V_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_extMemPtr_V_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_WLAST : OUT STD_LOGIC;
    m_axi_extMemPtr_V_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_ARVALID : OUT STD_LOGIC;
    m_axi_extMemPtr_V_ARREADY : IN STD_LOGIC;
    m_axi_extMemPtr_V_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_extMemPtr_V_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_extMemPtr_V_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_extMemPtr_V_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_extMemPtr_V_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_extMemPtr_V_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_extMemPtr_V_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_extMemPtr_V_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_RVALID : IN STD_LOGIC;
    m_axi_extMemPtr_V_RREADY : OUT STD_LOGIC;
    m_axi_extMemPtr_V_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
    m_axi_extMemPtr_V_RLAST : IN STD_LOGIC;
    m_axi_extMemPtr_V_RID : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
    m_axi_extMemPtr_V_BVALID : IN STD_LOGIC;
    m_axi_extMemPtr_V_BREADY : OUT STD_LOGIC;
    m_axi_extMemPtr_V_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
    m_axi_extMemPtr_V_BID : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_extMemPtr_V_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
    ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;


architecture behav of effect_delay is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000010";
    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000100";
    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000001000";
    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000010000";
    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000100000";
    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000001000000";
    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000010000000";
    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000100000000";
    constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000001000000000";
    constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000010000000000";
    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000100000000000";
    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000001000000000000";
    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000010000000000000";
    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000100000000000000";
    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000001000000000000000";
    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000010000000000000000";
    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000100000000000000000";
    constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000001000000000000000000";
    constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000010000000000000000000";
    constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000100000000000000000000";
    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000001000000000000000000000";
    constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000010000000000000000000000";
    constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000100000000000000000000000";
    constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000001000000000000000000000000";
    constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000010000000000000000000000000";
    constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000100000000000000000000000000";
    constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000001000000000000000000000000000";
    constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000010000000000000000000000000000";
    constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000100000000000000000000000000000";
    constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000001000000000000000000000000000000";
    constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000010000000000000000000000000000000";
    constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000100000000000000000000000000000000";
    constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000001000000000000000000000000000000000";
    constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000010000000000000000000000000000000000";
    constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000100000000000000000000000000000000000";
    constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000001000000000000000000000000000000000000";
    constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000010000000000000000000000000000000000000";
    constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (50 downto 0) := "000000000000100000000000000000000000000000000000000";
    constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (50 downto 0) := "000000000001000000000000000000000000000000000000000";
    constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (50 downto 0) := "000000000010000000000000000000000000000000000000000";
    constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (50 downto 0) := "000000000100000000000000000000000000000000000000000";
    constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (50 downto 0) := "000000001000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (50 downto 0) := "000000010000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (50 downto 0) := "000000100000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (50 downto 0) := "000001000000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (50 downto 0) := "000010000000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (50 downto 0) := "000100000000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (50 downto 0) := "001000000000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (50 downto 0) := "010000000000000000000000000000000000000000000000000";
    constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (50 downto 0) := "100000000000000000000000000000000000000000000000000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
    constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
    constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
    constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
    constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
    constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
    constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
    constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
    constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
    constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
    constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
    constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
    constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
    constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
    constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
    constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
    constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
    constant ap_const_lv32_3F4CCCCD : STD_LOGIC_VECTOR (31 downto 0) := "00111111010011001100110011001101";
    constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
    constant ap_const_lv9_6 : STD_LOGIC_VECTOR (8 downto 0) := "000000110";
    constant ap_const_lv55_0 : STD_LOGIC_VECTOR (54 downto 0) := "0000000000000000000000000000000000000000000000000000000";
    constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
    constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
    constant ap_const_lv9_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
    constant ap_const_lv9_3 : STD_LOGIC_VECTOR (8 downto 0) := "000000011";
    constant ap_const_lv9_4 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
    constant ap_const_lv9_5 : STD_LOGIC_VECTOR (8 downto 0) := "000000101";
    constant ap_const_lv9_7 : STD_LOGIC_VECTOR (8 downto 0) := "000000111";
    constant ap_const_lv9_8 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
    constant ap_const_lv9_9 : STD_LOGIC_VECTOR (8 downto 0) := "000001001";
    constant ap_const_lv9_181 : STD_LOGIC_VECTOR (8 downto 0) := "110000001";
    constant ap_const_lv8_7F : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
    constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
    constant ap_const_lv33_1 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000000001";
    constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
    constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
    constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
    constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
    constant ap_const_boolean_1 : BOOLEAN := true;

    signal ap_CS_fsm : STD_LOGIC_VECTOR (50 downto 0) := "000000000000000000000000000000000000000000000000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal extMemPtr_V_blk_n_AR : STD_LOGIC;
    signal ap_CS_fsm_state24 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
    signal extMemPtr_V_blk_n_R : STD_LOGIC;
    signal ap_CS_fsm_state31 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
    signal ap_CS_fsm_state25 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
    signal ap_CS_fsm_state32 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
    signal extMemPtr_V_blk_n_AW : STD_LOGIC;
    signal ap_CS_fsm_state44 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state44 : signal is "none";
    signal extMemPtr_V_blk_n_W : STD_LOGIC;
    signal ap_CS_fsm_state45 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state45 : signal is "none";
    signal extMemPtr_V_blk_n_B : STD_LOGIC;
    signal ap_CS_fsm_state50 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state50 : signal is "none";
    signal ap_CS_fsm_state46 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state46 : signal is "none";
    signal ap_CS_fsm_state51 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state51 : signal is "none";
    signal or_ln62_reg_1108 : STD_LOGIC_VECTOR (0 downto 0);
    signal reg_401 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state3 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
    signal ap_CS_fsm_state5 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
    signal reg_406 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state6 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
    signal ap_CS_fsm_state9 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
    signal reg_411 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state7 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
    signal ap_CS_fsm_state10 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
    signal icmp_ln891_reg_1169 : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_fu_343_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal reg_416 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_state45_io : BOOLEAN;
    signal tmp_31_fu_420_p3 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_31_reg_1031 : STD_LOGIC_VECTOR (8 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal trunc_ln368_fu_457_p1 : STD_LOGIC_VECTOR (30 downto 0);
    signal trunc_ln368_reg_1053 : STD_LOGIC_VECTOR (30 downto 0);
    signal icmp_ln257_fu_475_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp_ln257_reg_1058 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp_ln257_6_fu_481_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp_ln257_6_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
    signal bitcast_ln348_fu_508_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal bitcast_ln348_reg_1073 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state4 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
    signal memAddr_reg_1084 : STD_LOGIC_VECTOR (31 downto 0);
    signal feedbackVolRatio_fu_537_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal feedbackVolRatio_reg_1092 : STD_LOGIC_VECTOR (31 downto 0);
    signal val_assign_s_fu_562_p4 : STD_LOGIC_VECTOR (30 downto 0);
    signal val_assign_s_reg_1103 : STD_LOGIC_VECTOR (30 downto 0);
    signal or_ln62_fu_584_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state8 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
    signal wrIndex_reg_1136 : STD_LOGIC_VECTOR (7 downto 0);
    signal rdIndex_reg_1141 : STD_LOGIC_VECTOR (7 downto 0);
    signal directVolRatio_fu_646_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal directVolRatio_reg_1146 : STD_LOGIC_VECTOR (31 downto 0);
    signal delayVolRatio_fu_650_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal delayVolRatio_reg_1152 : STD_LOGIC_VECTOR (31 downto 0);
    signal periodRatio_fu_666_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal periodRatio_reg_1158 : STD_LOGIC_VECTOR (31 downto 0);
    signal maxIndex_V_fu_670_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal maxIndex_V_reg_1163 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_391_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp_ln891_1_reg_1173 : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_fu_383_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_s_reg_1177 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state16 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
    signal tmp_V_reg_1182 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_CS_fsm_state20 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state20 : signal is "none";
    signal tmp_V_1_fu_687_p1 : STD_LOGIC_VECTOR (22 downto 0);
    signal tmp_V_1_reg_1188 : STD_LOGIC_VECTOR (22 downto 0);
    signal isNeg_fu_700_p3 : STD_LOGIC_VECTOR (0 downto 0);
    signal isNeg_reg_1193 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state21 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none";
    signal ush_fu_717_p3 : STD_LOGIC_VECTOR (8 downto 0);
    signal ush_reg_1198 : STD_LOGIC_VECTOR (8 downto 0);
    signal icmp_ln76_fu_821_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp_ln76_reg_1204 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state22 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
    signal extMemPtr_V_addr_reg_1208 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state23 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
    signal extMemPtr_V_addr_1_reg_1214 : STD_LOGIC_VECTOR (31 downto 0);
    signal select_ln82_fu_907_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal select_ln82_reg_1220 : STD_LOGIC_VECTOR (31 downto 0);
    signal auxRawL_V_reg_1225 : STD_LOGIC_VECTOR (31 downto 0);
    signal auxRawR_V_reg_1230 : STD_LOGIC_VECTOR (31 downto 0);
    signal auxL_fu_915_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state33 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
    signal auxR_fu_918_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal icmp_ln887_1_fu_929_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp_ln887_1_reg_1245 : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_fu_355_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_16_reg_1250 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state37 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
    signal grp_fu_360_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_17_reg_1255 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_365_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_18_reg_1260 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_369_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_19_reg_1265 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_374_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_20_reg_1270 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_378_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_21_reg_1275 : STD_LOGIC_VECTOR (31 downto 0);
    signal extMemPtr_V_addr_2_reg_1280 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state43 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state43 : signal is "none";
    signal extMemPtr_V_addr_3_reg_1286 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_347_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal dst_l_reg_1292 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_351_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal dst_r_reg_1297 : STD_LOGIC_VECTOR (31 downto 0);
    signal i_op_assign_2_reg_279 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state11 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
    signal i_op_assign_3_reg_290 : STD_LOGIC_VECTOR (31 downto 0);
    signal auxL_0_reg_301 : STD_LOGIC_VECTOR (31 downto 0);
    signal auxR_0_reg_313 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4 : STD_LOGIC_VECTOR (31 downto 0);
    signal agg_result_l_write_a_reg_325 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_state51 : BOOLEAN;
    signal ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4 : STD_LOGIC_VECTOR (31 downto 0);
    signal agg_result_r_write_a_reg_334 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_37_fu_434_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_32_fu_448_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_33_fu_492_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_34_fu_518_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_35_fu_549_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_36_fu_595_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_38_fu_609_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_39_fu_623_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_40_fu_637_p3 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln78_4_fu_855_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln79_1_fu_881_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln89_4_fu_973_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln90_1_fu_999_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal bitcast_ln705_fu_1009_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal bitcast_ln705_4_fu_1014_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state34 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
    signal select_ln91_fu_941_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_343_p0 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_343_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state38 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state38 : signal is "none";
    signal ap_CS_fsm_state39 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state39 : signal is "none";
    signal grp_fu_355_p0 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_fu_355_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state17 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
    signal grp_fu_386_p0 : STD_LOGIC_VECTOR (31 downto 0);
    signal or_ln52_fu_428_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal or_ln46_fu_443_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_23_fu_465_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal trunc_ln257_fu_461_p1 : STD_LOGIC_VECTOR (22 downto 0);
    signal or_ln48_fu_487_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal p_Result_s_fu_501_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal or_ln49_fu_513_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal or_ln257_fu_527_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal and_ln257_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_ln50_fu_544_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal trunc_ln302_fu_558_p1 : STD_LOGIC_VECTOR (0 downto 0);
    signal hasMemSizeError_fu_578_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal isNotRunning_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_ln51_fu_590_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal or_ln53_fu_604_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal or_ln55_fu_618_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal or_ln56_fu_632_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal trunc_ln368_3_fu_654_p1 : STD_LOGIC_VECTOR (30 downto 0);
    signal p_Result_8_fu_658_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal p_Val2_8_fu_673_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal zext_ln339_fu_691_p1 : STD_LOGIC_VECTOR (8 downto 0);
    signal add_ln339_fu_694_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal sub_ln1311_fu_708_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal sext_ln1311_fu_713_p1 : STD_LOGIC_VECTOR (8 downto 0);
    signal mantissa_V_fu_725_p4 : STD_LOGIC_VECTOR (24 downto 0);
    signal sext_ln1311_1_fu_738_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal sext_ln1311_2_fu_741_p1 : STD_LOGIC_VECTOR (24 downto 0);
    signal zext_ln682_fu_734_p1 : STD_LOGIC_VECTOR (78 downto 0);
    signal zext_ln1287_fu_744_p1 : STD_LOGIC_VECTOR (78 downto 0);
    signal r_V_fu_748_p2 : STD_LOGIC_VECTOR (24 downto 0);
    signal tmp_fu_760_p3 : STD_LOGIC_VECTOR (0 downto 0);
    signal r_V_1_fu_754_p2 : STD_LOGIC_VECTOR (78 downto 0);
    signal zext_ln662_fu_768_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_42_fu_772_p4 : STD_LOGIC_VECTOR (31 downto 0);
    signal sub_ln72_1_fu_795_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal icmp_ln72_fu_789_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal add_ln72_fu_801_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal sub_ln72_fu_807_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal currentPeriod_fu_813_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal val_V_fu_782_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal shl_ln_fu_837_p3 : STD_LOGIC_VECTOR (32 downto 0);
    signal zext_ln78_1_fu_830_p1 : STD_LOGIC_VECTOR (33 downto 0);
    signal zext_ln78_3_fu_845_p1 : STD_LOGIC_VECTOR (33 downto 0);
    signal add_ln78_fu_849_p2 : STD_LOGIC_VECTOR (33 downto 0);
    signal zext_ln78_fu_827_p1 : STD_LOGIC_VECTOR (32 downto 0);
    signal add_ln79_fu_865_p2 : STD_LOGIC_VECTOR (32 downto 0);
    signal zext_ln79_fu_871_p1 : STD_LOGIC_VECTOR (33 downto 0);
    signal add_ln79_1_fu_875_p2 : STD_LOGIC_VECTOR (33 downto 0);
    signal grp_fu_396_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal zext_ln78_2_fu_833_p1 : STD_LOGIC_VECTOR (32 downto 0);
    signal sext_ln1354_fu_891_p1 : STD_LOGIC_VECTOR (32 downto 0);
    signal icmp_ln887_fu_895_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal add_ln82_fu_901_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal zext_ln89_2_fu_921_p1 : STD_LOGIC_VECTOR (32 downto 0);
    signal sext_ln1354_1_fu_925_p1 : STD_LOGIC_VECTOR (32 downto 0);
    signal add_ln91_fu_935_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal shl_ln1_fu_955_p3 : STD_LOGIC_VECTOR (32 downto 0);
    signal zext_ln89_1_fu_952_p1 : STD_LOGIC_VECTOR (33 downto 0);
    signal zext_ln89_3_fu_963_p1 : STD_LOGIC_VECTOR (33 downto 0);
    signal add_ln89_fu_967_p2 : STD_LOGIC_VECTOR (33 downto 0);
    signal zext_ln89_fu_949_p1 : STD_LOGIC_VECTOR (32 downto 0);
    signal add_ln90_fu_983_p2 : STD_LOGIC_VECTOR (32 downto 0);
    signal zext_ln90_fu_989_p1 : STD_LOGIC_VECTOR (33 downto 0);
    signal add_ln90_1_fu_993_p2 : STD_LOGIC_VECTOR (33 downto 0);
    signal grp_fu_343_ce : STD_LOGIC;
    signal ap_CS_fsm_state40 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state40 : signal is "none";
    signal ap_CS_fsm_state41 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state41 : signal is "none";
    signal ap_CS_fsm_state42 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state42 : signal is "none";
    signal grp_fu_347_ce : STD_LOGIC;
    signal grp_fu_351_ce : STD_LOGIC;
    signal ap_return_0_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    signal ap_return_1_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    signal ap_NS_fsm : STD_LOGIC_VECTOR (50 downto 0);

    component pynq_dsp_hls_faddbkb IS
    generic (
        ID : INTEGER;
        NUM_STAGE : INTEGER;
        din0_WIDTH : INTEGER;
        din1_WIDTH : INTEGER;
        dout_WIDTH : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        din0 : IN STD_LOGIC_VECTOR (31 downto 0);
        din1 : IN STD_LOGIC_VECTOR (31 downto 0);
        ce : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
    end component;


    component pynq_dsp_hls_fmulcud IS
    generic (
        ID : INTEGER;
        NUM_STAGE : INTEGER;
        din0_WIDTH : INTEGER;
        din1_WIDTH : INTEGER;
        dout_WIDTH : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        din0 : IN STD_LOGIC_VECTOR (31 downto 0);
        din1 : IN STD_LOGIC_VECTOR (31 downto 0);
        ce : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
    end component;


    component pynq_dsp_hls_uitodEe IS
    generic (
        ID : INTEGER;
        NUM_STAGE : INTEGER;
        din0_WIDTH : INTEGER;
        dout_WIDTH : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        din0 : IN STD_LOGIC_VECTOR (31 downto 0);
        ce : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
    end component;


    component pynq_dsp_hls_fcmpeOg IS
    generic (
        ID : INTEGER;
        NUM_STAGE : INTEGER;
        din0_WIDTH : INTEGER;
        din1_WIDTH : INTEGER;
        dout_WIDTH : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        din0 : IN STD_LOGIC_VECTOR (31 downto 0);
        din1 : IN STD_LOGIC_VECTOR (31 downto 0);
        ce : IN STD_LOGIC;
        opcode : IN STD_LOGIC_VECTOR (4 downto 0);
        dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
    end component;



begin
    pynq_dsp_hls_faddbkb_U12 : component pynq_dsp_hls_faddbkb
    generic map (
        ID => 1,
        NUM_STAGE => 7,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => grp_fu_343_p0,
        din1 => grp_fu_343_p1,
        ce => grp_fu_343_ce,
        dout => grp_fu_343_p2);

    pynq_dsp_hls_faddbkb_U13 : component pynq_dsp_hls_faddbkb
    generic map (
        ID => 1,
        NUM_STAGE => 7,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => tmp_18_reg_1260,
        din1 => tmp_19_reg_1265,
        ce => grp_fu_347_ce,
        dout => grp_fu_347_p2);

    pynq_dsp_hls_faddbkb_U14 : component pynq_dsp_hls_faddbkb
    generic map (
        ID => 1,
        NUM_STAGE => 7,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => tmp_20_reg_1270,
        din1 => tmp_21_reg_1275,
        ce => grp_fu_351_ce,
        dout => grp_fu_351_p2);

    pynq_dsp_hls_fmulcud_U15 : component pynq_dsp_hls_fmulcud
    generic map (
        ID => 1,
        NUM_STAGE => 4,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => grp_fu_355_p0,
        din1 => grp_fu_355_p1,
        ce => ap_const_logic_1,
        dout => grp_fu_355_p2);

    pynq_dsp_hls_fmulcud_U16 : component pynq_dsp_hls_fmulcud
    generic map (
        ID => 1,
        NUM_STAGE => 4,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => auxR_0_reg_313,
        din1 => feedbackVolRatio_reg_1092,
        ce => ap_const_logic_1,
        dout => grp_fu_360_p2);

    pynq_dsp_hls_fmulcud_U17 : component pynq_dsp_hls_fmulcud
    generic map (
        ID => 1,
        NUM_STAGE => 4,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => directVolRatio_reg_1146,
        din1 => inData_l,
        ce => ap_const_logic_1,
        dout => grp_fu_365_p2);

    pynq_dsp_hls_fmulcud_U18 : component pynq_dsp_hls_fmulcud
    generic map (
        ID => 1,
        NUM_STAGE => 4,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => auxL_0_reg_301,
        din1 => delayVolRatio_reg_1152,
        ce => ap_const_logic_1,
        dout => grp_fu_369_p2);

    pynq_dsp_hls_fmulcud_U19 : component pynq_dsp_hls_fmulcud
    generic map (
        ID => 1,
        NUM_STAGE => 4,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => directVolRatio_reg_1146,
        din1 => inData_r,
        ce => ap_const_logic_1,
        dout => grp_fu_374_p2);

    pynq_dsp_hls_fmulcud_U20 : component pynq_dsp_hls_fmulcud
    generic map (
        ID => 1,
        NUM_STAGE => 4,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => auxR_0_reg_313,
        din1 => delayVolRatio_reg_1152,
        ce => ap_const_logic_1,
        dout => grp_fu_378_p2);

    pynq_dsp_hls_uitodEe_U21 : component pynq_dsp_hls_uitodEe
    generic map (
        ID => 1,
        NUM_STAGE => 6,
        din0_WIDTH => 32,
        dout_WIDTH => 32)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => reg_401,
        ce => ap_const_logic_1,
        dout => grp_fu_383_p1);

    pynq_dsp_hls_fcmpeOg_U22 : component pynq_dsp_hls_fcmpeOg
    generic map (
        ID => 1,
        NUM_STAGE => 2,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 1)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        din0 => grp_fu_386_p0,
        din1 => ap_const_lv32_3F4CCCCD,
        ce => ap_const_logic_1,
        opcode => ap_const_lv5_2,
        dout => grp_fu_386_p2);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_return_0_preg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_return_0_preg <= ap_const_lv32_0;
            else
                if ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51))) then 
                    ap_return_0_preg <= ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4;
                end if; 
            end if;
        end if;
    end process;


    ap_return_1_preg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_return_1_preg <= ap_const_lv32_0;
            else
                if ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51))) then 
                    ap_return_1_preg <= ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4;
                end if; 
            end if;
        end if;
    end process;


    agg_result_l_write_a_reg_325_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state11) and (or_ln62_reg_1108 = ap_const_lv1_1))) then 
                agg_result_l_write_a_reg_325 <= inData_l;
            elsif ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51) and (or_ln62_reg_1108 = ap_const_lv1_0))) then 
                agg_result_l_write_a_reg_325 <= dst_l_reg_1292;
            end if; 
        end if;
    end process;

    agg_result_r_write_a_reg_334_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state11) and (or_ln62_reg_1108 = ap_const_lv1_1))) then 
                agg_result_r_write_a_reg_334 <= inData_r;
            elsif ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51) and (or_ln62_reg_1108 = ap_const_lv1_0))) then 
                agg_result_r_write_a_reg_334 <= dst_r_reg_1297;
            end if; 
        end if;
    end process;

    auxL_0_reg_301_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_ln76_reg_1204 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
                auxL_0_reg_301 <= ap_const_lv32_0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state33) and (icmp_ln76_reg_1204 = ap_const_lv1_0))) then 
                auxL_0_reg_301 <= auxL_fu_915_p1;
            end if; 
        end if;
    end process;

    auxR_0_reg_313_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_ln76_reg_1204 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
                auxR_0_reg_313 <= ap_const_lv32_0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state33) and (icmp_ln76_reg_1204 = ap_const_lv1_0))) then 
                auxR_0_reg_313 <= auxR_fu_918_p1;
            end if; 
        end if;
    end process;

    i_op_assign_2_reg_279_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((grp_fu_391_p2 = ap_const_lv1_1) and (icmp_ln891_reg_1169 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state10) and (or_ln62_reg_1108 = ap_const_lv1_0))) then 
                i_op_assign_2_reg_279 <= config_r_q0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and ((or_ln62_reg_1108 = ap_const_lv1_1) or ((icmp_ln891_1_reg_1173 = ap_const_lv1_0) or (icmp_ln891_reg_1169 = ap_const_lv1_0))))) then 
                i_op_assign_2_reg_279 <= ap_const_lv32_0;
            end if; 
        end if;
    end process;

    i_op_assign_3_reg_290_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((grp_fu_391_p2 = ap_const_lv1_1) and (icmp_ln891_reg_1169 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state10) and (or_ln62_reg_1108 = ap_const_lv1_0))) then 
                i_op_assign_3_reg_290 <= reg_406;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and ((or_ln62_reg_1108 = ap_const_lv1_1) or ((icmp_ln891_1_reg_1173 = ap_const_lv1_0) or (icmp_ln891_reg_1169 = ap_const_lv1_0))))) then 
                i_op_assign_3_reg_290 <= ap_const_lv32_0;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state31) and (m_axi_extMemPtr_V_RVALID = ap_const_logic_1))) then
                auxRawL_V_reg_1225 <= m_axi_extMemPtr_V_RDATA;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state32) and (m_axi_extMemPtr_V_RVALID = ap_const_logic_1))) then
                auxRawR_V_reg_1230 <= m_axi_extMemPtr_V_RDATA;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
                    bitcast_ln348_reg_1073(30 downto 0) <= bitcast_ln348_fu_508_p1(30 downto 0);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
                delayVolRatio_reg_1152 <= delayVolRatio_fu_650_p1;
                directVolRatio_reg_1146 <= directVolRatio_fu_646_p1;
                    maxIndex_V_reg_1163(30 downto 0) <= maxIndex_V_fu_670_p1(30 downto 0);
                    periodRatio_reg_1158(30 downto 0) <= periodRatio_fu_666_p1(30 downto 0);
                    rdIndex_reg_1141(7 downto 4) <= tmp_40_fu_637_p3(8 - 1 downto 0)(7 downto 4);
                    wrIndex_reg_1136(7 downto 4) <= tmp_39_fu_623_p3(8 - 1 downto 0)(7 downto 4);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44))) then
                dst_l_reg_1292 <= grp_fu_347_p2;
                dst_r_reg_1297 <= grp_fu_351_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state23) and (icmp_ln76_reg_1204 = ap_const_lv1_0))) then
                extMemPtr_V_addr_1_reg_1214 <= zext_ln79_1_fu_881_p1(32 - 1 downto 0);
                extMemPtr_V_addr_reg_1208 <= zext_ln78_4_fu_855_p1(32 - 1 downto 0);
                select_ln82_reg_1220 <= select_ln82_fu_907_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state43)) then
                extMemPtr_V_addr_2_reg_1280 <= zext_ln89_4_fu_973_p1(32 - 1 downto 0);
                extMemPtr_V_addr_3_reg_1286 <= zext_ln90_1_fu_999_p1(32 - 1 downto 0);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
                    feedbackVolRatio_reg_1092(30 downto 0) <= feedbackVolRatio_fu_537_p3(30 downto 0);
                memAddr_reg_1084 <= config_r_q0;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
                icmp_ln257_6_reg_1063 <= icmp_ln257_6_fu_481_p2;
                icmp_ln257_reg_1058 <= icmp_ln257_fu_475_p2;
                trunc_ln368_reg_1053 <= trunc_ln368_fu_457_p1;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state22)) then
                icmp_ln76_reg_1204 <= icmp_ln76_fu_821_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
                icmp_ln887_1_reg_1245 <= icmp_ln887_1_fu_929_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_ln891_reg_1169 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state10) and (or_ln62_reg_1108 = ap_const_lv1_0))) then
                icmp_ln891_1_reg_1173 <= grp_fu_391_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
                icmp_ln891_reg_1169 <= grp_fu_391_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state21)) then
                isNeg_reg_1193 <= add_ln339_fu_694_p2(8 downto 8);
                ush_reg_1198 <= ush_fu_717_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
                or_ln62_reg_1108 <= or_ln62_fu_584_p2;
                val_assign_s_reg_1103 <= config_r_q0(31 downto 1);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state3))) then
                reg_401 <= config_r_q0;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state6))) then
                reg_406 <= config_r_q0;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state7) or ((icmp_ln891_reg_1169 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state10) and (or_ln62_reg_1108 = ap_const_lv1_0)))) then
                reg_411 <= config_r_q0;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((((ap_const_boolean_0 = ap_block_state45_io) and (ap_const_logic_1 = ap_CS_fsm_state45)) or ((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44)))) then
                reg_416 <= grp_fu_343_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state37)) then
                tmp_16_reg_1250 <= grp_fu_355_p2;
                tmp_17_reg_1255 <= grp_fu_360_p2;
                tmp_18_reg_1260 <= grp_fu_365_p2;
                tmp_19_reg_1265 <= grp_fu_369_p2;
                tmp_20_reg_1270 <= grp_fu_374_p2;
                tmp_21_reg_1275 <= grp_fu_378_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                    tmp_31_reg_1031(8 downto 4) <= tmp_31_fu_420_p3(8 downto 4);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state20)) then
                tmp_V_1_reg_1188 <= tmp_V_1_fu_687_p1;
                tmp_V_reg_1182 <= p_Val2_8_fu_673_p1(30 downto 23);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
                tmp_s_reg_1177 <= grp_fu_383_p1;
            end if;
        end if;
    end process;
    tmp_31_reg_1031(3 downto 0) <= "0000";
    bitcast_ln348_reg_1073(31) <= '0';
    feedbackVolRatio_reg_1092(31) <= '0';
    wrIndex_reg_1136(3 downto 0) <= "1000";
    rdIndex_reg_1141(3 downto 0) <= "1001";
    periodRatio_reg_1158(31) <= '0';
    maxIndex_V_reg_1163(31) <= '0';

    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, m_axi_extMemPtr_V_AWREADY, m_axi_extMemPtr_V_WREADY, m_axi_extMemPtr_V_ARREADY, m_axi_extMemPtr_V_RVALID, m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state24, ap_CS_fsm_state31, ap_CS_fsm_state25, ap_CS_fsm_state32, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_CS_fsm_state50, ap_CS_fsm_state46, ap_CS_fsm_state51, or_ln62_reg_1108, ap_block_state45_io, ap_CS_fsm_state8, icmp_ln76_reg_1204, ap_CS_fsm_state23, ap_CS_fsm_state11)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                ap_NS_fsm <= ap_ST_fsm_state3;
            when ap_ST_fsm_state3 => 
                ap_NS_fsm <= ap_ST_fsm_state4;
            when ap_ST_fsm_state4 => 
                ap_NS_fsm <= ap_ST_fsm_state5;
            when ap_ST_fsm_state5 => 
                ap_NS_fsm <= ap_ST_fsm_state6;
            when ap_ST_fsm_state6 => 
                ap_NS_fsm <= ap_ST_fsm_state7;
            when ap_ST_fsm_state7 => 
                ap_NS_fsm <= ap_ST_fsm_state8;
            when ap_ST_fsm_state8 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state8) and (or_ln62_reg_1108 = ap_const_lv1_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state10;
                else
                    ap_NS_fsm <= ap_ST_fsm_state9;
                end if;
            when ap_ST_fsm_state9 => 
                ap_NS_fsm <= ap_ST_fsm_state10;
            when ap_ST_fsm_state10 => 
                ap_NS_fsm <= ap_ST_fsm_state11;
            when ap_ST_fsm_state11 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state11) and (or_ln62_reg_1108 = ap_const_lv1_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state51;
                else
                    ap_NS_fsm <= ap_ST_fsm_state12;
                end if;
            when ap_ST_fsm_state12 => 
                ap_NS_fsm <= ap_ST_fsm_state13;
            when ap_ST_fsm_state13 => 
                ap_NS_fsm <= ap_ST_fsm_state14;
            when ap_ST_fsm_state14 => 
                ap_NS_fsm <= ap_ST_fsm_state15;
            when ap_ST_fsm_state15 => 
                ap_NS_fsm <= ap_ST_fsm_state16;
            when ap_ST_fsm_state16 => 
                ap_NS_fsm <= ap_ST_fsm_state17;
            when ap_ST_fsm_state17 => 
                ap_NS_fsm <= ap_ST_fsm_state18;
            when ap_ST_fsm_state18 => 
                ap_NS_fsm <= ap_ST_fsm_state19;
            when ap_ST_fsm_state19 => 
                ap_NS_fsm <= ap_ST_fsm_state20;
            when ap_ST_fsm_state20 => 
                ap_NS_fsm <= ap_ST_fsm_state21;
            when ap_ST_fsm_state21 => 
                ap_NS_fsm <= ap_ST_fsm_state22;
            when ap_ST_fsm_state22 => 
                ap_NS_fsm <= ap_ST_fsm_state23;
            when ap_ST_fsm_state23 => 
                if (((icmp_ln76_reg_1204 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
                    ap_NS_fsm <= ap_ST_fsm_state33;
                else
                    ap_NS_fsm <= ap_ST_fsm_state24;
                end if;
            when ap_ST_fsm_state24 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state24) and (m_axi_extMemPtr_V_ARREADY = ap_const_logic_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state25;
                else
                    ap_NS_fsm <= ap_ST_fsm_state24;
                end if;
            when ap_ST_fsm_state25 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state25) and (m_axi_extMemPtr_V_ARREADY = ap_const_logic_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state26;
                else
                    ap_NS_fsm <= ap_ST_fsm_state25;
                end if;
            when ap_ST_fsm_state26 => 
                ap_NS_fsm <= ap_ST_fsm_state27;
            when ap_ST_fsm_state27 => 
                ap_NS_fsm <= ap_ST_fsm_state28;
            when ap_ST_fsm_state28 => 
                ap_NS_fsm <= ap_ST_fsm_state29;
            when ap_ST_fsm_state29 => 
                ap_NS_fsm <= ap_ST_fsm_state30;
            when ap_ST_fsm_state30 => 
                ap_NS_fsm <= ap_ST_fsm_state31;
            when ap_ST_fsm_state31 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state31) and (m_axi_extMemPtr_V_RVALID = ap_const_logic_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state32;
                else
                    ap_NS_fsm <= ap_ST_fsm_state31;
                end if;
            when ap_ST_fsm_state32 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state32) and (m_axi_extMemPtr_V_RVALID = ap_const_logic_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state33;
                else
                    ap_NS_fsm <= ap_ST_fsm_state32;
                end if;
            when ap_ST_fsm_state33 => 
                ap_NS_fsm <= ap_ST_fsm_state34;
            when ap_ST_fsm_state34 => 
                ap_NS_fsm <= ap_ST_fsm_state35;
            when ap_ST_fsm_state35 => 
                ap_NS_fsm <= ap_ST_fsm_state36;
            when ap_ST_fsm_state36 => 
                ap_NS_fsm <= ap_ST_fsm_state37;
            when ap_ST_fsm_state37 => 
                ap_NS_fsm <= ap_ST_fsm_state38;
            when ap_ST_fsm_state38 => 
                ap_NS_fsm <= ap_ST_fsm_state39;
            when ap_ST_fsm_state39 => 
                ap_NS_fsm <= ap_ST_fsm_state40;
            when ap_ST_fsm_state40 => 
                ap_NS_fsm <= ap_ST_fsm_state41;
            when ap_ST_fsm_state41 => 
                ap_NS_fsm <= ap_ST_fsm_state42;
            when ap_ST_fsm_state42 => 
                ap_NS_fsm <= ap_ST_fsm_state43;
            when ap_ST_fsm_state43 => 
                ap_NS_fsm <= ap_ST_fsm_state44;
            when ap_ST_fsm_state44 => 
                if (((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44))) then
                    ap_NS_fsm <= ap_ST_fsm_state45;
                else
                    ap_NS_fsm <= ap_ST_fsm_state44;
                end if;
            when ap_ST_fsm_state45 => 
                if (((ap_const_boolean_0 = ap_block_state45_io) and (ap_const_logic_1 = ap_CS_fsm_state45))) then
                    ap_NS_fsm <= ap_ST_fsm_state46;
                else
                    ap_NS_fsm <= ap_ST_fsm_state45;
                end if;
            when ap_ST_fsm_state46 => 
                if (((m_axi_extMemPtr_V_WREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state46))) then
                    ap_NS_fsm <= ap_ST_fsm_state47;
                else
                    ap_NS_fsm <= ap_ST_fsm_state46;
                end if;
            when ap_ST_fsm_state47 => 
                ap_NS_fsm <= ap_ST_fsm_state48;
            when ap_ST_fsm_state48 => 
                ap_NS_fsm <= ap_ST_fsm_state49;
            when ap_ST_fsm_state49 => 
                ap_NS_fsm <= ap_ST_fsm_state50;
            when ap_ST_fsm_state50 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state50) and (m_axi_extMemPtr_V_BVALID = ap_const_logic_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state51;
                else
                    ap_NS_fsm <= ap_ST_fsm_state50;
                end if;
            when ap_ST_fsm_state51 => 
                if ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_state51;
                end if;
            when others =>  
                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end case;
    end process;
    add_ln339_fu_694_p2 <= std_logic_vector(signed(ap_const_lv9_181) + signed(zext_ln339_fu_691_p1));
    add_ln72_fu_801_p2 <= std_logic_vector(unsigned(i_op_assign_2_reg_279) + unsigned(sub_ln72_1_fu_795_p2));
    add_ln78_fu_849_p2 <= std_logic_vector(unsigned(zext_ln78_1_fu_830_p1) + unsigned(zext_ln78_3_fu_845_p1));
    add_ln79_1_fu_875_p2 <= std_logic_vector(unsigned(zext_ln78_3_fu_845_p1) + unsigned(zext_ln79_fu_871_p1));
    add_ln79_fu_865_p2 <= std_logic_vector(unsigned(zext_ln78_fu_827_p1) + unsigned(ap_const_lv33_1));
    add_ln82_fu_901_p2 <= std_logic_vector(unsigned(i_op_assign_2_reg_279) + unsigned(ap_const_lv32_1));
    add_ln89_fu_967_p2 <= std_logic_vector(unsigned(zext_ln89_1_fu_952_p1) + unsigned(zext_ln89_3_fu_963_p1));
    add_ln90_1_fu_993_p2 <= std_logic_vector(unsigned(zext_ln89_3_fu_963_p1) + unsigned(zext_ln90_fu_989_p1));
    add_ln90_fu_983_p2 <= std_logic_vector(unsigned(zext_ln89_fu_949_p1) + unsigned(ap_const_lv33_1));
    add_ln91_fu_935_p2 <= std_logic_vector(unsigned(i_op_assign_3_reg_290) + unsigned(ap_const_lv32_1));
    and_ln257_fu_531_p2 <= (or_ln257_fu_527_p2 and grp_fu_386_p2);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state10 <= ap_CS_fsm(9);
    ap_CS_fsm_state11 <= ap_CS_fsm(10);
    ap_CS_fsm_state16 <= ap_CS_fsm(15);
    ap_CS_fsm_state17 <= ap_CS_fsm(16);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state20 <= ap_CS_fsm(19);
    ap_CS_fsm_state21 <= ap_CS_fsm(20);
    ap_CS_fsm_state22 <= ap_CS_fsm(21);
    ap_CS_fsm_state23 <= ap_CS_fsm(22);
    ap_CS_fsm_state24 <= ap_CS_fsm(23);
    ap_CS_fsm_state25 <= ap_CS_fsm(24);
    ap_CS_fsm_state3 <= ap_CS_fsm(2);
    ap_CS_fsm_state31 <= ap_CS_fsm(30);
    ap_CS_fsm_state32 <= ap_CS_fsm(31);
    ap_CS_fsm_state33 <= ap_CS_fsm(32);
    ap_CS_fsm_state34 <= ap_CS_fsm(33);
    ap_CS_fsm_state37 <= ap_CS_fsm(36);
    ap_CS_fsm_state38 <= ap_CS_fsm(37);
    ap_CS_fsm_state39 <= ap_CS_fsm(38);
    ap_CS_fsm_state4 <= ap_CS_fsm(3);
    ap_CS_fsm_state40 <= ap_CS_fsm(39);
    ap_CS_fsm_state41 <= ap_CS_fsm(40);
    ap_CS_fsm_state42 <= ap_CS_fsm(41);
    ap_CS_fsm_state43 <= ap_CS_fsm(42);
    ap_CS_fsm_state44 <= ap_CS_fsm(43);
    ap_CS_fsm_state45 <= ap_CS_fsm(44);
    ap_CS_fsm_state46 <= ap_CS_fsm(45);
    ap_CS_fsm_state5 <= ap_CS_fsm(4);
    ap_CS_fsm_state50 <= ap_CS_fsm(49);
    ap_CS_fsm_state51 <= ap_CS_fsm(50);
    ap_CS_fsm_state6 <= ap_CS_fsm(5);
    ap_CS_fsm_state7 <= ap_CS_fsm(6);
    ap_CS_fsm_state8 <= ap_CS_fsm(7);
    ap_CS_fsm_state9 <= ap_CS_fsm(8);

    ap_block_state45_io_assign_proc : process(m_axi_extMemPtr_V_AWREADY, m_axi_extMemPtr_V_WREADY)
    begin
                ap_block_state45_io <= ((m_axi_extMemPtr_V_WREADY = ap_const_logic_0) or (m_axi_extMemPtr_V_AWREADY = ap_const_logic_0));
    end process;


    ap_block_state51_assign_proc : process(m_axi_extMemPtr_V_BVALID, or_ln62_reg_1108)
    begin
                ap_block_state51 <= ((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0));
    end process;


    ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state51, or_ln62_reg_1108)
    begin
        if ((((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1)) or (not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51)))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4_assign_proc : process(ap_CS_fsm_state51, or_ln62_reg_1108, dst_l_reg_1292, agg_result_l_write_a_reg_325)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state51) and (or_ln62_reg_1108 = ap_const_lv1_0))) then 
            ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4 <= dst_l_reg_1292;
        else 
            ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4 <= agg_result_l_write_a_reg_325;
        end if; 
    end process;


    ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4_assign_proc : process(ap_CS_fsm_state51, or_ln62_reg_1108, dst_r_reg_1297, agg_result_r_write_a_reg_334)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state51) and (or_ln62_reg_1108 = ap_const_lv1_0))) then 
            ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4 <= dst_r_reg_1297;
        else 
            ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4 <= agg_result_r_write_a_reg_334;
        end if; 
    end process;


    ap_ready_assign_proc : process(m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state51, or_ln62_reg_1108)
    begin
        if ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;


    ap_return_0_assign_proc : process(m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state51, or_ln62_reg_1108, ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4, ap_return_0_preg)
    begin
        if ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51))) then 
            ap_return_0 <= ap_phi_mux_agg_result_l_write_a_phi_fu_328_p4;
        else 
            ap_return_0 <= ap_return_0_preg;
        end if; 
    end process;


    ap_return_1_assign_proc : process(m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state51, or_ln62_reg_1108, ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4, ap_return_1_preg)
    begin
        if ((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51))) then 
            ap_return_1 <= ap_phi_mux_agg_result_r_write_a_phi_fu_337_p4;
        else 
            ap_return_1 <= ap_return_1_preg;
        end if; 
    end process;

    auxL_fu_915_p1 <= auxRawL_V_reg_1225;
    auxR_fu_918_p1 <= auxRawR_V_reg_1230;
    bitcast_ln348_fu_508_p1 <= p_Result_s_fu_501_p3;
    bitcast_ln705_4_fu_1014_p1 <= reg_416;
    bitcast_ln705_fu_1009_p1 <= reg_416;

    config_r_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state24, ap_CS_fsm_state3, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state9, ap_CS_fsm_state7, ap_CS_fsm_state10, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state8, wrIndex_reg_1136, rdIndex_reg_1141, ap_CS_fsm_state11, tmp_37_fu_434_p3, tmp_32_fu_448_p3, tmp_33_fu_492_p3, tmp_34_fu_518_p3, tmp_35_fu_549_p3, tmp_36_fu_595_p3, tmp_38_fu_609_p3, tmp_39_fu_623_p3, ap_CS_fsm_state34)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state34) or (ap_const_logic_1 = ap_CS_fsm_state10))) then 
            config_r_address0 <= wrIndex_reg_1136;
        elsif (((ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state24))) then 
            config_r_address0 <= rdIndex_reg_1141;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
            config_r_address0 <= tmp_39_fu_623_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
            config_r_address0 <= tmp_38_fu_609_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then 
            config_r_address0 <= tmp_36_fu_595_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then 
            config_r_address0 <= tmp_35_fu_549_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
            config_r_address0 <= tmp_34_fu_518_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
            config_r_address0 <= tmp_33_fu_492_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
            config_r_address0 <= tmp_32_fu_448_p3(8 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then 
            config_r_address0 <= tmp_37_fu_434_p3(8 - 1 downto 0);
        else 
            config_r_address0 <= "XXXXXXXX";
        end if; 
    end process;


    config_r_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, m_axi_extMemPtr_V_ARREADY, ap_CS_fsm_state24, ap_CS_fsm_state3, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state9, ap_CS_fsm_state7, ap_CS_fsm_state10, ap_CS_fsm_state2, ap_CS_fsm_state4, ap_CS_fsm_state8, ap_CS_fsm_state11, ap_CS_fsm_state34)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state34) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state2) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1)) or ((ap_const_logic_1 = ap_CS_fsm_state24) and (m_axi_extMemPtr_V_ARREADY = ap_const_logic_1)))) then 
            config_r_ce0 <= ap_const_logic_1;
        else 
            config_r_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    config_r_d0_assign_proc : process(ap_CS_fsm_state24, ap_CS_fsm_state10, select_ln82_reg_1220, ap_CS_fsm_state11, ap_CS_fsm_state34, select_ln91_fu_941_p3)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
            config_r_d0 <= select_ln91_fu_941_p3;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
            config_r_d0 <= select_ln82_reg_1220;
        elsif (((ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state10))) then 
            config_r_d0 <= ap_const_lv32_0;
        else 
            config_r_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    config_r_we0_assign_proc : process(m_axi_extMemPtr_V_ARREADY, ap_CS_fsm_state24, or_ln62_reg_1108, ap_CS_fsm_state10, icmp_ln891_reg_1169, grp_fu_391_p2, icmp_ln891_1_reg_1173, ap_CS_fsm_state11, ap_CS_fsm_state34)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state34) or ((ap_const_logic_1 = ap_CS_fsm_state11) and ((or_ln62_reg_1108 = ap_const_lv1_1) or ((icmp_ln891_1_reg_1173 = ap_const_lv1_0) or (icmp_ln891_reg_1169 = ap_const_lv1_0)))) or ((ap_const_logic_1 = ap_CS_fsm_state10) and ((or_ln62_reg_1108 = ap_const_lv1_1) or ((grp_fu_391_p2 = ap_const_lv1_0) or (icmp_ln891_reg_1169 = ap_const_lv1_0)))) or ((ap_const_logic_1 = ap_CS_fsm_state24) and (m_axi_extMemPtr_V_ARREADY = ap_const_logic_1)))) then 
            config_r_we0 <= ap_const_logic_1;
        else 
            config_r_we0 <= ap_const_logic_0;
        end if; 
    end process;

    currentPeriod_fu_813_p3 <= 
        add_ln72_fu_801_p2 when (icmp_ln72_fu_789_p2(0) = '1') else 
        sub_ln72_fu_807_p2;
    delayVolRatio_fu_650_p1 <= reg_411;
    directVolRatio_fu_646_p1 <= reg_406;

    extMemPtr_V_blk_n_AR_assign_proc : process(m_axi_extMemPtr_V_ARREADY, ap_CS_fsm_state24, ap_CS_fsm_state25)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state24))) then 
            extMemPtr_V_blk_n_AR <= m_axi_extMemPtr_V_ARREADY;
        else 
            extMemPtr_V_blk_n_AR <= ap_const_logic_1;
        end if; 
    end process;


    extMemPtr_V_blk_n_AW_assign_proc : process(m_axi_extMemPtr_V_AWREADY, ap_CS_fsm_state44, ap_CS_fsm_state45)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state45) or (ap_const_logic_1 = ap_CS_fsm_state44))) then 
            extMemPtr_V_blk_n_AW <= m_axi_extMemPtr_V_AWREADY;
        else 
            extMemPtr_V_blk_n_AW <= ap_const_logic_1;
        end if; 
    end process;


    extMemPtr_V_blk_n_B_assign_proc : process(m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state50, ap_CS_fsm_state51, or_ln62_reg_1108)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state50) or ((ap_const_logic_1 = ap_CS_fsm_state51) and (or_ln62_reg_1108 = ap_const_lv1_0)))) then 
            extMemPtr_V_blk_n_B <= m_axi_extMemPtr_V_BVALID;
        else 
            extMemPtr_V_blk_n_B <= ap_const_logic_1;
        end if; 
    end process;


    extMemPtr_V_blk_n_R_assign_proc : process(m_axi_extMemPtr_V_RVALID, ap_CS_fsm_state31, ap_CS_fsm_state32)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state31))) then 
            extMemPtr_V_blk_n_R <= m_axi_extMemPtr_V_RVALID;
        else 
            extMemPtr_V_blk_n_R <= ap_const_logic_1;
        end if; 
    end process;


    extMemPtr_V_blk_n_W_assign_proc : process(m_axi_extMemPtr_V_WREADY, ap_CS_fsm_state45, ap_CS_fsm_state46)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state45))) then 
            extMemPtr_V_blk_n_W <= m_axi_extMemPtr_V_WREADY;
        else 
            extMemPtr_V_blk_n_W <= ap_const_logic_1;
        end if; 
    end process;

    feedbackVolRatio_fu_537_p3 <= 
        ap_const_lv32_3F4CCCCD when (and_ln257_fu_531_p2(0) = '1') else 
        bitcast_ln348_reg_1073;

    grp_fu_343_ce_assign_proc : process(m_axi_extMemPtr_V_AWREADY, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_block_state45_io, ap_CS_fsm_state43, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state40) or (ap_const_logic_1 = ap_CS_fsm_state39) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state43) or ((ap_const_boolean_0 = ap_block_state45_io) and (ap_const_logic_1 = ap_CS_fsm_state45)) or ((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44)))) then 
            grp_fu_343_ce <= ap_const_logic_1;
        else 
            grp_fu_343_ce <= ap_const_logic_0;
        end if; 
    end process;


    grp_fu_343_p0_assign_proc : process(tmp_16_reg_1250, tmp_17_reg_1255, ap_CS_fsm_state38, ap_CS_fsm_state39)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state39)) then 
            grp_fu_343_p0 <= tmp_17_reg_1255;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state38)) then 
            grp_fu_343_p0 <= tmp_16_reg_1250;
        else 
            grp_fu_343_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    grp_fu_343_p1_assign_proc : process(inData_l, inData_r, ap_CS_fsm_state38, ap_CS_fsm_state39)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state39)) then 
            grp_fu_343_p1 <= inData_r;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state38)) then 
            grp_fu_343_p1 <= inData_l;
        else 
            grp_fu_343_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    grp_fu_347_ce_assign_proc : process(m_axi_extMemPtr_V_AWREADY, ap_CS_fsm_state44, ap_CS_fsm_state43, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state40) or (ap_const_logic_1 = ap_CS_fsm_state39) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state43) or ((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44)))) then 
            grp_fu_347_ce <= ap_const_logic_1;
        else 
            grp_fu_347_ce <= ap_const_logic_0;
        end if; 
    end process;


    grp_fu_351_ce_assign_proc : process(m_axi_extMemPtr_V_AWREADY, ap_CS_fsm_state44, ap_CS_fsm_state43, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state40) or (ap_const_logic_1 = ap_CS_fsm_state39) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state43) or ((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44)))) then 
            grp_fu_351_ce <= ap_const_logic_1;
        else 
            grp_fu_351_ce <= ap_const_logic_0;
        end if; 
    end process;


    grp_fu_355_p0_assign_proc : process(tmp_s_reg_1177, auxL_0_reg_301, ap_CS_fsm_state34, ap_CS_fsm_state17)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
            grp_fu_355_p0 <= auxL_0_reg_301;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then 
            grp_fu_355_p0 <= tmp_s_reg_1177;
        else 
            grp_fu_355_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    grp_fu_355_p1_assign_proc : process(feedbackVolRatio_reg_1092, periodRatio_reg_1158, ap_CS_fsm_state34, ap_CS_fsm_state17)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
            grp_fu_355_p1 <= feedbackVolRatio_reg_1092;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then 
            grp_fu_355_p1 <= periodRatio_reg_1158;
        else 
            grp_fu_355_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;

    grp_fu_386_p0 <= p_Result_s_fu_501_p3;
    grp_fu_391_p2 <= "1" when (unsigned(config_r_q0) < unsigned(maxIndex_V_reg_1163)) else "0";
    grp_fu_396_p2 <= std_logic_vector(unsigned(maxIndex_V_reg_1163) + unsigned(ap_const_lv32_FFFFFFFE));
    hasMemSizeError_fu_578_p2 <= "1" when (val_assign_s_fu_562_p4 = ap_const_lv31_0) else "0";
    icmp_ln257_6_fu_481_p2 <= "1" when (trunc_ln257_fu_461_p1 = ap_const_lv23_0) else "0";
    icmp_ln257_fu_475_p2 <= "0" when (tmp_23_fu_465_p4 = ap_const_lv8_FF) else "1";
    icmp_ln72_fu_789_p2 <= "1" when (unsigned(i_op_assign_3_reg_290) < unsigned(i_op_assign_2_reg_279)) else "0";
    icmp_ln76_fu_821_p2 <= "1" when (unsigned(currentPeriod_fu_813_p3) < unsigned(val_V_fu_782_p3)) else "0";
    icmp_ln887_1_fu_929_p2 <= "1" when (signed(zext_ln89_2_fu_921_p1) < signed(sext_ln1354_1_fu_925_p1)) else "0";
    icmp_ln887_fu_895_p2 <= "1" when (signed(zext_ln78_2_fu_833_p1) < signed(sext_ln1354_fu_891_p1)) else "0";
    isNeg_fu_700_p3 <= add_ln339_fu_694_p2(8 downto 8);
    isNotRunning_fu_572_p2 <= (trunc_ln302_fu_558_p1 xor ap_const_lv1_1);

    m_axi_extMemPtr_V_ARADDR_assign_proc : process(m_axi_extMemPtr_V_ARREADY, ap_CS_fsm_state24, ap_CS_fsm_state25, extMemPtr_V_addr_reg_1208, extMemPtr_V_addr_1_reg_1214)
    begin
        if ((m_axi_extMemPtr_V_ARREADY = ap_const_logic_1)) then
            if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
                m_axi_extMemPtr_V_ARADDR <= extMemPtr_V_addr_1_reg_1214;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
                m_axi_extMemPtr_V_ARADDR <= extMemPtr_V_addr_reg_1208;
            else 
                m_axi_extMemPtr_V_ARADDR <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
            end if;
        else 
            m_axi_extMemPtr_V_ARADDR <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;

    m_axi_extMemPtr_V_ARBURST <= ap_const_lv2_0;
    m_axi_extMemPtr_V_ARCACHE <= ap_const_lv4_0;
    m_axi_extMemPtr_V_ARID <= ap_const_lv1_0;
    m_axi_extMemPtr_V_ARLEN <= ap_const_lv32_1;
    m_axi_extMemPtr_V_ARLOCK <= ap_const_lv2_0;
    m_axi_extMemPtr_V_ARPROT <= ap_const_lv3_0;
    m_axi_extMemPtr_V_ARQOS <= ap_const_lv4_0;
    m_axi_extMemPtr_V_ARREGION <= ap_const_lv4_0;
    m_axi_extMemPtr_V_ARSIZE <= ap_const_lv3_0;
    m_axi_extMemPtr_V_ARUSER <= ap_const_lv1_0;

    m_axi_extMemPtr_V_ARVALID_assign_proc : process(m_axi_extMemPtr_V_ARREADY, ap_CS_fsm_state24, ap_CS_fsm_state25)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state25) and (m_axi_extMemPtr_V_ARREADY = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state24) and (m_axi_extMemPtr_V_ARREADY = ap_const_logic_1)))) then 
            m_axi_extMemPtr_V_ARVALID <= ap_const_logic_1;
        else 
            m_axi_extMemPtr_V_ARVALID <= ap_const_logic_0;
        end if; 
    end process;


    m_axi_extMemPtr_V_AWADDR_assign_proc : process(m_axi_extMemPtr_V_AWREADY, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_block_state45_io, extMemPtr_V_addr_2_reg_1280, extMemPtr_V_addr_3_reg_1286)
    begin
        if (((ap_const_boolean_0 = ap_block_state45_io) and (ap_const_logic_1 = ap_CS_fsm_state45))) then 
            m_axi_extMemPtr_V_AWADDR <= extMemPtr_V_addr_3_reg_1286;
        elsif (((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44))) then 
            m_axi_extMemPtr_V_AWADDR <= extMemPtr_V_addr_2_reg_1280;
        else 
            m_axi_extMemPtr_V_AWADDR <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;

    m_axi_extMemPtr_V_AWBURST <= ap_const_lv2_0;
    m_axi_extMemPtr_V_AWCACHE <= ap_const_lv4_0;
    m_axi_extMemPtr_V_AWID <= ap_const_lv1_0;
    m_axi_extMemPtr_V_AWLEN <= ap_const_lv32_1;
    m_axi_extMemPtr_V_AWLOCK <= ap_const_lv2_0;
    m_axi_extMemPtr_V_AWPROT <= ap_const_lv3_0;
    m_axi_extMemPtr_V_AWQOS <= ap_const_lv4_0;
    m_axi_extMemPtr_V_AWREGION <= ap_const_lv4_0;
    m_axi_extMemPtr_V_AWSIZE <= ap_const_lv3_0;
    m_axi_extMemPtr_V_AWUSER <= ap_const_lv1_0;

    m_axi_extMemPtr_V_AWVALID_assign_proc : process(m_axi_extMemPtr_V_AWREADY, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_block_state45_io)
    begin
        if ((((ap_const_boolean_0 = ap_block_state45_io) and (ap_const_logic_1 = ap_CS_fsm_state45)) or ((m_axi_extMemPtr_V_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state44)))) then 
            m_axi_extMemPtr_V_AWVALID <= ap_const_logic_1;
        else 
            m_axi_extMemPtr_V_AWVALID <= ap_const_logic_0;
        end if; 
    end process;


    m_axi_extMemPtr_V_BREADY_assign_proc : process(m_axi_extMemPtr_V_BVALID, ap_CS_fsm_state50, ap_CS_fsm_state51, or_ln62_reg_1108)
    begin
        if (((not(((m_axi_extMemPtr_V_BVALID = ap_const_logic_0) and (or_ln62_reg_1108 = ap_const_lv1_0))) and (ap_const_logic_1 = ap_CS_fsm_state51) and (or_ln62_reg_1108 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state50) and (m_axi_extMemPtr_V_BVALID = ap_const_logic_1)))) then 
            m_axi_extMemPtr_V_BREADY <= ap_const_logic_1;
        else 
            m_axi_extMemPtr_V_BREADY <= ap_const_logic_0;
        end if; 
    end process;


    m_axi_extMemPtr_V_RREADY_assign_proc : process(m_axi_extMemPtr_V_RVALID, ap_CS_fsm_state31, ap_CS_fsm_state32)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state32) and (m_axi_extMemPtr_V_RVALID = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state31) and (m_axi_extMemPtr_V_RVALID = ap_const_logic_1)))) then 
            m_axi_extMemPtr_V_RREADY <= ap_const_logic_1;
        else 
            m_axi_extMemPtr_V_RREADY <= ap_const_logic_0;
        end if; 
    end process;


    m_axi_extMemPtr_V_WDATA_assign_proc : process(ap_CS_fsm_state45, ap_CS_fsm_state46, bitcast_ln705_fu_1009_p1, bitcast_ln705_4_fu_1014_p1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state46)) then 
            m_axi_extMemPtr_V_WDATA <= bitcast_ln705_4_fu_1014_p1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state45)) then 
            m_axi_extMemPtr_V_WDATA <= bitcast_ln705_fu_1009_p1;
        else 
            m_axi_extMemPtr_V_WDATA <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;

    m_axi_extMemPtr_V_WID <= ap_const_lv1_0;
    m_axi_extMemPtr_V_WLAST <= ap_const_logic_0;
    m_axi_extMemPtr_V_WSTRB <= ap_const_lv4_F;
    m_axi_extMemPtr_V_WUSER <= ap_const_lv1_0;

    m_axi_extMemPtr_V_WVALID_assign_proc : process(m_axi_extMemPtr_V_WREADY, ap_CS_fsm_state45, ap_CS_fsm_state46, ap_block_state45_io)
    begin
        if ((((m_axi_extMemPtr_V_WREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state46)) or ((ap_const_boolean_0 = ap_block_state45_io) and (ap_const_logic_1 = ap_CS_fsm_state45)))) then 
            m_axi_extMemPtr_V_WVALID <= ap_const_logic_1;
        else 
            m_axi_extMemPtr_V_WVALID <= ap_const_logic_0;
        end if; 
    end process;

    mantissa_V_fu_725_p4 <= ((ap_const_lv1_1 & tmp_V_1_reg_1188) & ap_const_lv1_0);
    maxIndex_V_fu_670_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(val_assign_s_reg_1103),32));
    or_ln257_fu_527_p2 <= (icmp_ln257_reg_1058 or icmp_ln257_6_reg_1063);
    or_ln46_fu_443_p2 <= (tmp_31_reg_1031 or ap_const_lv9_1);
    or_ln48_fu_487_p2 <= (tmp_31_reg_1031 or ap_const_lv9_2);
    or_ln49_fu_513_p2 <= (tmp_31_reg_1031 or ap_const_lv9_3);
    or_ln50_fu_544_p2 <= (tmp_31_reg_1031 or ap_const_lv9_4);
    or_ln51_fu_590_p2 <= (tmp_31_reg_1031 or ap_const_lv9_5);
    or_ln52_fu_428_p2 <= (tmp_31_fu_420_p3 or ap_const_lv9_6);
    or_ln53_fu_604_p2 <= (tmp_31_reg_1031 or ap_const_lv9_7);
    or_ln55_fu_618_p2 <= (tmp_31_reg_1031 or ap_const_lv9_8);
    or_ln56_fu_632_p2 <= (tmp_31_reg_1031 or ap_const_lv9_9);
    or_ln62_fu_584_p2 <= (isNotRunning_fu_572_p2 or hasMemSizeError_fu_578_p2);
    p_Result_8_fu_658_p3 <= (ap_const_lv1_0 & trunc_ln368_3_fu_654_p1);
    p_Result_s_fu_501_p3 <= (ap_const_lv1_0 & trunc_ln368_reg_1053);
    p_Val2_8_fu_673_p1 <= grp_fu_355_p2;
    periodRatio_fu_666_p1 <= p_Result_8_fu_658_p3;
    r_V_1_fu_754_p2 <= std_logic_vector(shift_left(unsigned(zext_ln682_fu_734_p1),to_integer(unsigned('0' & zext_ln1287_fu_744_p1(31-1 downto 0)))));
    r_V_fu_748_p2 <= std_logic_vector(shift_right(unsigned(mantissa_V_fu_725_p4),to_integer(unsigned('0' & sext_ln1311_2_fu_741_p1(25-1 downto 0)))));
    select_ln82_fu_907_p3 <= 
        add_ln82_fu_901_p2 when (icmp_ln887_fu_895_p2(0) = '1') else 
        ap_const_lv32_0;
    select_ln91_fu_941_p3 <= 
        add_ln91_fu_935_p2 when (icmp_ln887_1_reg_1245(0) = '1') else 
        ap_const_lv32_0;
        sext_ln1311_1_fu_738_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(ush_reg_1198),32));

        sext_ln1311_2_fu_741_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(ush_reg_1198),25));

        sext_ln1311_fu_713_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sub_ln1311_fu_708_p2),9));

        sext_ln1354_1_fu_925_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(grp_fu_396_p2),33));

        sext_ln1354_fu_891_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(grp_fu_396_p2),33));

    shl_ln1_fu_955_p3 <= (i_op_assign_3_reg_290 & ap_const_lv1_0);
    shl_ln_fu_837_p3 <= (i_op_assign_2_reg_279 & ap_const_lv1_0);
    sub_ln1311_fu_708_p2 <= std_logic_vector(unsigned(ap_const_lv8_7F) - unsigned(tmp_V_reg_1182));
    sub_ln72_1_fu_795_p2 <= std_logic_vector(unsigned(i_op_assign_3_reg_290) - unsigned(reg_401));
    sub_ln72_fu_807_p2 <= std_logic_vector(unsigned(i_op_assign_3_reg_290) - unsigned(i_op_assign_2_reg_279));
    tmp_23_fu_465_p4 <= config_r_q0(30 downto 23);
    tmp_31_fu_420_p3 <= (config_offset & ap_const_lv4_0);
    tmp_32_fu_448_p3 <= (ap_const_lv55_0 & or_ln46_fu_443_p2);
    tmp_33_fu_492_p3 <= (ap_const_lv55_0 & or_ln48_fu_487_p2);
    tmp_34_fu_518_p3 <= (ap_const_lv55_0 & or_ln49_fu_513_p2);
    tmp_35_fu_549_p3 <= (ap_const_lv55_0 & or_ln50_fu_544_p2);
    tmp_36_fu_595_p3 <= (ap_const_lv55_0 & or_ln51_fu_590_p2);
    tmp_37_fu_434_p3 <= (ap_const_lv55_0 & or_ln52_fu_428_p2);
    tmp_38_fu_609_p3 <= (ap_const_lv55_0 & or_ln53_fu_604_p2);
    tmp_39_fu_623_p3 <= (ap_const_lv55_0 & or_ln55_fu_618_p2);
    tmp_40_fu_637_p3 <= (ap_const_lv55_0 & or_ln56_fu_632_p2);
    tmp_42_fu_772_p4 <= r_V_1_fu_754_p2(55 downto 24);
    tmp_V_1_fu_687_p1 <= p_Val2_8_fu_673_p1(23 - 1 downto 0);
    tmp_fu_760_p3 <= r_V_fu_748_p2(24 downto 24);
    trunc_ln257_fu_461_p1 <= config_r_q0(23 - 1 downto 0);
    trunc_ln302_fu_558_p1 <= reg_401(1 - 1 downto 0);
    trunc_ln368_3_fu_654_p1 <= config_r_q0(31 - 1 downto 0);
    trunc_ln368_fu_457_p1 <= config_r_q0(31 - 1 downto 0);
    ush_fu_717_p3 <= 
        sext_ln1311_fu_713_p1 when (isNeg_fu_700_p3(0) = '1') else 
        add_ln339_fu_694_p2;
    val_V_fu_782_p3 <= 
        zext_ln662_fu_768_p1 when (isNeg_reg_1193(0) = '1') else 
        tmp_42_fu_772_p4;
    val_assign_s_fu_562_p4 <= config_r_q0(31 downto 1);
    zext_ln1287_fu_744_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(sext_ln1311_1_fu_738_p1),79));
    zext_ln339_fu_691_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_V_reg_1182),9));
    zext_ln662_fu_768_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_760_p3),32));
    zext_ln682_fu_734_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(mantissa_V_fu_725_p4),79));
    zext_ln78_1_fu_830_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(memAddr_reg_1084),34));
    zext_ln78_2_fu_833_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_op_assign_2_reg_279),33));
    zext_ln78_3_fu_845_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(shl_ln_fu_837_p3),34));
    zext_ln78_4_fu_855_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln78_fu_849_p2),64));
    zext_ln78_fu_827_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(memAddr_reg_1084),33));
    zext_ln79_1_fu_881_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln79_1_fu_875_p2),64));
    zext_ln79_fu_871_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln79_fu_865_p2),34));
    zext_ln89_1_fu_952_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(memAddr_reg_1084),34));
    zext_ln89_2_fu_921_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_op_assign_3_reg_290),33));
    zext_ln89_3_fu_963_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(shl_ln1_fu_955_p3),34));
    zext_ln89_4_fu_973_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln89_fu_967_p2),64));
    zext_ln89_fu_949_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(memAddr_reg_1084),33));
    zext_ln90_1_fu_999_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln90_1_fu_993_p2),64));
    zext_ln90_fu_989_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln90_fu_983_p2),34));
end behav;
