--
-- VHDL Test Bench CAD_lib.nop_ctrl_tb.nop_ctrl_tester
--
-- Created:
--          by - W.UNKNOWN (DESKTOP-86TQKQ1)
--          at - 16:55:03 02/22/2021
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.2 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY nop_ctrl_tb IS
END nop_ctrl_tb;


LIBRARY CAD_lib;
USE CAD_lib.ALL;


ARCHITECTURE rtl OF nop_ctrl_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL jmp   : std_ulogic;
   SIGNAL rst   : std_ulogic;
   SIGNAL delay : std_ulogic;
   SIGNAL mdata : std_ulogic_vector(31 downto 0);
   SIGNAL Inst  : std_ulogic_vector(31 downto 0);


   -- Component declarations
   COMPONENT nop_ctrl
      PORT (
         jmp   : IN     std_ulogic;
         rst   : IN     std_ulogic;
         delay : IN     std_ulogic;
         mdata : IN     std_ulogic_vector(31 downto 0);
         Inst  : OUT    std_ulogic_vector(31 downto 0)
      );
   END COMPONENT;

   -- embedded configurations
   -- pragma synthesis_off
   FOR U_0 : nop_ctrl USE ENTITY CAD_lib.nop_ctrl;
   -- pragma synthesis_on

BEGIN

         U_0 : nop_ctrl
            PORT MAP (
               jmp   => jmp,
               rst   => rst,
               delay => delay,
               mdata => mdata,
               Inst  => Inst
            );

process
begin
  mdata<=(others=>'1');
  jmp <= '0'; rst <= '0'; delay <= '0';
  wait for 100ns;
  
  jmp <= '1'; rst <= '0'; delay <= '0';
  wait for 100ns;
  
  jmp <= '0'; rst <= '1'; delay <= '0';
  wait for 100ns;
  
  jmp <= '0'; rst <= '0'; delay <= '1';
  wait for 100ns;
  
  
  jmp <= '1'; rst <= '1'; delay <= '0';
  wait for 100ns;
  
  jmp <= '1'; rst <= '0'; delay <= '1';
  wait for 100ns;
  
  jmp <= '0'; rst <= '1'; delay <= '1';
  wait for 100ns;
  
  jmp <= '1'; rst <= '1'; delay <= '1';
  wait for 100ns;
  
 
wait;
end process;
END rtl;