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cass-opencl-instruct

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cuda_device stringlengths 526 34.8M	cuda_host null	hip_device stringlengths 802 2.82M	hip_host null	cuda_source null	hip_source null	filename stringlengths 6 10
.headerflags @"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" .elftype @"ET_EXEC" //--------------------- .debug_frame -------------------------- .section .debug_frame,"",@progbits //--------------------- .nv.rel.action -------------------------- .section .nv.rel.action,"",@"SHT_CUDA_RELOCINFO" .align 8 .sectionentsize 8 /0000/ .byte 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x25, 0x00, 0x05, 0x36	null	.text .amdgcn_target "amdgcn-amd-amdhsa-opencl-gfx1100" .amdhsa_code_object_version 5 .hidden WangHash ; -- Begin function WangHash .globl WangHash .p2align 2 .type WangHash,@function WangHash: ; @WangHash ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) v_lshrrev_b32_e32 v1, 16, v0 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor3_b32 v0, v1, v0, 61 v_lshl_add_u32 v0, v0, 3, v0 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_lshrrev_b32_e32 v1, 4, v0 v_xor_b32_e32 v0, v1, v0 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_mul_lo_u32 v0, 0x27d4eb2d, v0 v_lshrrev_b32_e32 v1, 15, v0 s_delay_alu instid0(VALU_DEP_1) v_xor_b32_e32 v0, v1, v0 s_setpc_b64 s[30:31] .Lfunc_end0: .size WangHash, .Lfunc_end0-WangHash ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 72 ; NumSgprs: 32 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 .text .hidden RandomInt ; -- Begin function RandomInt .globl RandomInt .p2align 2 .type RandomInt,@function RandomInt: ; @RandomInt ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) scratch_load_b32 v1, v0, off s_waitcnt vmcnt(0) v_lshlrev_b32_e32 v2, 13, v1 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v1, v2, v1 v_lshrrev_b32_e32 v2, 17, v1 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v1, v2, v1 v_lshlrev_b32_e32 v2, 5, v1 s_delay_alu instid0(VALU_DEP_1) v_xor_b32_e32 v1, v2, v1 scratch_store_b32 v0, v1, off v_mov_b32_e32 v0, v1 s_setpc_b64 s[30:31] .Lfunc_end1: .size RandomInt, .Lfunc_end1-RandomInt ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 68 ; NumSgprs: 32 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 .text .hidden RandomFloat ; -- Begin function RandomFloat .globl RandomFloat .p2align 2 .type RandomFloat,@function RandomFloat: ; @RandomFloat ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) scratch_load_b32 v1, v0, off s_waitcnt vmcnt(0) v_lshlrev_b32_e32 v2, 13, v1 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v1, v2, v1 v_lshrrev_b32_e32 v2, 17, v1 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v1, v2, v1 v_lshlrev_b32_e32 v2, 5, v1 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v1 v_cvt_f32_u32_e32 v1, v2 scratch_store_b32 v0, v2, off v_mul_f32_e32 v1, 0x2f800000, v1 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v0, v1 s_setpc_b64 s[30:31] .Lfunc_end2: .size RandomFloat, .Lfunc_end2-RandomFloat ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 84 ; NumSgprs: 32 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .hidden __oclc_ABI_version ; @__oclc_ABI_version .type __oclc_ABI_version,@object .section .rodata,"a",@progbits .weak __oclc_ABI_version .p2align 2, 0x0 __oclc_ABI_version: .long 500 ; 0x1f4 .size __oclc_ABI_version, 4 .ident "Ubuntu clang version 18.1.3 (1ubuntu1)" .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa-opencl-gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata	null	null	null	file_89
.headerflags @"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" .elftype @"ET_EXEC" //--------------------- .debug_frame -------------------------- .section .debug_frame,"",@progbits //--------------------- .nv.rel.action -------------------------- .section .nv.rel.action,"",@"SHT_CUDA_RELOCINFO" .align 8 .sectionentsize 8 /0000/ .byte 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x25, 0x00, 0x05, 0x36	null	.text .amdgcn_target "amdgcn-amd-amdhsa-opencl-gfx1100" .amdhsa_code_object_version 5 .hidden octlf_intersect_wide ; -- Begin function octlf_intersect_wide .globl octlf_intersect_wide .p2align 2 .type octlf_intersect_wide,@function octlf_intersect_wide: ; @octlf_intersect_wide ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_clause 0x1 scratch_load_b128 v[0:3], v8, off scratch_load_b128 v[11:14], v8, off offset:16 s_clause 0x1 scratch_load_b128 v[14:17], v9, off scratch_load_b128 v[17:20], v9, off offset:16 v_cmp_ne_u16_e32 vcc_lo, 0, v4 v_lshrrev_b32_e32 v21, 16, v4 v_add_nc_u32_e32 v22, 48, v10 v_lshrrev_b32_e32 v9, 16, v5 v_lshrrev_b32_e32 v8, 16, v6 v_cndmask_b32_e64 v4, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v5 s_waitcnt vmcnt(3) v_lshrrev_b32_e32 v3, 16, v7 v_cndmask_b32_e64 v5, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v6 v_cndmask_b32_e64 v6, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v7 v_cndmask_b32_e64 v7, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v21 v_cndmask_b32_e64 v21, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v9 v_cndmask_b32_e64 v9, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v8 v_cndmask_b32_e64 v8, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, 0, v3 v_cndmask_b32_e64 v3, 0, -1, vcc_lo s_waitcnt vmcnt(2) v_dual_add_f32 v23, v0, v11 :: v_dual_add_f32 v24, v1, v12 v_add_f32_e32 v25, v2, v13 s_waitcnt vmcnt(1) v_sub_f32_e32 v2, v2, v16 v_dual_sub_f32 v0, v0, v14 :: v_dual_sub_f32 v1, v1, v15 v_mul_f32_e32 v23, 0.5, v23 v_dual_mul_f32 v25, 0.5, v25 :: v_dual_mul_f32 v24, 0.5, v24 v_dual_sub_f32 v11, v11, v14 :: v_dual_sub_f32 v12, v12, v15 s_delay_alu instid0(VALU_DEP_3) \| instskip(NEXT) \| instid1(VALU_DEP_3) v_dual_sub_f32 v13, v13, v16 :: v_dual_sub_f32 v14, v23, v14 v_dual_sub_f32 v15, v24, v15 :: v_dual_sub_f32 v16, v25, v16 s_waitcnt vmcnt(0) v_dual_mul_f32 v0, v17, v0 :: v_dual_mul_f32 v1, v18, v1 v_dual_mul_f32 v11, v17, v11 :: v_dual_mul_f32 v12, v18, v12 v_dual_mul_f32 v14, v17, v14 :: v_dual_mul_f32 v13, v19, v13 v_dual_mul_f32 v2, v19, v2 :: v_dual_mul_f32 v15, v18, v15 s_delay_alu instid0(VALU_DEP_2) \| instskip(NEXT) \| instid1(VALU_DEP_4) v_dual_mul_f32 v16, v19, v16 :: v_dual_min_f32 v17, v0, v14 v_min_f32_e32 v18, v14, v11 v_dual_max_f32 v0, v0, v14 :: v_dual_max_f32 v11, v14, v11 s_delay_alu instid0(VALU_DEP_3) \| instskip(SKIP_4) \| instid1(VALU_DEP_4) v_dual_min_f32 v14, v1, v15 :: v_dual_min_f32 v23, v16, v13 v_min_f32_e32 v19, v15, v12 v_dual_max_f32 v1, v1, v15 :: v_dual_max_f32 v12, v15, v12 v_min_f32_e32 v15, v2, v16 v_dual_max_f32 v2, v2, v16 :: v_dual_max_f32 v13, v16, v13 v_max3_f32 v16, v18, v19, v23 v_max3_f32 v24, v17, v19, v23 v_max3_f32 v25, v18, v14, v23 v_max3_f32 v23, v17, v14, v23 v_max3_f32 v26, v18, v19, v15 v_max3_f32 v19, v17, v19, v15 v_max3_f32 v18, v18, v14, v15 v_max3_f32 v14, v17, v14, v15 v_min3_f32 v15, v11, v12, v13 v_min3_f32 v17, v0, v12, v13 v_min3_f32 v28, v0, v1, v2 v_min3_f32 v27, v11, v1, v13 v_cmp_lt_f32_e64 s15, v16, v20 v_cmp_lt_f32_e64 s6, v16, v15 v_min3_f32 v30, v0, v12, v2 v_cmp_lt_f32_e32 vcc_lo, v14, v28 v_cmp_lt_f32_e64 s5, v24, v17 v_cmp_lt_f32_e64 s7, 0, v15 v_cmp_lt_f32_e64 s16, v24, v20 v_cmp_lt_f32_e64 s22, v14, v20 v_min3_f32 v29, v11, v1, v2 v_cmp_lt_f32_e64 s4, v25, v27 v_cmp_lt_f32_e64 s8, 0, v17 v_cmp_lt_f32_e64 s17, v25, v20 s_and_b32 s6, s6, s15 v_cmp_lt_f32_e64 s1, v19, v30 v_cmp_lt_f32_e64 s9, 0, v27 v_cmp_lt_f32_e64 s20, v19, v20 v_min3_f32 v0, v0, v1, v13 s_and_b32 s5, s5, s16 s_and_b32 s15, vcc_lo, s22 s_and_b32 vcc_lo, s6, s7 v_cmp_lt_f32_e64 s0, v18, v29 v_cmp_lt_f32_e64 s12, 0, v30 v_cmp_lt_f32_e64 s21, v18, v20 v_min3_f32 v2, v11, v12, v2 s_and_b32 s4, s4, s17 v_cndmask_b32_e32 v1, 0, v3, vcc_lo s_and_b32 vcc_lo, s5, s8 v_cmp_lt_f32_e64 s13, 0, v29 s_and_b32 s1, s1, s20 v_cndmask_b32_e32 v3, 0, v7, vcc_lo s_and_b32 vcc_lo, s4, s9 v_cmp_lt_f32_e64 s3, v23, v0 v_cmp_lt_f32_e64 s14, 0, v28 v_cmp_lt_f32_e64 s18, v23, v20 s_and_b32 s0, s0, s21 v_cndmask_b32_e32 v7, 0, v8, vcc_lo s_and_b32 vcc_lo, s1, s12 v_cmp_lt_f32_e64 s2, v26, v2 v_cmp_lt_f32_e64 s10, 0, v0 v_cmp_lt_f32_e64 s19, v26, v20 v_cndmask_b32_e32 v5, 0, v5, vcc_lo s_and_b32 vcc_lo, s0, s13 v_cmp_lt_f32_e64 s11, 0, v2 s_and_b32 s3, s3, s18 v_cndmask_b32_e32 v8, 0, v21, vcc_lo s_and_b32 vcc_lo, s15, s14 s_and_b32 s2, s2, s19 v_cndmask_b32_e32 v4, 0, v4, vcc_lo s_and_b32 vcc_lo, s3, s10 v_cndmask_b32_e32 v6, 0, v6, vcc_lo s_and_b32 vcc_lo, s2, s11 v_cndmask_b32_e32 v9, 0, v9, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v5 v_dual_cndmask_b32 v12, 0x7f800000, v30 :: v_dual_add_nc_u32 v11, v4, v8 v_cmp_gt_i32_e32 vcc_lo, 0, v7 v_cndmask_b32_e32 v13, 0x7f800000, v27, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v6 v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v3 v_cndmask_b32_e32 v14, 0x7f800000, v17, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v1 v_cndmask_b32_e32 v15, 0x7f800000, v15, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v8 v_cndmask_b32_e32 v8, 0x7f800000, v29, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v4 v_cndmask_b32_e32 v4, 0x7f800000, v28, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v9 v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_min_f32_e32 v17, v2, v12 v_max_f32_e32 v19, v15, v14 v_max_f32_e32 v21, v4, v8 v_min_f32_e32 v16, v4, v8 v_max_f32_e32 v20, v2, v12 v_add3_u32 v5, v5, v11, v9 v_min_f32_e32 v9, v15, v14 v_cmp_le_f32_e64 s1, v15, v14 v_min_f32_e32 v14, v21, v17 v_min_f32_e32 v11, v0, v13 v_cmp_nle_f32_e64 s0, v4, v8 v_max_f32_e32 v18, v0, v13 v_cmp_le_f32_e32 vcc_lo, v2, v12 v_cmp_le_f32_e64 s2, v4, v8 v_add3_u32 v5, v6, v5, v7 v_cndmask_b32_e64 v12, 0, 1, s0 v_cmp_le_f32_e64 s0, v0, v13 v_cndmask_b32_e64 v2, 2, 3, vcc_lo v_cndmask_b32_e64 v13, 6, 7, s1 v_cndmask_b32_e64 v4, 0, 1, s2 v_cndmask_b32_e64 v6, 3, 2, vcc_lo v_cndmask_b32_e64 v0, 5, 4, s0 v_cndmask_b32_e64 v7, 7, 6, s1 v_cndmask_b32_e64 v8, 4, 5, s0 v_cmp_le_f32_e32 vcc_lo, v16, v20 v_cmp_le_f32_e64 s0, v19, v11 v_min_f32_e32 v23, v19, v11 v_max_f32_e32 v25, v21, v17 v_max_f32_e32 v11, v19, v11 v_max_f32_e32 v19, v9, v18 v_min_f32_e32 v15, v16, v20 v_max_f32_e32 v16, v16, v20 v_cmp_le_f32_e64 s2, v9, v18 v_min_f32_e32 v24, v9, v18 v_cmp_le_f32_e64 s1, v21, v17 v_add3_u32 v9, v3, v5, v1 v_cndmask_b32_e64 v3, v0, v7, s0 v_cndmask_b32_e64 v1, v8, v13, s2 v_cndmask_b32_e32 v5, v6, v12, vcc_lo v_cndmask_b32_e64 v8, v13, v8, s2 v_cndmask_b32_e64 v0, v7, v0, s0 v_cndmask_b32_e32 v6, v12, v6, vcc_lo v_max_f32_e32 v20, v16, v25 v_cmp_le_f32_e32 vcc_lo, v19, v11 v_cndmask_b32_e64 v17, v2, v4, s1 v_cndmask_b32_e64 v2, v4, v2, s1 v_cmp_le_f32_e64 s0, v24, v23 v_cmp_le_f32_e64 s1, v16, v25 v_cndmask_b32_e32 v21, v0, v8, vcc_lo v_cndmask_b32_e32 v0, v8, v0, vcc_lo v_min_f32_e32 v4, v19, v11 v_dual_min_f32 v7, v24, v23 :: v_dual_max_f32 v18, v15, v14 v_cmp_le_f32_e64 s2, v15, v14 v_dual_min_f32 v12, v15, v14 :: v_dual_min_f32 v13, v16, v25 v_cndmask_b32_e64 v15, v3, v1, s0 s_delay_alu instid0(VALU_DEP_4) \| instskip(NEXT) \| instid1(VALU_DEP_4) v_max_f32_e32 v26, v18, v4 v_cndmask_b32_e64 v14, v17, v5, s2 v_cndmask_b32_e64 v1, v1, v3, s0 v_cndmask_b32_e64 v3, v5, v17, s2 v_dual_min_f32 v8, v20, v7 :: v_dual_min_f32 v17, v18, v4 v_max_f32_e32 v11, v19, v11 v_max_f32_e32 v19, v24, v23 v_max_f32_e32 v25, v20, v7 v_cmp_le_f32_e32 vcc_lo, v18, v4 v_cndmask_b32_e64 v16, v2, v6, s1 v_cndmask_b32_e64 v2, v6, v2, s1 v_cmp_le_f32_e64 s0, v20, v7 v_cmp_le_f32_e64 s1, v12, v11 v_max_f32_e32 v18, v17, v8 v_max_f32_e32 v23, v13, v19 v_cmp_le_f32_e64 s2, v13, v19 v_max_f32_e32 v20, v26, v25 v_min_f32_e32 v6, v12, v11 v_dual_cndmask_b32 v4, v21, v3 :: v_dual_cndmask_b32 v3, v3, v21 v_max_f32_e32 v24, v12, v11 v_cndmask_b32_e64 v11, v0, v14, s1 v_cndmask_b32_e64 v12, v1, v16, s2 v_cndmask_b32_e64 v0, v14, v0, s1 v_cndmask_b32_e64 v1, v16, v1, s2 v_cmp_le_f32_e32 vcc_lo, v24, v23 v_min_f32_e32 v5, v13, v19 v_cndmask_b32_e64 v7, v15, v2, s0 v_cndmask_b32_e64 v2, v2, v15, s0 v_min_f32_e32 v14, v17, v8 v_min_f32_e32 v16, v24, v23 v_max_f32_e32 v21, v24, v23 v_cndmask_b32_e32 v23, v1, v0, vcc_lo v_cmp_le_f32_e64 s0, v26, v25 v_cndmask_b32_e32 v0, v0, v1, vcc_lo v_min_f32_e32 v15, v6, v5 v_max_f32_e32 v19, v6, v5 v_cmp_le_f32_e64 s1, v6, v5 v_cndmask_b32_e64 v24, v2, v3, s0 v_cndmask_b32_e64 v27, v3, v2, s0 v_dual_max_f32 v2, v15, v14 :: v_dual_min_f32 v13, v26, v25 v_cmp_le_f32_e64 s2, v17, v8 v_cndmask_b32_e64 v25, v12, v11, s1 v_cndmask_b32_e64 v12, v11, v12, s1 v_cmp_le_f32_e64 s1, v19, v18 v_max_f32_e32 v6, v16, v13 v_cmp_le_f32_e32 vcc_lo, v16, v13 v_min_f32_e32 v5, v16, v13 v_cndmask_b32_e64 v26, v7, v4, s2 v_cndmask_b32_e64 v28, v4, v7, s2 v_cmp_le_f32_e64 s2, v15, v14 v_cndmask_b32_e32 v16, v23, v24, vcc_lo v_cmp_le_f32_e64 s0, v21, v20 v_dual_min_f32 v3, v19, v18 :: v_dual_max_f32 v8, v21, v20 v_dual_min_f32 v7, v21, v20 :: v_dual_max_f32 v4, v19, v18 s_delay_alu instid0(VALU_DEP_3) v_cndmask_b32_e64 v17, v27, v0, s0 v_cndmask_b32_e64 v18, v0, v27, s0 v_sub_nc_u32_e32 v0, 0, v9 v_min_f32_e32 v1, v15, v14 v_cndmask_b32_e32 v15, v24, v23, vcc_lo v_cndmask_b32_e64 v13, v28, v12, s1 v_cndmask_b32_e64 v11, v26, v25, s2 v_cndmask_b32_e64 v14, v12, v28, s1 v_cndmask_b32_e64 v12, v25, v26, s2 s_clause 0x3 scratch_store_b128 v10, v[5:8], off offset:16 scratch_store_b128 v10, v[1:4], off scratch_store_b128 v22, v[15:18], off scratch_store_b128 v10, v[11:14], off offset:32 s_setpc_b64 s[30:31] .Lfunc_end0: .size octlf_intersect_wide, .Lfunc_end0-octlf_intersect_wide ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 1636 ; NumSgprs: 34 ; NumVgprs: 31 ; ScratchSize: 0 ; MemoryBound: 0 .text .hidden octet_intersect_wide ; -- Begin function octet_intersect_wide .globl octet_intersect_wide .p2align 2 .type octet_intersect_wide,@function octet_intersect_wide: ; @octet_intersect_wide ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_clause 0x1 scratch_load_b128 v[12:15], v4, off scratch_load_b128 v[8:11], v4, off offset:16 v_add_nc_u32_e32 v4, 48, v7 v_add_nc_u32_e32 v39, 0x50, v7 v_add_nc_u32_e32 v55, 0x90, v7 v_add_nc_u32_e32 v54, 0x70, v7 v_add_nc_u32_e32 v70, 0xb0, v7 v_add_nc_u32_e32 v71, 0xd0, v7 v_add_nc_u32_e32 v83, 0xf0, v7 v_cmp_ne_u16_e32 vcc_lo, -1, v0 s_waitcnt vmcnt(1) v_mov_b32_e32 v16, v13 s_waitcnt vmcnt(0) v_mov_b32_e32 v18, v8 v_dual_add_f32 v19, v12, v8 :: v_dual_add_f32 v20, v13, v9 v_dual_add_f32 v22, v14, v10 :: v_dual_mov_b32 v31, v9 s_delay_alu instid0(VALU_DEP_2) \| instskip(NEXT) \| instid1(VALU_DEP_2) v_dual_mov_b32 v33, v12 :: v_dual_mul_f32 v64, 0.5, v19 v_dual_mul_f32 v65, 0.5, v20 :: v_dual_mul_f32 v66, 0.5, v22 v_mov_b32_e32 v67, v12 v_mov_b32_e32 v17, v14 v_mov_b32_e32 v21, v12 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v51, v8 :: v_dual_mov_b32 v20, v66 v_dual_mov_b32 v24, v64 :: v_dual_mov_b32 v19, v65 v_mov_b32_e32 v36, v64 v_mov_b32_e32 v26, v66 s_clause 0x1 scratch_store_b128 v7, v[12:15], off scratch_store_b128 v7, v[64:67], off offset:16 v_dual_mov_b32 v15, v64 :: v_dual_mov_b32 v28, v65 v_dual_mov_b32 v23, v14 :: v_dual_mov_b32 v30, v8 v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v38, v10 v_dual_mov_b32 v53, v10 :: v_dual_mov_b32 v22, v65 v_dual_mov_b32 v27, v64 :: v_dual_mov_b32 v50, v66 v_dual_mov_b32 v29, v14 :: v_dual_mov_b32 v34, v13 v_dual_mov_b32 v37, v65 :: v_dual_mov_b32 v80, v64 v_dual_mov_b32 v81, v9 :: v_dual_mov_b32 v32, v66 v_dual_mov_b32 v35, v66 :: v_dual_mov_b32 v48, v64 v_dual_mov_b32 v52, v65 :: v_dual_mov_b32 v69, v66 v_dual_mov_b32 v49, v13 :: v_dual_mov_b32 v82, v10 v_mov_b32_e32 v68, v65 s_clause 0xd scratch_store_b128 v7, v[15:18], off offset:32 scratch_store_b128 v7, v[21:24], off offset:64 scratch_store_b128 v39, v[24:27], off scratch_store_b128 v54, v[30:33], off scratch_store_b128 v7, v[27:30], off offset:96 scratch_store_b128 v7, v[33:36], off offset:128 scratch_store_b128 v55, v[36:39], off scratch_store_b128 v70, v[51:54], off scratch_store_b128 v7, v[48:51], off offset:160 scratch_store_b128 v7, v[67:70], off offset:192 scratch_store_b128 v4, v[18:21], off scratch_store_b128 v7, v[64:67], off offset:224 scratch_store_b128 v71, v[80:83], off scratch_store_b128 v83, v[8:11], off s_clause 0x1 scratch_load_b128 v[15:18], v5, off scratch_load_b128 v[18:21], v5, off offset:16 v_lshrrev_b32_e32 v11, 16, v0 v_cndmask_b32_e64 v0, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v1 v_lshrrev_b32_e32 v7, 16, v1 v_lshrrev_b32_e32 v5, 16, v2 v_add_nc_u32_e32 v22, 48, v6 v_lshrrev_b32_e32 v4, 16, v3 v_cndmask_b32_e64 v1, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v2 v_cndmask_b32_e64 v2, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v3 v_cndmask_b32_e64 v3, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v11 v_cndmask_b32_e64 v11, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v7 v_cndmask_b32_e64 v7, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v5 v_cndmask_b32_e64 v5, 0, -1, vcc_lo v_cmp_ne_u16_e32 vcc_lo, -1, v4 v_cndmask_b32_e64 v4, 0, -1, vcc_lo s_waitcnt vmcnt(1) v_dual_sub_f32 v13, v13, v16 :: v_dual_sub_f32 v12, v12, v15 v_sub_f32_e32 v23, v64, v15 v_dual_sub_f32 v8, v8, v15 :: v_dual_sub_f32 v9, v9, v16 v_dual_sub_f32 v15, v65, v16 :: v_dual_sub_f32 v14, v14, v17 v_sub_f32_e32 v16, v66, v17 s_waitcnt vmcnt(0) v_dual_sub_f32 v10, v10, v17 :: v_dual_mul_f32 v13, v13, v19 v_mul_f32_e32 v17, v23, v18 v_dual_mul_f32 v12, v12, v18 :: v_dual_mul_f32 v9, v9, v19 v_dual_mul_f32 v15, v15, v19 :: v_dual_mul_f32 v8, v8, v18 v_mul_f32_e32 v16, v16, v20 v_mul_f32_e32 v10, v10, v20 s_delay_alu instid0(VALU_DEP_4) \| instskip(NEXT) \| instid1(VALU_DEP_4) v_min_f32_e32 v18, v12, v17 v_dual_max_f32 v12, v12, v17 :: v_dual_min_f32 v19, v17, v8 v_max_f32_e32 v8, v17, v8 v_min_f32_e32 v17, v13, v15 v_dual_max_f32 v13, v13, v15 :: v_dual_mul_f32 v14, v14, v20 v_min_f32_e32 v20, v15, v9 v_max_f32_e32 v9, v15, v9 v_min_f32_e32 v23, v16, v10 s_delay_alu instid0(VALU_DEP_4) \| instskip(SKIP_1) \| instid1(VALU_DEP_3) v_dual_max_f32 v10, v16, v10 :: v_dual_min_f32 v15, v14, v16 v_max_f32_e32 v14, v14, v16 v_max3_f32 v16, v19, v20, v23 v_max3_f32 v24, v18, v20, v23 v_max3_f32 v25, v19, v17, v23 v_max3_f32 v23, v18, v17, v23 v_max3_f32 v26, v19, v20, v15 v_max3_f32 v20, v18, v20, v15 v_max3_f32 v19, v19, v17, v15 v_max3_f32 v15, v18, v17, v15 v_min3_f32 v17, v8, v9, v10 v_min3_f32 v18, v12, v9, v10 v_min3_f32 v28, v12, v13, v14 v_cmp_lt_f32_e64 s15, v16, v21 v_cmp_lt_f32_e64 s16, v24, v21 v_cmp_lt_f32_e64 s6, v16, v17 v_cmp_lt_f32_e64 s5, v24, v18 v_cmp_lt_f32_e32 vcc_lo, v15, v28 v_cmp_lt_f32_e64 s7, 0, v17 v_cmp_lt_f32_e64 s22, v15, v21 v_cmp_lt_f32_e64 s8, 0, v18 s_and_b32 s6, s6, s15 s_and_b32 s5, s5, s16 v_cmp_lt_f32_e64 s17, v25, v21 s_and_b32 s15, vcc_lo, s22 s_and_b32 vcc_lo, s6, s7 v_cmp_lt_f32_e64 s20, v20, v21 v_cndmask_b32_e32 v4, 0, v4, vcc_lo s_and_b32 vcc_lo, s5, s8 v_cmp_lt_f32_e64 s21, v19, v21 v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_min3_f32 v27, v8, v13, v10 v_cmp_lt_f32_e64 s14, 0, v28 v_cmp_lt_f32_e64 s18, v23, v21 v_cmp_lt_f32_e64 s19, v26, v21 s_delay_alu instid0(VALU_DEP_4) \| instskip(SKIP_1) \| instid1(VALU_DEP_2) v_cmp_lt_f32_e64 s4, v25, v27 v_cmp_lt_f32_e64 s9, 0, v27 s_and_b32 s4, s4, s17 s_delay_alu instid0(VALU_DEP_1) \| instid1(SALU_CYCLE_1) s_and_b32 vcc_lo, s4, s9 v_cndmask_b32_e32 v5, 0, v5, vcc_lo v_min3_f32 v30, v12, v9, v14 v_min3_f32 v29, v8, v13, v14 v_min3_f32 v8, v8, v9, v14 s_delay_alu instid0(VALU_DEP_3) \| instskip(SKIP_1) \| instid1(VALU_DEP_4) v_cmp_lt_f32_e64 s1, v20, v30 v_cmp_lt_f32_e64 s12, 0, v30 v_cmp_lt_f32_e64 s0, v19, v29 v_cmp_lt_f32_e64 s13, 0, v29 v_cmp_lt_f32_e64 s2, v26, v8 s_and_b32 s1, s1, s20 v_cmp_lt_f32_e64 s11, 0, v8 s_and_b32 vcc_lo, s1, s12 s_and_b32 s0, s0, s21 v_cndmask_b32_e32 v1, 0, v1, vcc_lo v_min3_f32 v9, v12, v13, v10 s_and_b32 vcc_lo, s0, s13 s_and_b32 s2, s2, s19 v_cndmask_b32_e32 v10, 0, v11, vcc_lo s_and_b32 vcc_lo, s15, s14 v_cmp_lt_f32_e64 s3, v23, v9 v_cmp_lt_f32_e64 s10, 0, v9 v_cndmask_b32_e32 v0, 0, v0, vcc_lo s_delay_alu instid0(VALU_DEP_3) s_and_b32 s3, s3, s18 s_delay_alu instid0(VALU_DEP_2) \| instid1(SALU_CYCLE_1) s_and_b32 vcc_lo, s3, s10 s_delay_alu instid0(VALU_DEP_1) \| instskip(SKIP_4) \| instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v0, v10 v_cndmask_b32_e32 v2, 0, v2, vcc_lo s_and_b32 vcc_lo, s2, s11 v_cndmask_b32_e32 v7, 0, v7, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v1 v_add3_u32 v1, v1, v11, v7 v_cndmask_b32_e32 v12, 0x7f800000, v30, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v5 v_cndmask_b32_e32 v13, 0x7f800000, v27, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v2 v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v3 s_delay_alu instid0(VALU_DEP_2) \| instskip(SKIP_3) \| instid1(VALU_DEP_2) v_dual_min_f32 v11, v9, v13 :: v_dual_cndmask_b32 v14, 0x7f800000, v18 v_cmp_gt_i32_e32 vcc_lo, 0, v4 v_cndmask_b32_e32 v15, 0x7f800000, v17, vcc_lo v_cmp_gt_i32_e32 vcc_lo, 0, v10 v_dual_max_f32 v19, v15, v14 :: v_dual_cndmask_b32 v10, 0x7f800000, v29 v_cmp_gt_i32_e32 vcc_lo, 0, v0 s_delay_alu instid0(VALU_DEP_2) \| instskip(SKIP_2) \| instid1(VALU_DEP_3) v_dual_min_f32 v23, v19, v11 :: v_dual_cndmask_b32 v0, 0x7f800000, v28 v_cmp_gt_i32_e32 vcc_lo, 0, v7 v_min_f32_e32 v7, v15, v14 v_min_f32_e32 v16, v0, v10 v_dual_cndmask_b32 v8, 0x7f800000, v8 :: v_dual_max_f32 v21, v0, v10 s_delay_alu instid0(VALU_DEP_1) \| instskip(SKIP_1) \| instid1(VALU_DEP_1) v_max_f32_e32 v20, v8, v12 v_max_f32_e32 v18, v9, v13 v_min_f32_e32 v24, v7, v18 v_cmp_le_f32_e64 s1, v15, v14 s_delay_alu instid0(VALU_DEP_4) \| instskip(SKIP_4) \| instid1(VALU_DEP_4) v_min_f32_e32 v15, v16, v20 v_min_f32_e32 v17, v8, v12 v_cmp_le_f32_e32 vcc_lo, v8, v12 v_add3_u32 v1, v2, v1, v5 v_cndmask_b32_e64 v5, 7, 6, s1 v_max_f32_e32 v25, v21, v17 v_cmp_nle_f32_e64 s0, v0, v10 v_cmp_le_f32_e64 s2, v0, v10 v_cndmask_b32_e64 v8, 2, 3, vcc_lo v_cndmask_b32_e64 v2, 3, 2, vcc_lo v_cmp_le_f32_e32 vcc_lo, v16, v20 v_cndmask_b32_e64 v12, 0, 1, s0 v_cmp_le_f32_e64 s0, v9, v13 v_cndmask_b32_e64 v13, 6, 7, s1 v_cndmask_b32_e64 v0, 0, 1, s2 v_min_f32_e32 v14, v21, v17 v_cmp_le_f32_e64 s1, v21, v17 v_cndmask_b32_e64 v9, 5, 4, s0 v_cndmask_b32_e64 v10, 4, 5, s0 v_cmp_le_f32_e64 s0, v19, v11 v_max_f32_e32 v11, v19, v11 v_dual_max_f32 v19, v7, v18 :: v_dual_max_f32 v16, v16, v20 v_cmp_le_f32_e64 s2, v7, v18 v_cndmask_b32_e64 v17, v8, v0, s1 v_add3_u32 v20, v3, v1, v4 v_cndmask_b32_e64 v3, v9, v5, s0 v_cndmask_b32_e32 v4, v2, v12, vcc_lo v_cndmask_b32_e64 v1, v10, v13, s2 v_cndmask_b32_e64 v7, v13, v10, s2 v_cndmask_b32_e64 v5, v5, v9, s0 v_min_f32_e32 v9, v24, v23 v_cndmask_b32_e32 v2, v12, v2, vcc_lo v_cndmask_b32_e64 v0, v0, v8, s1 v_cmp_le_f32_e32 vcc_lo, v19, v11 v_cmp_le_f32_e64 s0, v24, v23 v_min_f32_e32 v10, v15, v14 v_dual_max_f32 v13, v15, v14 :: v_dual_min_f32 v12, v16, v25 v_dual_cndmask_b32 v21, v5, v7 :: v_dual_max_f32 v18, v16, v25 v_min_f32_e32 v8, v19, v11 v_max_f32_e32 v11, v19, v11 v_max_f32_e32 v19, v24, v23 v_cmp_le_f32_e64 s1, v16, v25 v_cmp_le_f32_e64 s2, v15, v14 v_cndmask_b32_e64 v15, v3, v1, s0 v_cndmask_b32_e64 v1, v1, v3, s0 v_cndmask_b32_e32 v3, v7, v5, vcc_lo v_cndmask_b32_e64 v16, v0, v2, s1 v_cndmask_b32_e64 v14, v17, v4, s2 v_cndmask_b32_e64 v0, v2, v0, s1 v_cndmask_b32_e64 v2, v4, v17, s2 v_min_f32_e32 v4, v12, v19 v_min_f32_e32 v5, v10, v11 v_min_f32_e32 v7, v18, v9 v_dual_min_f32 v17, v13, v8 :: v_dual_max_f32 v24, v10, v11 v_dual_max_f32 v23, v12, v19 :: v_dual_max_f32 v26, v13, v8 v_cmp_le_f32_e32 vcc_lo, v13, v8 v_max_f32_e32 v25, v18, v9 v_cmp_le_f32_e64 s0, v18, v9 v_cmp_le_f32_e64 s1, v10, v11 v_cmp_le_f32_e64 s2, v12, v19 v_cndmask_b32_e32 v8, v21, v2, vcc_lo v_cndmask_b32_e32 v2, v2, v21, vcc_lo v_cndmask_b32_e64 v9, v15, v0, s0 v_cndmask_b32_e64 v10, v3, v14, s1 v_cndmask_b32_e64 v11, v1, v16, s2 v_cndmask_b32_e64 v0, v0, v15, s0 v_min_f32_e32 v15, v24, v23 v_cndmask_b32_e64 v3, v14, v3, s1 v_cndmask_b32_e64 v1, v16, v1, s2 v_dual_min_f32 v14, v5, v4 :: v_dual_max_f32 v19, v26, v25 v_dual_max_f32 v18, v5, v4 :: v_dual_max_f32 v21, v24, v23 v_cmp_le_f32_e32 vcc_lo, v24, v23 v_cmp_le_f32_e64 s0, v26, v25 v_dual_min_f32 v12, v17, v7 :: v_dual_min_f32 v13, v26, v25 v_max_f32_e32 v16, v17, v7 v_cmp_le_f32_e64 s1, v5, v4 v_cmp_le_f32_e64 s2, v17, v7 v_dual_cndmask_b32 v23, v1, v3 :: v_dual_cndmask_b32 v26, v3, v1 v_cndmask_b32_e64 v24, v0, v2, s0 v_cndmask_b32_e64 v0, v2, v0, s0 v_cmp_le_f32_e64 s0, v21, v19 v_cmp_le_f32_e32 vcc_lo, v15, v13 v_cndmask_b32_e64 v5, v11, v10, s1 v_cndmask_b32_e64 v25, v9, v8, s2 v_cndmask_b32_e64 v27, v10, v11, s1 v_cndmask_b32_e64 v28, v8, v9, s2 v_min_f32_e32 v1, v14, v12 v_cmp_le_f32_e64 s1, v18, v16 v_cmp_le_f32_e64 s2, v14, v12 v_dual_min_f32 v3, v18, v16 :: v_dual_max_f32 v10, v21, v19 v_dual_min_f32 v9, v21, v19 :: v_dual_max_f32 v4, v18, v16 v_dual_min_f32 v7, v15, v13 :: v_dual_max_f32 v2, v14, v12 v_dual_max_f32 v8, v15, v13 :: v_dual_cndmask_b32 v15, v24, v23 v_cndmask_b32_e64 v17, v0, v26, s0 v_cndmask_b32_e64 v18, v26, v0, s0 v_sub_nc_u32_e32 v0, 0, v20 v_cndmask_b32_e32 v16, v23, v24, vcc_lo v_cndmask_b32_e64 v13, v28, v27, s1 v_cndmask_b32_e64 v11, v25, v5, s2 v_cndmask_b32_e64 v14, v27, v28, s1 v_cndmask_b32_e64 v12, v5, v25, s2 s_clause 0x3 scratch_store_b128 v6, v[7:10], off offset:16 scratch_store_b128 v6, v[1:4], off scratch_store_b128 v22, v[15:18], off scratch_store_b128 v6, v[11:14], off offset:32 s_setpc_b64 s[30:31] .Lfunc_end1: .size octet_intersect_wide, .Lfunc_end1-octet_intersect_wide ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 2000 ; NumSgprs: 34 ; NumVgprs: 84 ; ScratchSize: 0 ; MemoryBound: 0 .text .hidden xorshift ; -- Begin function xorshift .globl xorshift .p2align 2 .type xorshift,@function xorshift: ; @xorshift ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) v_lshlrev_b32_e32 v1, 13, v0 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v0, v1, v0 v_lshrrev_b32_e32 v1, 17, v0 s_delay_alu instid0(VALU_DEP_1) \| instskip(NEXT) \| instid1(VALU_DEP_1) v_xor_b32_e32 v0, v1, v0 v_lshlrev_b32_e32 v1, 5, v0 s_delay_alu instid0(VALU_DEP_1) v_xor_b32_e32 v0, v1, v0 s_setpc_b64 s[30:31] .Lfunc_end2: .size xorshift, .Lfunc_end2-xorshift ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 44 ; NumSgprs: 32 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .hidden __oclc_ABI_version ; @__oclc_ABI_version .type __oclc_ABI_version,@object .section .rodata,"a",@progbits .weak __oclc_ABI_version .p2align 2, 0x0 __oclc_ABI_version: .long 500 ; 0x1f4 .size __oclc_ABI_version, 4 .ident "Ubuntu clang version 18.1.3 (1ubuntu1)" .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa-opencl-gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata	null	null	null	file_8221
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_12487
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_7584
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_17685
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_2786
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_18823
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_11301
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_14553
"\t.headerflags\t@\"EF_CUDA_TEXMODE_INDEPENDENT EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_S(...TRUNCATED)	null	"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa-opencl-gfx1100\"\n\t.amdhsa_code_object_version 5\n\t(...TRUNCATED)	null	null	null	file_5940

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