//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARHOST1X_UCLASS_H_INC_
#define ___ARHOST1X_UCLASS_H_INC_
// --------------------------------------------------------------------------
//
// Copyright (c) 2004-2012, NVIDIA Corp.
// All Rights Reserved.
//
// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
// the contents of this file may not be disclosed to third parties, copied or
// duplicated in any form, in whole or in part, without the prior written
// permission of NVIDIA Corp.
//
// RESTRICTED RIGHTS LEGEND:
// Use, duplication or disclosure by the Government is subject to restrictions
// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
// rights reserved under the Copyright Laws of the United States.
//
// --------------------------------------------------------------------------
//
// --------------------------------------------------------------------------
//
// Copyright (c) 2004, NVIDIA Corp.
// All Rights Reserved.
//
// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
// the contents of this file may not be disclosed to third parties, copied or
// duplicated in any form, in whole or in part, without the prior written
// permission of NVIDIA Corp.
//
// RESTRICTED RIGHTS LEGEND:
// Use, duplication or disclosure by the Government is subject to restrictions
// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
// rights reserved under the Copyright Laws of the United States.
//
// --------------------------------------------------------------------------
//
// Channel IDs
// class offsets are always relative to the class (based at 0)
// All Classes have the INCR_SYNCPT method
// For host, this method, immediately increments
// SYNCPT[indx], irrespective of the cond.
// Note that INCR_SYNCPT_CNTRL and INCR_SYNCPT_ERROR
// are included for consistency with host clients,
// but writes to INCR_SYNCPT_CNTRL have no effect
// on the operation of host1x, and because there
// are no condition fifos to overflow,
// INCR_SYNCPT_ERROR will never be set.
// --------------------------------------------------------------------------
//
// Copyright (c) 2004, NVIDIA Corp.
// All Rights Reserved.
//
// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
// the contents of this file may not be disclosed to third parties, copied or
// duplicated in any form, in whole or in part, without the prior written
// permission of NVIDIA Corp.
//
// RESTRICTED RIGHTS LEGEND:
// Use, duplication or disclosure by the Government is subject to restrictions
// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
// rights reserved under the Copyright Laws of the United States.
//
// --------------------------------------------------------------------------
//

// Register NV_CLASS_HOST_INCR_SYNCPT_0
#define NV_CLASS_HOST_INCR_SYNCPT_0                     _MK_ADDR_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_SECURE                      0x0
#define NV_CLASS_HOST_INCR_SYNCPT_0_WORD_COUNT                  0x1
#define NV_CLASS_HOST_INCR_SYNCPT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define NV_CLASS_HOST_INCR_SYNCPT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define NV_CLASS_HOST_INCR_SYNCPT_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
// Condition mapped from raise/wait
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_SHIFT                  _MK_SHIFT_CONST(8)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_FIELD                  (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_INCR_SYNCPT_0_COND_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_RANGE                  15:8
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_WOFFSET                        0x0
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_IMMEDIATE                      _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_OP_DONE                        _MK_ENUM_CONST(1)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_RD_DONE                        _MK_ENUM_CONST(2)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_REG_WR_SAFE                    _MK_ENUM_CONST(3)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_4                 _MK_ENUM_CONST(4)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_5                 _MK_ENUM_CONST(5)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_6                 _MK_ENUM_CONST(6)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_7                 _MK_ENUM_CONST(7)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_8                 _MK_ENUM_CONST(8)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_9                 _MK_ENUM_CONST(9)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_10                        _MK_ENUM_CONST(10)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_11                        _MK_ENUM_CONST(11)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_12                        _MK_ENUM_CONST(12)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_13                        _MK_ENUM_CONST(13)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_14                        _MK_ENUM_CONST(14)
#define NV_CLASS_HOST_INCR_SYNCPT_0_COND_COND_15                        _MK_ENUM_CONST(15)

// syncpt index value
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_FIELD                  (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_INCR_SYNCPT_0_INDX_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_RANGE                  7:0
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_WOFFSET                        0x0
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_0_INDX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0                       _MK_ADDR_CONST(0x1)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_SECURE                        0x0
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_WORD_COUNT                    0x1
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_RESET_MASK                    _MK_MASK_CONST(0x101)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_READ_MASK                     _MK_MASK_CONST(0x101)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x101)
// If NO_STALL is 1, then when fifos are full,
// INCR_SYNCPT methods will be dropped and the
// INCR_SYNCPT_ERROR[COND] bit will be set.
// If NO_STALL is 0, then when fifos are full,
// the client host interface will be stalled.
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_SHIFT                    _MK_SHIFT_CONST(8)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_FIELD                    (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_RANGE                    8:8
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_WOFFSET                  0x0
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_DEFAULT                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// If SOFT_RESET is set, then all internal state
// of the client syncpt block will be reset.
// To do soft reset, first set SOFT_RESET of
// all host1x clients affected, then clear all
// SOFT_RESETs.
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_FIELD                  (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_RANGE                  0:0
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_WOFFSET                        0x0
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INCR_SYNCPT_ERROR_0
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0                       _MK_ADDR_CONST(0x2)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_SECURE                        0x0
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_WORD_COUNT                    0x1
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// COND_STATUS[COND] is set if the fifo for COND overflows.
// This bit is sticky and will remain set until cleared.
// Cleared by writing 1.
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_SHIFT                     _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_FIELD                     (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_RANGE                     31:0
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_WOFFSET                   0x0
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_ERROR_0_COND_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// reserve locations for future expansion

// Reserved address 3 [0x3]

// Reserved address 4 [0x4]

// Reserved address 5 [0x5]

// Reserved address 6 [0x6]

// Reserved address 7 [0x7]
// just in case names were redefined using macros
// Wait on syncpt method
// Command dispatch will stall until
// SYNCPT[indx][NV_HOST1X_SYNCPT_THRESH_WIDTH-1:0] >= threshold[NV_HOST1X_SYNCPT_THRESH_WIDTH-1:0]
// The comparison takes into account the possibility of wrapping.
// Note that more bits are allocated for indx and threshold than may be used in an implementation
// Use NV_HOST1X_SYNCPT_NB_PTS for the number of syncpts, and
// NV_HOST1X_SYNCPT_THESH_WIDTH for the number of bits used by the comparison

// Register NV_CLASS_HOST_WAIT_SYNCPT_0
#define NV_CLASS_HOST_WAIT_SYNCPT_0                     _MK_ADDR_CONST(0x8)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_SECURE                      0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_0_WORD_COUNT                  0x1
#define NV_CLASS_HOST_WAIT_SYNCPT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_SHIFT                  _MK_SHIFT_CONST(24)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_FIELD                  (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_SHIFT)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_RANGE                  31:24
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_WOFFSET                        0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_INDX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_SHIFT                        _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_FIELD                        (_MK_MASK_CONST(0xffffff) << NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_SHIFT)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_RANGE                        23:0
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_WOFFSET                      0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_0_THRESH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Wait on syncpt method using base register
// Command dispatch will stall until
// SYNCPT[indx][NV_HOST1X_SYNCPT_THRESH_WIDTH-1:0] >= (SYNCPT_BASE[base_indx]+offset)
// The comparison takes into account the possibility of wrapping.
// Note that more bits are allocated for indx and base_indx than may be used in an implementation.
// Use NV_HOST1X_SYNCPT_NB_PTS for the number of syncpts,
// Use NV_HOST1X_SYNCPT_NB_BASES for the number of syncpt_bases, and
// NV_HOST1X_SYNCPT_THESH_WIDTH for the number of bits used by the comparison
// If NV_HOST1X_SYNCPT_THESH_WIDTH is greater than 16, offset is sign-extended before it is added to SYNCPT_BASE.

// Register NV_CLASS_HOST_WAIT_SYNCPT_BASE_0
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0                        _MK_ADDR_CONST(0x9)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_SECURE                         0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_WORD_COUNT                     0x1
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_SHIFT                     _MK_SHIFT_CONST(24)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_FIELD                     (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_SHIFT)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_RANGE                     31:24
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_WOFFSET                   0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_SHIFT                        _MK_SHIFT_CONST(16)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_FIELD                        (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_SHIFT)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_RANGE                        23:16
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_WOFFSET                      0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_BASE_INDX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_FIELD                   (_MK_MASK_CONST(0xffff) << NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_SHIFT)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_RANGE                   15:0
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_WOFFSET                 0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_BASE_0_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Wait on syncpt increment method
// Command dispatch will stall until the next time that SYNCPT[indx] is incremented.
// Note that more bits are allocated for indx than may be used in an implementation.
// Use NV_HOST1X_SYNCPT_NB_PTS for the number of syncpts.

// Register NV_CLASS_HOST_WAIT_SYNCPT_INCR_0
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0                        _MK_ADDR_CONST(0xa)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_SECURE                         0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_WORD_COUNT                     0x1
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_READ_MASK                      _MK_MASK_CONST(0xff000000)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_WRITE_MASK                     _MK_MASK_CONST(0xff000000)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_SHIFT                     _MK_SHIFT_CONST(24)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_FIELD                     (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_SHIFT)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_RANGE                     31:24
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_WOFFSET                   0x0
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_SYNCPT_INCR_0_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Load syncpt base method
// SYNCPT_BASE[indx] = value

// Register NV_CLASS_HOST_LOAD_SYNCPT_BASE_0
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0                        _MK_ADDR_CONST(0xb)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_SECURE                         0x0
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_WORD_COUNT                     0x1
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_SHIFT                        _MK_SHIFT_CONST(24)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_FIELD                        (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_SHIFT)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_RANGE                        31:24
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_WOFFSET                      0x0
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_BASE_INDX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_FIELD                    (_MK_MASK_CONST(0xffffff) << NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_SHIFT)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_RANGE                    23:0
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_WOFFSET                  0x0
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_LOAD_SYNCPT_BASE_0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Increment syncpt base method
// SYNCPT_BASE[indx] += offset

// Register NV_CLASS_HOST_INCR_SYNCPT_BASE_0
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0                        _MK_ADDR_CONST(0xc)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_SECURE                         0x0
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_SHIFT                        _MK_SHIFT_CONST(24)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_FIELD                        (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_RANGE                        31:24
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_WOFFSET                      0x0
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_BASE_INDX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_FIELD                   (_MK_MASK_CONST(0xffffff) << NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_SHIFT)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_RANGE                   23:0
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_WOFFSET                 0x0
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INCR_SYNCPT_BASE_0_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Clear method.  Any bits set in VECTOR will be cleared in the channel's RAISE
// vector.

// Register NV_CLASS_HOST_CLEAR_0
#define NV_CLASS_HOST_CLEAR_0                   _MK_ADDR_CONST(0xd)
#define NV_CLASS_HOST_CLEAR_0_SECURE                    0x0
#define NV_CLASS_HOST_CLEAR_0_WORD_COUNT                        0x1
#define NV_CLASS_HOST_CLEAR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_CLEAR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_CLEAR_0_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_CLEAR_0_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_CLEAR_0_VECTOR_SHIFT)
#define NV_CLASS_HOST_CLEAR_0_VECTOR_RANGE                      31:0
#define NV_CLASS_HOST_CLEAR_0_VECTOR_WOFFSET                    0x0
#define NV_CLASS_HOST_CLEAR_0_VECTOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_CLEAR_0_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Wait method.  Command dispatch will stall until any of the bits set in
// VECTOR become set in the channel's RAISE vector.

// Register NV_CLASS_HOST_WAIT_0
#define NV_CLASS_HOST_WAIT_0                    _MK_ADDR_CONST(0xe)
#define NV_CLASS_HOST_WAIT_0_SECURE                     0x0
#define NV_CLASS_HOST_WAIT_0_WORD_COUNT                         0x1
#define NV_CLASS_HOST_WAIT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_0_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_WAIT_0_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_WAIT_0_VECTOR_SHIFT)
#define NV_CLASS_HOST_WAIT_0_VECTOR_RANGE                       31:0
#define NV_CLASS_HOST_WAIT_0_VECTOR_WOFFSET                     0x0
#define NV_CLASS_HOST_WAIT_0_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_0_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Wait w/ interrupt method.  Identical to the WAIT method except an interrupt
// will be triggered when the WAIT requirement is satisfied.

// Register NV_CLASS_HOST_WAIT_WITH_INTR_0
#define NV_CLASS_HOST_WAIT_WITH_INTR_0                  _MK_ADDR_CONST(0xf)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_SECURE                   0x0
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_WORD_COUNT                       0x1
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_SHIFT)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_RANGE                     31:0
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_WOFFSET                   0x0
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_WAIT_WITH_INTR_0_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Delay number of microseconds.  Command dispatch will stall until the number
// of microseconds indicated in NUSEC has passed.  The timing of microseconds
// is controlled by the USEC_CLK register.

// Register NV_CLASS_HOST_DELAY_USEC_0
#define NV_CLASS_HOST_DELAY_USEC_0                      _MK_ADDR_CONST(0x10)
#define NV_CLASS_HOST_DELAY_USEC_0_SECURE                       0x0
#define NV_CLASS_HOST_DELAY_USEC_0_WORD_COUNT                   0x1
#define NV_CLASS_HOST_DELAY_USEC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define NV_CLASS_HOST_DELAY_USEC_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
// Enough for 1.05 seconds
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_FIELD                  (_MK_MASK_CONST(0xfffff) << NV_CLASS_HOST_DELAY_USEC_0_NUSEC_SHIFT)
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_RANGE                  19:0
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_WOFFSET                        0x0
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_DELAY_USEC_0_NUSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// This register value will initialize the high 32 bits of
// tick count value in the host clock counter

// Register NV_CLASS_HOST_TICKCOUNT_HI_0
#define NV_CLASS_HOST_TICKCOUNT_HI_0                    _MK_ADDR_CONST(0x11)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_SECURE                     0x0
#define NV_CLASS_HOST_TICKCOUNT_HI_0_WORD_COUNT                         0x1
#define NV_CLASS_HOST_TICKCOUNT_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
// read or write tick count
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_SHIFT                     _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_FIELD                     (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_SHIFT)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_RANGE                     31:0
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_WOFFSET                   0x0
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_HI_0_TICKS_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// This register value will initialize the low 32 bits of
// tick count value in the host clock counter

// Register NV_CLASS_HOST_TICKCOUNT_LO_0
#define NV_CLASS_HOST_TICKCOUNT_LO_0                    _MK_ADDR_CONST(0x12)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_SECURE                     0x0
#define NV_CLASS_HOST_TICKCOUNT_LO_0_WORD_COUNT                         0x1
#define NV_CLASS_HOST_TICKCOUNT_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
// read or write tick count
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_SHIFT                     _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_FIELD                     (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_SHIFT)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_RANGE                     31:0
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_WOFFSET                   0x0
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCOUNT_LO_0_TICKS_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// This register write enables the tick counter on the host clock to start counting

// Register NV_CLASS_HOST_TICKCTRL_0
#define NV_CLASS_HOST_TICKCTRL_0                        _MK_ADDR_CONST(0x13)
#define NV_CLASS_HOST_TICKCTRL_0_SECURE                         0x0
#define NV_CLASS_HOST_TICKCTRL_0_WORD_COUNT                     0x1
#define NV_CLASS_HOST_TICKCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define NV_CLASS_HOST_TICKCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
// Enable or Disable tick counter
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_SHIFT)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_RANGE                   0:0
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_WOFFSET                 0x0
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_TICKCTRL_0_TICKCNT_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Reserved address 20 [0x14]

// Reserved address 21 [0x15]

// Reserved address 22 [0x16]

// Reserved address 23 [0x17]

// Reserved address 24 [0x18]

// Reserved address 25 [0x19]

// Reserved address 26 [0x1a]

// Reserved address 27 [0x1b]

// Reserved address 28 [0x1c]

// Reserved address 29 [0x1d]

// Reserved address 30 [0x1e]

// Reserved address 31 [0x1f]

// Reserved address 32 [0x20]

// Reserved address 33 [0x21]

// Reserved address 34 [0x22]

// Reserved address 35 [0x23]

// Reserved address 36 [0x24]

// Reserved address 37 [0x25]

// Reserved address 38 [0x26]

// Reserved address 39 [0x27]

// Reserved address 40 [0x28]

// Reserved address 41 [0x29]

// Reserved address 42 [0x2a]
// Indirect addressing
// These registers (along with INDDATA) are used to indirectly read/write either
// register or memory.  Host registers are not accessible using this interface.
// If AUTOINC is set, INDOFFSET increments by 4 on every access of INDDATA.
//
// Either INDCTRL/INDOFF2 or INDOFF can be used, but INDOFF may not be able to
// address all memory in chips with large memory maps.  The rundundant bits in
// INDCTRL and INDOFF are shared, so writing either offset sets those bits.
//
// NOTE: due to a HW bug (bug #343175) the following restrictions apply to the
// use of indirect memory writes:
// (1) at initialization time, do a dummy indirect write (with all byte enables set to zero), and
// (2) dedicate an MLOCK for indirect memory writes, then before a channel issues
//     a set of indirect memory writes it must acquire this MLOCK; after the writes
//     have been issued, the MLOCK is released -- this will restrict the use of
//     indirect memory writes to a single channel at a time.

// Register NV_CLASS_HOST_INDCTRL_0
#define NV_CLASS_HOST_INDCTRL_0                 _MK_ADDR_CONST(0x2b)
#define NV_CLASS_HOST_INDCTRL_0_SECURE                  0x0
#define NV_CLASS_HOST_INDCTRL_0_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDCTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_READ_MASK                       _MK_MASK_CONST(0xfc000003)
#define NV_CLASS_HOST_INDCTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xfc000003)
// Byte enables.  Will apply to all subsequent data transactions.  Not applicable for reads.
#define NV_CLASS_HOST_INDCTRL_0_INDBE_SHIFT                     _MK_SHIFT_CONST(28)
#define NV_CLASS_HOST_INDCTRL_0_INDBE_FIELD                     (_MK_MASK_CONST(0xf) << NV_CLASS_HOST_INDCTRL_0_INDBE_SHIFT)
#define NV_CLASS_HOST_INDCTRL_0_INDBE_RANGE                     31:28
#define NV_CLASS_HOST_INDCTRL_0_INDBE_WOFFSET                   0x0
#define NV_CLASS_HOST_INDCTRL_0_INDBE_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_INDBE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_INDBE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_INDBE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Auto increment of read/write address
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_SHIFT                   _MK_SHIFT_CONST(27)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_FIELD                   (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDCTRL_0_AUTOINC_SHIFT)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_RANGE                   27:27
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_WOFFSET                 0x0
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_DISABLE                 _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDCTRL_0_AUTOINC_ENABLE                  _MK_ENUM_CONST(1)

// Route return data to spool FIFO, only applicable to reads
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_SHIFT                     _MK_SHIFT_CONST(26)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_FIELD                     (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDCTRL_0_SPOOL_SHIFT)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_RANGE                     26:26
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_WOFFSET                   0x0
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_DISABLE                   _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDCTRL_0_SPOOL_ENABLE                    _MK_ENUM_CONST(1)

// Access type: indirect register or indirect framebuffer
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_SHIFT                   _MK_SHIFT_CONST(1)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_FIELD                   (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDCTRL_0_ACCTYPE_SHIFT)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_RANGE                   1:1
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_WOFFSET                 0x0
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_REG                     _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDCTRL_0_ACCTYPE_FB                      _MK_ENUM_CONST(1)

// Read/write
#define NV_CLASS_HOST_INDCTRL_0_RWN_SHIFT                       _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDCTRL_0_RWN_FIELD                       (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDCTRL_0_RWN_SHIFT)
#define NV_CLASS_HOST_INDCTRL_0_RWN_RANGE                       0:0
#define NV_CLASS_HOST_INDCTRL_0_RWN_WOFFSET                     0x0
#define NV_CLASS_HOST_INDCTRL_0_RWN_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_RWN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_RWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_RWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDCTRL_0_RWN_WRITE                       _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDCTRL_0_RWN_READ                        _MK_ENUM_CONST(1)


// Register NV_CLASS_HOST_INDOFF2_0
#define NV_CLASS_HOST_INDOFF2_0                 _MK_ADDR_CONST(0x2c)
#define NV_CLASS_HOST_INDOFF2_0_SECURE                  0x0
#define NV_CLASS_HOST_INDOFF2_0_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDOFF2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
#define NV_CLASS_HOST_INDOFF2_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
// ACCTYPE=FB: framebuffer address
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_SHIFT                 _MK_SHIFT_CONST(2)
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_FIELD                 (_MK_MASK_CONST(0x3fffffff) << NV_CLASS_HOST_INDOFF2_0_INDOFFSET_SHIFT)
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_RANGE                 31:2
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_WOFFSET                       0x0
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDOFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// ACCTYPE=REG: register module ID
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_SHIFT                  _MK_SHIFT_CONST(18)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_FIELD                  (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_INDOFF2_0_INDMODID_SHIFT)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_RANGE                  25:18
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_WOFFSET                        0x0
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_HOST1X                 _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_MPE                    _MK_ENUM_CONST(1)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_VI                     _MK_ENUM_CONST(2)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_EPP                    _MK_ENUM_CONST(3)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_ISP                    _MK_ENUM_CONST(4)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_GR2D                   _MK_ENUM_CONST(5)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_GR3D                   _MK_ENUM_CONST(6)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_DISPLAY                        _MK_ENUM_CONST(8)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_TVO                    _MK_ENUM_CONST(11)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_DISPLAYB                       _MK_ENUM_CONST(9)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_DSI                    _MK_ENUM_CONST(12)
#define NV_CLASS_HOST_INDOFF2_0_INDMODID_HDMI                   _MK_ENUM_CONST(10)

// ACCTYPE=REG: register offset ([15:0])
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_SHIFT                        _MK_SHIFT_CONST(2)
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_FIELD                        (_MK_MASK_CONST(0xffff) << NV_CLASS_HOST_INDOFF2_0_INDROFFSET_SHIFT)
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_RANGE                        17:2
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_WOFFSET                      0x0
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF2_0_INDROFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDOFF_0
#define NV_CLASS_HOST_INDOFF_0                  _MK_ADDR_CONST(0x2d)
#define NV_CLASS_HOST_INDOFF_0_SECURE                   0x0
#define NV_CLASS_HOST_INDOFF_0_WORD_COUNT                       0x1
#define NV_CLASS_HOST_INDOFF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDOFF_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
// Byte enables.  Will apply to all subsequent data transactions.  Not applicable for reads.
#define NV_CLASS_HOST_INDOFF_0_INDBE_SHIFT                      _MK_SHIFT_CONST(28)
#define NV_CLASS_HOST_INDOFF_0_INDBE_FIELD                      (_MK_MASK_CONST(0xf) << NV_CLASS_HOST_INDOFF_0_INDBE_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_INDBE_RANGE                      31:28
#define NV_CLASS_HOST_INDOFF_0_INDBE_WOFFSET                    0x0
#define NV_CLASS_HOST_INDOFF_0_INDBE_DEFAULT                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDBE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Auto increment of read/write address
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_SHIFT                    _MK_SHIFT_CONST(27)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_FIELD                    (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDOFF_0_AUTOINC_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_RANGE                    27:27
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_WOFFSET                  0x0
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_DEFAULT                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_DISABLE                  _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDOFF_0_AUTOINC_ENABLE                   _MK_ENUM_CONST(1)

// Route return data to spool FIFO, only applicable to reads
#define NV_CLASS_HOST_INDOFF_0_SPOOL_SHIFT                      _MK_SHIFT_CONST(26)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_FIELD                      (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDOFF_0_SPOOL_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_RANGE                      26:26
#define NV_CLASS_HOST_INDOFF_0_SPOOL_WOFFSET                    0x0
#define NV_CLASS_HOST_INDOFF_0_SPOOL_DEFAULT                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_DISABLE                    _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDOFF_0_SPOOL_ENABLE                     _MK_ENUM_CONST(1)

// ACCTYPE=FB: framebuffer address
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_SHIFT                  _MK_SHIFT_CONST(2)
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_FIELD                  (_MK_MASK_CONST(0xffffff) << NV_CLASS_HOST_INDOFF_0_INDOFFSET_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_RANGE                  25:2
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_WOFFSET                        0x0
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDOFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// ACCTYPE=REG: register module ID
#define NV_CLASS_HOST_INDOFF_0_INDMODID_SHIFT                   _MK_SHIFT_CONST(18)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_FIELD                   (_MK_MASK_CONST(0xff) << NV_CLASS_HOST_INDOFF_0_INDMODID_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_RANGE                   25:18
#define NV_CLASS_HOST_INDOFF_0_INDMODID_WOFFSET                 0x0
#define NV_CLASS_HOST_INDOFF_0_INDMODID_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_HOST1X                  _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_MPE                     _MK_ENUM_CONST(1)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_VI                      _MK_ENUM_CONST(2)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_EPP                     _MK_ENUM_CONST(3)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_ISP                     _MK_ENUM_CONST(4)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_GR2D                    _MK_ENUM_CONST(5)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_GR3D                    _MK_ENUM_CONST(6)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_DISPLAY                 _MK_ENUM_CONST(8)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_TVO                     _MK_ENUM_CONST(11)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_DISPLAYB                        _MK_ENUM_CONST(9)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_DSI                     _MK_ENUM_CONST(12)
#define NV_CLASS_HOST_INDOFF_0_INDMODID_HDMI                    _MK_ENUM_CONST(10)

// ACCTYPE=REG: register offset ([15:0])
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_SHIFT                 _MK_SHIFT_CONST(2)
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_FIELD                 (_MK_MASK_CONST(0xffff) << NV_CLASS_HOST_INDOFF_0_INDROFFSET_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_RANGE                 17:2
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_WOFFSET                       0x0
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_INDROFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Access type: indirect register or indirect framebuffer
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_SHIFT                    _MK_SHIFT_CONST(1)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_FIELD                    (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDOFF_0_ACCTYPE_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_RANGE                    1:1
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_WOFFSET                  0x0
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_REG                      _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDOFF_0_ACCTYPE_FB                       _MK_ENUM_CONST(1)

// Read/write
#define NV_CLASS_HOST_INDOFF_0_RWN_SHIFT                        _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDOFF_0_RWN_FIELD                        (_MK_MASK_CONST(0x1) << NV_CLASS_HOST_INDOFF_0_RWN_SHIFT)
#define NV_CLASS_HOST_INDOFF_0_RWN_RANGE                        0:0
#define NV_CLASS_HOST_INDOFF_0_RWN_WOFFSET                      0x0
#define NV_CLASS_HOST_INDOFF_0_RWN_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_RWN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_RWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_RWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDOFF_0_RWN_WRITE                        _MK_ENUM_CONST(0)
#define NV_CLASS_HOST_INDOFF_0_RWN_READ                 _MK_ENUM_CONST(1)

// These registers, when written, either writes to the data to the INDOFFSET in
// INDOFF or triggers a read of the offset at INDOFFSET.

// Register NV_CLASS_HOST_INDDATA_0
#define NV_CLASS_HOST_INDDATA_0                 _MK_ADDR_CONST(0x2e)
#define NV_CLASS_HOST_INDDATA_0_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_0_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_0_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_0_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_0_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_0_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_0_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_0_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_0_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA
#define NV_CLASS_HOST_INDDATA                   _MK_ADDR_CONST(0x2e)
#define NV_CLASS_HOST_INDDATA_SECURE                    0x0
#define NV_CLASS_HOST_INDDATA_WORD_COUNT                        0x1
#define NV_CLASS_HOST_INDDATA_RESET_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_RESET_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_INDDATA_SHIFT                     _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_INDDATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_INDDATA_RANGE                     31:0
#define NV_CLASS_HOST_INDDATA_INDDATA_WOFFSET                   0x0
#define NV_CLASS_HOST_INDDATA_INDDATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_INDDATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_INDDATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_INDDATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_1
#define NV_CLASS_HOST_INDDATA_1                 _MK_ADDR_CONST(0x2f)
#define NV_CLASS_HOST_INDDATA_1_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_1_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_1_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_1_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_1_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_1_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_1_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_1_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_1_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_1_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_1_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_2
#define NV_CLASS_HOST_INDDATA_2                 _MK_ADDR_CONST(0x30)
#define NV_CLASS_HOST_INDDATA_2_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_2_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_2_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_2_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_2_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_2_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_2_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_2_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_2_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_2_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_2_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_3
#define NV_CLASS_HOST_INDDATA_3                 _MK_ADDR_CONST(0x31)
#define NV_CLASS_HOST_INDDATA_3_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_3_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_3_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_3_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_3_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_3_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_3_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_3_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_3_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_3_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_3_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_4
#define NV_CLASS_HOST_INDDATA_4                 _MK_ADDR_CONST(0x32)
#define NV_CLASS_HOST_INDDATA_4_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_4_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_4_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_4_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_4_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_4_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_4_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_4_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_4_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_4_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_4_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_5
#define NV_CLASS_HOST_INDDATA_5                 _MK_ADDR_CONST(0x33)
#define NV_CLASS_HOST_INDDATA_5_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_5_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_5_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_5_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_5_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_5_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_5_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_5_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_5_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_5_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_5_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_6
#define NV_CLASS_HOST_INDDATA_6                 _MK_ADDR_CONST(0x34)
#define NV_CLASS_HOST_INDDATA_6_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_6_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_6_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_6_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_6_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_6_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_6_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_6_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_6_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_6_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_6_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_7
#define NV_CLASS_HOST_INDDATA_7                 _MK_ADDR_CONST(0x35)
#define NV_CLASS_HOST_INDDATA_7_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_7_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_7_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_7_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_7_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_7_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_7_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_7_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_7_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_7_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_7_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_8
#define NV_CLASS_HOST_INDDATA_8                 _MK_ADDR_CONST(0x36)
#define NV_CLASS_HOST_INDDATA_8_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_8_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_8_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_8_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_8_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_8_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_8_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_8_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_8_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_8_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_8_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_9
#define NV_CLASS_HOST_INDDATA_9                 _MK_ADDR_CONST(0x37)
#define NV_CLASS_HOST_INDDATA_9_SECURE                  0x0
#define NV_CLASS_HOST_INDDATA_9_WORD_COUNT                      0x1
#define NV_CLASS_HOST_INDDATA_9_RESET_VAL                       _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_RESET_MASK                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_9_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_9_INDDATA_SHIFT                   _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_9_INDDATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_9_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_9_INDDATA_RANGE                   31:0
#define NV_CLASS_HOST_INDDATA_9_INDDATA_WOFFSET                 0x0
#define NV_CLASS_HOST_INDDATA_9_INDDATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_INDDATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_INDDATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_9_INDDATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_10
#define NV_CLASS_HOST_INDDATA_10                        _MK_ADDR_CONST(0x38)
#define NV_CLASS_HOST_INDDATA_10_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_10_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_10_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_10_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_10_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_10_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_10_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_10_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_10_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_10_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_10_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_11
#define NV_CLASS_HOST_INDDATA_11                        _MK_ADDR_CONST(0x39)
#define NV_CLASS_HOST_INDDATA_11_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_11_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_11_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_11_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_11_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_11_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_11_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_11_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_11_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_11_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_11_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_12
#define NV_CLASS_HOST_INDDATA_12                        _MK_ADDR_CONST(0x3a)
#define NV_CLASS_HOST_INDDATA_12_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_12_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_12_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_12_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_12_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_12_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_12_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_12_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_12_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_12_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_12_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_13
#define NV_CLASS_HOST_INDDATA_13                        _MK_ADDR_CONST(0x3b)
#define NV_CLASS_HOST_INDDATA_13_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_13_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_13_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_13_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_13_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_13_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_13_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_13_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_13_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_13_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_13_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_14
#define NV_CLASS_HOST_INDDATA_14                        _MK_ADDR_CONST(0x3c)
#define NV_CLASS_HOST_INDDATA_14_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_14_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_14_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_14_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_14_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_14_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_14_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_14_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_14_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_14_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_14_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_15
#define NV_CLASS_HOST_INDDATA_15                        _MK_ADDR_CONST(0x3d)
#define NV_CLASS_HOST_INDDATA_15_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_15_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_15_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_15_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_15_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_15_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_15_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_15_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_15_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_15_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_15_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_16
#define NV_CLASS_HOST_INDDATA_16                        _MK_ADDR_CONST(0x3e)
#define NV_CLASS_HOST_INDDATA_16_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_16_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_16_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_16_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_16_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_16_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_16_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_16_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_16_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_16_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_16_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_17
#define NV_CLASS_HOST_INDDATA_17                        _MK_ADDR_CONST(0x3f)
#define NV_CLASS_HOST_INDDATA_17_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_17_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_17_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_17_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_17_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_17_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_17_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_17_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_17_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_17_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_17_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_18
#define NV_CLASS_HOST_INDDATA_18                        _MK_ADDR_CONST(0x40)
#define NV_CLASS_HOST_INDDATA_18_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_18_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_18_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_18_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_18_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_18_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_18_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_18_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_18_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_18_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_18_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_19
#define NV_CLASS_HOST_INDDATA_19                        _MK_ADDR_CONST(0x41)
#define NV_CLASS_HOST_INDDATA_19_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_19_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_19_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_19_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_19_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_19_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_19_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_19_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_19_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_19_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_19_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_20
#define NV_CLASS_HOST_INDDATA_20                        _MK_ADDR_CONST(0x42)
#define NV_CLASS_HOST_INDDATA_20_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_20_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_20_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_20_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_20_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_20_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_20_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_20_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_20_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_20_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_20_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_21
#define NV_CLASS_HOST_INDDATA_21                        _MK_ADDR_CONST(0x43)
#define NV_CLASS_HOST_INDDATA_21_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_21_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_21_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_21_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_21_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_21_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_21_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_21_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_21_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_21_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_21_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_22
#define NV_CLASS_HOST_INDDATA_22                        _MK_ADDR_CONST(0x44)
#define NV_CLASS_HOST_INDDATA_22_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_22_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_22_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_22_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_22_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_22_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_22_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_22_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_22_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_22_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_22_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_23
#define NV_CLASS_HOST_INDDATA_23                        _MK_ADDR_CONST(0x45)
#define NV_CLASS_HOST_INDDATA_23_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_23_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_23_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_23_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_23_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_23_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_23_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_23_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_23_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_23_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_23_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_24
#define NV_CLASS_HOST_INDDATA_24                        _MK_ADDR_CONST(0x46)
#define NV_CLASS_HOST_INDDATA_24_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_24_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_24_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_24_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_24_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_24_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_24_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_24_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_24_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_24_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_24_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_25
#define NV_CLASS_HOST_INDDATA_25                        _MK_ADDR_CONST(0x47)
#define NV_CLASS_HOST_INDDATA_25_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_25_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_25_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_25_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_25_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_25_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_25_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_25_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_25_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_25_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_25_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_26
#define NV_CLASS_HOST_INDDATA_26                        _MK_ADDR_CONST(0x48)
#define NV_CLASS_HOST_INDDATA_26_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_26_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_26_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_26_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_26_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_26_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_26_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_26_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_26_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_26_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_26_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_27
#define NV_CLASS_HOST_INDDATA_27                        _MK_ADDR_CONST(0x49)
#define NV_CLASS_HOST_INDDATA_27_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_27_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_27_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_27_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_27_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_27_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_27_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_27_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_27_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_27_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_27_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_28
#define NV_CLASS_HOST_INDDATA_28                        _MK_ADDR_CONST(0x4a)
#define NV_CLASS_HOST_INDDATA_28_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_28_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_28_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_28_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_28_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_28_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_28_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_28_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_28_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_28_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_28_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_29
#define NV_CLASS_HOST_INDDATA_29                        _MK_ADDR_CONST(0x4b)
#define NV_CLASS_HOST_INDDATA_29_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_29_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_29_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_29_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_29_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_29_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_29_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_29_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_29_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_29_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_29_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register NV_CLASS_HOST_INDDATA_30
#define NV_CLASS_HOST_INDDATA_30                        _MK_ADDR_CONST(0x4c)
#define NV_CLASS_HOST_INDDATA_30_SECURE                         0x0
#define NV_CLASS_HOST_INDDATA_30_WORD_COUNT                     0x1
#define NV_CLASS_HOST_INDDATA_30_RESET_VAL                      _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_RESET_MASK                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define NV_CLASS_HOST_INDDATA_30_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// read or write data
#define NV_CLASS_HOST_INDDATA_30_INDDATA_SHIFT                  _MK_SHIFT_CONST(0)
#define NV_CLASS_HOST_INDDATA_30_INDDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << NV_CLASS_HOST_INDDATA_30_INDDATA_SHIFT)
#define NV_CLASS_HOST_INDDATA_30_INDDATA_RANGE                  31:0
#define NV_CLASS_HOST_INDDATA_30_INDDATA_WOFFSET                        0x0
#define NV_CLASS_HOST_INDDATA_30_INDDATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_INDDATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_INDDATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define NV_CLASS_HOST_INDDATA_30_INDDATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 77 [0x4d]

//
// REGISTER LIST
//
#define LIST_ARHOST1X_UCLASS_REGS(_op_) \
_op_(NV_CLASS_HOST_INCR_SYNCPT_0) \
_op_(NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0) \
_op_(NV_CLASS_HOST_INCR_SYNCPT_ERROR_0) \
_op_(NV_CLASS_HOST_WAIT_SYNCPT_0) \
_op_(NV_CLASS_HOST_WAIT_SYNCPT_BASE_0) \
_op_(NV_CLASS_HOST_WAIT_SYNCPT_INCR_0) \
_op_(NV_CLASS_HOST_LOAD_SYNCPT_BASE_0) \
_op_(NV_CLASS_HOST_INCR_SYNCPT_BASE_0) \
_op_(NV_CLASS_HOST_CLEAR_0) \
_op_(NV_CLASS_HOST_WAIT_0) \
_op_(NV_CLASS_HOST_WAIT_WITH_INTR_0) \
_op_(NV_CLASS_HOST_DELAY_USEC_0) \
_op_(NV_CLASS_HOST_TICKCOUNT_HI_0) \
_op_(NV_CLASS_HOST_TICKCOUNT_LO_0) \
_op_(NV_CLASS_HOST_TICKCTRL_0) \
_op_(NV_CLASS_HOST_INDCTRL_0) \
_op_(NV_CLASS_HOST_INDOFF2_0) \
_op_(NV_CLASS_HOST_INDOFF_0) \
_op_(NV_CLASS_HOST_INDDATA_0) \
_op_(NV_CLASS_HOST_INDDATA) \
_op_(NV_CLASS_HOST_INDDATA_1) \
_op_(NV_CLASS_HOST_INDDATA_2) \
_op_(NV_CLASS_HOST_INDDATA_3) \
_op_(NV_CLASS_HOST_INDDATA_4) \
_op_(NV_CLASS_HOST_INDDATA_5) \
_op_(NV_CLASS_HOST_INDDATA_6) \
_op_(NV_CLASS_HOST_INDDATA_7) \
_op_(NV_CLASS_HOST_INDDATA_8) \
_op_(NV_CLASS_HOST_INDDATA_9) \
_op_(NV_CLASS_HOST_INDDATA_10) \
_op_(NV_CLASS_HOST_INDDATA_11) \
_op_(NV_CLASS_HOST_INDDATA_12) \
_op_(NV_CLASS_HOST_INDDATA_13) \
_op_(NV_CLASS_HOST_INDDATA_14) \
_op_(NV_CLASS_HOST_INDDATA_15) \
_op_(NV_CLASS_HOST_INDDATA_16) \
_op_(NV_CLASS_HOST_INDDATA_17) \
_op_(NV_CLASS_HOST_INDDATA_18) \
_op_(NV_CLASS_HOST_INDDATA_19) \
_op_(NV_CLASS_HOST_INDDATA_20) \
_op_(NV_CLASS_HOST_INDDATA_21) \
_op_(NV_CLASS_HOST_INDDATA_22) \
_op_(NV_CLASS_HOST_INDDATA_23) \
_op_(NV_CLASS_HOST_INDDATA_24) \
_op_(NV_CLASS_HOST_INDDATA_25) \
_op_(NV_CLASS_HOST_INDDATA_26) \
_op_(NV_CLASS_HOST_INDDATA_27) \
_op_(NV_CLASS_HOST_INDDATA_28) \
_op_(NV_CLASS_HOST_INDDATA_29) \
_op_(NV_CLASS_HOST_INDDATA_30)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_NV_CLASS_HOST      0x00000000

//
// ARHOST1X_UCLASS REGISTER BANKS
//

#define NV_CLASS_HOST0_FIRST_REG 0x0000 // NV_CLASS_HOST_INCR_SYNCPT_0
#define NV_CLASS_HOST0_LAST_REG 0x0002 // NV_CLASS_HOST_INCR_SYNCPT_ERROR_0
#define NV_CLASS_HOST1_FIRST_REG 0x0008 // NV_CLASS_HOST_WAIT_SYNCPT_0
#define NV_CLASS_HOST1_LAST_REG 0x0013 // NV_CLASS_HOST_TICKCTRL_0
#define NV_CLASS_HOST2_FIRST_REG 0x002b // NV_CLASS_HOST_INDCTRL_0
#define NV_CLASS_HOST2_LAST_REG 0x004c // NV_CLASS_HOST_INDDATA_30

#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

#endif // ifndef ___ARHOST1X_UCLASS_H_INC_
