Question: I have a state diagram that is consisted of 3 states and in reset it comes to state s0 then if an event happen on start signal goes to state 2 and statye there for 15 clock sycle and then after that goes to state 3 and then back to state s0.
My question is that when VHDL coding how could I do the 15 clock delay of state 2.
I know that a counter needs to be there but it is not clear for me how to do the VHDL coding.
Could any one please give me some help.
Thank you

Answer: 
A capacitor "drops voltage" only if it is used as a voltage divider in conjuction with another impedance. You would have gotten the same result if you had used a resistor in this configuration. In this case, the second impedance is the input impedance of your voltmeter, which is probably 10MΩ or more.
In order to drop voltage, first the capacitor has to charge up. And in order to charge up it needs a current, which clearly that circuit doesn't have. 

Just connecting the open ends would be a bad idea; put a resistor in series.