Question: Project type :- Spring-boot JPA project

Hi,
I have below Rest service which increments a number in database.

```
  @RestController
    public class IncrementController {

    @Autowired
    MyNumberRepository mynumberRepository;

    @GetMapping(path="/incrementnumber")
    public String incrementNumber(){    
        Optional<MyNumber> mynumber = mynumberRepository.findById(1);
        int i = mynumber.get().getNumber();

        System.out.println("value of no is "+i);
        i = i+1;
        System.out.println("value of no post increment is "+i);
        mynumber.get().setNumber(i);

        MyNumber entity = new MyNumber();
        entity.setId(1);
        entity.setNumber(i);

        mynumberRepository.save(entity);
        return "done";      
    }   
}

```

Entity is as below :-

```
    @Entity
@Table(name = "my_number")
public class MyNumber {

    @Id
    private Integer id;

    private Integer number;

    public Integer getId() {
        return id;
    }

    public void setId(Integer id) {
        this.id = id;
    }

    public Integer getNumber() {
        return number;
    }

    public void setNumber(Integer number) {
        this.number = number;
    }
 }

```

Below is the Repository :-

```
   public interface MyNumberRepository extends JpaRepository<MyNumber, Integer>{

   }

```

The service works well when I call increment number sequentially , but when concurrent threads call the incrementservice then i get non consistent results. How can I handle this situation ?

Also have to deploy the app on multiple places and connecting to same DB. i.e Scalability concern.

Thanks,
Rahul

Answer: 
You need to model the pull-up resistor. In your test bench, assign 'H' (driving a weak one) to your tri-state signal:

```
o_sample_trig <= 'H';

```

You also probably need to fix your second process and add a conditional for the clock signal. What you have might simulate, but it likely won't synthesize into hardware.
according to Pedroni's book you cannot use a in/out port in that way and you should configure Tristate buffer in the following way:

```
1 ------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------
5 ENTITY bidir IS
6 PORT (a, b: IN STD_LOGIC;
7 c: INOUT STD_LOGIC;
8 d: OUT STD_LOGIC);
9 END ENTITY;
10 ------------------------------
11 ARCHITECTURE arch1 OF bidir IS
12 BEGIN
13 c <= a WHEN b='1' ELSE 'Z';
14 d <= c;
15 END ARCHITECTURE;
16 ------------------------------
17 ARCHITECTURE arch2 OF bidir IS
18 BEGIN
19 PROCESS (a, b)
20 BEGIN
21 d <= c;
22 IF (b='1') THEN c <= a;
23 ELSE c <= 'Z';
24 END IF;
25 END PROCESS;
26 END ARCHITECTURE;
27 ------------------------------

```

using above code I managed to actually synthesize a tristate buffer.