Question: PWM Freq : 30 HZ and 5% Duty cycle, uC internal ADC sampling time is configurable.
any limitations with ADC sampling time & Duty cycle of PWM should be considered for choosing RC ?

Answer: 
A rule of thumb is to use a 10:1 ratio of PWM frequency to filter cutoff. This will reduce ripple so that you have a nice "flat" signal.

So for your values that would be an RC cutoff of 3Hz, which is pretty low and will result in long settling times whenever the duty cycle changes.

If your system allows it, I would recomend upping your PWM freq. to 1kHz or 10kHz, thus allowing you to use a much higher RC cutoff frequency and giving you a fast response time to any changes in duty cycle.
This sounds like an RC servo control signal (0.5 to 2 ms or so pulse width every 30 ms) not a true PWM signal.

Smoothing it adequately to read with an ADC with any accuracy is a losing game unless you can tolerate settling times of about a second per Aaron's answer.

Instead, use a timer peripheral on your MCU to measure the pulse width directly.