Question: I need to determine a circuit's response to variations in component values. What are common go-to methods for this?

**Background**: I'm a growing novice in electronics design. So, my question is about common, de facto strategies accepted by experienced hobbyists and professionals alike. What for? To analyze how a circuit behaves for different combinations of its components' values (and other parameters). And to do so in a structured, systematic, efficient way.

My first thought is a SPICE simulation. But I would like to confirm whether this is 'it' or whether there are other approaches that I'm unaware of. 

**Context**: I have a simple optocoupler circuit as shown below. The left side (1) operates on a different potential than the right (2). And a MCU on the right needs to read an analog signal on the left (`V_ana_1`). Hence the optocoupler. I use it to convert `V_ana_1` to `V_ana_2` which then is fed to the MCU.

Now the optocoupler's response is not linear. So I would like to **choose `R1` and `R2` such that** `V_ana_2`'s range falls within the sensitive (as opposed to the saturated) region of this response for a given `V_ana_1` range of, say, 2-3 V.

What's a good way to go about doing this without physically and manually trying out different resistor values? (Which is what I did, which is why I'm asking this question - that was a pain.)

![schematic](https://i.stack.imgur.com/zwURr.png)

[simulate this circuit](/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fzwURr.png) – Schematic created using [CircuitLab](https://www.circuitlab.com/)

Answer: 
* The best way is to apply worst case tolerances over T and V with some margin for vendor variation, aging must be done for reliable production designs.
* Often specs for worst case V are given for CMOS at Vcc-10% at 25'C and over T range.
* if design cannot meet worst case then Monte Carlo methods for parameters like dielectric constant of PCB on controlled impedances, trace accuracy etc. or pay for TDR coupon tests done for Zo.
* The best way to verify a design is test to functional failure (HASS) during DVT to determine margins and root cause. e.g. vary Xtal f over spec range incl tolerance at 25'C and temp. by injection and Vmin at cycle temps with high RH with vibration to board.
* Every test should have a margin budget verified, e.g. comparator asymmetry, regulator error margin etc, surge or ripple current/rating, noise margin, timing margin, real-time stack margin, buffer overflow margin etc etc.
* the best design has DFT and these parameters defined in the design spec. then DVT is easier to perform. DVT= Design Validation Test. DFT=Design for Testability). This enables good fault detection/isolation for self-Test, Functional(FT) and In-cct test(ICT) then sys test.
* Once the functional design is verified, solderability is the #1 cause of poor yields, which gets into bad design, process, or procedure
* Each test should fit onto 1 page with method illustrated and equip. used
The most common method is to use SPICE simulator. Go here,

<http://www.linear.com/designtools/software/#LTspice>

Download and install. It is free. 
It has many examples for starters, including optocouplers.

Briefly, every element of schematics can be represented by a realistic parameter (SPICE) model, extracted by part manufacturer. The simulator then calculates EVERYTHING depending on type of stimulus applied to circuit inputs. For commercial-grade simulator it would calculate everything for all temperature and voltage corners of the parts. LTspice will give you results for typical parameters. Read tutorials and enjoy the journey.