Question: I have two pieces of modules as below, may I ask which one is the right verilog to represent an Asynchronous active high set/reset D-flip flop (Rising clock edge)? Are both of them logically equivalent? 

Expected Truth Table for my D-flip Flop

```
reset  set     clk        q
  1     x       x         0
  0     1       x         1
  0     0   rise-edge     d1
  0     0       0         Qo (previous d1)        

```

First Module dff\_async\_RS

```
module dff_async_RS(q, d1, clk, reset, set);
  input d1, clk, set, reset;
  output q;
  reg q_reg;
  always @ (posedge clk)
    begin
    if (reset)
      q_reg <= 1'b0;
    else if (set)
      q_reg <= 1'b1;
    else
      q_reg <= d1;
    end
  assign q = reset ? 1'b0 : (set ? 1'b1 : q_reg);
endmodule

```

Second Module dff\_async

```
module dff_async(q, d1, clk, reset, set);
  input d1, clk, set, reset;
  output q;
  reg q;
  always @ (posedge clk or posedge set or posedge reset)
    begin
    if (reset)
      q <= 1'b0;
    else if (set)
      q <= 1'b1;
    else
      q <= d1;
    end
endmodule

```

Answer: 
The problem with your first module is after releasing `set` or `reset` back to 0, the `q` output goes back to the previous `q_reg` state.

Try it in simulation.
When set or reset is 'HIGH', irrespective of clock, output should be made 1 or 0.
In the first case every event happens at the positive edge of clock. So even if set/reset was 'HIGH', it waits until the posedge clk to change the output. So it is not asynchronous.

In second case whenever reset/set is 'HIGH' the always block is immediately passed and output changes.