Question: I am using a very simple model to show the unity gainbandwidth of a closed loop sample and hold with a closed loop gain of 2. One would expect an ideal OTA to have a GBW independent of rout as GBW is just \$ \frac{g\_m\*r\_{out}}{r\_{out}\*C\_L} \$ or \$GBW = g\_m/C\_L (\frac {rad}{s}).\$

Yet, the simulation I contrived shows something very different. It can be seen that \$f\_{unity} = GBW\$ varies with \$rout\$. It has a peak that matches the calc exactly, but tapers off to a value far different than calculated. A clue is that the closed loop gain also behaves oddly. We would expect it to start at 0 and rise and settle to an expected close loop gain of 2, as the open loop gain is getting larger with rout, and the closed loop accuracy should increase. The gain plot shows a peaking coincident with the \$f\_{unity}\$ far above 2.

I'm not certain if it is the actual simulation or something with LTSPICE or my theoretical expectations that are amiss. Anyone have an explanation?

[![enter image description here](https://i.stack.imgur.com/1zNEH.png)](https://i.stack.imgur.com/1zNEH.png)

Answer: 
If it helps anyone, I figured out (through a fairly tedious analysis) that it's more complicated than the numerous texts, literature, and theses using sample and hold and multiplying dac calculations make it out to be (it can be quite sensitive to low feedback factor and output impedance for example).

I found an [excellent paper/blog](https://www.electronicdesign.com/technologies/analog/article/21807892/gainbandwidth-product-is-not-always-constant) explaining the fallacy of perpetuating gainbandwidth product is always constant (even with very simple op amp open/closed loop structures).
The author shows that it requires assumptions such as closed loop gain greater than about 20. Below that, the more rigorous calculations are called for. Notice that a common pipeline ADC MDAC uses a gain on the order of 2, falling into this zone.

As an example, here, instead of just using \$fu= \frac {g\_m}{2\*pi\*C\_{L}}\$ as is typically shown in texts, a more complex analysis (for the circuit I showed) returns something like

\$fu= \frac {g\_m}{2\*pi\*C\_{L}} - \frac{1}{r\_{out}\*{c\_{L}}}\$
where the sensitivity to rout is more clear for smaller rout.
I tried this circuit, but as soon as I run the simulator, it gives an error (logical).  

This error is dependent on the two capacitors.  

The midpoint has no DC path to the ground.  

If one adds paralleled resistors, behavior change immediately.

Here is a simulation where (my) R1 and C2 are stepped logs (x10).  

One can see that there is a low-frequency corner (logical) but bandwidth is quasi illimited. (Gain only changes with C2, R2 and R3 must change accordingly with C2 and C1).

[![enter image description here](https://i.stack.imgur.com/rdHO5.png)](https://i.stack.imgur.com/rdHO5.png)

And here when "resistors" are "adapted" ...

[![enter image description here](https://i.stack.imgur.com/OJdQR.png)](https://i.stack.imgur.com/OJdQR.png)