Question: this is my first post here. I am new to FPGAs. I would like to implement a NOT gate on the BASYS (Spartan3E-100) FPGA. I've been looking at the tutorial [HERE](https://docs.numato.com/kb/learning-fpga-verilog-beginners-guide-part-4-synthesis/) to work my way towards a synthesis. I wish to keep everything on-board, i.e. only use the LEDs and switches on this board. How should I proceed?

My thoughts/questions so far:

* Do I have to use LD2-LD7 on Bank 3 and not LD1, LD0?
* What does LHCLK0, LHCLK1 mean? Why are the labels not corresponding to LD1, LD0? Do the LHCLK prevent me from using LD0, LD1 for the gate?
* The push button switches are connected to Bank 2, but the LEDs are on Bank 3, how do I connect the switch to the LED?

I would be grateful if somebody could point me in the right direction.

Edit: I should have clarified that I realize that the tutorial is NOT for my board, but I would still like to implement the not-gate on my board.

Answer: 
Find a different tutorial!

The tutorial you're reading is written for a completely different board -- it's written for the Mimas v2, from Numato Labs. This board has almost nothing in common with the Basys, beyond that they both have Xilinx FPGAs on them.

Some of the general concepts will line up, but the details of which pins to use will be completely different. Look for a tutorial written specifically for the board you're using. (This may be difficult for such an old board; you may want to look for any university teaching materials which were written for students using this board.)
If you come with programming background, then probably FPGA-s will have some surprises for you. However I assume you know how to use ISE WebPack or whatever environment you use right now.

What you need is schematics for your board (probably delivered by Digilent). Second this is knowledge of constraint files. This files describes how your project will be fitted into platform. One of the things it describes is the signal - pin allocation.

Here is Xilinx's document regarding constraints (could be old). <https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf>
Second thing I googled in 2 minutes is
<https://learn.digilentinc.com/Classroom/Tutorials/Xilinx%20ISE%20WebPACK%20Verilog%20Tutorial.pdf>

It's Verilog, not VHDL however should give you an overview even or VHDL.