Question: I have a state diagram that is consisted of 3 states and in reset it comes to state s0 then if an event happen on start signal goes to state 2 and statye there for 15 clock sycle and then after that goes to state 3 and then back to state s0.
My question is that when VHDL coding how could I do the 15 clock delay of state 2.
I know that a counter needs to be there but it is not clear for me how to do the VHDL coding.
Could any one please give me some help.
Thank you

Answer: 
First of all: BE CARFEUL WHAT YOU DO HERE! 220 VAC (I assume 50 Hz) are no fun to get in touch with. 
You dont have a closed circuit here, cause your cap isnt connected to ground, so the 220 Volts are dropping all over the open clamps (infinite resistance --> maximum voltage drop). Please dont connect it this way because you're gonna blow it up and it might get nasty. 

Edit: The calculation of the reactance is rather irrelevant, since as Dave Tweed mentions, the only power dissipated are for parasitic losses. 

Maybe we can help you more, if you show the rest of your schematic.
In order to drop voltage, first the capacitor has to charge up. And in order to charge up it needs a current, which clearly that circuit doesn't have. 

Just connecting the open ends would be a bad idea; put a resistor in series.