Question: I thought the braces require 5 matches.

```
import re

rMatch = re.search(r'(.*[0-9]){5,}', 'A1B2C3D4E5')
print(rMatch)
print(rMatch.groups())

```

Why only one group?
How can I see the 5 matches that are taking place given the use of curly braces?

Answer: 
Automatic variables, i.e. variables without memory space specification within the scope of functions, are placed in one of the following locations:

1. When optimized away:

1.1 **Nowhere** - if the variable isn't actually necessary. This actually happens a lot, since CUDA functions are often inlined, with some variables becoming copies of a variable in the calling function. [Example](https://godbolt.org/z/f1e96ch31) (note the `x` from `foo()` in the compilation of `bar()` - completely gone).

1.2 **Immediate values in the program's compiled code** - if the variable's value is constant, and doesn't get updated, its value may simply be "plugged" into the code. [Here's an example](https://godbolt.org/z/xedqrohcY) with two variables taking constants, which are replaced with the constant which is their sum.
2. When not optimized away:

2.1 **Registers** - If your variable can't be optimized-away, the better alternative is to keep it in a hardware register on (one of the symmetric multiprocessor core on) the GPU. [Example](https://godbolt.org/z/G75hPPrvj) (the variables `x` and `y` are placed in registers `%r1` and `%r2`).
the best and most performant option, which the compiler

2.2 **'Local' memory** - The 'local memory' of a CUDA thread is an area in global device memory which is (in principle) accessible only by that thread.

Now, obviously, local memory is much slower to use. When will the compiler choose it, then?

The CUDA Programming Guide [gives us](https://docs.nvidia.com/cuda/cuda-c-programming-guide/#device-memory-accesses) the answer:

1. When the automatic variable is **too large** to fit in the register file for the current thread (each thread typically gets between 63 and 255 4-byte registers).
2. When the automatic variable is an **array**, or has an array member, which is **indexed with a non-constant offset**. Unfortunately, NVIDIA GPU multiprocessors don't support register indexing.
3. When the kernel is **overusing its available quota of registers** is already full with other variables or uses by the compiled code - even if the variable itself is very small. This is referred to as *register spilling*.
GPUs have a bunch of space dedicated for many registers stored directly in GPU computing units (ie. Streaming Multiprocessors). **Registers are not stored in memory** unless there is some *register spilling* happening (typically when you use too many registers in a given kernel). Register have no address unlike all memory bytes. The same thing happen for CPU except that the number of CPU registers is usually much smaller than on GPU. For example, an Intel Skylake core has 180 integer register and 168 vector registers while the instruction set architecture is limited to something like 16 integer/vector registers. Note that in case of register spilling, the value of registers is temporary stored in local memory (typically in the L1 cache if possible). Here is the overall memory hierarchy of a basic (Nvidia Fermi) GPU:

[![enter image description here](https://i.stack.imgur.com/hnMVq.png)](https://i.stack.imgur.com/hnMVq.png)

For more information, consider reading: [Local Memory and Register Spilling](https://developer.download.nvidia.com/CUDA/training/register_spilling.pdf).