Question: Why is it that the produced clock frequency is 6.144 MHz, but internally it (8085 processor) uses only 3.072 MHz. Also what leads to the specific value of 6.144 in a clock. 

I found an answer at yahoo.... <http://answers.yahoo.com/question/index?qid=20080810090119AAurr2i>

but I must admit I didn't still get it it well. Could any of you guys throw out a few lines on this, please?

Answer: 
One reason to divide a clock by two is to obtain an even 50% duty cycle square wave. It may be that the 8085 internally uses both clock edges, and wouldn't function if one half of the cycle happened to be much shorter than the other. 

In the days when the 8085 was new, those nice canned oscillators weren't common, and people often cobbled together clock circuits out of discrete crystals, capacitors, and logic gates. Dividing by two ensures that you have equally spaced rising and falling edges.

As for 6.144MHz, you will find that it can be divided by an integer to get common baud rate values, at least up to 38400. 

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*follow up ...*
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Looking at an Intel data sheet for the 8085, there are three interesting statements

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> The 8085 incorporates all of the features that the 8224 clock generator and 8228 system controller provided for the 8080A
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2. > 
> X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. The input frequency is divided by 2 to give the processor's internal operating frequency.
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3. > 
> CLK: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.
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So, speculations about using the odd edges of the clock to move stuff around internally aside, it becomes apparent that when they designed the 8085, Intel was replacing the need for a special clock controller by integrating that feature into the chip. Dividing the X1-X2 timebase in half before outputting it as CLK ensures that the *system* gets a nice even duty cycle, if nothing else.
Internally, the core of the 8085A requires a two-phase clock. The internal logic that derives the two clock phases also divides the input clock by two. As previously stated, the reason for using a 6.144MHz input clock is for baud-rate purposes, the chip will run just fine at 6MHz. The chip is actually rated at 3MHz requiring a 6MHz crystal, but runs happily with a 6.144MHz giving easier baud rate generation (An Uart could be clocked with either the 6.144MHz from an Oscillator driving the 8085 or at 3.072MHz from the 8085's CLK output providing many usable Baud rates). I still use these archaic chips to perform special functions in some of my robots. I clock the Uarts with their own oscillator and I clock the 8085A's with a 6.4MHz oscillator, which runs the chip at 3.2MHz. The 3.2MHz divides down nicely to provide the 40KHz clock for my ultrasonic transducers. It makes more sense to use more modern I.C. devices in my 'bots, but I have a ton of old 8085's, Z80's, 63C09 and 63C09E's, 68B09 and 68B09E's, etc. that I really enjoy playing with.