Question: Why is it that the produced clock frequency is 6.144 MHz, but internally it (8085 processor) uses only 3.072 MHz. Also what leads to the specific value of 6.144 in a clock. 

I found an answer at yahoo.... <http://answers.yahoo.com/question/index?qid=20080810090119AAurr2i>

but I must admit I didn't still get it it well. Could any of you guys throw out a few lines on this, please?

Answer: 
One reason to divide a clock by two is to obtain an even 50% duty cycle square wave. It may be that the 8085 internally uses both clock edges, and wouldn't function if one half of the cycle happened to be much shorter than the other. 

In the days when the 8085 was new, those nice canned oscillators weren't common, and people often cobbled together clock circuits out of discrete crystals, capacitors, and logic gates. Dividing by two ensures that you have equally spaced rising and falling edges.

As for 6.144MHz, you will find that it can be divided by an integer to get common baud rate values, at least up to 38400. 

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*follow up ...*
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Looking at an Intel data sheet for the 8085, there are three interesting statements

1. > 
> The 8085 incorporates all of the features that the 8224 clock generator and 8228 system controller provided for the 8080A
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2. > 
> X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. The input frequency is divided by 2 to give the processor's internal operating frequency.
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3. > 
> CLK: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.
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So, speculations about using the odd edges of the clock to move stuff around internally aside, it becomes apparent that when they designed the 8085, Intel was replacing the need for a special clock controller by integrating that feature into the chip. Dividing the X1-X2 timebase in half before outputting it as CLK ensures that the *system* gets a nice even duty cycle, if nothing else.
At the time this chip was designed, people used as few transistors as possible in the CPU, to make them small enough to fit on the available chips.

I suspect that practically every "register" (both programmer-visible instruction-set registers and also internal microarchitecture latches) in a CPU of that era stored data in a transparent [gated D latch](http://en.wikipedia.org/wiki/gated_D_latch) or something similar.
Nowadays, there's plenty of transistors on a chip, so it's simpler to use full master-slave D flip-flops, even though they use twice as many transistors.

Many instructions take data from some register A, combine it with some other data with the ALU, and store the result back in register A.
That is pretty easy to do if register A is implemented with a full master-slave D flip-flop.

But if register A is a transparent gated D latch, you need non-overlapping clocks.
You use a pulse on one clock to store some intermediate result somewhere (while register A holds its output constant), and then a pulse on another clock to load register A with the new value (while the intermediate register holds its output constant).

This requires a 2-phase clock.
The easiest way to make a non-overlapping 2-phase clock (in those days when transistors were scarce) was a little external circuit that takes an input clock and divides it by two.

As time went on, people figured out how to pack more and more transistors onto an IC.
So people designing CPUs integrated more and more of the stuff around the CPU in a full computer system onto the CPU chip.

Reading between the lines of the [Wikipedia clock signal article](http://en.wikipedia.org/wiki/clock_signal),
I get the impression that the people who designed the 8085 and the 6502 and other chips of that era had just a little more room than the previous generation of integrated CPUs,
and they decided the best use of that room was to put that little external circuit on-chip.
But they kept all the registers the same gated D latch as before.

So that's why the clock frequency is divided by two. You can think of the first external clock pulse generating a pulse on the phase\_one internal clock signal to update that intermediate result register, and the second pulse from the external clock generating a pulse on the phase\_two internal clock signal to update the programmer-visible register.