Question: **Need of SSC:**

Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. These levels or energy is radiated and therefore this is where a potential EMI issue arises.

**Doubt:**

Assume that SSC clock has range from -5300 to 300 ppm, assuming down-spreaded SSC. SSC clock is only driven to output lines (USB Tx D+/D- lines) or given to whole system blocks? 

* If it is only at the PHY-Layer, then how does it compensate for the clock difference for data exchange between PHY to/from Upper Layers? (Need buffer at SerDes?)
* If core clock (with generated SSC) is given to whole system blocks then does it affect `Fmax` of designed system? (Frequency of operation may vary!!), every thing including SerDes have same source of frequency.

Any idea which is preferable or best way other than these two that I have outlined?

Answer: 
Most of radiated energy in EMI/RFI comes from the edges or clock transitions. How SSC works is by dithering these edges to reduce the reinforcement of the transmitted frequencies. Essentially you are broadening out the peak transmission energy. You are not really changing the energy as the integrated energy (integrated wrt to frequency) or the area under the curve in the frequency domain stays the same. It is less "peaky" in the SSC case.

The key idea here is to have that edge transition at the same lockstep transmission but with +/- some small amount of time. The idea is that the setup and hold times of any logic is not adversely affected by this jittering.

In reality, it would be easiest to just dither your output stream. Most serial stream protocols and implementations can accept jitter in due course. Especially systems where there is the concept of an "eye diagram" and you actively re-align the sampling to the clear center of the eye.

In a larger system with purely digital logic, dithering the will necessitate the slowing down of the clock to maintain the same timing margins. However, it is necessary to point out this is a very small amount of slowing down so it probably would not be noticeable.
According to me, 

> 
> If core clock (generated SSC) is given to whole system blocks then does it affect Fmax of designed system? (Frequency of operation may varies!!), every thing including SerDes have same source of frequency.
> 
> 
> 

Option is better, because we know SSC, so we have to design our system accordingly, i.e. Core clock is of `500 MHz` and due to SSC `499.15 MHz` to `500.1 MHz`, so designed system must be capable of having `Fmax = 500.1 MHz`. Hence, we have omitted the requirement of Buffer at SerDes which was required for first option.

> 
> If it is only at PHY-Layer, then how it compensate clock difference for data exchange between PHY to/from Uper Layers? (Need buffer at SerDes?)
> 
> 
> 

It is too much complex to handle Buffer at bit clock, suppose USB3.0 then it should be capable of achieving `Fmax = 5 GHz` which is generally not feasible. 

**Inference:** 

As we know SSC and resulted SSC frequency, let design system for that worst case frequency. Which is more easier and feasible solution so far.