Question: Why is it that the produced clock frequency is 6.144 MHz, but internally it (8085 processor) uses only 3.072 MHz. Also what leads to the specific value of 6.144 in a clock. 

I found an answer at yahoo.... <http://answers.yahoo.com/question/index?qid=20080810090119AAurr2i>

but I must admit I didn't still get it it well. Could any of you guys throw out a few lines on this, please?

Answer: 
One reason to divide a clock by two is to obtain an even 50% duty cycle square wave. It may be that the 8085 internally uses both clock edges, and wouldn't function if one half of the cycle happened to be much shorter than the other. 

In the days when the 8085 was new, those nice canned oscillators weren't common, and people often cobbled together clock circuits out of discrete crystals, capacitors, and logic gates. Dividing by two ensures that you have equally spaced rising and falling edges.

As for 6.144MHz, you will find that it can be divided by an integer to get common baud rate values, at least up to 38400. 

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*follow up ...*
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Looking at an Intel data sheet for the 8085, there are three interesting statements

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> The 8085 incorporates all of the features that the 8224 clock generator and 8228 system controller provided for the 8080A
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2. > 
> X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. The input frequency is divided by 2 to give the processor's internal operating frequency.
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3. > 
> CLK: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.
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So, speculations about using the odd edges of the clock to move stuff around internally aside, it becomes apparent that when they designed the 8085, Intel was replacing the need for a special clock controller by integrating that feature into the chip. Dividing the X1-X2 timebase in half before outputting it as CLK ensures that the *system* gets a nice even duty cycle, if nothing else.
There are lots of reasons to split the instruction cycle into multiple clock cycles. A good example is accessing the main memory bus.

Most modern processors are Von-Neumann architectures; that is, their code and data both exist in the same memory chip. Well, if you want to read an instruction, and that instruction is going to load a variable from memory...that's two memory accesses. But most memory is only single-port (that is, it can only do one read or write per cycle). So how do you read the instruction *and* read your variable?

The solution is to use a two-stage instruction cycle. The first stage will fetch the instruction from memory, and the second stage can then read (or write!) the variable from main memory.

Some older chips went even further. Back in the day, if your chip had 16-bits of addressable memory, but the external address bus is only 8-bits, then you would be familiar with the Address Latch Enable. One clock cycle sends the upper 8-bits of the 16-bit address, and the next clock cycle sends the lower 8-bits. A third cycle could then read/write the variable from/to memory.

There are other, better reasons to have an instruction cycle that is multiple clock cycles in length. One of the best reasons is pipelining. This is a trick that modern processors use to more fully exploit all the execution units available in a chip; for example, while one instruction is being executed, the next is being fetched at the same time.