Question: I have the following transaction:

```
typedef enum {READ = 0, WRITE = 1} direction_enum;

//Transaction

class axi_transaction extends uvm_sequence_item();
   bit id = 0;  //const
   bit [31:0] addr;
   bit [2:0]  size = 0'b100;//const
   direction_enum rw;
   bit [31:0] transfers [$];

   //factory registration
   `uvm_object_utils_begin(axi_transaction)
   `uvm_field_int(id, UVM_ALL_ON)
   `uvm_field_int(addr, UVM_ALL_ON)
   `uvm_field_int(size, UVM_ALL_ON)
   `uvm_field_enum(rw, UVM_ALL_ON)
   `uvm_field_int(transfers, UVM_ALL_ON)      
   `uvm_object_utils_end  

   //constructor
   function new(string name = "axi_transaction");
      super.new(name);
   endfunction: new

endclass: axi_transaction

```

I want to extend the new function, so I can initializes the transaction in the sequence with arguments which initialize some of the transaction members (like addr, transfers) by:

```
 ax_trx =  axi_transaction::type_id::create(); 

```

How to write the constructor of the transaction and how do I initialize the transaction from the sequencer?

Answer: 
You cannot add arguments to the class constructor when using the UVM factory. In general this is not good OOP programing practice for re-use because if you do add arguments to either the base class or extended class, you have to modify every place where the class gets constructed.

A better option is to use the uvm\_config\_db or set the individual fields you need to after constructing the object.

```
ax_trx =  axi_transaction::type_id::create(); 
ax_trx.addr = some_address
ax_trx.transfers = '{word1,word2,word3};

```
You can use uvm\_config\_db class for initialisation. 

You can set the value using following syntax. And then you can get that value inside the constructor of that class.

```
uvm_config_db#(int)::set(this,“my_subblock_a”,“max_cycles”,max_cycles)
uvm_config_db#(int)::get(this,“”, “max_cycles”,max_cycles)

```

For more information of "uvm\_config\_db", you can refer to the following paper.
<https://www.synopsys.com/Services/Documents/hierarchical-testbench-configuration-using-uvm.pdf>