Question: Why is it that the produced clock frequency is 6.144 MHz, but internally it (8085 processor) uses only 3.072 MHz. Also what leads to the specific value of 6.144 in a clock. 

I found an answer at yahoo.... <http://answers.yahoo.com/question/index?qid=20080810090119AAurr2i>

but I must admit I didn't still get it it well. Could any of you guys throw out a few lines on this, please?

Answer: 
There are lots of reasons to split the instruction cycle into multiple clock cycles. A good example is accessing the main memory bus.

Most modern processors are Von-Neumann architectures; that is, their code and data both exist in the same memory chip. Well, if you want to read an instruction, and that instruction is going to load a variable from memory...that's two memory accesses. But most memory is only single-port (that is, it can only do one read or write per cycle). So how do you read the instruction *and* read your variable?

The solution is to use a two-stage instruction cycle. The first stage will fetch the instruction from memory, and the second stage can then read (or write!) the variable from main memory.

Some older chips went even further. Back in the day, if your chip had 16-bits of addressable memory, but the external address bus is only 8-bits, then you would be familiar with the Address Latch Enable. One clock cycle sends the upper 8-bits of the 16-bit address, and the next clock cycle sends the lower 8-bits. A third cycle could then read/write the variable from/to memory.

There are other, better reasons to have an instruction cycle that is multiple clock cycles in length. One of the best reasons is pipelining. This is a trick that modern processors use to more fully exploit all the execution units available in a chip; for example, while one instruction is being executed, the next is being fetched at the same time.
Internally, the core of the 8085A requires a two-phase clock. The internal logic that derives the two clock phases also divides the input clock by two. As previously stated, the reason for using a 6.144MHz input clock is for baud-rate purposes, the chip will run just fine at 6MHz. The chip is actually rated at 3MHz requiring a 6MHz crystal, but runs happily with a 6.144MHz giving easier baud rate generation (An Uart could be clocked with either the 6.144MHz from an Oscillator driving the 8085 or at 3.072MHz from the 8085's CLK output providing many usable Baud rates). I still use these archaic chips to perform special functions in some of my robots. I clock the Uarts with their own oscillator and I clock the 8085A's with a 6.4MHz oscillator, which runs the chip at 3.2MHz. The 3.2MHz divides down nicely to provide the 40KHz clock for my ultrasonic transducers. It makes more sense to use more modern I.C. devices in my 'bots, but I have a ton of old 8085's, Z80's, 63C09 and 63C09E's, 68B09 and 68B09E's, etc. that I really enjoy playing with.