Question: In the few textbooks I'm reading on CMOS analog design, they all seem to have reference currents of \$10 \mu A\$ or similar that get mirrored, and there doesn't seem to be any discussion on how this reference value was arrived at.

Is there any science to choosing these bias current numbers? Why is it not \$1\mu A\$, or \$200nA\$ or something to save power?

Answer: 
These are probably chipscale packages. So you're looking at the top of the actual silicon die. The bottom is processed so that there are solder balls for connection to the PCB.

If you've ever seen a silicon wafer you know that it's polished to a mirror like silvery-gray finish.

One issue you can sometimes have with CSP devices is that they can be sensitive to light, since the silicon is exposed.
> 
> What is on the surface of these chips and why?
> 
> 
> 

You are seeing the silicon die of the chip itself. This isn't a new phenomena.

[![enter image description here](https://i.stack.imgur.com/FWasd.jpg)](https://i.stack.imgur.com/FWasd.jpg)

*Figure 1. An Intel 1702A EPROM, one of the earliest (1971) EPROM types, 256 by 8 bit. The small quartz window admits UV light to the chip for erasure. Source: Wikipedia [EPROM}([https://en.wikipedia.org/wiki/EPROM).](https://en.wikipedia.org/wiki/EPROM)._)*

What has changed is the packaging. In the photo the gold wires are bonded to the top of the chip and out to the lead frame. With surface mount the connections between chip and board are made out of sight below the chip.