Question: For example, I have a single long statement:

```
    $display("input_data: %x, 
              output_data: %x,
              result: %x",
              input_data,
              output_data,
              result);

```

How can I make it into single statement and multiple lines in Verilog?

Answer: 
You need to break up the quoted string. Here is one way:

```
module tb;

initial begin
    integer input_data  = 1;
    integer output_data = 0;
    integer result      = 55;
    $display("input_data: %x "  , input_data,
             "output_data: %x " , output_data,
             "result: %x "      , result);
end

endmodule

```

Outputs:

```
input_data: 00000001 output_data: 00000000 result: 00000037 

```
More generally, you can also use the string concatenation operator:

{"string1", "string2", "string3"}