Articles+ start Keyword "Surface treatment" Remove constraint Keyword: "Surface treatment" Journal title ieee transactions on components, packaging & manufacturing technology Remove constraint Journal title: ieee transactions on components, packaging & manufacturing technology
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substrates150
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surface preparation55
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coatings40
electroplating40
integrated circuit interconnections40
integrated circuits40
temperature measurement40
through-silicon vias40
solder & soldering35
substrates (materials science)35
surface topography35
annealing30
assembly30
dielectrics30
electrodes30
fabrication30
light emitting diodes30
microstructure30
surfaces (technology)30
tin30
microfabrication25
plasma treatment25
printed circuits25
soldering25
temperature measurements25
thermal expansion25
thin films25
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455 articles+ results
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1. Plasma Treatment and Copper Metallization for Reliable Plated-Through-Holes in Microwave PCBs for Space Electronic Packaging. [2020]
C., Hanumanth Rao, Kothuru, Avinash, Singh, Amrendra Pratap, Varaprasad, B. K. S. V. L., and Goel, Sanket
IEEE Transactions on Components, Packaging & Manufacturing Technology. Nov2020, Vol. 10 Issue 1, p1921-1928. 8p.
ELECTRONIC packaging, MICROWAVE plasmas, DIELECTRIC materials, CHEMICAL processes, ELECTROLESS deposition, MICROWAVE materials, OHMIC contacts, and THERMAL stresses
Radio frequency (RF) or microwave printed circuit board (PCB) is a type of PCB designed to operate on signals in megahertz-to-gigahertz frequency (medium to extremely high frequency) ranges. The materials used to construct these PCBs are advanced composites with very specific characteristics for dielectric constant, loss tangent, and coefficient of thermal expansion (CTE). These microwave materials with critical values of very low dielectric loss and absolute dielectric constant allow high-speed signals to travel through the PCB with more stable impedance characteristics than in standard FR-4 dielectric materials. These microwave substrates are composite dielectric materials produced generally with combination of polytetrafluoroethylene (PTFE), ceramics, hydrocarbons, and/or various forms of glass. PTFE-based microwave PCB laminates, which require vias after drilling, are subjected to an appropriate surface modification for metallization, because of its hydrophobic nature and very low surface energy. Sodium-based wet chemical process followed by various copper deposition process techniques are commonly employed for metallization of microwave PCBs. In our study, plasma treatment process is used to generate microroughened surface in drilled vias, and electroless copper deposition followed by copper electroplating process have been employed for void-free metallization in microwave PCBs with enhanced plated-through-hole (PTH) reliability for space electronics packaging applications, as evidenced from the results of thermal stress and PTH bond strength tests conducted as per IPC-TM-650. [ABSTRACT FROM AUTHOR]
2. Comprehensive Analysis of a Cu Nitride Passivated Surface That Enhances Cu-to-Cu Bonding. [2020]
Seo, Hankyeol, Park, Haesung, and Kim, Sarah Eunkyung
COPPER oxide, COPPER oxidation, VERTICAL integration, COPPER analysis, MASS production, COPPER surfaces, ANALYTICAL chemistry, and NITRIDES
As 3-D packaging is expected to meet new requirements for next-generation system-in-packaging (SiP), various technologies have been discussed for vertical integration. To enable high-performance vertical interconnects, Cu-to-Cu bonding is an essential process for decreasing the metal-interconnect size between vertically stacked devices and for improving system performance. However, the high-temperature and high-pressure conditions of the Cu bonding process and copper surface oxidation are important issues to be resolved for better mass production, especially for chip-to-wafer bonding. In this study, a comprehensive analysis was performed on the effects of a two-step Ar and N2 plasma treatment used to create a copper nitride passivated surface. Chemical and structural analyses of the copper nitride surface showed that this two-step plasma treatment removed nonuniformly formed native copper oxides and formed an ultrathin copper nitride passivation layer. Electrical and mechanical analyses showed that the resulting uniform conductive copper nitride surface and plastic property have the potential to improve the quality of thermocompression bonding. The results of these comprehensive analyses demonstrate the excellent ability of copper nitride to passivate copper surfaces and indicate the possibility of achieving effective Cu bonding in air. [ABSTRACT FROM AUTHOR]
3. Linkage Control Policy on Area Pacesetter and Active Compensation for Chip Angle Correction. [2020]
Wu, Tao, Li, Changhong, Ye, Weilin, Wu, Fupei, and Li, Bin
IEEE Transactions on Components, Packaging & Manufacturing Technology. Sep2020, Vol. 10 Issue 9, p1524-1533. 10p.
LIGHT emitting diodes, ANGLES, PETRI nets, ELASTIC deformation, and MANUFACTURING processes
In order to improve the optical and electrical consistency in lighting and display, light emitting diode (LED) dies should be sorted and aligned precisely one by one. As per given current production process practices, the sorting efficiency is required to be more than 36 thousand units per hour (KUPH), while the alignment deviation should not exceed 1 mil (25.4 $\mu \text{m}$) and all dies' angle deviations should fall within 5°. Among all the requirements, the chip angle correction is particularly difficult to achieve because a small die correction on wafer would cause a change in all dies' positions, leading to significant performance degradation. This results in an ambiguity, due to the difficulty in balancing efficiency and accuracy. In this article, the influence factors of the accuracy deviation caused by the angle correction are analyzed in detail, and the negative effect caused by tiny deformation of the elastic substrate is studied with comprehensive experiments. The parallel scheduling mechanism of the angle correction is analyzed, and the influences on sorting performance are evaluated with stochastic petri net (SPN) model, so that the suitable working area is disclosed. A local compensation strategy using the local deformation trend of the membrane is utilized to optimize the accuracy of precorrection. Further, the alignment area is actively compensated according to the alignment precision requirements, so that the performance and accuracy requirements are balanced. In the chip packaging field, microchip angle correction is often needed. This method is applicable to similar situation and chips are adhesive on membrane. [ABSTRACT FROM AUTHOR]
4. Effect of Solder Paste Volume and Reflow Parameters on Solder Paste Wicking and Joint Shear Strength of Ni–Au-Coated Cu Spheres. [2020]
Gupte, Omkar, Murtagian, Gregorio, Tummala, Rao, and Smet, Vanessa
IEEE Transactions on Components, Packaging & Manufacturing Technology. May2020, Vol. 10 Issue 5, p828-835. 8p.
SOLDER pastes, SHEAR strength, SURFACE mount technology (Printed circuits), SOLDER joints, OHMIC contacts, and METAL coating
Ball grid array (BGA) architectures are being widely used in the semiconductor industry in surface mount technology (SMT) applications to satisfy the miniaturization needs of emerging microelectronics systems. However, these architectures are not compatible with socketing applications as the mechanical contact between the gold paddle and the solder sphere leads to undesired reactions, increasing the contact resistance and degrading the reworkability overtime. To address this challenge, surface modification of BGA spheres with multilayered thin-film metallic coatings such as Ni-Au is proposed to maintain a nonreactive noble metal interface when used in a socket. This article focuses on the process of attaching the surface-modified spheres on a package using two solder pastes—Sn57.6Bi0.4Ag (SBA) and Sn3.0Ag0.5Cu (SAC305) with liquidus temperatures of 138 °C and 219 °C, respectively. The challenge of solder paste wicking on the entire surface of the Au-coated sphere was addressed by controlling the volume of the solder paste, and the joint shear strength was optimized by controlling the time above liquidus (TAL) during reflow. A 30–40-s window for TAL was established to achieve a strong solder joint with controlled paste wicking for both solder pastes. The strength of the joint was measured by a single-ball shear test, followed by microstructural analysis to identify the failure modes. Brittle fractures were observed for both solder pastes with an optimum joint shear strength ranging from 55 to 70 MPa for the SBA paste, and 72 to 75 MPa for the SAC305 paste. [ABSTRACT FROM AUTHOR]
5. A CNN-Based CMP Planarization Model Considering LDE Effect. [2020]
Bao, Han and Chen, Lan
IEEE Transactions on Components, Packaging & Manufacturing Technology. Apr2020, Vol. 10 Issue 4, p723-729. 7p.
ARTIFICIAL neural networks, SURFACE topography, ARCHITECTURAL models, SCANNING electron microscopes, INTEGRATED circuits, and NUCLEAR forces (Physics)
As integrated circuit (IC) industry advances to the nanometer scale, layout pattern plays more and more important role on chip fabrication. Layout-dependent effect (LDE) studies how different patterns influence the fabrication results. Chemical–mechanical polishing (CMP), one of the most important processes during IC fabrication, is strongly influenced by LDE. The purpose of this article is to show a convolutional neural network (CNN)-based method to model post-CMP surface topography problem. The method accurately predicts the topological height of the chip surface after CMP by using CNN to abstract features from layout patterns, aiming to analyze defects that may cause failure. This article first addresses about the principles and practicability of using the CNN method to build a CMP model, then builds up a complete CNN structure, and compares the CNN-based model with a traditional pressure-distribution-based CMP model. We designed test chips containing different structures and fabricated them with 28- and 45-nm process nodes. Surface topography is measured using atomic force profiler (AFP) and scanning electron microscope (SEM). The result shows that the total root-mean-squared error (RMSE) of the CNN-based model is 22.41 A, whereas the RMSE of the pressure-distribution-based model is 65.54 A. The CNN-based CMP model shows better accuracy. [ABSTRACT FROM AUTHOR]
6. Optically Transparent Protective Coating for ITO-Coated PET-Based Microwave Metamaterial Absorbers. [2020]
Chaudhary, Kajal, Singh, Gaganpreet, Ramkumar, J., Anantha Ramakrishna, S., Srivastava, Kumar Vaibhav, and Ramamurthy, Praveen C.
IEEE Transactions on Components, Packaging & Manufacturing Technology. Mar2020, Vol. 10 Issue 3, p378-388. 11p.
PROTECTIVE coatings, SURFACE preparation, NANOMECHANICS, CONTACT angle, INDIUM tin oxide, THIN films, and POLYVINYL butyral
In spite of indium tin oxide (ITO)-coated polyethylene terephthalate (PET) sheets being a thriving candidate for flexible and transparent microwave metamaterial absorbers (MMAs), these materials are not robust under severe environmental and handling conditions. The ITO coatings are brittle and have poor scratch resistance when coated over flexible PET sheets; hence, their electrical performance degrades in time. Here, thin films of polyvinyl butyral (PVB) and also its composite with 3-aminopropyltriehoxysilane (APTES) processed at room temperature have been investigated as protective coatings over ITO-coated PET sheets, particularly for MMA application. Prior to coating, the effectiveness of various surface treatments to increase the ITO's wettability by exposure to UV light, chemicals, and air plasma was demonstrated by contact angle measurements. Furthermore, the consequences of surface treatments on the adhesion of the protective coatings to the ITO surface were studied using microindentation, pencil scratch test, ultrasonication test, water soak test, and shower test. Measurements of microwave absorption of the coated and uncoated substrates (PET and ITO-PET) over the $X$ -band (8.2–12.4 GHz) showed a similar electromagnetic (EM) response approximately. Finally, free-space measurements of the MMA before and after PVB coating at its top and bottom were compared from 4 to 16 GHz, and the maximum EM absorption was found to have increased from 95.94% to 98.56%. Optical transparency of coated ITO-PET was quantified by measuring the optical transmittance at 632.8-nm wavelength using red laser and found to be equal to 68.9 ± 6.9. The mechanical strength of the developed coatings is analyzed by nanoindentation technique by obtaining values of hardness and elastic modulus. [ABSTRACT FROM AUTHOR]
7. Two-Step Plasma Treatment on Copper Surface for Low-Temperature Cu Thermo-Compression Bonding. [2020]
Park, Haesung and Kim, Sarah Eunkyung
IEEE Transactions on Components, Packaging & Manufacturing Technology. Feb2020, Vol. 10 Issue 2, p332-338. 7p.
SURFACE preparation, COPPER oxidation, PASSIVATION, SURFACE passivation, PLASMA pressure, and COPPER surfaces
The success of wafer-to-wafer or chip-to-chip bonding in 3-D packaging relies on the development of planarized, activated, and oxygen-free Cu surface. Preventing Cu oxidation is becoming a crucial issue in chip-to-chip bonding processes. In this study, a two-step plasma pretreatment process was demonstrated to prevent copper oxidation by virtue of forming a nitride passivation layer on the Cu surface. The two-step plasma pretreatment consisted of Ar plasma to activate the Cu surface, followed by N2 plasma to passivate the Cu surface. It was found that the pressure in the Ar plasma step had the greatest effect on the formation of nitrate passivation on the Cu surface, and the lower the pressure in the Ar plasma step, the better the formation of copper nitrate in the N2 plasma step. The two-step plasma pretreatment provided a nitride-passivated Cu surface and significantly improved the Cu-to-Cu bonding quality. This process may enable Cu-to-Cu bonding in an atmospheric environment. [ABSTRACT FROM AUTHOR]
8. 3-D-Printing-Based Selective-Ink-Deposition Technique Enabling Complex Antenna and RF Structures for 5G Applications up to 6 GHz. [2019]
Palazzi, Valentina, Su, Wenjing, Bahr, Ryan, Bittolo-Bon, Silvia, Alimenti, Federico, Mezzanotte, Paolo, Valentini, Luca, Tentzeris, Manos M., and Roselli, Luca
IEEE Transactions on Components, Packaging & Manufacturing Technology. Jul2019, Vol. 9 Issue 7, p1434-1447. 14p.
SLOT antennas, ANTENNAS (Electronics), THREE-dimensional printing, REFLECTANCE, BROADBAND antennas, and CAD/CAM systems
This paper introduces a novel additive-manufacturing technique to obtain high-resolution selective-ink-deposition on complex 3-D objects, packages, and modules for 5G applications. The technique consists of embossing the desired pattern directly on the 3-D printed dielectric surface and then applying ink with a suitable tool. This approach is tested in combination with stereolithography 3-D printing technology to obtain selectively metallized 3-D circuits. In particular, the "clear" resin from FormLab is utilized for the 3-D printed dielectric, while the metallization is performed with silver nanoparticle ink from Suntronic. As a preliminary study, test samples containing lines with different widths are manufactured, demonstrating a pitch down to $135~\mu \text {m}$ and satisfactory sheet resistance of $0.011~\Omega /\text {sq.}$ (the electromagnetic characterization of the dielectric resin is reported in the Appendix). Then, two broadband multiport RF structures are developed to show the versatility of the proposed technology. First, an ultrawideband 3-D crossover, operating in the range 100 MHz–5 GHz, is conceived to test the suitability of the proposed technology to perform selective metallization on curved semienclosed areas. Then, the technology is applied to a multiple-input–multiple-output (MIMO) antenna system, based on four proximity-fed annular slot antennas, arranged on the lateral sides of a cube and decoupled by introducing a cross-shaped structure in the interior of the cube. This circuit offers a broad range of metallization challenges, as it features embossed and engraved parts, high-resolution patterns (line widths down to 0.7 mm) and sharp edges. Each slot radiates unidirectionally with the same polarization and uses the cube and its internal cross-shaped structure as a resonant cavity. The antenna system is designed to operate in the band 3.4–3.8 GHz, which is one of the sub-6-GHz 5G bands in Europe, and it is thought for hotspot and access-point applications. The final antenna topology is composed of only two blocks, weighs 21.29 g, and occupies a volume of $44.4\times 45.8\times 45.8\,\,\text {mm}^{3}$ , featuring an envelope correlation coefficient (ECC) lower than 0.005 and a total active reflection coefficient (TARC) lower than −6 dB in all the bands of interests. [ABSTRACT FROM AUTHOR]
9. Transfer, Assembly, and Embedding of Small CMOS-Die Arrays for the Build-Up of Flexible Smart Implants. [2019]
Heid, Andreas, Camoleze de Andrade, Marcio, Bleck, Lena, von Metzen, Rene P., Kern, Dieter, Giehl, Jurgen, and Bucher, Volker
NANOFABRICATION, TRANSFER printing, THERAPEUTICS, SURFACE preparation, and POLYDIMETHYLSILOXANE
The integration of small wafer-based devices into flexible polymeric systems allows the fabrication of smart systems. Such systems are of high interest and are being developed in different fields. Active implants for biomedical applications promise new insights and therapy possibilities including the novel field of electroceuticals, which focuses on the treatment of systemic diseases by neuromodulation. For the fabrication of a new active flexible microelectrode array, we developed a process that allows the embedding of an array of small CMOS dies into a polymer foil. The process includes a transfer printing process based on adhesion, transferring the desired of the separated dies from UV-curable dicing tape to a substrate coated with sugar solution. The transfer printing process has shown to be highly reliable and selective, yielding a transfer success rate of 100% in most cases. The relative position of the transferred dies is conserved to less than $15~\mu \text{m}$ lateral displacement. To evaluate the process, the pull-off strength of the employed silicone stamps was measured. For stamps made of soft silicone, a pulling strength up to 83 kPa was obtained. In addition to this, a process for the embedding of the dies into a flexible foil system is presented. Using polydimethylsiloxane, the topography due to the dies' height is reduced from more than $200~\mu \text{m}$ to approximately $10~\mu \text{m}$ , enabling the use of standard microelectromechanical fabrication processes on top. [ABSTRACT FROM AUTHOR]
10. Study on Correction Method for Die Position Deviation Caused by Adhesive Tape Puncture. [2019]
Wu, Tao, Lou, Yuxian, Wu, Fupei, and Li, Bin
IEEE Transactions on Components, Packaging & Manufacturing Technology. Jul2019, Vol. 9 Issue 7, p1388-1395. 8p.
ADHESIVE tape, PETRI nets, DEFORMATION of surfaces, IMPACT testing, INTEGRATED circuits, and COMPUTER vision
Accurate peeling off and transferring of microchips play a critical role in LED die sorting technology. Generally, sorting efficiency of more than 36 KUPH, and an alignment deviation less than 1 mil ($25.4~\mu \text{m}$) is required. High precision position control and cooperation of multifactors should be implemented precisely. Among all the factors, the film deformation is an important one. As the sorting proceeds, dies are peeled off from substrates one by one, and the adhesive substrate is penetrated through a hole each time. As the number of stripped chips increases, viscoelastic deformation of tape surface takes place and tiny position shift of die adhered on tape arises. This shift may cause a negative impact on the peeling process. In this paper, linear viscoelastic deformation impact is tested with well-designed experiments. To evaluate the effect of tape deformation accurately for sorting the performance, stochastic Petri net model of the transferring system with dual-independent arms is formulated to analyze the influence of factors. On this basis, strategy on coordinating motion control and scheduling is proposed, rational velocity section is planned, and the active position compensation of supply platform is set, so that the die can be peeled off correctly and efficiently. Finally, to improve sorting performance, methods on active compensation of aligning platform are proposed and proven effective by an experimental validation. [ABSTRACT FROM AUTHOR]
11. Droplet Jumping on Superhydrophobic Copper Oxide Nanostructured Surfaces. [2019]
Lee, Jonggyu, Shao, Bowen, and Won, Yoonjin
IEEE Transactions on Components, Packaging & Manufacturing Technology. Jun2019, Vol. 9 Issue 6, p1075-1081. 7p.
COPPER oxide, FILM condensation, OPTICAL microscopes, COPPER surfaces, SCANNING electron microscopes, WATER harvesting, and DROPS
Condensation has been widely explored because of its importance in numerous applications including water desalination, water harvesting, power generation, and thermal management. Previous studies have shown that the enhancement in condensation heat transfer can be achieved with the engineering of surface wettability by promoting dropwise condensation that has lower thermal resistances than film condensation. In this paper, we explore microscopic-level droplet dynamics using various copper surfaces by employing a simple two-step chemical method. Nanostructured copper surfaces are prepared by a chemical immersion method using alkaline solution and are further functionalized by using dodecanoic acid that provides the hydrophobicity. The wetting properties and corresponding condensation processes are examined using an optical microscope and environmental scanning electron microscope by capturing the real-time phase change process. The measurements confirm that the surface morphology with the largest feature ratio promotes droplet jumping events. The understanding of condensation behaviors associated with nanostructured copper oxide surfaces can provide design rules for efficient surface structures for numerous condensation applications. [ABSTRACT FROM AUTHOR]
12. Study of Annular Copper-Filled TSVs of Sensor and Interposer Chips for 3-D Integration. [2019]
Cao Li, Jinglong Zou, Sheng Liu, Huai Zheng, and Peng Fei
IEEE Transactions on Components, Packaging & Manufacturing Technology. Mar2019, Vol. 9 Issue 3, p391-398. 8p.
COPPER, THREE-dimensional integrated circuits, INTEGRATED circuit interconnections, SILICON, ETCHING, and ELECTRIC conductivity
Actually, the 3-D integrating process is often viewed as the integration of wafer thinning, through-silicon vias (TSVs) etching and filling, redistribution layer formulation, and microbump bonding. The TSV formulation is a critical process because TSV decides the quality of the interconnection. In this paper, the annular copper-filled TSVs are fabricated into the sensor and interposer chips, which are thinned to 100 $\mu \text{m}$ , and 10- $\mu \text{m}$ -diameter TSV is etched and annularly filled by 2- $\mu \text{m}$ -thick copper only utilizing sputtering. It can significantly simplify the chip fabricating process, which only includes the TSV etching (deep reactive-ion etching), insulating layer formation, barrier layer sputtering and copper layer sputtering, and peeling. The thermal reliability of the annularly filled TSV structure is studied by the finite-element simulation, and it is found that the thermal stress is markedly reduced, and in the thermal cycle test, annularly filled TSV samples show better reliability. Meanwhile, the measured electrical conductivity shows a slightly worse but enough electrical conductivity property. [ABSTRACT FROM AUTHOR]
13. Cu–Cu Bonding in Ambient Environment by Ar/N2 Plasma Surface Activation and Its Characterization. [2019]
Shen Lin Chua, Jiawei Marvin Chan, Simon Chun Kiat Goh, and Chuan Seng Tan
IEEE Transactions on Components, Packaging & Manufacturing Technology. Mar2019, Vol. 9 Issue 3, p596-605. 10p.
COPPER bonding, SIMULATED annealing, PLASMA surface alloying, SHEAR strength, and ELECTRICAL properties of compound semiconductors
Ar/N2 plasma surface activation in ambient environment for Cu–Cu bonding has been performed and characterized. Cu–Cu bonding occurs at room temperature and under normal atmospheric conditions. Postbonding annealing is performed at 300 °C and below to control the overall thermal budget. Shear strength and hermeticity property of samples with varying annealing temperature are investigated. Samples annealed at 250 °C demonstrate the highest average shear strength of 20.3 MPa and the lowest average helium leak rate of $8.7 \times 10^{-9}\,\,\text {atm}\cdot \text {cc}$ /s. Daisy chain structures are used to examine the electrical property of sample bonded at 300 °C, and the temperature cycling tests from −40 °C to 125 °C for 1000 cycles have been performed for the reliability assessment. It is observed that the dies are well-bonded and intact after 1000 cycles even though the exposed Cu surface is heavily oxidized. [ABSTRACT FROM AUTHOR]
14. Optimization and Characterization of Low-Temperature Wafer-Level Hybrid Bonding Using Photopatternable Dry Film Adhesive and Symmetric Micro Cu Pillar Solder Bumps. [2018]
Yao, Mingjun, Zhao, Ning, Wang, Teng, Yu, Daquan, Xiao, Zhiyi, and Ma, Haitao
IEEE Transactions on Components, Packaging & Manufacturing Technology. Oct2018, Vol. 8 Issue 10, p1855-1862. 8p.
HYDROGEN bonding, SEMICONDUCTOR wafer bonding, CHEMICAL bonds, MICROELECTROMECHANICAL systems, and WAFER level packaging
A low-temperature wafer-level hybrid bonding process using micro Cu pillar solder bumps and photopatternable dry film adhesive is developed and investigated, where the microbumps and dry film adhesive are simultaneously bonded at a low temperature of 240 °C. The proposed hybrid bonding method has been applied to an 8-in wafer-to-wafer bonding. The effects of two kinds of bonding profiles, i.e., conventional bonding profile and optimized step applying force bonding profile, on post-bonding misalignment are evaluated, and the results show that a misalignment below $5~\mu \text{m}$ is achieved using optimized step applying force bonding profile. In addition, by optimizing the total thickness difference between the bump part and the dry film adhesive part and by increasing the bonding force to 13 KN, a seam-free hybrid bonding interface can be achieved, which shows an average shear strength of about 21.3 MPa. Herein, the proposed method is highly cost-effective and promising for wafer-level low-temperature hybrid bonding aimed at the future 3-D integrated circuit integration. [ABSTRACT FROM AUTHOR]
15. Effect of Solder Mask Surface Chemistry and Morphology on the Water Layer Formation Under Humid Conditions. [2018]
Piotrowska, Kamila, Din, Rameez Ud, Jellesen, Morten Stendahl, and Ambat, Rajan
IEEE Transactions on Components, Packaging & Manufacturing Technology. Oct2018, Vol. 8 Issue 10, p1756-1768. 13p.
SURFACE chemistry, THIN films, SOLDER & soldering, MICROSTRUCTURE, and SCANNING electron microscopy
This paper investigates the water film buildup on solder masked printed circuit board assembly (PCBA) laminates under humid conditions. The effects of solder mask surface chemistry, morphology, and roughness were investigated using different commercial laminates coated with solder mask. Chemical composition of the materials was analyzed using Fourier transform infrared spectroscopy. Microstructure and surface morphology were investigated using scanning electron microscopy, whereas the wettability was assessed using static contact angle technique, and correlated with the morphological observations. Solder mask surface waviness was characterized and quantified using a mechanical stylus profilometer. The formation of water film on a PCBA surface was monitored in situ by optical microscopy and electrochemical impedance spectroscopy and correlated with the observations of surface features. The results show that the solder mask surface chemistry and morphology significantly influence the water film formation, which is important for corrosion reliability of electronics exposed to humid conditions. [ABSTRACT FROM AUTHOR]
16. An Analytical Model for Permeability of Underfill Flow in Flip-Chip Packaging With Consideration of the Actual Specific Surface and Tortuosity. [2018]
Yao, Xing Jun and Zhang, Wen Jun
IEEE Transactions on Components, Packaging & Manufacturing Technology. Aug2018, Vol. 8 Issue 8, p1507-1514. 8p.
POROUS materials, PERMEABILITY, FLOW (Fluid dynamics), SURFACE preparation, and TORTUOSITY
Permeability is an important concept in understanding and modeling the flow or dynamic behavior of fluids in a porous medium (e.g., flip chip in electronics packaging). There are two factors (specific surface and tortuosity) that affect the permeability of a porous medium, but they are ignored by analytical models for permeability in the literature. In this paper, we present an analytical model for permeability of the underfill porous medium in flip-chip packaging by consideration of the actual specific surface and tortuosity. The proposed model and other models without consideration of the actual specific surface and tortuosity are compared with reference to a well-proven numerical model. The result of comparison has shown a significant improvement in accuracy with our model. This paper contributes not only to the underfill flip-chip package, but also to the field of porous mediums with regular arrangements of pores. [ABSTRACT FROM AUTHOR]
17. Thermal Management of Electronic Devices Using Combined Effects of Nanoparticle Coating and Graphene–Water Nanofluid in a Miniature Loop Heat Pipe. [2018]
Tharayil, Trijo, Asirvatham, Lazarus Godson, Rajesh, S., and Wongwises, Somchai
ELECTRONICS, EVAPORATORS, NANOFLUIDS, NANOPARTICLES, and THERMAL management (Electronic packaging)
The thermal management of electronic devices such as high-end central processing units, graphic processing units, insulated gate bipolar transistor, and circuit breaker in low-voltage switchboard operating between 20 and 380 W is investigated using a miniature loop heat pipe (mLHP) having nanoparticle-coated evaporator with graphene–water nanofluid. The thermal evaporation method is used to deposit copper nanoparticles on the evaporator surface for a coating thickness of 400 nm. The experimental results show that the combination of nanoparticle coating and nanofluid gives the highest heat transfer compared to the mLHP having uncoated and coated evaporator with distilled water as a working fluid. The use of nanofluid enhances the heat transfer performance of mLHP with an average reduction of 45.2% in thermal resistance and an average enhancement of 113.4% in evaporator heat transfer coefficient for the optimum nanofluid volume concentration of 0.006%. Similarly, the lowest evaporator temperatures are also obtained with the same concentration of nanofluid for various heat loads. The experimental results of mLHP having nanoparticle coating and nanofluid are also found to be repeatable from the repeated tests and suitable for a long-term operation. [ABSTRACT FROM AUTHOR]
18. Probing Molecular Structures of Buried Interfaces in Thick Multilayered Microelectronic Packages. [2018]
Ulrich, Nathan W., Xiao, Minyu, Zou, Xingquan, Williamson, Jaimal, and Chen, Zhan
NONLINEAR optics, MOLECULAR structure, MICROELECTRONICS, POLYIMIDES, and CYCLING
The fast development of flip-chip (FC) devices has helped to keep ICs on pace for Moore's law. FC devices have many buried interfaces, the structures of which all need to be investigated in order to optimize them. It is extremely difficult to examine molecular structures of buried interfaces in samples with multiple layers due to the lack of appropriate analytical tools. In this paper, real FC-on-leadframe devices, manufactured by Texas Instruments Incorporated, were investigated using the intrinsically interface-sensitive technique and sum-frequency generation (SFG) vibrational spectroscopy. By milling down the Si wafer, we can probe the polyimide (PI)/mold compound (MC) interface. By milling down further, we can examine the air/MC and the MC/leadframe (LF) interfaces. Methylene and methyl groups were detected from each of the three interfaces, and the orientation of methyl groups was determined at each interface. It was calculated that at the PI/MC interface, the methyl group tilt angle was 20° (from the surface normal). For the air/MC interface, the tilt angle was 43.5°, and for the LF/MC interface, the tilt angle was measured to be 45°. The deduced different methyl orientations at the two buried solid/solid interfaces can be interpreted by the interfacial interactions. The PI surface is more hydrophobic than the LF surface; therefore, it has more favorable interactions with the hydrophobic methyl groups, leading to a more "standing up" (smaller tilt angle) position for the methyl groups at the PI/MC interface. In this paper, SFG was successfully applied to study the buried interfaces in real devices. The SFG method used in this paper is general and can be applied to other real-world, complicated thick systems. [ABSTRACT FROM AUTHOR]
19. Nondestructive Analysis of Buried Interfacial Behaviors of Flux Residue and Their Impact on Interfacial Mechanical Property. [2018]
Ulrich, Nathan W., Andre, John S., Khanna, Kunal, Wei, Yuying, Xiu, Yonghao, and Chen, Zhan
IEEE Transactions on Components, Packaging & Manufacturing Technology. Jun2018, Vol. 12 Issue 3, p982-990. 9p.
FLUX (Metallurgy), MECHANICAL properties of metals, METALLIC oxides, COPPER oxide, and PHOTOELECTRON spectroscopy
Flux materials are ubiquitously utilized in the microelectronics industry during back-end processing. The Cu oxides or organic solderability preservatives present on Cu posts used in flip-chip packages must be removed by flux before solder reflow and die attachment to ensure a quality connection between the substrate and the die. However, flux residues can cause solder bridging, which renders the device useless. These residues must be studied in situ at the buried interface to determine fundamental interactions and how the residues can be eliminated. In this paper, model flux residues were investigated at the surface and the buried epoxy interface with sum frequency generation vibrational spectroscopy. Glutaric acid. served as the model flux, simulating fluxes that use dicarboxylic acids as one of the main components of the fluxing agent. It was found that the flux residues greatly change the buried interface on both Cu and silica surfaces, which affects properties such as adhesion. It was also observed that the fluxes require long washing times before they are completely removed. This paper is a step forward in flux residue analysis and will help the industry better understand molecular-level details of commonly used processes. [ABSTRACT FROM AUTHOR]
20. An Efficient Process of Surface Modification and Patterning for LED Encapsulation. [2018]
Moulin, G., Consonni, M., Nonglaton, G., Ait-Mani, N., Vandeneynde, A., Levy, F., and Gasse, A.
IEEE Transactions on Components, Packaging & Manufacturing Technology. May2018, Vol. 8 Issue 5, p904-909. 6p.
LIGHT emitting diodes, PLASTIC embedment of electronic equipment, COMPUTER simulation, ELECTRONICS packaging, MONTE Carlo method, and SURFACES (Technology)
Encapsulation is a critical step in LED packaging to ensure good light extraction and protection. We present a novel mold-free process using a specific functionalization of the substrate to master the shape of the encapsulant dome. By controlling its aspect ratio, it is possible to increase light extraction. Experiments are correlated with Monte Carlo simulations to evidence the impact of surface tension on the dome shape as well as the effect of the refractive index on the light output. A moderate optical gain of 10% is obtained as the refractive index of the encapsulant material increases from 1.42 to 1.64, which is explained with the simulations as a strong effect of the die parameters (roughness and back mirror) on the light extraction. [ABSTRACT FROM PUBLISHER]
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