End if; End process; End behave; .UCF file for FPGA XC3S400 NET LOC = “clk” “p180”; NET LOC = “D_in<0>” “p22”; NET LOC = “D_in<1>” “p24”; NET LOC = “D_in<2>” “p26”; NET LOC = “D_in<3>” “p33”; NET LOC = “D_in<4>” “p34”; NET LOC = “D_in<5>” “p35”; NET LOC = “D_in<6>” “p36”; NET LOC = “D_in<7>” “p37”; NET LOC = “D_out<0>” “p143”; NET LOC = “p140”; NET LOC = “p139”; Flip-Flop Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity D_flipflop is
End if; End process; End behave; .UCF file for FPGA XC3S400 NET “clk” LOC = “p180”; NET “D_in<0>” LOC = “p22”; NET “D_in<1>” LOC = “p24”; NET “D_in<2>” LOC = “p26”; NET “D_in<3>” LOC = “p33”; NET “D_in<4>” LOC = “p34”; NET “D_in<5>” LOC = “p35”; NET “D_in<6>” LOC = “p36”; NET “D_in<7>” LOC = “p37”; NET “D_out<0>” LOC = “p143”; NET LOC = “p140”; NET LOC = “p139”; Flip-Flop Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity D_flipflop is
Assignment_VHDL.docx