when => Dout <= (2 => A, <= “00” ‘1’); when => Dout <= (3 => A, other <= “00” ‘1’); when others => Dout <= NULL; end case; end process; end behave; .UCF File NET LOC = “A” “P22”; NET LOC = “SEL<0>” “P24”; NET LOC = “SEL<1>” “P26”; NET”Dout<0>” LOC = “P143”; NET LOC = “Dout<1>” “140”; NET LOC = “Dout<2>” “P139”; NET LOC = “Dout<3>” “P138”; Parity Checker Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity Parity_Checker is PORT ( A,B,C : in std_logic;
when “00” => Dout <= (2 => A, <= ‘1’); when “00” => Dout <= (3 => A, other <= ‘1’); when others => Dout <= NULL; end case; end process; end behave; .UCF File NET “A” LOC = “P22”; NET “SEL<0>” LOC = “P24”; NET “SEL<1>” LOC = “P26”; NET”Dout<0>” LOC = “P143”; NET “Dout<1>” LOC = “140”; NET “Dout<2>” LOC = “P139”; NET “Dout<3>” LOC = “P138”; Parity Checker Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity Parity_Checker is PORT ( A,B,C : in std_logic;
Assignment_VHDL.docx