NET LOC = “Y<6>” “p131”; NET LOC = “Y<7>” “p130”; Half Adder Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity HA is PORT (X, Y : in std_logic; SUM, Carry : out std_logic ); End HA; Architecture behave of HA is begin Sum <= X xor Y; <= X and Y; End behave; .UCF file for FPGA XC3S400 NET LOC = “X” “p22”; NET LOC = “Y” “p24”; NET LOC = “SUM” “p140”; NET LOC = “Carry” “p143”; Half Subtractor
NET “Y<6>” LOC = “p131”; NET “Y<7>” LOC = “p130”; Half Adder Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity HA is PORT (X, Y : in std_logic; SUM, Carry : out std_logic ); End HA; Architecture behave of HA is begin Sum <= X xor Y; <= X and Y; End behave; .UCF file for FPGA XC3S400 NET “X” LOC = “p22”; NET “Y” LOC = “p24”; NET “SUM” LOC = “p140”; NET “Carry” LOC = “p143”; Half Subtractor
Assignment_VHDL.docx