Variable ring : std_logic_vector(3 downto 0); If clk’event and clk=’1’ then If FREEZE = then ‘0’ Case ring is When => ring := “1110” “1101”; When => ring := “1101” “1011”; When => ring := “1011” “0111”; When => ring := “0111” “1110”; When others => ring := “1110”; End case; End if; DAV <= FREEZE; End if; Row <= ring; CASE ring is When => DATA(3 downt 2) <= “1110” “00”; When => DATA(3 2) <= “1101” “01”; When => DATA(3 downt 2) <= “1011” “10”; When => DATA(3 2) <= “0111” “11”; When others => DATA(3 downt 2) <= “00”; End case; CASE col is When => DATA(1 downt 0) <= FREEZE <= “1110” “00”; ‘1’; When => DATA(1 downt 0) <= FREEZE <= “1101” “01”; ‘1’;
Variable ring : std_logic_vector(3 downto 0); If clk’event and clk=’1’ then If FREEZE = ‘0’ then Case ring is When “1110” => ring := “1101”; When “1101” => ring := “1011”; When “1011” => ring := “0111”; When “0111” => ring := “1110”; When others => ring := “1110”; End case; End if; DAV <= FREEZE; End if; Row <= ring; CASE ring is When “1110” => DATA(3 downt 2) <= “00”; When “1101” => DATA(3 2) <= “01”; When “1011” => DATA(3 downt 2) <= “10”; When “0111” => DATA(3 2) <= “11”; When others => DATA(3 downt 2) <= “00”; End case; CASE col is When “1110” => DATA(1 downt 0) <= “00”; FREEZE <= ‘1’; When “1101” => DATA(1 downt 0) <= “01”; FREEZE <= ‘1’;
Assignment_VHDL.docx