Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity HS is PORT (X, Y : in std_logic; Diff, Borrow : out std_logic ); End HS; Architecture behave of HS is begin Diff <= X xor Y; Borrow <= NOT X and Y; End behave; .UCF file for FPGA XC3S400 NET LOC = “X” “p22”; NET LOC = “Y” “p24”; NET LOC = “Diff” “p140”; NET LOC = “Borrow” “p143”; Encoder Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;
Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity HS is PORT (X, Y : in std_logic; Diff, Borrow : out std_logic ); End HS; Architecture behave of HS is begin Diff <= X xor Y; Borrow <= NOT X and Y; End behave; .UCF file for FPGA XC3S400 NET “X” LOC = “p22”; NET “Y” LOC = “p24”; NET “Diff” LOC = “p140”; NET “Borrow” LOC = “p143”; Encoder Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;
Assignment_VHDL.docx