End FA_4bit; Architecture behave of FA_4bit is Signal c : std_logic_vector (4 downto 0); Begin Process (a,b,cin,c) Begin C(0) < cin; for I in a’range loop Sum(i) <= a(i) xor b(i) xor c(i); C(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i)); End loop; Cout <= c(c’HIGH); .UCF file for FPGA XC3S400 NET LOC = “a<0>” “p33” NET LOC = “a<1>” “p26”; NET LOC = “a<2>” “p24”; NET LOC = “a<3>” “p22”; NET LOC = “b<0>” “p37”; NET LOC = “b<1>” “p36”; NET LOC = “b<2>” “p35”; NET LOC = “b<3>” “p34”; NET LOC = “cin” “p42”; NET LOC = “cout” “p133”;
End FA_4bit; Architecture behave of FA_4bit is Signal c : std_logic_vector (4 downto 0); Begin Process (a,b,cin,c) Begin C(0) < cin; for I in a’range loop Sum(i) <= a(i) xor b(i) xor c(i); C(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i)); End loop; Cout <= c(c’HIGH); .UCF file for FPGA XC3S400 NET “a<0>” LOC = “p33” NET “a<1>” LOC = “p26”; NET “a<2>” LOC = “p24”; NET “a<3>” LOC = “p22”; NET “b<0>” LOC = “p37”; NET “b<1>” LOC = “p36”; NET “b<2>” LOC = “p35”; NET “b<3>” LOC = “p34”; NET “cin” LOC = “p42”; NET “cout” LOC = “p133”;
Assignment_VHDL.docx