Architecture behave of Counter_4bit is Signal cnt_state : std_logic_vector (7 downto 0); Begin Process (clk, reset, cnt_en) Begin If(reset = then ‘1’) --asynchronous reset Cnt_state <= “00000000”; Elsif (clk’event and clk=’1’ ) then If (cnt_en = then ‘1’) Cnt_state <= cnt_state+1; End if; End if; End process; Dout <= cnt_state (6 downto 3); End behave; .UCF file for FPGA XC3S400 NET LOC = “clk” “p180”; NET LOC = “cnt_en” “p22”; NET LOC = “dout<0>” “p143”; NET LOC = “dout<1>” “p140”; NET LOC = “dout<2>” “p139”; NET LOC = “dout<3>” “p138”; NET LOC = “p204”;
Architecture behave of Counter_4bit is Signal cnt_state : std_logic_vector (7 downto 0); Begin Process (clk, reset, cnt_en) Begin If(reset = ‘1’) then --asynchronous reset Cnt_state <= “00000000”; Elsif (clk’event and clk=’1’ ) then If (cnt_en = ‘1’) then Cnt_state <= cnt_state+1; End if; End if; End process; Dout <= cnt_state (6 downto 3); End behave; .UCF file for FPGA XC3S400 NET “clk” LOC = “p180”; NET “cnt_en” LOC = “p22”; NET “dout<0>” LOC = “p143”; NET “dout<1>” LOC = “p140”; NET “dout<2>” LOC = “p139”; NET “dout<3>” LOC = “p138”; NET LOC = “p204”;
Assignment_VHDL.docx