When => Y(0) <= “000” ‘0’; When => Y(0) <= “000” ‘0’; When => Y(1) <= “001” ‘0’; When => Y(2) <= “010” ‘0’; When => Y(3) <= “011” ‘0’; When => Y(4) <= “100” ‘0’; When => Y(5) <= “101” ‘0’; When => Y(6) <= “110” ‘0’; When => Y(7) <= “111” ‘0’; End case; End if; End process; End behave; .UCF file for FPGA XC3S400 NET LOC = “en” “p33”; NET LOC = “sel<0>” “p26”; NET LOC = “sel<1>” “p24” NET LOC = “sel<2> “p22”; NET LOC = “Y<0>” “p143”; NET LOC = “Y<1>” “p140”; NET LOC = “Y<2>” “p139”; NET LOC = “Y<3>” “p138”; NET LOC = “Y<4>” “p133”; NET LOC = “Y<5>” “p132”;
When “000” => Y(0) <= ‘0’; When “000” => Y(0) <= ‘0’; When “001” => Y(1) <= ‘0’; When “010” => Y(2) <= ‘0’; When “011” => Y(3) <= ‘0’; When “100” => Y(4) <= ‘0’; When “101” => Y(5) <= ‘0’; When “110” => Y(6) <= ‘0’; When “111” => Y(7) <= ‘0’; End case; End if; End process; End behave; .UCF file for FPGA XC3S400 NET “en” LOC = “p33”; NET “sel<0>” LOC = “p26”; NET “sel<1>” LOC = “p24” NET “sel<2> LOC = “p22”; NET “Y<0>” LOC = “p143”; NET “Y<1>” LOC = “p140”; NET “Y<2>” LOC = “p139”; NET “Y<3>” LOC = “p138”; NET “Y<4>” LOC = “p133”; NET “Y<5>” LOC = “p132”;
Assignment_VHDL.docx