Library IEEE; Use ieee.std_logic_1164.all Entity Priority_Encod is PORT ( Sw : in std_logic_vector(9 downto 0); OE : in std_logic; D : out std_logic_vector(3 downto 0) ); End; Architecture concur of Priority_Encod is Begin D <= when OE = or SW=”1111111111” else “ZZZZ” ‘0’ when SW(9)=’0’ else “1001” when SW(8)=’0’ else “1000” when SW(7)=’0’ else “0111” when SW(6)=’0’ else “0110” when SW(5)=’0’ else “0101” when SW(4)=’0’ else “0100” when SW(3)=’0’ else “0011” when SW(2)=’0’ else “0010” when SW(1)=’0’ else “0001” when SW(0)=’0’ ; “0000” End;
Library IEEE; Use ieee.std_logic_1164.all Entity Priority_Encod is PORT ( Sw : in std_logic_vector(9 downto 0); OE : in std_logic; D : out std_logic_vector(3 downto 0) ); End; Architecture concur of Priority_Encod is Begin D <= “ZZZZ” when OE = ‘0’ or SW=”1111111111” else “1001” when SW(9)=’0’ else “1000” when SW(8)=’0’ else “0111” when SW(7)=’0’ else “0110” when SW(6)=’0’ else “0101” when SW(5)=’0’ else “0100” when SW(4)=’0’ else “0011” when SW(3)=’0’ else “0010” when SW(2)=’0’ else “0001” when SW(1)=’0’ else “0000” when SW(0)=’0’ ; End;
Assignment_VHDL.docx