Truth Table for 2 to 4 decoder Sw S3 Sw S2 Sw S2 LED4 o/p LED3 o/p LED2 o/p LED1 o/p input En input a input a Y3 Y2 Y1 Y0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 Decoder 3 to 8 Line Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity decoder3to8 is PORT ( signal sel : in std_logic_vector( 2 downto 0); Signal en : in std_logic; Signal Y : out std_logic_vector( 7 downto 0) ); End decoder3to8; Architecture behave of decoder3to8 is Process ( sel, en) Y <= “11111111”; If(en=’1’) then Case sel is
Truth Table for 2 to 4 decoder Sw S3 input En Sw S2 input a Sw S2 input a LED4 o/p Y3 LED3 o/p Y2 LED2 o/p Y1 LED1 o/p Y0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 Decoder 3 to 8 Line Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity decoder3to8 is PORT ( signal sel : in std_logic_vector( 2 downto 0); Signal en : in std_logic; Signal Y : out std_logic_vector( 7 downto 0) ); End decoder3to8; Architecture behave of decoder3to8 is Process ( sel, en) Y <= “11111111”; If(en=’1’) then Case sel is
Assignment_VHDL.docx