Decoder 2 to 4 Line Library IEEE; Use ieee.std_logic_1164.all; Entity decode2to4 is PORT ( a,b, enable : in std_logic; z : out std_logic_vector ( 3 downto 0) ); End decode2to4; Architecture DECODE_Concurrent of decode2to4 is Begin Z(0) <= when ((enable =’1’) and (a=’0’) and (b=’0’)) else ‘1’ ‘0’; Z(1) <= when ((enable =’1’) and (a=’0’) and (b=’1’)) else ‘1’ ‘0’; Z(0) <= when ((enable =’1’) and (a=’1’) and (b=’0’)) else ‘1’ ‘0’; Z(0) <= when ((enable =’1’) and (a=’1’) and (b=’1’)) else ‘1’ ‘0’; End DECODE_Concurrent; .UCF file for FPGA XC3S400 NET LOC = “a” “p22”; NET LOC = “b” “p24”; NET LOC = “a” “p22”; NET LOC = “enable” “p26”; NET LOC = “z<0>” “p143”; NET LOC = “z<1>” “p140”; NET LOC = “z<2>” “p139”; NET LOC = “z<3>” “p138”;
Decoder 2 to 4 Line Library IEEE; Use ieee.std_logic_1164.all; Entity decode2to4 is PORT ( a,b, enable : in std_logic; z : out std_logic_vector ( 3 downto 0) ); End decode2to4; Architecture DECODE_Concurrent of decode2to4 is Begin Z(0) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’0’)) else ‘0’; Z(1) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’1’)) else ‘0’; Z(0) <= ‘1’ when ((enable =’1’) and (a=’1’) and (b=’0’)) else ‘0’; Z(0) <= ‘1’ when ((enable =’1’) and (a=’1’) and (b=’1’)) else ‘0’; End DECODE_Concurrent; .UCF file for FPGA XC3S400 NET “a” LOC = “p22”; NET “b” LOC = “p24”; NET “a” LOC = “p22”; NET “enable” LOC = “p26”; NET “z<0>” LOC = “p143”; NET “z<1>” LOC = “p140”; NET “z<2>” LOC = “p139”; NET “z<3>” LOC = “p138”;
Assignment_VHDL.docx