Else Y(0) <= ‘0’; End if; ------------Remainder----------------------------- R <= conv_std_logic_vector (temp,4); End if; End process; End behavioural; .UCF File NET LOC = “a<0> “p34”; NET LOC = “a<1> “p35”; NET LOC = “a<2> “p36”; NET LOC = “a<3> “p37”; NET LOC = “b<0> “p22”; NET LOC = “b<1> “p24”; NET LOC = “b<2> “p26”; NET LOC = “b<3> “p33”; NET LOC = “y<0> “p143”; NET LOC = “y<1> “p140”; NET LOC = “y<2> “p139”; NET LOC = “y<3> “p138”; NET LOC = “r<0> “p133”; NET LOC = “r<1> “p132”; NET LOC = “r<2> “p131”;
Else Y(0) <= ‘0’; End if; ------------Remainder----------------------------- R <= conv_std_logic_vector (temp,4); End if; End process; End behavioural; .UCF File NET “a<0> LOC = “p34”; NET “a<1> LOC = “p35”; NET “a<2> LOC = “p36”; NET “a<3> LOC = “p37”; NET “b<0> LOC = “p22”; NET “b<1> LOC = “p24”; NET “b<2> LOC = “p26”; NET “b<3> LOC = “p33”; NET “y<0> LOC = “p143”; NET “y<1> LOC = “p140”; NET “y<2> LOC = “p139”; NET “y<3> LOC = “p138”; NET “r<0> LOC = “p133”; NET “r<1> LOC = “p132”; NET “r<2> LOC = “p131”;
Assignment_VHDL.docx