NET LOC = “Sel<0>” “p34”; NET LOC = “Sel<1>” “p35”; NET LOC = “A” “p22”; NET LOC = “B” “p24”; NET LOC = “C” “p26”; NET LOC = “D” “p33”; NET LOC = “Dout” “p143”; DeMultiplexure Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity DeMux is PORT ( A : in std_logic; SEL : in std_logic_vector(1 downto 0); Dout : out std_logic_vector(3 downto 0); ); Architecture behave of DeMux is Begin Process(SEL,A) Begin Case SEL is when => Dout <= (0 => A, <= “00” ‘1’); when => Dout <= (1 => A, other <= “01” ‘1’);
NET “Sel<0>” LOC = “p34”; NET “Sel<1>” LOC = “p35”; NET “A” LOC = “p22”; NET “B” LOC = “p24”; NET “C” LOC = “p26”; NET “D” LOC = “p33”; NET “Dout” LOC = “p143”; DeMultiplexure Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity DeMux is PORT ( A : in std_logic; SEL : in std_logic_vector(1 downto 0); Dout : out std_logic_vector(3 downto 0); ); Architecture behave of DeMux is Begin Process(SEL,A) Begin Case SEL is when “00” => Dout <= (0 => A, <= ‘1’); when “01” => Dout <= (1 => A, other <= ‘1’);
Assignment_VHDL.docx