6. Design of Synchronous Counters Qn Qn+1 J K Aim: To design a counter using JK flip-flops for the following 0 0 0 X binary sequence: 0, 4, 2, 1, 6 and repeat. Apparatus: S. No Quantity 0 1 1 X Design Procedure: 1 0 X 1 In a also known as a all the synchronous counter, parallel counter, 1 1 X 0 flip-flops in the counter changestate at the same time in Description of Item 1. IC 7408, 7432 01 Each synchronism with the input clock signal. The clock signal in this case issimultaneously applied to 2. IC 7476 02 the clock inputs of all the flip-flops. 3. Digital Trainer Kit 01 4. Bread Board 01 Circuit Excitation and output table: Present State Next (NS) Flip-flop Input functions (PS) 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 1 0 Excitation table for JK FF
6. Design of Synchronous Counters Aim: To design a counter using JK flip-flops for the following binary sequence: 0, 4, 2, 1, 6 and repeat. S. No Description of Item Quantity 1. IC 7408, 7432 01 Each 2. IC 7476 02 3. Digital Trainer Kit 01 4. Bread Board 01 Apparatus: Design Procedure: In a synchronous counter, also known as a parallel counter, all the flip-flops in the counter changestate at the same time in synchronism with the input clock signal. The clock signal in this case issimultaneously applied to the clock inputs of all the flip-flops. Present State (PS) Next (NS) Flip-flop Input functions 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 1 0 Circuit Excitation and output table: Excitation table for JK FF Qn Qn+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0
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