Entity encoder is PORT ( Reset : in std_logic; Clk : in std_logic; D_in : in std_logic_vector (7 downto 0); D_out : out std_logic_vector (2 downto 0) ); End encoder Architecture behave of encoder is Begin Process(reset, clk, D_in) Begin If (reset=’1’) then D_out <= “000”; Elsif (Clk’event and Clk = then ‘1’) Case D_in is When => D_out <= “00000001” “000”; When => D_out <= “00000010” “001”; When => D_out <= “00000100” “010”; When => D_out <= “00001000” “011”; When => D_out <= “00010000” “100”; When => D_out <= “00100000” “101”; When => D_out <= “01000000” “110”; When => D_out <= “10000000” “111”; End case;
Entity encoder is PORT ( Reset : in std_logic; Clk : in std_logic; D_in : in std_logic_vector (7 downto 0); D_out : out std_logic_vector (2 downto 0) ); End encoder Architecture behave of encoder is Begin Process(reset, clk, D_in) Begin If (reset=’1’) then D_out <= “000”; Elsif (Clk’event and Clk = ‘1’) then Case D_in is When “00000001” => D_out <= “000”; When “00000010” => D_out <= “001”; When “00000100” => D_out <= “010”; When “00001000” => D_out <= “011”; When “00010000” => D_out <= “100”; When “00100000” => D_out <= “101”; When “01000000” => D_out <= “110”; When “10000000” => D_out <= “111”; End case;
Assignment_VHDL.docx