GOVERNMENT POLYTECHNIC COLLEGE PURASAWALKAM, CHENNAI - 12 DEPARTMENT OF COMPUTER ENGINEERING II YEAR / III SEM / I1ST SHIFT SUBJCT LOG : 35231- BASICS OF ELECTRICAL AND ELECTRONICS ENGINEERING Subject handled by: LAVANYA.V Designation : Part Time / Guest Lecturer CHAPTER HOURS PORTIONS COVERED DATE NO UNIT 4 : BOOLEAN ALGEBRA ,LOGIC GATES COMBINATIONAL SYSTEM (14 Hrs) Number representation: Decimal, Binary, Octal and Hexa decimal 11.06.18 number systems Conversion of number from one number system to another 4.1 13.06.18 (without decimal point) BCD CODE ASCII Codes – 13.06.18 Parity bit Use of a parity bit Odd parity and Even parity Logic gates: Positive and Negative logic System - Definition, Truth 14.06.18 table, Symbol and Logical equations of AND OR - NOT – Definition, Truth table, Symbol and Logical equations of EXOR - 4.2 14.06.18 EXNOR (Only 2- inputs) gates 15.06.18 Universal gates - NAND - NOR Symbol and truth table – Boolean Algebra : Basic laws of Boolean algebra Demorgan’s – 15.06.18 Theorem and proofs Duality theorem - Simplification of logical equations using 4.3 15.06.18 Boolean laws - De-Morgan’s theorem 18.06.18 Two and three variable Karnaugh map 21.06.18 Arithmetic Circuits: Half Adder and full adder- Truth table, 4.4 Circuit diagram Half subtractor and Full subtractor - table, – 21.06.18 Circuit diagram. Combinational circuits: Parity generator and checker 22.06.18 4.5 Multiplexer De Multiplexer 22.06.18 – Encoder - Decoder (Definition and Circuits only) 25.06.18 25.06.18 Comparator Circuit for two bit UNIT V . SEQUENTIAL LOGIC SYSTEM 13 Hrs Flip flops: Basic principle of operation - S-R D flip-flop – 28.06.18 Operation and truth table Race Condition JK flip flop T flip flop 28.06.18 – – 5.1 Toggling - Edge Triggered Flip-flop 02.07.18 – Level Triggered flip flop - Need for a Master-slave flip flop 02.07.18
GOVERNMENT POLYTECHNIC COLLEGE PURASAWALKAM, CHENNAI - 12 DEPARTMENT OF COMPUTER ENGINEERING II YEAR / III SEM / I1ST SHIFT SUBJCT LOG : 35231- BASICS OF ELECTRICAL AND ELECTRONICS ENGINEERING Subject handled by: LAVANYA.V Designation : Part Time / Guest Lecturer HOURS CHAPTER NO PORTIONS COVERED DATE UNIT 4 : BOOLEAN ALGEBRA ,LOGIC GATES COMBINATIONAL SYSTEM (14 Hrs) 4.1 Number representation: Decimal, Binary, Octal and Hexa decimal number systems 11.06.18 Conversion of number from one number system to another (without decimal point) BCD CODE – ASCII Codes 13.06.18 Parity bit Use of a parity bit Odd parity and Even parity 13.06.18 4.2 Logic gates: Positive and Negative logic System - Definition, Truth table, Symbol and Logical equations of AND – OR - NOT 14.06.18 Definition, Truth table, Symbol and Logical equations of EXOR - EXNOR (Only 2- inputs) gates 14.06.18 Universal gates - NAND - NOR – Symbol and truth table 15.06.18 4.3 Boolean Algebra : Basic laws of Boolean algebra – Demorgan’s Theorem and proofs 15.06.18 Duality theorem - Simplification of logical equations using Boolean laws - De-Morgan’s theorem 15.06.18 Two and three variable Karnaugh map 18.06.18 4.4 Arithmetic Circuits: Half Adder and full adder- Truth table, 21.06.18 Circuit diagram – Half subtractor and Full subtractor - table, Circuit diagram. 21.06.18 4.5 Combinational circuits: Parity generator and checker 22.06.18 Multiplexer – De Multiplexer 22.06.18 Encoder - Decoder (Definition and Circuits only) 25.06.18 Comparator Circuit for two bit 25.06.18 UNIT V . SEQUENTIAL LOGIC SYSTEM 13 Hrs 5.1 Flip flops: Basic principle of operation - S-R D flip-flop – Operation and truth table 28.06.18 Race Condition – JK flip flop – T flip flop 28.06.18 Toggling - Edge Triggered Flip-flop – 02.07.18 Level Triggered flip flop - Need for a Master-slave flip flop 02.07.18
EEE_LESSON_PLAN_II_SHIFT_2year_2shift.docx