P4 Arithmetic circuits for 2C integer numbers: subtraction, comparison, etc. and gate-level simulations Objectives After studying the content of these projects, you will be able to: Use standard arithmetic blocks for integer numbers based on two’s complement (2C) convention: subtractors, adders, comparators, multipliers, etc. arithmetic operations in two’s complement format (2C). Explain the range of an N-bit number in 2C and the meaning of an overflow operation result. Design combinational circuits in a hierarchical way using multiple combinational circuits as components. Explain why a XOR gate can be considered a programmable gate that can be both, an inverter or a buffer. Perform VHDL gate-level simulations to calculate propagation delays and the maximum speed of computation of a given circuit. Discuss the main features of a CPLD or FPGA. Implement circuits in the PLD device (CPLD or FPGA) populating a laboratory training board. Addition and subtraction in two’s complement Draw the symbol and the internal schematic of a 6-bit two’s complement adder/subtractor and determine the range of the operants and the result. Explain how the overflow (OV) flag works.
P4 Arithmetic circuits for 2C integer numbers: subtraction, comparison, etc. and gate-level simulations Objectives After studying the content of these projects, you will be able to: Use standard arithmetic blocks for integer numbers based on two’s complement (2C) convention: subtractors, adders, comparators, multipliers, etc. arithmetic operations in two’s complement format (2C). Explain the range of an N-bit number in 2C and the meaning of an overflow operation result. Design combinational circuits in a hierarchical way using multiple combinational circuits as components. Explain why a XOR gate can be considered a programmable gate that can be both, an inverter or a buffer. Perform VHDL gate-level simulations to calculate propagation delays and the maximum speed of computation of a given circuit. Discuss the main features of a CPLD or FPGA. Implement circuits in the PLD device (CPLD or FPGA) populating a laboratory training board. Addition and subtraction in two’s complement Draw the symbol and the internal schematic of a 6-bit two’s complement adder/subtractor and determine the range of the operants and the result. Explain how the overflow (OV) flag works.
CSD_Problems_v4.docx