memory addresses. also cover word addresses in a byte addressable processor Ch#4 P1 Review overflow detection in 7, 8, ALU lab 2 unsigned Week #4 Lab #3 and signed 9/12-9/15 arithmetic and ALU design Ch#5 P1 9, 10, HW #5A 2 Single Week #5 (Single-cycle 9/19-9/22 CPU, CPU) Quiz exam on Thursday Sept. 22, 0 2016 Quiz slot in Lab 4 Ch#5 P2 Part #4 CPU (Multi-cycle 11, 12 Datapath and CPU) Week 2 control design (paper #6 Ch#5 P2 submission) HW #5B CPU 2nd (Multi-cycle edition design CPU) Ch#6 5-stage pipeline: data dependency solutions (Compiler 13,14, Pipelining solution, HDU & 15, 16 Lab 6 – FU), and branch Week 4 Part 4 implementations #7,8 (late branch vs. submission) early branch), branch delay slots. Also cover exceptions. Ch#7 P1 17, 18 Cache Cache: Mapping Week HW #6 2 techniques, #9 Pipeline CPU address lab #7 division into
memory addresses. also cover word addresses in a byte addressable processor 2 7, 8, Week #4 9/12-9/15 Ch#4 P1 Review overflow detection in unsigned and signed arithmetic and ALU design ALU lab Lab #3 2 9, 10, Week #5 9/19-9/22 Ch#5 P1 Single CPU, HW #5A (Single-cycle CPU) 0 Quiz exam on Thursday Sept. 22, 2016 in Quiz slot 2 11, 12 Week #6 Ch#5 P2 CPU Datapath and control design Ch#5 P2 CPU 2nd edition design Lab 4 Part #4 (Multi-cycle CPU) (paper submission) HW #5B (Multi-cycle CPU) 4 13,14, 15, 16 Week #7,8 Ch#6 5-stage pipeline: data dependency solutions (Compiler solution, HDU & FU), and branch implementations (late branch vs. early branch), branch delay slots. Also cover exceptions. Pipelining Lab 6 – Part 4 submission) 2 17, 18 Week #9 Ch#7 P1 Cache: Mapping techniques, CPU address division into Cache HW #6 Pipeline lab #7
EE457_Syllabus_Fall_2016.docx