card. The four clock outputs of a block consist of a global delay that is the sum of two global delays settings (common to all four outputs), plus a specific delay setting for each channel. The global delay setting can span the 14 nsec bunch spacing. The channel delays are intended to compensate for cable length variations and should generally be within +/- 1.5 nsec of each other. The delay for each chip can vary from 3.2ns to 14.8ns in 10ps increments. BSM/FLM (Block A Only; Block B not used for BSM/FLM) Offset Contents 0 A, Global Delay 1 1 Block A, Global Delay 0 2 Block A, Card 3 Delay (chan 24 - 31) 3 Block A, Card 2 Delay (chan 16 - 23) 4 Block A, Card 1 Delay (chan 8 - 15) 5 Block A, Card 0 Delay (chan 0 7) – BPM (Block A for one species; Block B for the other) Offset Contents 0 Block A, Global Delay 1 1 Block A, Global Delay 0 2 Block A, Card 3 Delay 3 Block A, Card 2 Delay 4 Block A, Card 1 Delay 5 Block A, Card 0 Delay 10 Block A, Turns Marker Delay 11 Block A, Clock Frequency 12 Block A, Clock Width 8 Block B, Global Delay 1 9 Block B, Global Delay 0 A Block B, Card 3 Delay B Block B, Card 2 Delay C Block B, Card 1 Delay D Block B, Card 0 Delay 18 Block B, Turns Marker Delay 19 Block B, Clock Frequency 1A Block B, Clock Width 1F Common Turns Marker Delay A typical calibration scheme is to set the channel delays to mid-scale and adjust the global delay for optimal results looking at the sum of all four channels. Then increment or decrement the individual channel delays to optimize the results for each channel. Timing Board (250 MHz only boards) TIMING BOARD 0X10020000 - 0X100200FF (dec=268566528) ADD PROGRAMMING DATA FOR MELLER’S %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Auxiliary
card. The four clock outputs of a block consist of a global delay that is the sum of two global delays settings (common to all four outputs), plus a specific delay setting for each channel. The global delay setting can span the 14 nsec bunch spacing. The channel delays are intended to compensate for cable length variations and should generally be within +/- 1.5 nsec of each other. The delay for each chip can vary from 3.2ns to 14.8ns in 10ps increments. BSM/FLM (Block A Only; Block B not used for BSM/FLM) Offset Contents 0 A, Global Delay 1 1 Block A, Global Delay 0 2 Block A, Card 3 Delay (chan 24 - 31) 3 Block A, Card 2 Delay (chan 16 - 23) 4 Block A, Card 1 Delay (chan 8 - 15) 5 Block A, Card 0 Delay (chan 0 – 7) BPM (Block A for one species; Block B for the other) Offset Contents 0 Block A, Global Delay 1 1 Block A, Global Delay 0 2 Block A, Card 3 Delay 3 Block A, Card 2 Delay 4 Block A, Card 1 Delay 5 Block A, Card 0 Delay 10 Block A, Turns Marker Delay 11 Block A, Clock Frequency 12 Block A, Clock Width 8 Block B, Global Delay 1 9 Block B, Global Delay 0 A Block B, Card 3 Delay B Block B, Card 2 Delay C Block B, Card 1 Delay D Block B, Card 0 Delay 18 Block B, Turns Marker Delay 19 Block B, Clock Frequency 1A Block B, Clock Width 1F Common Turns Marker Delay A typical calibration scheme is to set the channel delays to mid-scale and adjust the global delay for optimal results looking at the sum of all four channels. Then increment or decrement the individual channel delays to optimize the results for each channel. Timing Board (250 MHz only boards) TIMING BOARD 0X10020000 - 0X100200FF (dec=268566528) ADD PROGRAMMING DATA FOR MELLER’S %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Auxiliary
DSP_Board_Programming_V5-13_July2014.docx