Homework Lecture # of Item lectures # /Lab Ch#1 Intro to course, review of prerequisite material, Review data path and control unit design, Moore and Mealy, 1, 2 2 Glitches in HW#1 Week #1 control 8/22-8/25 signals, Data registers with Data enable, State diagram design, All Inclusive and Mutually Exclusive rules, Verilog coding: the 6-part EE354L lectures at home and 0 learn by installation yourself. Install Modelsim and learn to use the tool by yourself. Compare and contrast: diagram 3 1 vs. Lab #1 Week #2 8/29-8/30 (a 6-part lab) Ch#2 4 Performance, 1 HW #2 Week #2 MIPs, 8/31-9/1 MFLOPs Ch#3 MIPs ISA, SLT, 5, 6, SLTU lw, sw, 2 HW#1B Week #3 Byte 9/5-9/8 addressable processors,
# of lectures Lecture # Item Homework /Lab 2 1, 2 Week #1 8/22-8/25 Ch#1 Intro to course, review of prerequisite material, Review data path and control unit design, Moore and Mealy, Glitches in control signals, Data registers with Data enable, State diagram design, All Inclusive and Mutually Exclusive rules, HW#1 0 Verilog coding: the 6-part EE354L lectures at home and learn by yourself. Install Modelsim and learn to use the tool by yourself. installation 1 3 Week #2 8/29-8/30 Compare and contrast: diagram vs. (a 6-part lab) Lab #1 1 4 Week #2 8/31-9/1 Ch#2 Performance, MIPs, MFLOPs HW #2 2 5, 6, Week #3 9/5-9/8 Ch#3 MIPs ISA, SLT, SLTU lw, sw, Byte addressable processors, HW#1B
EE457_Syllabus_Fall_2016.docx