SIDDHARTH INSTITUTE OF ENGINEERING &TECHNOLOGY: PUTTUR ELECTRONICS & COMMUNICATON ENGINEERING LESSON PLAN John D.Carpinelli Academic Year/Sem: Ref: B.Tech III-I Sem. COMPUTER ORGANIZATION ANDARCHITECTURE M. Mano Subject: Subject code: 16EC408 Branch: E.C.E. Hours Module Topics covered Name of the book Page No L T UNIT I Module 1 Basic Computer Organization CPU John D.Carpinelli – Organization Memory& I/O Subsystem – 6 1 2-18 Organization and Interfacing Module 2 A Simple Computer Levels of John D.Carpinelli Programming Languages, Assembly Language Instructions, Instruction Set 5 1 64-74 Architecture Design, A simple Instruction Set Architecture UNIT II Module 1 Instruction Cycle Memory Reference M. Moris Mano – – Instructions Input/output and Interrupt – 8 93-134 Addressing Modes Data Transfer and – Manipulation Program Control. – Module 2 Addition and Subtraction Multiplication M. Moris Mano – 5 1 134-148 Algorithms Division Algorithms – Module 3 Floating-Point Arithmetic Operations M. Moris Mano – 4 1 148-155 Decimal Arithmetic unit UNIT III Module 1 Register Transfer Language Register M. Moris Mano – Transfer Bus and Memory Transfers, – 255-272 10 Arithmetic and Logic Micro operations – 280-283 Shift Micro operations Module 2 Control Memory Address Sequencing – – Micro program Example Design of M. Moris Mano – 5 1 213-232 Control Unit UNIT IV: Module 1 Memory Hierarchy - Main Memory M. Moris Mano – Auxiliary Memory Associative – 6 333-348 Memory Cache Memory Virtual – – Memory. M. Moris Mano Module 2 Input-Output Interface Asynchronous – Data Transfer Modes of – 3 354-363 Transfer Module 3 Priority Interrupt Direct Memory Access M. Moris Mano – 2 363-376 (DMA). UNIT V
SIDDHARTH INSTITUTE OF ENGINEERING &TECHNOLOGY: PUTTUR ELECTRONICS & COMMUNICATON ENGINEERING LESSON PLAN Academic Year/Sem: B.Tech III-I Sem. Ref: John D.Carpinelli Subject: COMPUTER ORGANIZATION ANDARCHITECTURE M. Mano Subject code: 16EC408 Branch: E.C.E. Module Topics covered Hours Name of the book Page No L T UNIT I Module 1 Basic Computer Organization – CPU Organization – Memory& I/O Subsystem Organization and Interfacing 6 1 John D.Carpinelli 2-18 Module 2 A Simple Computer Levels of Programming Languages, Assembly Language Instructions, Instruction Set Architecture Design, A simple Instruction Set Architecture 5 1 John D.Carpinelli 64-74 UNIT II Module 1 Instruction Cycle – Memory – Reference Instructions – Input/output and Interrupt Modes – Data Transfer and Manipulation – Program Control. 8 M. Moris Mano 93-134 Module 2 Addition and Subtraction – Multiplication Algorithms – Division Algorithms 5 1 M. Moris Mano 134-148 Module 3 Floating-Point Arithmetic Operations – Decimal Arithmetic unit 4 1 M. Moris Mano 148-155 UNIT III Module 1 Register Transfer Language – Register Transfer – Bus and Memory Transfers, Arithmetic and Logic Micro operations – Shift Micro operations 10 M. Moris Mano 255-272 280-283 Module 2 Control Memory – Address Sequencing – Micro program Example – Design of Control Unit 5 1 M. Moris Mano 213-232 UNIT IV: Module 1 Memory Hierarchy - Main Memory – Auxiliary Memory – Associative Memory – Cache Memory – Virtual Memory. 6 M. Moris Mano 333-348 Module 2 Input-Output Interface – Asynchronous Data Transfer – Modes of Transfer 3 M. Moris Mano 354-363 Module 3 Priority Interrupt – Direct Memory Access (DMA). 2 M. Moris Mano 363-376 UNIT V Addressing
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