The integrated charge is discharged through the feedback network. If electrons are being read out the switches “e” will be closed and a single resistor of 200k forms the feedback resistance. If holes are being read out then switches will be closed and a t-network forms the “h” resistive feedback. The resistance of the feedback network must be sufficiently large such that the time constant RfCf is not so small compared to the rise time of the signal such that signal is lost. However, the feedback resistor must not be so large that any offset due to detector leakage current reduces the dynamic range of the amplifier. The resulting voltage pulse is driven to the gain amplifier with the low output impedance of the source follower which also provides a voltage step which ensures the cascode transistor remains in saturation. The cascode bias Vpc must be supplied. The single ended nature of the amplifier does make it susceptible to noise on the power and ground lines. The design use of the triple well process allowing the NFET substrates to be biased independently from ground. The nominal current used by the preamplifier is 90+10+25 = Figure 4. Preamplifier Schematic 3.4 Postamp The postamp (Figure is comprised of a differential amplifier an input capacitor Cin – 5) and feedback capacitor Cf provide the voltage gain. DC stability is provided by a feedback network, selectable depending on the polarity of the signal. Two diode connected PFETs are used in the first stage of the amplifier to limit the differential swing to speed recovery time for very large (HIP) signals. A capacitor Cc compensates the amplifier, providing stability. A resistor in the output branch allows the offsetting of the postamp output voltage. This is done by adjusting the differential currents Ipaos1 and Ipaos2. These are set by loading an 8 bit control register in the channel. The nominal current in the postamplifier is 20+ 12.7 = 32.7uA The feedback network in both case of polarity comprises a long PFET biased with a small current. However the connections are slightly different for electrons and holes. shows the conguration for electrons. The 3 switches connect a current “e” Figure 6 mirror in the configuration shown. Since the output signals are negative going, the sources of the current mirror transistors must be connected to the higher potential
The integrated charge is discharged through the feedback network. If electrons are being read out the switches “e” will be closed and a single resistor of 200k forms the feedback resistance. If holes are being read out then switches “h” will be closed and a t-network forms the resistive feedback. The resistance of the feedback network must be sufficiently large such that the time constant RfCf is not so small compared to the rise time of the signal such that signal is lost. However, the feedback resistor must not be so large that any offset due to detector leakage current reduces the dynamic range of the amplifier. The resulting voltage pulse is driven to the gain amplifier with the low output impedance of the source follower which also provides a voltage step which ensures the cascode transistor remains in saturation. The cascode bias Vpc must be supplied. The single ended nature of the amplifier does make it susceptible to noise on the power and ground lines. The design use of the triple well process allowing the NFET substrates to be biased independently from ground. The nominal current used by the preamplifier is 90+10+25 = Figure 4. Preamplifier Schematic 3.4 Postamp The postamp (Figure 5) is comprised of a differential amplifier – an input capacitor Cin and feedback capacitor Cf provide the voltage gain. DC stability is provided by a feedback network, selectable depending on the polarity of the signal. Two diode connected PFETs are used in the first stage of the amplifier to limit the differential swing to speed recovery time for very large (HIP) signals. A capacitor Cc compensates the amplifier, providing stability. A resistor in the output branch allows the offsetting of the postamp output voltage. This is done by adjusting the differential currents Ipaos1 and Ipaos2. These are set by loading an 8 bit control register in the channel. The nominal current in the postamplifier is 20+ 12.7 = 32.7uA The feedback network in both case of polarity comprises a long PFET biased with a small current. However the connections are slightly different for electrons and holes. Figure 6 shows the conguration for electrons. The 3 switches “e” connect a current mirror in the configuration shown. Since the output signals are negative going, the sources of the current mirror transistors must be connected to the higher potential
CBC2_User_Guide_v1.0.docx