2 Sync lost (read only) 0 1 Sync stat (read only) 0 0 Bad code (read only) 0 Table Fast Command Interface and Error Flags — Bits (7:6) are used to select a delay to the serial command word by either one or two 320 MHz clock cycles. This is used to coarsely adjust the timing of the 40MHz clock derived from the serial command. The default is no delay. Values 00, 01 (one clock cycle delay) and 11 (two clock cycles delay) are valid. The value 10 is not valid. Bits (4:0) are error flags and are read only. Bit 4 indicates an overflow in the buffer RAM in the event that more than 32 triggers are received before the L1 data can be read. Bit 3 indicates a mismatch between the programmed latency and the difference between the pipeline read and write counters. Bits (2:0) are error flags for the fast command interface. Bit 2 indicates that synchronization has been lost at some time and does not imply that this is still the case. Bit one indicates the current synchronization status only. Bit zero indicates whether an invalid code has been received. This may be due to synchronization issues or simply the user sending an incorrect command code. Page1 Register 32 to 62: Mask Channels 1-248 — Addresses 00100000 to 00111110 Bit Function Default 7 Mask Channel<8> <248> 1 … 6 Mask Channel<7> <247> 1 … 5 Mask Channel<6> <246> 1 … 4 Mask Channel<5> <245> 1 … 3 Mask Channel<4> <244> 1 … 2 Mask Channel<3> <243> 1 … 1 Mask Channel<2> <242> 1 … 0 Mask Channel<1> <241> 1 … Table Channel Masking registers — These registers are used to either mask channels that are behaving badly or for test purposes. One bit is used per channel, with 8 bits per register requiring 31 register for channels 1-248. In the default case all of channels are unmasked. Page1 Register 63: Mask Channels 249-254 —
2 Sync lost (read only) 0 1 Sync stat (read only) 0 0 Bad code (read only) 0 Table — Fast Command Interface and Error Flags Bits (7:6) are used to select a delay to the serial command word by either one or two 320 MHz clock cycles. This is used to coarsely adjust the timing of the 40MHz clock derived from the serial command. The default is no delay. Values 00, 01 (one clock cycle delay) and 11 (two clock cycles delay) are valid. The value 10 is not valid. Bits (4:0) are error flags and are read only. Bit 4 indicates an overflow in the buffer RAM in the event that more than 32 triggers are received before the L1 data can be read. Bit 3 indicates a mismatch between the programmed latency and the difference between the pipeline read and write counters. Bits (2:0) are error flags for the fast command interface. Bit 2 indicates that synchronization has been lost at some time and does not imply that this is still the case. Bit one indicates the current synchronization status only. Bit zero indicates whether an invalid code has been received. This may be due to synchronization issues or simply the user sending an incorrect command code. Page1 — Register 32 to 62: Mask Channels 1-248 Addresses 00100000 to 00111110 Bit Function Default 7 Mask Channel<8> … <248> 1 6 Mask Channel<7> … <247> 1 5 Mask Channel<6> … <246> 1 4 Mask Channel<5> … <245> 1 3 Mask Channel<4> … <244> 1 2 Mask Channel<3> … <243> 1 1 Mask Channel<2> … <242> 1 0 Mask Channel<1> … <241> 1 Table — Channel Masking registers These registers are used to either mask channels that are behaving badly or for test purposes. One bit is used per channel, with 8 bits per register requiring 31 register for channels 1-248. In the default case all of channels are unmasked. Page1 — Register 63: Mask Channels 249-254
CBC3_User_Manual_V1p1.docx