parallel processing techniques: instruction level, thread level and 1.1 RISC processors and Characteristics of RISC processors process level 1.2 RISC Vs CISC Classification of parallel architectures 1.3 Classification of Instruction Set Architectures 1.4 Review of performance Measurements Basic parallel processing techniques: instruction 1.5 level, thread level and process level 1.5 Classification of parallel architectures 2 Instruction Parallelism 08 Hrs. 17 % 2.1 Basic concepts of pipelining Pipelining Hazards and Solutions 2.2 parallelism using software approaches 2.3 Superscalar techniques 2.4 Speculative execution 2.5 Review of modern processors /*The objective is to explain how ILP techniques have been deployed in modern processors*/ 2.6 Pentium Processor: IA 32 and P6 microarchitectures ARM Processor 3 Memory Hierarchies 10 Hrs. 22 % concept of hierarchical memory organization: Main memory, 3.1 Cache memory and Optimization, Virtual memory. 3.2 Memory protection and Evaluating memory hierarchy Pentium Processor: IA 32 and P6 microarchitectures performance 3.3 RAID ARM Processor 4 Thread Parallelism 08 Hrs. 17 % 4.1 Centralized vs. distributed shared memory 4.2 Interconnection topologies 4.3 Synchronization and Memory consistency 4.4 Review of modern multiprocessors 5 Process Level Parallelism 07 Hrs. 16 % Distributed Computing 5.1 5.2 Grid 5.3 Cluster
parallel processing techniques: instruction level, thread level and process level Classification of parallel architectures 1.1 RISC processors and Characteristics of RISC processors 1.2 RISC Vs CISC 1.3 Classification of Instruction Set Architectures 1.4 Review of performance 1.5 Measurements Basic parallel processing techniques: instruction level, thread level and process level 1.5 Classification of parallel architectures 2 Instruction Parallelism 08 Hrs. 17 % 2.1 Basic concepts of pipelining 2.2 Pipelining Hazards and Solutions 2.3 parallelism using software approaches 2.4 Superscalar techniques 2.5 Speculative execution 2.6 Review of modern processors /*The objective is to explain how ILP techniques have been deployed in modern processors*/ Pentium Processor: IA 32 and P6 microarchitectures ARM Processor Pentium Processor: IA 32 and P6 microarchitectures ARM Processor 3 Memory Hierarchies 10 Hrs. 22 % 3.1 concept of hierarchical memory organization: Main memory, Cache memory and Optimization, Virtual memory. 3.2 Memory protection and Evaluating memory hierarchy performance 3.3 RAID 4 Thread Parallelism 08 Hrs. 17 % 4.1 Centralized vs. distributed shared memory 4.2 Interconnection topologies 4.3 Synchronization and Memory consistency 4.4 Review of modern multiprocessors 5 Process Level Parallelism 07 Hrs. 16 % 5.1 Distributed Computing 5.2 Grid 5.3 Cluster
BTech_IT_Booklet_Final_2018-19_05-05-18.docx