the logical OR of the FIFO Full Flag and the Latency Error Flag, both of which also appear separately in the packet, and are also stored in a register which can be read via the I2C interface. Triggered Data The SYNC bit is output with every Stub Data packet (every 8 clock cycles at 320MHz) and can be used by the receiver for data synchronization purposes. Figure Illustration of the Stub Data packet. — Figure An illustration of the serial Triggered Data packet in relationship to the Stub — Data Packet. NOTE: The Triggered Data header (11) is always aligned with the SYNC bit. ► Interfaces Fast Control Interface In addition to the I2C Slow Control Interface, there is a Fast Control Interface operating serially at 320 MHz via a differential SLVS input. Running at the 320 MHz clock frequency allows eight bits of serial data to be input within a Bunch-Crossing period of 25 ns. These eight bits of data have pre-defined functions, as set out in Table 1 below. Fast Command B7 B6 B5 B4 B3 B2 B1 B0 Fast Reset 1 1 0 1 0 0 0 1 Trigger 1 1 0 0 1 0 0 1 Test 1 1 0 0 0 1 0 1 Trigger Orbit Reset 1 1 0 0 0 0 1 1 Orbit Reset & 1 1 0 1 0 0 1 1 Fast Reset Orbit Reset & 1 1 0 0 1 0 1 1 Trigger Orbit Reset & 1 1 0 0 0 1 1 1 Test Pulse Table Fast Trigger Control Interface commands and their corresponding serial codes — The CBC3 detects the 110 synchronisation pattern on bits <7:5> and uses this to produce the on-chip 40 MHz reference clock. In the event that this synchronisation pattern is not received, the on-chip 40 MHz clock will freeze until the synchronisation pattern is resumed. Two flags are made available via the I2C
the logical OR of the FIFO Full Flag and the Latency Error Flag, both of which also appear separately in the Triggered Data packet, and are also stored in a register which can be read via the I2C interface. The SYNC bit is output with every Stub Data packet (every 8 clock cycles at 320MHz) and can be used by the receiver for data synchronization purposes. Figure — Illustration of the Stub Data packet. Figure — An illustration of the serial Triggered Data packet in relationship to the Stub Data Packet. ► NOTE: The Triggered Data header (11) is always aligned with the SYNC bit. Interfaces Fast Control Interface In addition to the I2C Slow Control Interface, there is a Fast Control Interface operating serially at 320 MHz via a differential SLVS input. Running at the 320 MHz clock frequency allows eight bits of serial data to be input within a Bunch-Crossing period of 25 ns. These eight bits of data have pre-defined functions, as set out in Table 1 below. Fast Command B7 B6 B5 B4 B3 B2 B1 B0 Fast Reset 1 1 0 1 0 0 0 1 Trigger 1 1 0 0 1 0 0 1 Test Trigger 1 1 0 0 0 1 0 1 Orbit Reset 1 1 0 0 0 0 1 1 Orbit Reset & Fast Reset 1 1 0 1 0 0 1 1 Orbit Reset & Trigger 1 1 0 0 1 0 1 1 Orbit Reset & Test Pulse Trigger 1 1 0 0 0 1 1 1 Table — Fast Control Interface commands and their corresponding serial codes The CBC3 detects the 110 synchronisation pattern on bits <7:5> and uses this to produce the on-chip 40 MHz reference clock. In the event that this synchronisation pattern is not received, the on-chip 40 MHz clock will freeze until the synchronisation pattern is resumed. Two flags are made available via the I2C
CBC3_User_Manual_V1p1.docx