Reset Block (Functional Specification): Monitor external signal. When external reset is asserted, generate three auxiliary reset signals for use inside local digital systems. The three auxiliary signals must each stay asserted for a specific amount of time from the assertion of the external reset. Once all auxiliary resets are de-asserted, the reset block must be ready to repeat the process. Block (Technical Specification): The Reset Block is synchronized to the rest of the system via a clock with a frequency of 50 MHz. The external signal stays asserted for 4 clock cycles. Auxiliary reset signal rstAux1 must stay asserted for 30 clock cycles after the external reset is first asserted. Auxiliary reset signal rstAux2 must stay asserted for 24 clock cycles after the external reset is first asserted. Auxiliary reset signal rstAux3 must stay asserted for 16 clock cycles after the external reset is first asserted. Symbol Creation A component symbol gives a box” top-level view of the component being designed. The symbol “black diagram consists of a rectangle representing the component proper, with arrows representing all top level ports. Input ports are represented by arrows pointing towards the rectangle from the left, while output ports are represented as arrows pointing away from the rectangle, towards the right. The component symbol is the first part of the design which is created; it is important that the symbol is as complete as possible before proceeding to other design steps. While an iterative process may be used in certain situations, it is best to try to clarify the majority of top-level ports before any other steps are taken. Once the component symbol is complete, it corresponds with the top-level Entity declaration for your designed component. EXAMPLE: The Reset Block receives one input: the external reset signal. It generates three outputs: the three internal reset signals. The Reset Block must be synchronized with the rest of the systems surrounding it, and receives a clock signals as an input as well. The external reset signal and the clock are single-bit signals. The three internal reset signals generated by the Reset Block are also single-bit signals. Based on this, the symbol for the Reset Block is shown below in Figure 1, with the component entity declaration listed after it.
Reset Block (Functional Specification): Monitor external signal. When external reset is asserted, generate three auxiliary reset signals for use inside local digital systems. The three auxiliary signals must each stay asserted for a specific amount of time from the assertion of the external reset. Once all auxiliary resets are de-asserted, the reset block must be ready to repeat the process. Block (Technical Specification): The Reset Block is synchronized to the rest of the system via a clock with a frequency of 50 MHz. The external signal stays asserted for 4 clock cycles. Auxiliary reset signal rstAux1 must stay asserted for 30 clock cycles after the external reset is first asserted. Auxiliary reset signal rstAux2 must stay asserted for 24 clock cycles after the external reset is first asserted. Auxiliary reset signal rstAux3 must stay asserted for 16 clock cycles after the external reset is first asserted. Symbol Creation A component symbol gives a “black box” top-level view of the component being designed. The symbol diagram consists of a rectangle representing the component proper, with arrows representing all top level ports. Input ports are represented by arrows pointing towards the rectangle from the left, while output ports are represented as arrows pointing away from the rectangle, towards the right. The component symbol is the first part of the design which is created; it is important that the symbol is as complete as possible before proceeding to other design steps. While an iterative process may be used in certain situations, it is best to try to clarify the majority of top-level ports before any other steps are taken. Once the component symbol is complete, it corresponds with the top-level Entity declaration for your designed component. EXAMPLE: The Reset Block receives one input: the external reset signal. It generates three outputs: the three internal reset signals. The Reset Block must be synchronized with the rest of the systems surrounding it, and receives a clock signals as an input as well. The external reset signal and the clock are single-bit signals. The three internal reset signals generated by the Reset Block are also single-bit signals. Based on this, the symbol for the Reset Block is shown below in Figure 1, with the component entity declaration listed after it.
COE758_Digital_Design_Tutorial.docx