Lab 8 1 - 0 Inverters 0 - 1 (NOT Gate) Lab 9 Gate: Lab # / Name Input A Input B Output (LED) Lab 9 0 0 1 (NAND Gate) 0 1 1 1 0 1 1 1 0 Lab 10 Gate: Lab # / Name A Input B Output (LED) Lab 10 0 0 1 (NOR Gate) 0 1 0 1 0 0 1 1 0
Lab 8 Inverters (NOT Gate) 1 - 0 0 - 1 Lab 9 Gate: Lab # / Name Input A Input B Output (LED) Lab 9 (NAND Gate) 0 0 1 0 1 1 1 0 1 1 1 0 Lab 10 Gate: Lab # / Name A Input B Output (LED) Lab 10 (NOR Gate) 0 0 1 0 1 0 1 0 0 1 1 0
brenen_thayaparans_logic_gates_lab_report.docx