ports and and 1 output port The first flip-flop has 2 inputs “ASYNC” “CLOCK” “SYNC”. ‘D’ and and 1 output The second flip-flop 2 inputs “ASYNC” “CLOCK” “C1_ASYNC”. ‘D’ and and 1 output “C1_ASYNC” “CLOCK” “SYNC”. 2.3.1 MODULE PORT CONNECTION BY module SYNCHRO(ASYNC,SYNC,CLOCK); input ASYNC; input CLOCK; output SYNC; wire C1_ASYNC; DFF DFF1 (C1_ASYNC, ASYNC, CLOCK); DFF DFF2 (SYNC, C1_ASYNC, CLOCK); //DFF DFF1 (ASYNC, C1_ASYNC, CLOCK); //DFF DFF2 (SYNC, C1_ASYNC, CLOCK); endmodule Here first instance name of flip-flop is and second instance name is In this ‘D’ “DFF1” “DFF2”. module ports are connected by order. Order of ports in instantiation of DFF1 and DFF2 is same as order of ports in DFF. If the number of ports increased, then it is very difficult to do ports connection by order”. “module 2.3.2 MODULE PORT CONNECTION BY NAME Module SYNCHRO (ASYNC, SYNC, CLOCK); input ASYNC; input CLOCK; output SYNC; wire C1_ASYNC; DFF DFF1 (.D (ASYNC), .CLK (CLOCK), .Q (C1_ASYNC)); DFF DFF2 (.D (C1_ASYNC), .Q (SYNC), .CLK (CLOCK)); endmodule; In this module are connected by Name. Order of ports in instantiation of DFF1 and DFF2 is different from order of ports in DFF. In this Is used to represent port name followed by ‘.’
ports “ASYNC” and “CLOCK” and 1 output port “SYNC”. The first ‘D’ flip-flop has 2 inputs “ASYNC” and “CLOCK” and 1 output “C1_ASYNC”. The second ‘D’ flip-flop 2 inputs “C1_ASYNC” and “CLOCK” and 1 output “SYNC”. 2.3.1 MODULE PORT CONNECTION BY module SYNCHRO(ASYNC,SYNC,CLOCK); input ASYNC; input CLOCK; output SYNC; wire C1_ASYNC; DFF DFF1 (C1_ASYNC, ASYNC, CLOCK); DFF DFF2 (SYNC, C1_ASYNC, CLOCK); //DFF DFF1 (ASYNC, C1_ASYNC, CLOCK); //DFF DFF2 (SYNC, C1_ASYNC, CLOCK); endmodule Here first instance name of ‘D’ flip-flop is “DFF1” and second instance name is “DFF2”. In this module ports are connected by order. Order of ports in instantiation of DFF1 and DFF2 is same as order of ports in DFF. If the number of ports increased, then it is very difficult to do “module ports connection by order”. 2.3.2 MODULE PORT CONNECTION BY NAME Module SYNCHRO (ASYNC, SYNC, CLOCK); input ASYNC; input CLOCK; output SYNC; wire C1_ASYNC; DFF DFF1 (.D (ASYNC), .CLK (CLOCK), .Q (C1_ASYNC)); DFF DFF2 (.D (C1_ASYNC), .Q (SYNC), .CLK (CLOCK)); endmodule; In this module are connected by Name. Order of ports in instantiation of DFF1 and DFF2 is different from order of ports in DFF. In this ‘.’ Is used to represent port name followed by
training_manual_for_fpga_programming_using_verilog_hdl_language.docx