It executes the or if statement statement_group the condition evaluates as true. If we need more than one statement (i.e if statement_group) then we need to use or a begin-end fork-join if (alu_func == 2’b00) block. The here can be an expression condition aluout = a + b; or a single value. If the evaluates to condition else if (alu_func == 2’b01) or unknown then the is condition ‘0’ aluout = a - b; considered false, and if the evaluates condition else if (alu_func == 2’b10) to or more then the is considered condition ‘1’ aluout = a & b; true. else // alu_func == 2’b11 aluout = a | b; if (a == b) begin x = 1; ot = 4’b1111; It executes the first or statement end if the condition evaluates as if-else statement_group true and executes the second or statement if the condition evaluates as statement_group false. The here can be an expression condition or a single value. If the evaluates to condition or unknown then the is condition ‘0’ considered false, and if the evaluates condition to 1’ or more then the is considered condition ‘ true. case (alu_ctr) 2’b00: aluout = a + b; 2’b01: aluout = a - b; 2’b10: aluout = a & b; default: aluout = 1’bx; /* Treated as don’t for minimum logic generation. */ case endcase It compares the with each of the case (x, y, z) expression and executes the or 2’b00: aluout = a + b; /*case case_item’s statement if x or y or z is 2’b00.*/
if It executes the statement or statement_group if the condition evaluates as true. If we need more than one statement (i.e statement_group) then we need to use begin-end or a fork-join block. The condition here can be an expression or a single value. If the condition evaluates to ‘0’ or unknown then the condition is considered false, and if the condition evaluates to ‘1’ or more then the condition is considered true. if (alu_func == 2’b00) aluout = a + b; else if (alu_func == 2’b01) aluout = a - b; else if (alu_func == 2’b10) aluout = a & b; else // alu_func == 2’b11 aluout = a | b; if (a == b) begin x = 1; ot = 4’b1111; end if-else It executes the first statement or statement_group if the condition evaluates as true and executes the second statement or statement_group if the condition evaluates as false. The condition here can be an expression or a single value. If the condition evaluates to ‘0’ or unknown then the condition is considered false, and if the condition evaluates to ‘ 1’ or more then the condition is considered true. case It compares the expression with each of the case_item’s and executes the statement or case (alu_ctr) 2’b00: aluout = a + b; 2’b01: aluout = a - b; 2’b10: aluout = a & b; default: aluout = 1’bx; /* Treated as don’t for minimum logic generation. */ endcase case (x, y, z) 2’b00: aluout = a + b; /*case if x or y or z is 2’b00.*/
training_manual_for_fpga_programming_using_verilog_hdl_language.docx