associated with the statement_group matching case_item. It executes the if none of the default match. Here the default case is case_item’s 2’b01: aluout = a - b; optional. 2’b10: aluout = a & b; default: aluout = a | b; endcase casez (d) 3’b1??: b = 2’b11; /* b = 11 if d = 100 or 101 or 110 or 111 */ 3’b01?: b = 2’b10; // b = 10 if d = 010 or 011 It is special version of case statement where default: b = 2’b00; ‘z’ and are treated as don’t cares. Similar to endcase ‘?’ case statement it compares the with expression each of the and executes the case_item’s or associated with statement statement_group the first matching It executes the case_item. if none of the match. Here default case_item’s the default case is optional. casex (a) 2’b1x: msb = 1; // msb = 1 if a = 10 or a = 11 /* casex If this were case(a) then only a=1x would match.*/ default: msb = 0; endcase It is special version of case statement where and are treated as don’t cares. ‘x’, ‘z’ ‘?’ Similar to case statement it compares the with each of the and expression case_item’s executes the or statement statement_group
statement_group associated with the matching case_item. It executes the default if none of the case_item’s match. Here the default case is optional. 2’b01: aluout = a - b; 2’b10: aluout = a & b; default: aluout = a | b; endcase It is special version of case statement where ‘z’ and ‘?’ are treated as don’t cares. Similar to case statement it compares the expression with each of the case_item’s and executes the statement or statement_group associated with the first matching case_item. It executes the default if none of the case_item’s match. Here the default case is optional. casez (d) 3’b1??: b = 2’b11; /* b = 11 if d = 100 or 101 or 110 or 111 */ 3’b01?: b = 2’b10; // b = 10 if d = 010 or 011 default: b = 2’b00; endcase casex It is special version of case statement where ‘x’, ‘z’ and ‘?’ are treated as don’t cares. Similar to case statement it compares the expression with each of the case_item’s and executes the statement or statement_group casex (a) 2’b1x: msb = 1; // msb = 1 if a = 10 or a = 11 /* If this were case(a) then only a=1x would match.*/ default: msb = 0; endcase
training_manual_for_fpga_programming_using_verilog_hdl_language.docx