Scan chains can be fully triggered at either positive or negative. But at a crossing of positive to negative clock triggered scan chains, a flip-flop’ is a must. This is to guarantee a ‘copy reliable chain operation. Figure 2.18: Scan_40 validation If either the f3a’s input is not the output of f3 or that net is not consisted with even number of inverters then a violation is said to happen. This will issue a violation message under Scan_40. Understood the basic concept and validated the rule on the following bases. No violation With two clocks Simple violation With dftStrictTestClkDomains Negative to positive FF_(L-1)’s and FF_L’s d pins are connected MUX between FF_(L-1) and FF_L with inversion After rectifying what has been given in all_case_netlist_01 Two FF_(L-1) for FF_L Two ffs are in different scan chains Only two scans Two negative edge scan chains More in one scan Comb in between scan chains 2.1.3.2.4 Intel LSSD support in DFT This is another request made by Russ Roan of Intel on behalf of Kavita Rachakatla. The validation of this modification was brought down in two phases. This modification introduces the scannability of latches in addition to the extension. ‘pipeline’ When test clocks are inferred at outputs of ICG using constraint then the ‘pipeline’ registers driven by them will be considered to be scannable.
Scan chains can be fully triggered at either positive or negative. But at a crossing of positive to negative clock triggered scan chains, a ‘copy flip-flop’ is a must. This is to guarantee a reliable chain operation. Figure 2.18: Scan_40 validation If either the f3a’s input is not the output of f3 or that net is not consisted with even number of inverters then a violation is said to happen. This will issue a violation message under Scan_40. Understood the basic concept and validated the rule on the following bases. No violation Simple violation Negative to positive MUX between FF_(L-1) and FF_L After rectifying what has been given in all_case_netlist_01 Two ffs are in different scan chains Two negative edge scan chains Comb in between scan chains With two clocks With dftStrictTestClkDomains FF_(L-1)’s and FF_L’s d pins are connected with inversion Two FF_(L-1) for FF_L Only two scans More in one scan 2.1.3.2.4 Intel LSSD support in DFT This is another request made by Russ Roan of Intel on behalf of Kavita Rachakatla. The validation of this modification was brought down in two phases. This modification introduces the scannability of latches in addition to the ‘pipeline’ extension. When test clocks are inferred at outputs of ICG using ‘pipeline’ constraint then the registers driven by them will be considered to be scannable.
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