2. Two (out of three) data pins are driven by one clock in above (i) design 3. Two clocks are converged so as to feed a data pin of one flop out of two flops 4. Clock blocked by a flop (for the design in (i)) 5. Clock blocked by a MUX 6. One flip-flop is defined to be ‘no_scan’ Clock_16: A bug was detected while validating test’ under this rule. This was reported and ‘Robust rectified. The bug is described below. This is related to the unit test case in the following path. dft/test/Ruledecks/dft/Verilog/Clock_16/case0 The top module diagram is, Figure 2.29: Clock_16 reported bug As the says for the Clock_16 rule, “Metric_Possibilities_for_Robust_Tests-v6.docx” “Count the # of FFs with a data path from a FF that is clocked on opposite edge” As we can figure out, and flip-flops are victims of Clock_04 violation whereas “q2” “q3” is a victim of Clock_16 violation. BTW for the robustness testing (as the above “q1” reference suggests) is flagged though is the one which should be flagged. We can “q2” “q1” see that in the following too. There, even though the percentages per rule are correct, the overall percentage is incorrect. Figure 2.30: Incorrect Robustness Clock_17: 1. Output to d pin of a flip-flop 2. Using two test-clocks
2. Two (out of three) data pins are driven by one clock in above (i) design 3. Two clocks are converged so as to feed a data pin of one flop out of two flops 4. Clock blocked by a flop (for the design in (i)) 5. Clock blocked by a MUX 6. One flip-flop is defined to be ‘no_scan’ Clock_16: A bug was detected while validating ‘Robust test’ under this rule. This was reported and rectified. The bug is described below. This is related to the unit test case in the following path. dft/test/Ruledecks/dft/Verilog/Clock_16/case0 The top module diagram is, Figure 2.29: Clock_16 reported bug As the “Metric_Possibilities_for_Robust_Tests-v6.docx” says for the Clock_16 rule, “Count the # of FFs with a data path from a FF that is clocked on opposite edge” As we can figure out, “q2” and “q3” flip-flops are victims of Clock_04 violation whereas “q1” is a victim of Clock_16 violation. BTW for the robustness testing (as the above reference suggests) “q2” is flagged though “q1” is the one which should be flagged. We can see that in the following too. There, even though the percentages per rule are correct, the overall percentage is incorrect. Figure 2.30: Incorrect Robustness Clock_17: 1. Output to d pin of a flip-flop 2. Using two test-clocks
training-experience-2.docx