Figure 2.19: Intel LSSD validation The constraint in sgdc file can only be specified with the value which is ‘pipeline_depth’ the depth of the registers which are presented before ICGC. But the ‘pipeline_depth_range’ comes handy in use as the user can specify a value range on which it will automatically define a depth of registers which match the design. The impact on latch scannability was also validated along with the functional validation of ‘pipeline’. 2.1.3.2.4.1 Functional validation on ‘pipeline’ The bases on which this modification is tested is listed below. Case 00 default case where is left without defining. – ‘-pipeline_depth’ Case 01 There are two and one is left without – ‘gating_cell_enable’ ‘-pipeline_depth’ defining. Case 02 Normal operation of (two latches are placed before and – ‘-pipeline_depth’ after CGC) Case 03 Normal operation of (two latches are placed before – ‘-pipeline_depth_range’ and after CGC) Case 04 0 5’ and placing a CGC 6th flop – ‘pipeline_depth_range Case 05 3 6’ and placing a CGC before 2nd flop – ‘pipeline_depth_range Case 06 0 5’ and placing many CGCs in between – ‘pipeline_depth_range Case 07 Check whether both are working together – Case 08 Negative value for – ‘-pipeline_depth’ Case 09 Negative values for – ‘-pipeline_depth_range’ Case 10 More valid values for – ‘-pipeline_depth’ Case 11 More valid values for – ‘-pipeline_depth_range’ Case 12 One valid value for – ‘-pipeline_depth_range’ Case 13 Zero valid values for – ‘-pipeline_depth’ Case 14 Zero values for – ‘-pipeline_depth_range’ Case 15 Two CGCs and for one CGC and – ‘-pipeline_depth’ ‘-pipeline_depth_range’ for other one 2.1.3.2.4.2 Latch Scannability
Figure 2.19: Intel LSSD validation The ‘pipeline_depth’ constraint in sgdc file can only be specified with the value which is the depth of the registers which are presented before ICGC. But the ‘pipeline_depth_range’ comes handy in use as the user can specify a value range on which it will automatically define a depth of registers which match the design. The impact on latch scannability was also validated along with the functional validation of ‘pipeline’. 2.1.3.2.4.1 Functional validation on ‘pipeline’ The bases on which this modification is tested is listed below. Case 00 – default case where ‘-pipeline_depth’ is left without defining. Case 01 – There are two ‘gating_cell_enable’ and one ‘-pipeline_depth’ is left without defining. Case 02 – Normal operation of ‘-pipeline_depth’ (two latches are placed before and after CGC) Case 03 – Normal operation of ‘-pipeline_depth_range’ (two latches are placed before and after CGC) Case 04 – ‘pipeline_depth_range 0 5’ and placing a CGC 6th flop Case 05 – ‘pipeline_depth_range 3 6’ and placing a CGC before 2nd flop Case 06 – ‘pipeline_depth_range 0 5’ and placing many CGCs in between Case 07 – Check whether both are working together Case 08 – Negative value for ‘-pipeline_depth’ Case 09 – Negative values for ‘-pipeline_depth_range’ Case 10 – More valid values for ‘-pipeline_depth’ Case 11 – More valid values for ‘-pipeline_depth_range’ Case 12 – One valid value for ‘-pipeline_depth_range’ Case 13 – Zero valid values for ‘-pipeline_depth’ Case 14 – Zero values for ‘-pipeline_depth_range’ Case 15 – Two CGCs and ‘-pipeline_depth’ for one CGC and ‘-pipeline_depth_range’ for other one 2.1.3.2.4.2 Latch Scannability
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