Built-in Self-Test 73 When MC1=0 and MC2=1, sub-circuit C2 is disabled; sub-circuit shown in Figure C1, 4.2c, can be tested by applying all possible input combinations at and Similarly, when a, b, c, d. MC1=1 and MC2=0, sub-circuit is disabled. In this mode, the circuit structure is as shown in C1 Figure 4.2d and sub-circuit can be tested by applying all input combinations at and C2 c, d, e, f. When MC1=MC2=0, the circuit functions as the unmodified circuit except for the added gate delay. The advantage of the design method is that any fault in the circuit itself and the testing circuit is detectable. A modified version of the autonomous testing, called the has been verification testing, in Ref. [3]. This method is applicable to multi-output combinational circuits, provided each output depends only on a proper subset of the inputs. The verification test set for a circuit is derived from its The dependence matrix of a circuit has rows and columns; each row dependence matrix. m n Figure 4.3: (a) Circuit under test. (b) Dependence matrix. (c) Partition-dependent matrix. (d) test set. (e) Reduced verification test set.
Built-in Self-Test 73 When MC1=0 and MC2=1, sub-circuit C2 is disabled; sub-circuit C1, shown in Figure 4.2c, can be tested by applying all possible input combinations at a, b, c, and d. Similarly, when MC1=1 and MC2=0, sub-circuit C1 is disabled. In this mode, the circuit structure is as shown in Figure 4.2d and sub-circuit C2 can be tested by applying all input combinations at c, d, e, and f. When MC1=MC2=0, the circuit functions as the unmodified circuit except for the added gate delay. The advantage of the design method is that any fault in the circuit itself and the testing circuit is detectable. A modified version of the autonomous testing, called the verification testing, has been in Ref. [3]. This method is applicable to multi-output combinational circuits, provided each output depends only on a proper subset of the inputs. The verification test set for a circuit is derived from its dependence matrix. The dependence matrix of a circuit has m rows and n columns; each row Figure 4.3: (a) Circuit under test. (b) Dependence matrix. (c) Partition-dependent matrix. (d) test set. (e) Reduced verification test set.
tv-unit-4_bist.docx