File inclusion. The contents of ‘include another Verilog source file is inserted where the ‘include directive appears. Here the contents of are ‘define.h’ included within the module. ‘idu’ Allows a text string to be defined Example ‘define as a macro name. 1 gate_regression ‘define Allows to be ‘gate_regression’ substituted by 1 where ever it gets used. 2.8 WHAT ARE THE TIMING CONTROL STATEMENTS IN VERILOG Timing Controls Description # It delays execution for a specific amount of time, may be a number, ‘delay’ a variable or an expression. Example of a procedural block using is ‘#” shown below. Here & d)’ gets evaluated at time 0 but gets assigned to after 2 time ‘(c ‘a’ units whereas gets evaluated after 3 time units and gets assigned to ‘e’ immediately.
‘include File inclusion. The contents of another Verilog source file is inserted where the ‘include directive appears. Here the contents of ‘define.h’ are included within the ‘idu’ module. ‘define Allows a text string to be defined as a macro name. Example ‘define gate_regression 1 Allows ‘gate_regression’ to be substituted by 1 where ever it gets used. 2.8 WHAT ARE THE TIMING CONTROL STATEMENTS IN VERILOG Timing Controls Description # It delays execution for a specific amount of time, ‘delay’ may be a number, a variable or an expression. Example of a procedural block using ‘#” is shown below. Here ‘(c & d)’ gets evaluated at time 0 but gets assigned to ‘a’ after 2 time units whereas gets evaluated after 3 time units and gets assigned to ‘e’ immediately.
training_manual_for_fpga_programming_using_verilog_hdl_language.docx