Data is transferred in eight bit sequences. The eight bit sequence is placed on the SDA line (the data line) starting with the most significant bit. Then the SCL line (the clock line) pulses high then low. The SCL line has to pulse nine times to send an eight bit data sequence (one for every bit and the ninth one to send back an acknowledge bit). See Figure 19.3.1 for a diagram of the SDA line and the SCL line. The receiver sends the acknowledge bit (ACK bit) to indicate it has receive the last bit of the byte and is ready to receive another eight bit sequence; however if the receiver does not send back an acknowledge bit then it means it is not ready for further data and the master should stop transferring. Figure 19.3.1. SDA line with 8 bits and one acknowledge bit (ACK). SCL line with 9 pulses, one for every bit and one for the ACK bit. The inter-integrated circuit software protocol, as previously mentioned, has a master and slave relationship between each component attached to the circuit bus. Transmissions always have a start and stop sequence at the beginning and at the end of each of them. Here are examples of the protocol for a master component writing to and reading from a slave component. Master Writing To Send a start sequence Send the inter-integrated circuit address of the slave with the read/write bit low Send the internal register number that needs to be written Send the eight bit date sequence If necessary send the rest of the eight bit sequences Send a stop sequence Master Reading From A Slave Send a start sequence Send 0xC0 Send 0x01 Send a start sequence again Send 0xC1 Read data byte from CMPS03 Send the stop sequence The standard clock speed for inter-integrated circuit is up to one hundred In fast mode the speed increases to four hundred kilo-hertz and then there is high speed mode which is up to three and a half mega-hertz.
Data is transferred in eight bit sequences. The eight bit sequence is placed on the SDA line (the data line) starting with the most significant bit. Then the SCL line (the clock line) pulses high then low. The SCL line has to pulse nine times to send an eight bit data sequence (one for every bit and the ninth one to send back an acknowledge bit). See Figure 19.3.1 for a diagram of the SDA line and the SCL line. The receiver sends the acknowledge bit (ACK bit) to indicate it has receive the last bit of the byte and is ready to receive another eight bit sequence; however if the receiver does not send back an acknowledge bit then it means it is not ready for further data and the master should stop transferring. Figure 19.3.1. SDA line with 8 bits and one acknowledge bit (ACK). SCL line with 9 pulses, one for every bit and one for the ACK bit. The inter-integrated circuit software protocol, as previously mentioned, has a master and slave relationship between each component attached to the circuit bus. Transmissions always have a start and stop sequence at the beginning and at the end of each of them. Here are examples of the protocol for a master component writing to and reading from a slave component. Master Writing To Send a start sequence Send the inter-integrated circuit address of the slave with the read/write bit low Send the internal register number that needs to be written Send the eight bit date sequence If necessary send the rest of the eight bit sequences Send a stop sequence Master Reading From A Slave Send a start sequence Send 0xC0 Send 0x01 Send a start sequence again Send 0xC1 Read data byte from CMPS03 Send the stop sequence The standard clock speed for inter-integrated circuit is up to one hundred In fast mode the speed increases to four hundred kilo-hertz and then there is high speed mode which is up to three and a half mega-hertz.
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