(CVD chemical vapor deposition), P (photolithography), D (dry etch), A (ALD atomic layer – – deposition), W (wet etch) and I (ion implantation). Summary Although different opinions are held throughout industry regarding the trend, reduction in IC manufacturing cost is the key challenge as technology advances to extend Law. The iFinFET technology and TII double patterning Moore’s technique show promise for cost reduction in future technology nodes, especially beyond the 7 nm technology node where the industry does not yet have clear solutions. References [5.1] G. E. Moore, more components onto integrated Electronics, “Cramming circuits”, 38, number 8, April 19, 1965, pp.114-117. [5.2] W. M. Law: A 2016 International Solid State Holt, “Moore’s Path Forward”, paper 1.1. Circuits Conference, [5.3] S. Jones, Law is dead, long live April 21th, SemiWiki, “Moore’s Moore’s Law”, 2015. [Online]. [5.4] H. Jones, "10 nm Chips Promise Lower Costs", June 15th 2015. [Online]. EETimes, [5.5] H. Jones, "Why migration to 20nm bulk CMOS and 16/14nm finFETs is not best approach for semiconductor industry," January 2014. [Online]. Available: . [5.6] G. Yeric, Law at 50: Are we planning for in IEDM Tech. “Moore’s retirement?” Dec. 2015, pp. 1.1.1-1.1.8. Dig., [5.7] B.-Y. Nguyen, private communication. [5.8] Z. Or-Bach, B. Cronquist, I. Beinglass, Z. much does ion-cut Wurman, “How cost?” July 25th 2011. [Online]. Available: [5.9] M. Lapedus, if EUV April 17th, 2014. Semi. Engineering, “What fails?” [5.10] L. Rubin, private communication.
(CVD – chemical vapor deposition), P (photolithography), D (dry etch), A (ALD – atomic layer deposition), W (wet etch) and I (ion implantation). Summary Although different opinions are held throughout industry regarding the trend, reduction in IC manufacturing cost is the key challenge as technology advances to extend Moore’s Law. The iFinFET technology and TII double patterning technique show promise for cost reduction in future technology nodes, especially beyond the 7 nm technology node where the industry does not yet have clear solutions. References [5.1] G. E. Moore, “Cramming more components onto integrated circuits”, Electronics, 38, number 8, April 19, 1965, pp.114-117. [5.2] W. M. Holt, “Moore’s Law: A Path Forward”, 2016 International Solid State Circuits Conference, paper 1.1. [5.3] S. Jones, “Moore’s Law is dead, long live Moore’s Law”, SemiWiki, April 21th, 2015. [Online]. [5.4] H. Jones, "10 nm Chips Promise Lower Costs", EETimes, June 15th 2015. [Online]. [5.5] H. Jones, "Why migration to 20nm bulk CMOS and 16/14nm finFETs is not best approach for semiconductor industry," January 2014. [Online]. Available: . [5.6] G. Yeric, “Moore’s Law at 50: Are we planning for retirement?” in IEDM Tech. Dig., Dec. 2015, pp. 1.1.1-1.1.8. [5.7] B.-Y. Nguyen, private communication. [5.8] Z. Or-Bach, B. Cronquist, I. Beinglass, Z. Wurman, “How much does ion-cut cost?” July 25th 2011. [Online]. Available: [5.9] M. Lapedus, “What if EUV fails?” Semi. Engineering, April 17th, 2014. [5.10] L. Rubin, private communication.
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