Day 1 Agenda Day 1 Materials Class Intro 01_class_intro.pptx 7-Series Architecture Overview 11_7_Series_Architecture_Overview.ppt x Vivado Design Flow 12_ Vivado Design Flow.pptx Lab 1: Vivado Design Flow 12a_lab1_intro.pptx Lab1.docx Synthesis 13_Synthesis.pptx Lab 2: Synthesizing a RTL Design 13a_lab2_intro.pptx Lab2.docx Implementation and STA 14_ Implementation_and_STA.pptx Lab 3: Implementing and Verify the design in 14a_lab3_intro.pptx hardware Lab3.docx Day 2 Agenda Day 2 Materials IP Integrator and IP Catalog 15_ IPI_and_IP_Catalog.pptx Lab 4: Using IP Catalog 15a_lab4_intro.pptx Lab4.docx Xilinx Design Constraints 16_Xilinx_Design_Constraints.pptx Lab 5: Xilinx Design Constraints 16a_lab5_into.pptx Lab5.docx Hardware Debugging 17_Hardware_Debugging.pptx Lab 6: Hardware Debugging 17a_lab6_intro.pptx Lab6.docx LAB DESCRIPTIONS Lab 1 - Vivado Design Flow: Use Vivado IDE to create a simple HDL design targeting the NEXYS4. Lab 2 - Synthesizing a RTL Design: Synthesize a design with the default settings as well as some settings changed and observe the effect. Lab 3 - Implementing and verify the design in hardware: Implement the synthesized design of previous lab, perform timing analysis, generate bitstream, download the bitstream and verify the functionality. Lab 4 - Using IP Catalog: Use the IP Catalog to generate a clock resource and instantiate in a design. Use IP Integrate to generate a core and instantiate in the design. Lab 5 - Xilinx Design Constraints: Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Then create the timing constraints and perform the timing analysis. Lab 6 - Hardware Debugging: Use Mark Debug feature and also available Integrated Logic Analyzer (ILA) core (available in IP Catalog) to debug the hardware. Contact XUP Send an email to for questions or comments
Day 1 Agenda Day 1 Materials Class Intro 01_class_intro.pptx 7-Series Architecture Overview 11_7_Series_Architecture_Overview.ppt x Vivado Design Flow 12_ Vivado Design Flow.pptx Lab 1: Vivado Design Flow 12a_lab1_intro.pptx Lab1.docx Synthesis 13_Synthesis.pptx Lab 2: Synthesizing a RTL Design 13a_lab2_intro.pptx Lab2.docx Implementation and STA 14_ Implementation_and_STA.pptx Lab 3: Implementing and Verify the design in hardware 14a_lab3_intro.pptx Lab3.docx Day 2 Agenda Day 2 Materials IP Integrator and IP Catalog 15_ IPI_and_IP_Catalog.pptx Lab 4: Using IP Catalog 15a_lab4_intro.pptx Lab4.docx Xilinx Design Constraints 16_Xilinx_Design_Constraints.pptx Lab 5: Xilinx Design Constraints 16a_lab5_into.pptx Lab5.docx Hardware Debugging 17_Hardware_Debugging.pptx Lab 6: Hardware Debugging 17a_lab6_intro.pptx Lab6.docx LAB DESCRIPTIONS Lab 1 - Vivado Design Flow: Use Vivado IDE to create a simple HDL design targeting the NEXYS4. Lab 2 - Synthesizing a RTL Design: Synthesize a design with the default settings as well as some settings changed and observe the effect. Lab 3 - Implementing and verify the design in hardware: Implement the synthesized design of previous lab, perform timing analysis, generate bitstream, download the bitstream and verify the functionality. Lab 4 - Using IP Catalog: Use the IP Catalog to generate a clock resource and instantiate in a design. Use IP Integrate to generate a core and instantiate in the design. Lab 5 - Xilinx Design Constraints: Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Then create the timing constraints and perform the timing analysis. Lab 6 - Hardware Debugging: Use Mark Debug feature and also available Integrated Logic Analyzer (ILA) core (available in IP Catalog) to debug the hardware. Contact XUP Send an email to for questions or comments
readme_nexysvideo.docx