K.Babulu, Mohammad Shaffi, Implementation of Multi-Rate Reconfigurable “FPGA Architecture with low complexity FIR International Journal of Emerging Filters”, Technology & Advanced Engineering, Volume-2, Issue-10, pp 89-98, October 2012. K.Babulu, K.Venkateswara Rao A new Parallel Counter Architecture with Reduced “ Transistor Count for Power and Area PARIPEX-Indian Journal of Optimization”, Research, Volume-2, Issue-1, pp 62-64, January 2013. K.Babulu, P.S.S.M.Kalyan, and Development of Activation and Monitoring of “Design Industry Automation System Via SMS Through International Journal of FPGA”, Innovative Research and Development, Volume-2, Issue-1, pp 216-226, January 2013. Analysis of wire redundancy in Bus encoding Techniques for Deep Sub K.Padmapriya” Micron Technology-A International Journal of Electrical and Electronics Review”, Engineering and Telecommunications, April 2013 issue, ISSN: Doddabasavana Goud.B, K.Padma A General Review of Practical Centrifuges Priya” Used to Detect RBC & WBC Count International Journal of Electrical and Values” Electronics Engineering and Telecommunications, April 2013 issue, ISSN: 2319-2518.pp 17-26.(i.f.0.384). Srinivas, Ramanaiah, Low Power Energy Efficient CMOS Voltage Level K.padmapriya” Shifter for Multi VDD International Journal of Electrical and Electronics Systems” Engineering and Telecommunications, April 2013 issue, ISSN: K.Padmapriya, Deepti and Verification of VLSI Based AES Crypto Core “Design Processor Using Verilog In May,2013 Issue, ISSN:2277-9655,pp- HDL”, IJESRT I.F.3.785). Efficiency cross talk avoidance scheme in VLSI K.PadmaPriya, Gopi, “Redundancy I International Journal of Computer & Organization Trends Issue4 circuits”, –Volume3 May 2013, ISSN: 2249-2593,pp 80-83.(i.f. 1.190). –
K.Babulu, Mohammad Shaffi, “FPGA Implementation of Multi-Rate Reconfigurable Architecture with low complexity FIR Filters”, International Journal of Emerging Technology & Advanced Engineering, Volume-2, Issue-10, pp 89-98, October 2012. K.Babulu, K.Venkateswara Rao “ A new Parallel Counter Architecture with Reduced Transistor Count for Power and Area Optimization”, PARIPEX-Indian Journal of Research, Volume-2, Issue-1, pp 62-64, January 2013. K.Babulu, P.S.S.M.Kalyan, “Design and Development of Activation and Monitoring of Industry Automation System Via SMS Through FPGA”, International Journal of Innovative Research and Development, Volume-2, Issue-1, pp 216-226, January 2013. K.Padmapriya” Analysis of wire redundancy in Bus encoding Techniques for Deep Sub Micron Technology-A Review”, International Journal of Electrical and Electronics Engineering and Telecommunications, April 2013 issue, ISSN: Doddabasavana Goud.B, K.Padma Priya” A General Review of Practical Centrifuges Used to Detect RBC & WBC Count Values” International Journal of Electrical and Electronics Engineering and Telecommunications, April 2013 issue, ISSN: 2319-2518.pp 17-26.(i.f.0.384). Srinivas, Ramanaiah, K.padmapriya” Low Power Energy Efficient CMOS Voltage Level Shifter for Multi VDD Systems” International Journal of Electrical and Electronics Engineering and Telecommunications, April 2013 issue, ISSN: K.Padmapriya, Deepti “Design and Verification of VLSI Based AES Crypto Core Processor Using Verilog HDL”, IJESRT In May,2013 Issue, ISSN:2277-9655,pp- I.F.3.785). K.PadmaPriya, Gopi, “Redundancy Efficiency cross talk avoidance scheme in VLSI circuits”, I International Journal of Computer & Organization Trends –Volume3 Issue4 – May 2013, ISSN: 2249-2593,pp 80-83.(i.f. 1.190).
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