11 Passband modulator signal spectrum Demodulator Shown in Fig. 12 is the demodulator architecture. The signal from the A/D converter, at a y1(n), sample rate of 8 000 Hz and length (L + + is down-converted from a real passband S)*(N P)*R, signal into a complex baseband signal, The complex signal, is also used for timing and y2(n). y2(n), frequency recovery. The frequency offset, is used in the downconverter, and the timing recovery, f, is used in selecting the first symbol in the cyclic prefix. The down converter output, is r, y2(n), decimated by into (L + + samples, The synchronization symbols are then removed R S)*(N P) y3(n). and converted from serial to parallel into by (N + symbols, Note that at this stage in L P) y4(m, n). the demodulator there is one sample per symbol, so the terms and can be “symbol” “sample” interchanged. The cyclic prefix is removed resulting in by symbols, at a sample rate L N y5(m, n), of: (11) A complex FFT is then applied to resulting in by symbols, Then a detector y5(m, n) L N y6(m, n). recovers the symbols using a differential method, which eliminates the need for recovering the carrier phase, but still requiring recovery of the carrier frequency. Frequency is recovered for all of the subcarriers at the same time and is not required for the individual carriers. The detection is done individually on each of the subcarriers. The symbols out of the detector are mapped into N log 2(M)*L by bits, using the same mapping as the modulator. The bits are descrambler N y7(m, n), using the inverse process as that used in the modulator resulting in log 2(M)*L by bits, N y8(m, n). The bits are then finally converted from parallel to serial resulting in log 2(M)*L*N bits, y9(n). Details of the individual blocks are provided below.
11 Passband modulator signal spectrum Demodulator Shown in Fig. 12 is the demodulator architecture. The signal from the A/D converter, y1(n), at a sample rate of 8 000 Hz and length (L + S)*(N + P)*R, is down-converted from a real passband signal into a complex baseband signal, y2(n). The complex signal, y2(n), is also used for timing and frequency recovery. The frequency offset, f, is used in the downconverter, and the timing recovery, r, is used in selecting the first symbol in the cyclic prefix. The down converter output, y2(n), is decimated by R into (L + S)*(N + P) samples, y3(n). The synchronization symbols are then removed and converted from serial to parallel into L by (N + P) symbols, y4(m, n). Note that at this stage in the demodulator there is one sample per symbol, so the terms “symbol” and “sample” can be interchanged. The cyclic prefix is removed resulting in L by N symbols, y5(m, n), at a sample rate of: (11) A complex FFT is then applied to y5(m, n) resulting in L by N symbols, y6(m, n). Then a detector recovers the symbols using a differential method, which eliminates the need for recovering the carrier phase, but still requiring recovery of the carrier frequency. Frequency is recovered for all of the subcarriers at the same time and is not required for the individual carriers. The detection is done individually on each of the N subcarriers. The symbols out of the detector are mapped into log 2(M)*L by N bits, y7(m, n), using the same mapping as the modulator. The bits are descrambler using the inverse process as that used in the modulator resulting in log 2(M)*L by N bits, y8(m, n). The bits are then finally converted from parallel to serial resulting in log 2(M)*L*N bits, y9(n). Details of the individual blocks are provided below.
R-REC-M.1798-1-201004-I!!MSW-E.docx