Wrapper Interface HV_STATUS HvAssertVirtualInterrupt( __in HV_PARTITION_ID DestinationPartition, __in HV_INTERRUPT_CONTROL InterruptControl, __in UINT64 DestinationAddress, __in HV_INTERRUPT_VECTOR RequestedVector ); Native Interface HvAssertVirtualInterrupt Call Code = 0x0055 Input Parameters 0 DestinationPartition (8 bytes) 8 InterruptControl (8 bytes) 16 DestinationAddress (8 bytes) 24 RequestedVector (4 bytes) Padding (4 bytes) Description For information on virtual interrupts, see section . If the call is made twice in a row with the same interrupt type specified in the InterruptControl parameter, the behavior depends upon whether or not the first interrupt was acknowledged by the virtual processor before the second call is made. If the first interrupt has already been acknowledged, then the second call is treated as a new assertion. If the first interrupt has not yet been acknowledged, then the second call supersedes the previous assertion with the new vector. If the second call specifies the vector HV_INTERRUPT_VECTOR_NONE, then the call acts as a deassertion. The behavior of this call differs for interrupts of type HvX64InterruptTypeExtInt in the following ways: This interrupt type is always targeted at the boot processor. The boot processor is identified by a virtual processor index of zero. The DestinationAddress parameter must, therefore, be zero. Calls to HvAssertVirtualInterrupt will fail if the interrupt asserted by a previous call has already been acknowledged by the processor. This acknowledgement must first be cleared by calling HvClearVirtualInterrupt. This is especially useful when implementing an external interrupt controller, such as the 8259 PIC. It prevents HvAssertVirtualInterrupt from overwriting the previous acknowledgement, which may need to be reported through the external interrupt controller. Input Parameters DestinationPartition specifies the partition. InterruptControl specifies the type of the virtual interrupt that should be asserted, its destination mode and whether the virtual interrupt is edge or level triggered.
Wrapper Interface HV_STATUS HvAssertVirtualInterrupt( __in HV_PARTITION_ID DestinationPartition, __in HV_INTERRUPT_CONTROL InterruptControl, __in UINT64 DestinationAddress, __in HV_INTERRUPT_VECTOR RequestedVector ); Native Interface HvAssertVirtualInterrupt Call Code = 0x0055 Input Parameters 0 DestinationPartition (8 bytes) 8 InterruptControl (8 bytes) 16 DestinationAddress (8 bytes) 24 RequestedVector (4 bytes) Padding (4 bytes) Description For information on virtual interrupts, see section . If the call is made twice in a row with the same interrupt type specified in the InterruptControl parameter, the behavior depends upon whether or not the first interrupt was acknowledged by the virtual processor before the second call is made. If the first interrupt has already been acknowledged, then the second call is treated as a new assertion. If the first interrupt has not yet been acknowledged, then the second call supersedes the previous assertion with the new vector. If the second call specifies the vector HV_INTERRUPT_VECTOR_NONE, then the call acts as a deassertion. The behavior of this call differs for interrupts of type HvX64InterruptTypeExtInt in the following ways: This interrupt type is always targeted at the boot processor. The boot processor is identified by a virtual processor index of zero. The DestinationAddress parameter must, therefore, be zero. Calls to HvAssertVirtualInterrupt will fail if the interrupt asserted by a previous call has already been acknowledged by the processor. This acknowledgement must first be cleared by calling HvClearVirtualInterrupt. This is especially useful when implementing an external interrupt controller, such as the 8259 PIC. It prevents HvAssertVirtualInterrupt from overwriting the previous acknowledgement, which may need to be reported through the external interrupt controller. Input Parameters DestinationPartition specifies the partition. InterruptControl specifies the type of the virtual interrupt that should be asserted, its destination mode and whether the virtual interrupt is edge or level triggered.
Hypervisor%20Top%20Level%20Functional%20Specification%20v0_83.docx