TSO P0: read 118 SC P0: write 110 80 TSO Problem 4: Instruction Flow and Branch Prediction [30 points] This problem investigates the effects of branches and control flow changes on program performance for a scalar pipeline (to keep the focus on branch prediction). Branch penalties increase as the number of pipeline stages increases between instruction fetch and branch resolution (or condition and target resolution). This effect of pipelined execution drives the need for branch prediction. This problem explores both static branch prediction in and dynamic branch prediction in For this Part C Part D. problem the base machine is a 5-Stage pipeline. The 5-Stage Pipeline without Dynamic Branch Prediction Execution Assumptions: unconditional branches execute in the decode stage conditional branches execute in the execute stage Effective address calculation is performed in the The fetch address is a choice execute stage between the sequential address All memory access is generation logic and the branch performed in the correction logic. If a mispredicted memory access stage branch is being corrected the All necessary correction address is chosen over the forwarding paths exist sequential address for the next fetch The register file is read address. after write Part A: Branch Penalties. [2 points] What are the branch penalties for unconditional and conditional branches?
TSO P0: read 118 P0: write 110 80 SC TSO Problem 4: Instruction Flow and Branch Prediction [30 points] This problem investigates the effects of branches and control flow changes on program performance for a scalar pipeline (to keep the focus on branch prediction). Branch penalties increase as the number of pipeline stages increases between instruction fetch and branch resolution (or condition and target resolution). This effect of pipelined execution drives the need for branch prediction. This problem explores both static branch prediction in Part C and dynamic branch prediction in Part D. For this problem the base machine is a 5-Stage pipeline. The 5-Stage Pipeline without Dynamic Branch Prediction Execution Assumptions: unconditional branches execute in the decode stage conditional branches execute in the execute stage Effective address calculation is performed in the execute stage All memory access is performed in the memory access stage All necessary forwarding paths exist The register file is read after write The fetch address is a choice between the sequential address generation logic and the branch correction logic. If a mispredicted branch is being corrected the correction address is chosen over the sequential address for the next fetch address. Part A: Branch Penalties. [2 points] What are the branch penalties for unconditional and conditional branches?
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