CHAPTER 1 INTRODUCTION Integrated circuits are designed and simulated by designers and then sent off to a wafer fabrication to be built on wafers. Unfortunately wafer fabrication manufacturing and design defects are only discovered during the electrical test of the integrated circuit. This testing of the circuit electrically can be performed at the wafer level, package level or both. Electrical testing produces a data-log that contains specific device characteristic data known as parametric data. Testing of the integrated circuit has become increasing expensive in an ultra competitive market and circuit manufactures are exploring new methods of discovering failures. Traditionally circuit manufactures would use a method that would set an upper and lower limit on a parametric measurement to detect circuit failures. This methodology has become only a portion of the criteria that is now required to discover potential defects of small geometry integrated circuits. Integrated circuit manufacturers are now employing additional methods of failure detection including wafer test structures and specialized BIST (built in self test) circuitry. After extensive characterization of the circuit on many devices, a high percentage failure mode trending on these devices can be used to detect lower parametric marginality. Design for manufacturing simulations is limited in that they only employ detecting a limited parametric measurement to the original design simulation.
CHAPTER 1 INTRODUCTION Integrated circuits are designed and simulated by designers and then sent off to a wafer fabrication to be built on wafers. Unfortunately wafer fabrication manufacturing and design defects are only discovered during the electrical test of the integrated circuit. This testing of the circuit electrically can be performed at the wafer level, package level or both. Electrical testing produces a data-log that contains specific device characteristic data known as parametric data. Testing of the integrated circuit has become increasing expensive in an ultra competitive market and circuit manufactures are exploring new methods of discovering failures. Traditionally circuit manufactures would use a method that would set an upper and lower limit on a parametric measurement to detect circuit failures. This methodology has become only a portion of the criteria that is now required to discover potential defects of small geometry integrated circuits. Integrated circuit manufacturers are now employing additional methods of failure detection including wafer test structures and specialized BIST (built in self test) circuitry. After extensive characterization of the circuit on many devices, a high percentage failure mode trending on these devices can be used to detect lower parametric marginality. Design for manufacturing simulations is limited in that they only employ detecting a limited parametric measurement to the original design simulation.
erickson_projectThesis_041311.docx