Control and Orchestration of Processor States On-Line Parameter Loading Off-Line Parameter Loading Design Physical Architecture of the Tomography Engine FPGA Design Xilinx Virtex 5 or 6 Higher density may lead to timing and pin-out issues Higher density logic may lead to more susceptibility to SEU’s Cell Layout FPGA Configuration System Monitor The System Monitor monitors the core temperatures and voltages of each FPGA. They are linked serially, so that the health of each FPGA in the tomography processor can be monitored independent of the operation state of the system. Clocks Data System Signaling Diagnostics and Telemetry
Control and Orchestration of Processor States On-Line Parameter Loading Off-Line Parameter Loading Design Physical Architecture of the Tomography Engine FPGA Design Xilinx Virtex 5 or 6 Higher density may lead to timing and pin-out issues Higher density logic may lead to more susceptibility to SEU’s Cell Layout FPGA Configuration System Monitor The System Monitor monitors the core temperatures and voltages of each FPGA. They are linked serially, so that the health of each FPGA in the tomography processor can be monitored independent of the operation state of the system. Clocks Data System Signaling Diagnostics and Telemetry
NGAO_RTC_Design_A.docx