N (user Y Tensilica manycore Y N defined) [13] based on manycore Y Y Y N (shared Tensilica tools memory) N (user N (user CoWare manycore Y N defined) defined) [28] based on manycore N (problem N (user Y N specific defined) Coware tools topology) N (user N Altera multicore Y N defined) [21] based on multicore Y Y Y N (mailbox) Altera tools N (user N Xilinx multicore Y N defined) manycore Y N Y Y Daedalus on Xilinx tools Srijan Y Y (not Y Y multicore integrated) RAMP based on massively N (user N Y N (user defined Xilinx tools parallel defined) through API) MILAN manycore Y N Y Y To build a usable toolchain takes man-years of effort and requires years of sustained effort and funding. "It takes approximately four years and many millions of dollars to prototype a new architecture in hardware, even at only research quality" [29]. And so we must limit our research to solving open problems with the hope that we can bring forward a platform which supports both MPSoC and ASIP technologies. Some open problems in the field of configurable MPSoC are: Describe mathematically the tradeoff between the number of processors and the number of custom instructions for an MPSoC with ASIPs. Extract concurrency in a general way from application software and apply it to the design of an MPSoC. This will require a balance between compile-time and run-time scheduling. Find a balance between AMP and SMP approaches based upon application software. Describe the proper mix of interprocessor communication hardware (point-to-point, busses, network-on-chip, shared memory) by analyzing application software. Describe the topology and memory hierarchy of a massively parallel MPSoC by analyzing application software. References Tom R. Halfhill, "The Future of Multicore Processors," Microprocessor Report [online], Dec. 2007 Mar. 12, 2009], available from World Wide Web: <http://www.mdronline.com/mpr_public/editorials/edit21_53.html>.
Tensilica manycore N (user defined) Y Y N [13] based on Tensilica tools manycore Y Y Y N (shared memory) CoWare manycore N (user defined) N (user defined) Y N [28] based on Coware tools manycore N (problem specific topology) N (user defined) Y N Altera multicore N (user defined) N Y N [21] based on Altera tools multicore Y Y Y N (mailbox) Xilinx multicore N (user defined) N Y N Daedalus on Xilinx tools manycore Y N Y Y Srijan multicore Y Y (not integrated) Y Y RAMP based on Xilinx tools massively parallel N (user defined) N Y N (user defined through API) MILAN manycore Y N Y Y To build a usable toolchain takes man-years of effort and requires years of sustained effort and funding. "It takes approximately four years and many millions of dollars to prototype a new architecture in hardware, even at only research quality" [29]. And so we must limit our research to solving open problems with the hope that we can bring forward a platform which supports both MPSoC and ASIP technologies. Some open problems in the field of configurable MPSoC are: Describe mathematically the tradeoff between the number of processors and the number of custom instructions for an MPSoC with ASIPs. Extract concurrency in a general way from application software and apply it to the design of an MPSoC. This will require a balance between compile-time and run-time scheduling. Find a balance between AMP and SMP approaches based upon application software. Describe the proper mix of interprocessor communication hardware (point-to-point, busses, network-on-chip, shared memory) by analyzing application software. Describe the topology and memory hierarchy of a massively parallel MPSoC by analyzing application software. References Tom R. Halfhill, "The Future of Multicore Processors," Microprocessor Report [online], Dec. 2007 Mar. 12, 2009], available from World Wide Web: <http://www.mdronline.com/mpr_public/editorials/edit21_53.html>.
Multiprocessor_ASIP_Lit_Review.docx