M.Tech VLSI 2016-2017 S.No PROJECT NAME Design IEEE Pre-Encoded Multipliers Based on Non-Redundant Radix-4 1 Front End 2016 Signed-Digit Encoding Floating-Point Butterfly Architecture Based on Binary 2 Front End 2016 Representation Flexible DSP Accelerator Architecture Exploiting Carry-Save 3 Front End 2016 Arithmetic A High-Performance FIR Filter Architecture for Fixed and 4 Front End 2016 Reconfigurable Applications A Method to Design Single Error Correction Codes 5 Front End 2016 With Fast Decoding for a Subset of Critical Bits 6 On Efficient Retiming of Fixed-Point Circuits Front End 2016 Concept, Design, and Implementation of Reconfigurable 7 Front End 2016 CORDIC Fault Tolerant Parallel FFTs Using Error Correction Codes 8 Front End 2016 and Parseval Checks Low-Power Parallel Chien Search Architecture Using a 9 Front End 2016 Approach An Efficient Single and Double-Adjacent Error Correcting 10 Front End 2016 Parallel Decoder for the (24,12) Extended Golay Code Memory-Reduced Turbo Decoding Architecture 11 Front End 2016 Using NII Metric Compression Multiple Constant Multiplication Algorithm for High-Speed and 12 Front End 2016 Low-Power Design 13 Design and Analysis of Inexact Floating-Point Adders Front End 2016 A Mixed-Decimation MDF Architecture for Radix-2k Parallel 14 Front End 2016 FFT A Modified Partial Product Generator for Redundant Binary 15 Front End 2016 Multipliers A Cellular Network Architecture With Polynomial Weight 16 Front End 2016 Functions A Normal I/O Order Radix-2 FFT Architecture to Process 17 Front End 2016 Twin Data Streams for MIMO High Speed Hybrid Double Multiplication Architectures Using 18 Front End 2016 New Serial-Out Bit- Level Mastrovito Multipliers Low-Cost High-Performance VLSI Architecture for 19 Front End 2016 Montgomery Modular Multiplication A High-Speed FPGA Implementation of an RSD-Based ECC 20 Front End 2016 Processor
M.Tech VLSI 2016-2017 S.No PROJECT NAME Design IEEE 1 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Front End 2016 2 Floating-Point Butterfly Architecture Based on Binary Representation Front End 2016 3 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2016 4 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Front End 2016 5 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits Front End 2016 6 On Efficient Retiming of Fixed-Point Circuits Front End 2016 7 Concept, Design, and Implementation of Reconfigurable CORDIC Front End 2016 8 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Front End 2016 9 Low-Power Parallel Chien Search Architecture Using a Approach Front End 2016 10 An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code Front End 2016 11 Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression Front End 2016 12 Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design Front End 2016 13 Design and Analysis of Inexact Floating-Point Adders Front End 2016 14 A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT Front End 2016 15 A Modified Partial Product Generator for Redundant Binary Multipliers Front End 2016 16 A Cellular Network Architecture With Polynomial Weight Functions Front End 2016 17 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Front End 2016 18 High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- Level Mastrovito Multipliers Front End 2016 19 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Front End 2016 20 A High-Speed FPGA Implementation of an RSD-Based ECC Processor Front End 2016