*. Branch: ALU output← NPC + (Imm << 2) Cond (A == O) ← The ALU adds the NPC to the sign-extended immediate value in Imm, which is Operation: shifted left by 2 bits to create a word offset, to compute the address of the branch target. Register A, which has been read in the prior cycle, is checked to determine whether the branch is taken. Since we are considering only one form of branch (BEQZ), the comparison is against 0. Note that BEQZ is actually a pseudoinstruction that translates to a BEQ with R0 as an operand. For simplicity, this is the only form of branch we consider. The load-store architecture of MIPS means that effective address and execution cycles can be combined into a single clock cycle, since no instruction needs to simultaneously calculate a data address, calculate an instruction target address, and perform an operation on the data. The other integer instructions not included above are jumps of various forms, which are similar to branches. 4. (MEM): Memory access/branch completion cycle The PC is updated for all instructions: PC NPC; ← *Memory reference: LMD Mem[ALUOutput] or ← Mem[ALUOutput] B; ← Access memory if needed. If instruction is a load, data returns Operation: from memory and is placed in the LMD (load memory data) register; if it is a store, then the data from the B register is written into memory. In either case the address used is the one computed during the prior cycle and stored in the register ALUOutput. * Branch: if (cond) PC ALUOutput ← If the instruction branches, the PC is replaced with the branch destination address in Operation: the register ALUOutput. 5. (WB): Write-back cycle * Register-Register ALU instruction: Regs[rd] ALUOutput; ←
*. Branch: ALU output← NPC + (Imm << 2) Cond ← (A == O) Operation: The ALU adds the NPC to the sign-extended immediate value in Imm, which is shifted left by 2 bits to create a word offset, to compute the address of the branch target. Register A, which has been read in the prior cycle, is checked to determine whether the branch is taken. Since we are considering only one form of branch (BEQZ), the comparison is against 0. Note that BEQZ is actually a pseudoinstruction that translates to a BEQ with R0 as an operand. For simplicity, this is the only form of branch we consider. The load-store architecture of MIPS means that effective address and execution cycles can be combined into a single clock cycle, since no instruction needs to simultaneously calculate a data address, calculate an instruction target address, and perform an operation on the data. The other integer instructions not included above are jumps of various forms, which are similar to branches. 4. Memory access/branch completion cycle (MEM): The PC is updated for all instructions: PC ← NPC; *Memory reference: LMD ← Mem[ALUOutput] or Mem[ALUOutput] ← B; Operation: Access memory if needed. If instruction is a load, data returns from memory and is placed in the LMD (load memory data) register; if it is a store, then the data from the B register is written into memory. In either case the address used is the one computed during the prior cycle and stored in the register ALUOutput. * Branch: if (cond) PC ← ALUOutput Operation: If the instruction branches, the PC is replaced with the branch destination address in the register ALUOutput. 5. Write-back cycle (WB): * Register-Register ALU instruction: Regs[rd] ← ALUOutput;