b. 8 c. 6 d. cannot be determined In a 6-stage dual-pipelined processor, how many clock cycles are required to execute 5 instructions? (Assume that stage 4 requires two clock cycles, and that stage 4 has two pipelines.) a. 10 b. 11 c. 12 d. 15 Which of the following correctly describes the sequence of reading from memory during a single clock cycle? a. Read line set low; Address placed on bus; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data. b. Address placed on bus; Operand placed on data bus by memory controller; Read line set low; Read line set high, indicating that data bus contains the requested data. c. Address placed on bus; Read line set low; Read line set high, indicating that data bus contains the requested data; Operand placed on data bus by memory controller. d. Address placed on bus; Read line set low; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data. Which register is known as a loop counter? a. EAX b. EBX c. ECX d. EDX Which mode is the native state of the Intel processor? a. Protected mode b. Virtual-8086 mode c. Real-address mode
b. 8 c. 6 d. cannot be determined In a 6-stage dual-pipelined processor, how many clock cycles are required to execute 5 instructions? (Assume that stage 4 requires two clock cycles, and that stage 4 has two pipelines.) a. 10 b. 11 c. 12 d. 15 Which of the following correctly describes the sequence of reading from memory during a single clock cycle? a. Read line set low; Address placed on bus; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data. b. Address placed on bus; Operand placed on data bus by memory controller; Read line set low; Read line set high, indicating that data bus contains the requested data. c. Address placed on bus; Read line set low; Read line set high, indicating that data bus contains the requested data; Operand placed on data bus by memory controller. d. Address placed on bus; Read line set low; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data. Which register is known as a loop counter? a. EAX b. EBX c. ECX d. EDX Which mode is the native state of the Intel processor? a. Protected mode b. Virtual-8086 mode c. Real-address mode