Y (13) <=’0’; elseif then (SEL=”1110”) Y (14) <=’0’; else Y (51) <=’0’; end if; end process; end RTL; This coding uses a process statement and it includes conv_integer from the package IEEE std_logic_unsigned. architecture RTL of ENCODER is begin P3: process (SEL) begin Y <= => (Y’range ‘1’); Y (conv_integer (SEL)) <= ‘0’; end process; end RTL; ?4? PROGRAMMABLE LOGIC DEVICES Programmable logic devices helps in the removal of multiple off-the shelf devices and the inconvenience associated external wires. These devices allow an easy reprogramming and it is easier to change the design in case of error. They basically contain an array of basic building
Y (13) <=’0’; elseif (SEL=”1110”) then Y (14) <=’0’; else Y (51) <=’0’; end if; end process; end RTL; This coding uses a process statement and it includes conv_integer from the package IEEE std_logic_unsigned. architecture RTL of ENCODER is begin P3: process (SEL) begin Y <= (Y’range => ‘1’); Y (conv_integer (SEL)) <= ‘0’; end process; end RTL; ?4? PROGRAMMABLE LOGIC DEVICES Programmable logic devices helps in the removal of multiple off-the shelf devices and the inconvenience associated external wires. These devices allow an easy reprogramming and it is easier to change the design in case of error. They basically contain an array of basic building