Basis For FPGA And ASIC Implementations A Generalized Algorithm And Reconfigurable Architecture For 47 Front End 2015 Efficient And Scalable Orthogonal Approximation Of DCT Fully Reused VLSI Architecture Of Fm0/Manchester Encoding 48 Front End 2015 Using Sols Technique For DSRC Applications 49 Obfuscating DSP Circuits Via High-Level Transformations Front End 2015 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 50 Front End 2015 Signed-Digit Encoding Flexible DSP Accelerator Architecture Exploiting Carry-Save 51 Front End 2015 Arithmetic Fault Tolerant Parallel Filters Based On Error Correction 52 Front End 2015 Codes A Synergetic Use Of Bloom Filters For Error Detection And 53 Front End 2015 Correction Reliable Low-Power Multiplier Design Using Fixed-Width 54 Front End 2015 Replica Redundancy Block Recursive Approach To The Design Of A Parallel Self-Timed 55 Front End 2015 Adder Aging-Aware Reliable Multiplier Design With Adaptive Hold 56 Front End 2015 Logic Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant 57 Front End 2015 Multiplications Scan Test Bandwidth Management For Ultralarge-Scale 58 Front End 2015 System-On-Chip Architectures Low-Power And Area-Efficient Shift Register Using Pulsed 59 Front End 2015 Latches Low-Power Programmable PRPG With Test Compression 60 Front End 2015 Capabilities One Minimum Only Trellis Decoder For Non – Binary Low - 61 Front End 2015 Density Parity - Check Codes A Low Complexity Scaling Method For The Lanczos Kernel In 62 Front End 2015 Fixed-Point Arithmetic Low-Latency High-Throughput Systolic Multipliers Over 63 Front End 2015 GF(2m) For NIST Recommended Pentanomials 64 Efficient Coding Schemes For Fault-Tolerant Parallel Filters Front End 2015 65 Partially Parallel Encoder Architecture For Long Polar Codes Front End 2015 Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture For multi - 66 Front End 2015 Standard SDR Applications Algorithm And Architecture For A Low-Power 67 Back End 2015 Memory Based On Sparse Clustered Networks A Self-Powered High-Efficiency Rectifier With Automatic 68 Resetting Of Transducer Capacitance In Piezoelectric Energy Back End 2015 Harvesting Systems 69 Mixing Drivers In Clock-Tree For Supply Noise Back End 2015
Basis For FPGA And ASIC Implementations 47 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT Front End 2015 48 Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications Front End 2015 49 Obfuscating DSP Circuits Via High-Level Transformations Front End 2015 50 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding Front End 2015 51 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2015 52 Fault Tolerant Parallel Filters Based On Error Correction Codes Front End 2015 53 A Synergetic Use Of Bloom Filters For Error Detection And Correction Front End 2015 54 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block Front End 2015 55 Recursive Approach To The Design Of A Parallel Self-Timed Adder Front End 2015 56 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Front End 2015 57 Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications Front End 2015 58 Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures Front End 2015 59 Low-Power And Area-Efficient Shift Register Using Pulsed Latches Front End 2015 60 Low-Power Programmable PRPG With Test Compression Capabilities Front End 2015 61 One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes Front End 2015 62 A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic Front End 2015 63 Low-Latency High-Throughput Systolic Multipliers Over GF(2m) For NIST Recommended Pentanomials Front End 2015 64 Efficient Coding Schemes For Fault-Tolerant Parallel Filters Front End 2015 65 Partially Parallel Encoder Architecture For Long Polar Codes Front End 2015 66 Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture For multi - Standard SDR Applications Front End 2015 67 Algorithm And Architecture For A Low-Power Memory Based On Sparse Clustered Networks Back End 2015 68 A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems Back End 2015 69 Mixing Drivers In Clock-Tree For Supply Noise Back End 2015