Integer ALU's •6 multimedia ALU's •6 Extended Precision FP •2 Single Precision FP units •2 Load and Units •2 Branch Units •3 Stage 6 Wide Pipeline •8 L1 Cache •32k L2 •256K L3 Cache(on die)þ •3MB Clock initially •1Ghz to 1.66Ghz on Montvale –Up Itanium2 Improvements a 180nm process •Initially to in 2003 –Increased increased to 90nm in 2007 –Further Thermal Management •Improved Speed increased to 1.0Ghz Speed Increase from 266Mhz to 400Mhz •Bus moved on die •L3 access rate IA-64 Pipeline Features Prediction •Branch Registers allow branches to be turned on or off –Predicate can provide branch prediction hints –Compiler Rotation •Register faster loop execution in parallel –Allows Controls Pipeline Stages •Predication Cache Features Cache •L1 way associative –4 Instruction Data –16Kb Cache •L2 –Itanium way associative •6 Kb •96 –Itanium2 way associative •8 Kb Initially •256 Data and 1Mb Instruction on Montvale! –256Kb
•6 Integer ALU's •6 multimedia ALU's •2 Extended Precision FP •2 Single Precision FP units •2 Load and Units •3 Branch Units •8 Stage 6 Wide Pipeline •32k L1 Cache •256K L2 •3MB L3 Cache(on die)þ •1Ghz Clock initially –Up to 1.66Ghz on Montvale Itanium2 Improvements •Initially a 180nm process –Increased to in 2003 –Further increased to 90nm in 2007 •Improved Thermal Management Speed increased to 1.0Ghz •Bus Speed Increase from 266Mhz to 400Mhz •L3 moved on die access rate IA-64 Pipeline Features •Branch Prediction –Predicate Registers allow branches to be turned on or off –Compiler can provide branch prediction hints •Register Rotation –Allows faster loop execution in parallel •Predication Controls Pipeline Stages Cache Features •L1 Cache –4 way associative Instruction –16Kb Data •L2 Cache –Itanium •6 way associative •96 Kb –Itanium2 •8 way associative •256 Kb Initially –256Kb Data and 1Mb Instruction on Montvale!