An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword Although it is possible to use reg as a general-purpose variable, integer. it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation-specific but is at least 32 bits. Registers declared as data type reg store values as quantities, whereas unsigned integers store values as quantities. signed integer counter; // general purpose variable used as a counter. initial counter = -1; // A negative one is stored in the counter Real: Real number constants and real register data types are declared with the keyword They can real. be specified in notation (e.g., 3.14) or in notation (e.g., 3e6, which is 3x106). decimal scientific Real numbers cannot have a range declaration, and their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer. real delta; // Define a real variable called delta initial begin = 4e10; // delta is assigned in scientific notation delta = 2.13; // delta is assigned a value 2.13 end integer i; // Define an integer i initial i = delta; // i gets the value 2 (rounded value of 2.13) Time: Verilog simulation is done with respect to A special time register data type is simulation time. used in Verilog to store simulation time. A time variable is declared with the keyword The time. width for time register data types is implementation-specific but is at least 64 bits. The system function is invoked to get the current simulation time. $time time save_sim_time; // Define a time variable save_sim_time initial save_sim_time = $time; // Save the current simulation time Simulation time is measured in terms of The unit is denoted by the same simulation seconds. s, as real time. However, the relationship between real time in the digital circuit and simulation time is left to the user. 2.5.7 PARAMETERS
An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword integer. Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation-specific but is at least 32 bits. Registers declared as data type reg store values as unsigned quantities, whereas integers store values as signed quantities. integer counter; // general purpose variable used as a counter. initial counter = -1; // A negative one is stored in the counter Real: Real number constants and real register data types are declared with the keyword real. They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which is 3x106). Real numbers cannot have a range declaration, and their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer. real delta; // Define a real variable called delta initial begin = 4e10; // delta is assigned in scientific notation delta = 2.13; // delta is assigned a value 2.13 end integer i; // Define an integer i initial i = delta; // i gets the value 2 (rounded value of 2.13) Time: Verilog simulation is done with respect to simulation time. A special time register data type is used in Verilog to store simulation time. A time variable is declared with the keyword time. The width for time register data types is implementation-specific but is at least 64 bits. The system function $time is invoked to get the current simulation time. time save_sim_time; // Define a time variable save_sim_time initial save_sim_time = $time; // Save the current simulation time Simulation time is measured in terms of simulation seconds. The unit is denoted by s, the same as real time. However, the relationship between real time in the digital circuit and simulation time is left to the user. 2.5.7 PARAMETERS