Aditya Institute of Technology and Management (Autonomous), Tekkali III Year B.Tech (Electronics and Communication Engineering) 1st Sem. – Digital IC Applications Subject Code: 13EC3013 Credits: 3 Internal Marks: 30 External Marks : 70 Objective The student will study about different logic families, combinational and sequential circuits and their corresponding digital IC’s with VHDL modeling. Outcome At the end of the course the student will be able to: Design and analyze combinational and sequential circuits and their functions with relevant digital ICs. Do modeling combinational and sequential circuits with VHDL. Syllabus Unit I Logic Families: Introduction to logic families, CMOS logic, CMOS steady state electrical behavior, CMOS dynamic electrical behavior, CMOS logic families. bipolar logic, diode Logic, transistor logic, TTL families, CMOS/TTL interfacing, low voltage CMOS logic and interfacing, emitter coupled logic, comparison of logic families. Unit II Design and analysis procedures of decoders, encoders, three Combinational Logic Design I: – state devices, multiplexers and de-multiplexers, EX-OR gates and parity circuits and comparators. Design considerations of the above combinational logic with relevant digital ICs. VHDL modeling of decoders, encoders, multiplexers and comparators. Unit III Combinational Design II: Design and analysis procedures of adders, subtractors, ALUs, – barrel shifter, simple floating-point encoder, dual parity encoder, cascading comparators and combinational multipliers. Design considerations of the above combinational logic with relevant digital ICs. VHDL modeling of adders, subtractors, barrel shifter and combinational multipliers. Unit IV Sequential Logic Design: Latches and flip-flops, counters, shift registers, synchronous design methodology, impediments to synchronous design. VHDL modeling of ripple counters, synchronous counters and shift registers. Unit V PLDs: Introduction to PROM, RAM, PLA, PAL, CPLD, FPGA. Design considerations of PLDs with relevant digital ICs. VHDL modeling of memories and PLDs.
Aditya Institute of Technology and Management (Autonomous), Tekkali III Year B.Tech (Electronics and Communication Engineering) – 1st Sem. Digital IC Applications Subject Code: 13EC3013 Credits: 3 Internal Marks: 30 External Marks : 70 Objective The student will study about different logic families, combinational and sequential circuits and their corresponding digital IC’s with VHDL modeling. Outcome At the end of the course the student will be able to: Design and analyze combinational and sequential circuits and their functions with relevant digital ICs. Do modeling combinational and sequential circuits with VHDL. Syllabus Unit I Logic Families: Introduction to logic families, CMOS logic, CMOS steady state electrical behavior, CMOS dynamic electrical behavior, CMOS logic families. bipolar logic, diode Logic, transistor logic, TTL families, CMOS/TTL interfacing, low voltage CMOS logic and interfacing, emitter coupled logic, comparison of logic families. Unit II Combinational Logic Design – I: Design and analysis procedures of decoders, encoders, three state devices, multiplexers and de-multiplexers, EX-OR gates and parity circuits and comparators. Design considerations of the above combinational logic with relevant digital ICs. VHDL modeling of decoders, encoders, multiplexers and comparators. Unit III Combinational Design – II: Design and analysis procedures of adders, subtractors, ALUs, barrel shifter, simple floating-point encoder, dual parity encoder, cascading comparators and combinational multipliers. Design considerations of the above combinational logic with relevant digital ICs. VHDL modeling of adders, subtractors, barrel shifter and combinational multipliers. Unit IV Sequential Logic Design: Latches and flip-flops, counters, shift registers, synchronous design methodology, impediments to synchronous design. VHDL modeling of ripple counters, synchronous counters and shift registers. Unit V PLDs: Introduction to PROM, RAM, PLA, PAL, CPLD, FPGA. Design considerations of PLDs with relevant digital ICs. VHDL modeling of memories and PLDs.