systemverilog introduces three new procedural blocks intended to model hardware: codice_17 (to model combinational logic), codice_18 (for flip-flops), and codice_19 (for latches). whereas verilog used a single, general-purpose codice_20 block to model different types of hardware structures, each of systemverilog's new blocks is intended to model a specific type of hardware, by imposing semantic restrictions to ensure that hardware described by the blocks matches the intended usage of the model. an hdl compiler or verification program can take extra steps to ensure that only the intended type of behavior occurs.