futurebus+ supports bus widths from 32 to 256 bits. it is possible to build a board that supports all of these bus widths and will interoperate with boards that only support a subset. split bus transactions are supported so that slow response to a read or write will not tie up the backplane bus. cache coherence, implemented using the mesi protocols, was very complicated but significantly improved performance. futurebus+ was one of the first open standards to support live insertion which allowed boards to be replaced while the system was running.