in 1989, hp thought reduced instruction set computing (risc) architectures were stuck at one instruction per cycle. hp researchers tried to create a new type of processor architecture, later called explicitly parallel instruction computing (epic), that allows the processor to use many instructions in each clock cycle. epic uses a form of very long instruction word (vliw) architecture, in which 1 instruction word had many instructions. with epic, the compiler checks which instructions can be used at the same time, so the processor can run the instructions without needing complicated methods to see which instructions to use at the same time.