verilog-1995 and -2001 limit reg variables to behavioral statements such as rtl code. systemverilog extends the reg type so it can be driven by a single driver such as gate or module. systemverilog names this type "logic" to remind users that it has this extra capability and is not a hardware register. the names "logic" and "reg" are interchangeable. a signal with more than one driver (such as a tri-state buffer for general-purpose input/output) needs to be declared a net type such as "wire" so systemverilog can resolve the final value.