classical verilog permitted only one dimension to be declared to the left of the variable name. systemverilog permits any number of such "packed" dimensions. a variable of packed array type maps 1:1 onto an integer arithmetic quantity. in the example above, each element of codice_4 may be used in expressions as a six-bit integer. the dimensions to the right of the name (32 in this case) are referred to as "unpacked" dimensions. as in verilog-2001, any number of unpacked dimensions is permitted.