Background information 97 ch05/b-show-stack ch05/c-fibers In addition, you will get two more examples that I refer to in the book but that should be explored in the repository: ch05/d-fibers-closure : This is an extended version of the first example that might inspire you to do more complex things yourself. The example tries to mimic the API used in the Rust standard library using std::thread::spawn. ch05/e-fibers-windows : This is a version of the example that we go through in this book that works on both Unix-based systems and Windows. There is a quite detailed explanation in the README of the changes we make for the example work on Windows. I consider this recommended reading if you want to dive deeper into the topic, but it's not important to understand the main concepts we go through in this chapter. Background information We are going to interfere with and control the CPU directly. This is not very portable since there are many kinds of CPUs out there. While the overall implementation will be the same, there is a small but important part of the implementation that will be very specific to the CPU architecture we're programming for. Another aspect that limits the portability of our code is that operating systems have different ABIs that we need to adhere to, and those same pieces of code will have to change based on the different ABIs. Let's explain exactly what we mean here before we go further so we know we're on the same page. Instruction sets, hardware architectures, and ABIs Okay, before we start, we need to know the differences between an application binary interface (ABI), a CPU architecture, and an instruction set architecture (ISA). We need this to write our own stack and make the CPU jump over to it. Fortunately, while this might sound complex, we only need to know a few specific things for our example to run. The information presented here is useful in many more circumstances than just our example, so it's worthwhile to cover it in some detail. An ISA describes an abstract model of a CPU that defines how the CPU is controlled by the software it runs. We often simply refer to this as the instruction set, and it defines what instructions the CPU can execute, what registers programmers can use, how the hardware manages memory, etc. Examples of ISAs are x86-64, x86, and the ARM ISA (used in Mac M-series chips). ISAs are broadly classified into two subgroups, complex instruction set computers (CISC ) and reduced instruction set computers (RISC ), based on their complexity. CISC architectures offer a lot of different instructions that the hardware must know how to execute, resulting in some instructions that are very specialized and rarely used by programs. RISC architectures accept fewer instructions 