Paging Table


### Paging Tables
|Title|
|:-:|
|[Hashed page table](https://texonom.com/hashed-page-table-5503e136b5d94731911edb2a21ccd4c9)|
|[Inverted page table](https://texonom.com/inverted-page-table-25d3365925cf4aea9b9eb834c1c6bbad)|

### One table (mean one image) for each process: part of process’s state
<details><summary>

Contents</summary>

1. Flags: valid/invalid (also called resident) bit, dirty bit, reference (also called clock or used) bit used for clock page change algorithm
2. Page frame number
</details>

Page table is kept in main memory
 - Page-table base register (PTBR) points to the page table of each process
 - Page-table length register (PTLR) indicates size of the page table of each process
> use tlb to lessen memory access overhead to find page

page table size is pretty big → –** Only need to map the portion of the address space actually being used** (tiny fraction of entire address space)
Approach Methods
> – Multi-level(Hierarchical) paging, Hashed page table, Inverted page table






