This LANai v11 RISC chip seems to be the successor of the LANai v7 and LANai v9 chips described here: <a href="https:&#x2F;&#x2F;www.myricom.com&#x2F;scs&#x2F;myrinet&#x2F;...ogramming.html" rel="nofollow">https:&#x2F;&#x2F;www.myricom.com&#x2F;scs&#x2F;myrinet&#x2F;...ogramming.html</a>
for which the gcc toolchain already exists: <a href="https:&#x2F;&#x2F;github.com&#x2F;myri" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;myri</a>
Porting this to LLVM makes more sense.<p>Nothing too interesting, as it doesn&#x27;t use IBM&#x27;s 7nm or Intel&#x27;s 10nm chip tech.
Just a simple but parallel high-speed network chip, as used in the Myrinet network cards. The old ones ran with 33MHz but very low latency.<p>Really exciting would be the Power8 based on IBM&#x27;s new 7nm, which would finally blow away Intel advantages on an fully open (and unbackdoored) design.