<i>Right now I&#x27;m looking at a Z-80 gate that is three triple-input ANDs, all NORed together, and this is a single gate.</i><p>An &quot;AOI333&quot;, like this?<p><pre><code>           Vdd
            |
            +-|
              |--+
            +&lt;|  |
            |    |
            +----+---&gt; out
            |
       +----+----+
       |    |    |
     +-+  +-+  +-+
    -+   -+   -+
     +&gt;+  +&gt;+  +&gt;+
       |    |    |
     +-+  +-+  +-+
    -+   -+   -+
     +&gt;+  +&gt;+  +&gt;+
       |    |    |
     +-+  +-+  +-+
    -+   -+   -+
     +&gt;+  +&gt;+  +&gt;+
       |    |    |
       +----+----+
            |
           Vss
</code></pre>
It&#x27;s a good example of how even at the hardware level, abstraction can hide optimisation --- someone who didn&#x27;t know about these compound gates would just design with the regular ones, using far more transistors than necessary. That (NMOS) gate has a total of 10 transistors, while the equivalent with individual gates would take 22 (6 for each AND -- 3 pulldown + 1 pullup for a NAND, followed by another 2 for an inverter, feeding into a 4-transistor NOR-3), more than double.<p>Given how &quot;loose&quot; its layout is compared to the Z80, I guess the ARM1 doesn&#x27;t have very many compound gates either? I wonder if they could&#x27;ve gotten an even lower-power and faster ARM1 if they did manually optimise the layout.