&gt; x86 does have a register for defining the location of page tables that it will walk, the it would trap on a miss if the PTE is missing. Idk, if Linux uses this register or not or uses a software defined TLB, or some kind of hybrid approach.<p>TLB management is done in hardware on x86. TLB misses don&#x27;t generate exceptions, they just trigger page table walks in hardware, and then if the page table walk fails (e.g. because of a non-present page table entry) it triggers a CPU exception (page fault) that the OS can then handle.<p>Things like MIPS use a software-managed TLB that works roughly as you describe, though.