They are specific. See 5 in 5.1.2.4 Multi-threaded executions and data races in n1570.<p>In term of real hardware it translates well in MESI&#x2F;MESI-like protocol on cache lines on ooo cores, without much more constraints (of course some arch are sufficiently weak to still require special instructions, but on the other hand x86 don&#x27;t need anything for acq&#x2F;rel). If the different cores never touch the same cache line, they don&#x27;t need to do interact at all even when both execute unrelated acq&#x2F;rel atomics.