A curious result: Using four-wide SIMD instructions gives a mere 40% speed-up compared to the scaler case.  I wonder if this is actually a net loss.<p>- CPU&#x27;s are power limited today (high-confidence)<p>- Using the SIMD units vice scalar units increases power consumption (medium confidence - certainly some arithmetic-limited algorithms consume much more power with SSE)<p>Conclusion - the incremental impact on total system throughput is negative for this speed boost?  I wonder how much of a raw throughput improvement is needed to justfiy using the SSE units&#x27; increased power consuption.