Citations please. This is the second time I&#x27;m asking.<p>If there are bulletproof STM implementations, there should be some papers which back that up (preferably <i>not</i> academic toys). What throughtput and latency profiles did the STM implementations get, how did that scale with cores, what work profiles do they work well with, and how did all that compare with regular threads? How were livelock and side-effects handled? Was this put in production, and what shortcomings were there (there are <i>always</i> shortcomings)? Etc, etc, etc.<p>Also, reread my initial post more carefully. I qualified it at the very beginning with &quot;in the context of high performance applications”, and I qualified it again near the end; I didn’t simply agree with any sweeping claims. Yet here I am, getting lectured by someone who says that &quot;performance assertion showed he was full of crap&quot;... which I have demonstrated isn&#x27;t true.<p>Back your claims up; maybe I&#x27;ll learn something interesting.