In high level parallel programming, say for SIMD or GPU (which really is just a fancy name for a wide SIMD engine with a ton of hardware threads to hide memory latency and a 2D-oriented gather&#x2F;scatter memory controller), I wish there was a way to still expose the situation when your data is in reality shared by multiple &quot;cores&quot;, when they&#x27;re actually just different lanes in a same SIMD&#x2F;WARP&#x2F;whatever unit. Right now you just pretend they&#x27;re separate, even when they can&#x27;t even branch individually.<p>Example: Think about image processing algorithm, say 3x3 kernel. If you have 16-wide SIMD, using 3 registers, you only need special handling for the first and last pixels, only they cross the processing boundary. 14 pixels in the middle already have all of the data. If you can plan your memory accesses, you can do even better by shifting a pixel in from each new 16 pixel fetch.<p>Through abstraction you need to gather the 9 (3x3 kernel) center+neighboring values and run clamping for each neighbor access, even if you&#x27;re not at the boundary of the image data. Even when a good SIMD&#x2F;GPU compiler notices the data is already loaded, you still end up with needless saturation arithmetic (clamp) and most likely extra memory loads, potentially many times as many.<p>Sure, swizzling for locality of reference and a good cache controller help, but extra ALU work and memory accesses still mean sub-optimal performance.<p>This is where I&#x27;ve gotten good gains (up to 2-5x) when manually writing SIMD asm or intrinsics.<p>That&#x27;s a lot of performance to leave on the table, given that CPU and GPU performance hasn&#x27;t improved much in last 3 years.<p>This year we will get HBM1&#x2F;2 [1] + more ALUs to use up that bandwidth for GPUs.<p>Next year AVX-512 for x86 CPUs. I guess HBM comes to also CPUs in a few years.<p>My guess is after that next significant improvements come maybe 2020-2025, if the current performance improvement trend holds.<p>Next step is probably CPUs absorbing GPU duties. So far memory bandwidth has been an issue, but now you can stick HBM chips just as well in a CPU package as in a GPU package. Just need some lower clocked ultra-wide cores.<p>[1]: <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;High_Bandwidth_Memory" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;High_Bandwidth_Memory</a>