On a side note, it&#x27;s interesting to me that emerging memory technologies currently seem to be mainly focused on addressing the &quot;from-DRAM-to-disk&quot; part of the memory hierarchy.<p>That is, as you mentioned, not directly competing with DRAM, and consistently on the same side of the 1 microsecond dividing line between memory and storage; as in:<p><a href="http:&#x2F;&#x2F;www.rambusblog.com&#x2F;2015&#x2F;10&#x2F;15&#x2F;mid-when-memory-and-storage-converge&#x2F;" rel="nofollow">http:&#x2F;&#x2F;www.rambusblog.com&#x2F;2015&#x2F;10&#x2F;15&#x2F;mid-when-memory-and-sto...</a> (note SCM placed between DRAM and SSD)<p><a href="http:&#x2F;&#x2F;semiengineering.com&#x2F;the-memory-and-storage-hierarchy&#x2F;" rel="nofollow">http:&#x2F;&#x2F;semiengineering.com&#x2F;the-memory-and-storage-hierarchy&#x2F;</a><p>As far as the other side of the line is concerned, I think I&#x27;ve only seen proposals for hybrid-cache architectures (HCA) -- other than <a href="http:&#x2F;&#x2F;link.springer.com&#x2F;chapter&#x2F;10.1007%2F978-1-4419-9551-3_7" rel="nofollow">http:&#x2F;&#x2F;link.springer.com&#x2F;chapter&#x2F;10.1007%2F978-1-4419-9551-3...</a> -- with a hybrid approach (e.g., combining SRAM&#x2F;eDRAM&#x2F;STT-RAM&#x2F;PCRAM) probably making sense due to latency&#x2F;endurance&#x2F;bandwidth trade-offs.<p>If anything, there seems to be more development on the DRAM interface itself -- with multiple candidates for the (or a) DDR4&#x27;s successor, so far involving Wide I&#x2F;O (Samsung), Hybrid Memory Cube (Intel, Micron), High Bandwidth Memory (SK Hynix, AMD, Nvidia): <a href="http:&#x2F;&#x2F;www.extremetech.com&#x2F;computing&#x2F;197720-beyond-ddr4-understand-the-differences-between-wide-io-hbm-and-hybrid-memory-cube" rel="nofollow">http:&#x2F;&#x2F;www.extremetech.com&#x2F;computing&#x2F;197720-beyond-ddr4-unde...</a><p>(Latency and bandwidth improvements seem promising, <a href="http:&#x2F;&#x2F;semiengineering.com&#x2F;which-memory-type-should-you-use&#x2F;" rel="nofollow">http:&#x2F;&#x2F;semiengineering.com&#x2F;which-memory-type-should-you-use&#x2F;</a>)<p>One interesting development I&#x27;ve seen involves reducing SRAM&#x27;s footprint, by moving from 6T (6-transistors) cell to a 1T (one-transistor) one:
<a href="http:&#x2F;&#x2F;www.eetimes.com&#x2F;document.asp?doc_id=1328453" rel="nofollow">http:&#x2F;&#x2F;www.eetimes.com&#x2F;document.asp?doc_id=1328453</a><p>It&#x27;s fairly recent development, though, and it remains to be seen how is it going to fare.<p>Other than the above, there doesn&#x27;t really seem to be much progress around competing with&#x2F;improving SRAM. However, this may become increasingly important, since some of the technological process scaling issues apply to SRAM, too.