Market success != technical merit.  However, if you&#x27;re willing to consider ARM a RISC (well, almost) then there&#x27;s your market success.  Alpha completely <i>dominated</i> the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC.  At the time, x86 compatibility mattered more than it does today.<p>For people designing their own cores for whatever reason (there can be many, research and commercial), RISC-V is very attractive because of all the reasons already given, but it&#x27;s obviously not the only option.<p>RISC-V is carefully designed compromise; it scales down to extremely cheap cores and up to superscalar.  Like Alpha before it, extreme attention has been paid to avoid features&#x2F;choices that would be bad for OoOE implementations.  Some examples:<p>- rs1, rs2, rd fields are <i>always</i> in the same location and <i>all</i> register sources and destinations are explicit (makes decoding faster and you can start fetching&#x2F;renaming without having decoded)<p>- there are no branch delay slots<p>- instructions produce at most a single result<p>- no condition codes etc (dependencies are explicit)<p>- the sign-bit for all immediate fields is in a fixed location (cheaper sign-extension)<p>and so forth.<p>I&#x27;m also a big fan of the conditional branch instruction which unlike the Alpha can compare two registers.