There&#x27;s a chapter in the current RISC-V manual that explains how you <i>could</i> make a RISC-V-like VLIW ISA. But VLIW is most certainly NOT the &quot;future&quot;. VLIW demands an even &quot;mix&quot; of instruction types, and that&#x27;s largely incompatible with general-purpose application code.<p>And the concept of baking into your ISA what the designer believes is the &quot;perfect functional unit mix&quot; is an anti-pattern. What&#x27;s the perfect mix depends on the benchmark, and it changes from basic block to basic block. A history of failed VLIW projects can attest to this. A dynamic superscalar is far superior, even in power-efficiency.