I guess that&#x27;s because unlike AMD, nVidia doesn&#x27;t officially document the GPU instruction set. But if you disassemble .cubin with nvdisasm, you&#x27;d see that code of Kepler&#x2F;Maxwell is organized in bundles of 4&#x2F;8 words, where the first word doesn&#x27;t encode any instruction. Here is what Scott Gray of Nervana Systems, who developed a native assembler for Maxwell, write about it[1]: &quot;Starting with the Kepler architecture Nvidia has been moving some control logic off of the chip and into kernel instructions which are determined by the assembler. This makes sense since it cuts down on die space and power usage, plus the assembler has access to the whole program and can make more globally optimal decisions about things like scheduling and other control aspects. The op codes are already pretty densely packed so Nvidia added a new type of op which is a pure control code. On Kepler there is 1 control instruction for every 7 operational instructions. Maxwell added additional control capabilities and so has 1 control for every 3 instructions.&quot;<p>[1] <a href="https:&#x2F;&#x2F;github.com&#x2F;NervanaSystems&#x2F;maxas&#x2F;wiki&#x2F;Control-Codes" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;NervanaSystems&#x2F;maxas&#x2F;wiki&#x2F;Control-Codes</a>