<i>However, if you&#x27;re willing to consider ARM a RISC (well, almost) then there&#x27;s your market success.</i><p>ARM wasn&#x27;t really a pure RISC from the beginning (e.g. multicycle instructions like LDM&#x2F;STM, pre&#x2F;post-increment addressing modes, built-in shifts), and I&#x27;d say the market success, especially more recently, is attributable to the fact that ARM cores are becoming more x86-like.<p>On the other hand, MIPS is the quintessential RISC, and hit as enjoyed some success, but was never really known much for amazing performance or efficiency. I suspect RISC-V will be similar, and all the cheap Chinese tablets&#x2F;phones&#x2F;etc. that are currently using MIPS may switch to RISC-V instead, although many are unlicensed clones so cost may not be a factor to them.<p><i>Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC.</i><p>Alphas relied primarily on clock frequency to achieve their performance, and were very power-hungry as a result. This is absolutely the RISC philosophy of performance via simpler designs and increasing clock frequency, which stopped being viable long ago. A 200MHz 21064 can do 0.675DMIPS&#x2F;MHz and consumes 30W, or 0.0225DMIPS&#x2F;MHz&#x2F;W; a Pentium (P5) 100MHz has 1.88DMIPS&#x2F;MHz and consumes 10W, for 0.188DMIPS&#x2F;MHz&#x2F;W.