It&#x27;s a process called scan chain insertion. As a chip designer, I can tell you that DFT (Design for Test, which scan chain falls under) can be a real PITA even though the tools are automated.<p>EDIT: Should have also said that it really isn&#x27;t that big in terms of area... a register plus two wires is nothing in the scheme of things.<p><a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Scan_chain" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Scan_chain</a>