Uh, tape out doesn&#x27;t mean you&#x27;ve verified anything properly.<p>Looking at the various Intel bugs found, I can&#x27;t help sniggering a little. Verification mistakes happen all the time though. It&#x27;s just a matter of when the bugs are found: if found later, it has much greater impact.<p>On the 28nm issue, getting your design to synthesize to 28 nm depends on the architecture and your constraints. Trickier data paths make it harder to get it meeting timing. Where your IOs are placed, where your RAMs are placed and how much you have, each thing can make it harder and harder to synthesize. Adapteva doesn&#x27;t have much RAM I believe.