&quot;Waveform-based verification is something I know nothing about. I haven&#x27;t seen it in any paper I&#x27;ve looked at. Is that what people do in logic analyzers and such? Do you have a link to a free reference discussing what people do with that stuff and how it&#x27;s used to verify digital designs? I really should have this info in mind and on hand if you all rely on it more than verification tools.&quot;<p>Yeah, waveforms from a logic analyzer are mimicked by simulator tools.<p>Not sure about free references. Just googling around I found this about using logic analyzers : <a href="http:&#x2F;&#x2F;www.eetimes.com&#x2F;document.asp?doc_id=1274572" rel="nofollow">http:&#x2F;&#x2F;www.eetimes.com&#x2F;document.asp?doc_id=1274572</a><p>For example, page 3 shows a RAM timing diagram. Like any good spec, the interface from one module to another is defined via a timing diagram. We build our UVM checkers and monitors to detect these memory transactions based on the sequences specified. When a transaction occurs it triggers a UVM event which in turn can be observed by other monitors&#x2F;checkers or it can create other events or record the event to a log file etc.<p>We build our verification infrastructure to automatically check transactions behave as specified. However knowing I can&#x27;t trust my own work, I manually check the waveforms to see whether the infrastructure is performing correctly.<p>&quot;Let&#x27;s just say it&#x27;s easier to parallelize stuff if one doesn&#x27;t force their implementation to be inherently sequential or even tied to CPU&#x27;s.&quot;<p>Sounds interesting. I don&#x27;t know much about how it&#x27;s all implemented in the simulator.