I like that breakdown. That sounds about right. Especially the FPGA&#x27;s and military. :)<p>Btw, I&#x27;d love a hardware engineeer&#x27;s take on my idea for bootstrapping open hardware. The idea is HW development issues make it too costly. Led me to consider an open-source FPGA on 45nm or below with tool-chain. Let academics build (and open) the hardest stuff with non-profit integrating that with I&#x2F;O and other key I.P. onto small number of chips selling it at cost.<p>Example open FGPA (a start, not end-goal)
<a href="http:&#x2F;&#x2F;www.eecs.berkeley.edu&#x2F;Pubs&#x2F;TechRpts&#x2F;2014&#x2F;EECS-2014-43.pdf" rel="nofollow">http:&#x2F;&#x2F;www.eecs.berkeley.edu&#x2F;Pubs&#x2F;TechRpts&#x2F;2014&#x2F;EECS-2014-43...</a><p>Example open-flow (add VPR or whatever FPGA tool is called)
<a href="http:&#x2F;&#x2F;opencircuitdesign.com&#x2F;qflow&#x2F;" rel="nofollow">http:&#x2F;&#x2F;opencircuitdesign.com&#x2F;qflow&#x2F;</a><p>Idea is we get an easy FPGA set up to allow targeting with open or commercial tools. Its specs are open for review and enhancement. There is a via- or metal-configurable S-ASIC co-developed that matches its architecture. Like with eASIC, people can do an inexpensive conversion if they choose. Even considered using people they turned down in their contest (but whose stuff worked) to build the tooling for that. ;)<p>So, you have cheap-as-possible 45nm or below FPGA&#x27;s being cranked out with more I.P. and tooling all the time. S-ASIC conversion is inexpensive due to matched architecture. If designed for it in mind, ASIC conversion wouldn&#x27;t be too difficult either for FPGA-proven designs given staff and tooling. The HW cost is essentially some important cells, NOC, key IP (eg USB, PCI, DDR), memories, some analog, and at least one integration. With MPW&#x27;s &amp; academic support, it might cost a fraction of what it otherwise would. Not going to be EDA or HW competitive with Xilinx or Altera but not $600-$2,000 a chip w&#x2F; closed bitstream either.<p>My main worry outside market demand is effect of patent suits, esp if they demand royalties per unit. Otherwise, I&#x27;m hoping combo of academics, existing tooling, open FPGA&#x27;s, and S-ASIC&#x27;s is a solid combo for a start on widely-accessible, open HW. Still getting feedback from HW pro&#x27;s before I start knocking on doors, though.