Are you joking? Intel uses (even invented) so much verification tech it&#x27;s crazy. I&#x27;m talking more than any small vendor could hope to use as it would slow them down or take too much brains&#x2F;training. Any bugs they&#x27;re having are more likely due to size of their project or how custom the optimizations are. Here&#x27;s some Intel techniques they use for verification:<p><a href="https:&#x2F;&#x2F;www7.in.tum.de&#x2F;um&#x2F;25&#x2F;pdf&#x2F;LimorFix-2.pdf" rel="nofollow">https:&#x2F;&#x2F;www7.in.tum.de&#x2F;um&#x2F;25&#x2F;pdf&#x2F;LimorFix-2.pdf</a><p><a href="https:&#x2F;&#x2F;www.cl.cam.ac.uk&#x2F;~jrh13&#x2F;slides&#x2F;nasa-14apr10&#x2F;slides.pdf" rel="nofollow">https:&#x2F;&#x2F;www.cl.cam.ac.uk&#x2F;~jrh13&#x2F;slides&#x2F;nasa-14apr10&#x2F;slides.p...</a><p>IBM&#x27;s papers on their verification system for POWER processors mention all kinds of optimizations for things like pipelines that make the logic ridiculous. Then they jump through hoops in verification. Yet, they don&#x27;t hit 3+GHz on good pipeline without that. Undoubtedly, Intel&#x27;s using similar tricks with similar issues.<p>Regular ASIC verification doesn&#x27;t cut it at their level. What they&#x27;re doing is on another level. It&#x27;s hard to say what exactly we should expect in terms of errata level given their operating constraints (esp marketing). Only thing I expect is to know <i>clearly</i> the circumstances errata appears so I can avoid it. They let me down...