&quot;I think you trust tools more than you&#x27;re letting on. You probably just cross-check tools with tools in various ways like I did with high assurance SW to catch tool-specific issues. That implies a lot of, but not total, trust in the tools. If I&#x27;m wrong, I&#x27;ll be surprised and probably learn something in the process.&quot;<p>While it is true that we use tools to cross check each other, what I mean is that we regularly are manually looking through waveforms. At every stage of the flow, we are checking that our verification infrastructure is actually doing what it should to find bugs. Because a lot of the time, either we&#x27;ve stuffed up using the tool or the tool itself is stuffed.<p>So much tooling is provided for you. Bus functional models, protocol checkers, etc. You are just cramming it all together and writing your own stuff over the top. There is always a mistake in there somewhere.<p>&quot;Trick for HW might be turning all the tool outputs into a series of steps like in an audit log that such tools can verify.&quot;<p>This is what happens with the UVM. A checker is written with a SystemVerilog interface by a third party or ourselves. It uses the UVM standard so you can integrate it with other UVM stuff to make even more abstract checkers. If I am writing the prover, I know I probably threw a few bugs in there!<p>If only it were all parallelised because it is slow as hell.