Even more interesting with NUMA: imagine 10K slow&#x2F;cheap cores, each with their own non-shared bit of NVMe (~10MB would do) for their heaps to live on. Perfect for running Erlang.<p>There might not even be a point in a &quot;classical&quot; CPU cache hierarchy in such a system, if the NVMe is fast enough, and has its own &quot;internal&quot; writeback cache (e.g. some volatile battery-backed memory) protecting it, so that cycling a bit at 3GHz doesn&#x27;t burn it out. At that point you may as well say you have a CPU with ten million nonvolatile registers.