It&#x27;s also able to load microcode patches very early on in the machine bring-up process. Microcode can be anywhere as simple as a single hardware enable bit &quot;turn on this hardware unit&quot; or as complex as &quot;this instruction should be decoded as this sequence of microops.&quot;<p>It&#x27;s hard to know exactly what&#x27;s wrong without more internal, never-to-see-the-light-of-day Intel information, but it&#x27;s possible the patch is as simple as tweaking the decoding, or disabling an optimization. It&#x27;s doubtful a fix like this would require disabling an entire instruction set or hardware unit (like the TSX fix required; those are fairly rare bugs, even for Intel).<p>Specifically, given that it happens to be a bug that only happens with FMA3 <i>disabled</i> and hyperthreading enabled, it&#x27;s probably some kind of hardware scheduling deadlock, and the patch could be as simple as &quot;when the decoder sees this sequence of instructions, add some strategically placed NOPs to avoid the deadlock.&quot;