&quot;Are you joking? Intel uses (even invented) so much verification tech it&#x27;s crazy.&quot;<p>That&#x27;s kinda why I am sniggering. Intel has a rep for letting bugs go to silicon despite all that stuff. In terms of verification, they dropped the ball probably (unless they found these bugs in verification and decided to tape out anyway).<p>One area where they fell on their face seems to be AVX.
From TFA, &quot;Certain Combinations of AVX Instructions May Cause Unpredictable System Behavior&quot;. That&#x27;s a huge bug. Remember how we discussed the torture testing of floating point on the RISC-V ? Kinda similar issue. A customer wouldn&#x27;t be happy with a huge bug there.<p>The big 3 of EDA tools (Cadence, Synopsis, Mentor Graphics) provide their own tools for verifying this stuff called UVM. Like anything, it still relies on the person using the tool. It takes a lot of effort and planning to use this stuff.<p>Whenever the verification engineer has to create Verification IP to test the IP, there&#x27;s a chance they create bugs of their own. It&#x27;s like a golden rule.<p>That&#x27;s why I am not a fan of formal methods.
Nothing is proven until you have it working in silicon.