I spent severaal years of my life in the latter 70&#x27;s and early 80&#x27;s living and dreaming in Z80, for my work at MICOM using it for hard real time data communictions (specifically, Statistical Multiplexors). A critical component to achieving HRT is interrupt response time. Z80 has two complete sets of hardware registers and a one byte instruction to toggle which is active. So with the basic 2.5MHz clock time from raising the interrupt to execution of the first instruction of the handler was 2 usecs. With zero additional context saving to do. Add to that hardware vectored interrupts and it was golden - you landed directly in the handler for the specific peripheral. No need to poll status registers.<p>Not only way ahead of its time, this kind of performance feature is still apparently unknown. Even in GHz SOC systems and modern DSPs.  I&#x27;ve seen some really arcane and baroque interrupt status trees in my time since. All take significant code to parse and dispatch. One really egregious offender was the i960 CPU, sold specifically into the data communications market by Intel in the mid 90&#x27;s. Sold into a necessarily HRT application domain. Even at a 50 MHz clock it still took 6 - 10 usecs to get started doing actual work. I was very surprised, but the hardware choice at that time was not open to me and I had to live with it.