The answer to the second unasked question is, if cost were no barrier, then the lower bound for our current class of tech is almost certainly an effective feature size of ~1.5nm, or about 5 or 6 generations. When I&#x27;m feeling bullish (usually after talking to my boys at Intel) I feel confident we&#x27;ll <i>eventually</i> see 3nm. I suspect something more exotic will intercept by then, and carry after that in effective feature size reduction. Of course, by then, my hot-air-lifting-body-balloon unicorn will have realized, so I won&#x27;t care =)