GPU&#x27;s don&#x27;t do any OoO processing like modern CPU&#x27;s do. They also don&#x27;t do any register renaming. They execute things really literally, up to the point where one has to manually put delay slots for pipelined stuff if one really writes the raw asm (Which the manufacturers tend to keep really hidden, in order to avoid the binary compatibility trap, see <a href="https:&#x2F;&#x2F;github.com&#x2F;NervanaSystems&#x2F;maxas" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;NervanaSystems&#x2F;maxas</a> as an example for third party assembler for nvidia Maxwell arch)<p>On GPU&#x27;s the binary compatibility issue is solved by having the driver compile the shader&#x2F;compute kernel before it&#x27;s used. As an example nvidia uses PTX (see <a href="http:&#x2F;&#x2F;docs.nvidia.com&#x2F;cuda&#x2F;parallel-thread-execution&#x2F;" rel="nofollow">http:&#x2F;&#x2F;docs.nvidia.com&#x2F;cuda&#x2F;parallel-thread-execution&#x2F;</a>) as an intermediate language in CUDA which is then compiled by the runtime into the actual ASM.<p>On modern CPU&#x27;s the register renaming has already decoupled the physical registers from the instruction set register. As an example modern haswell has over 100 registers per core.