That&#x27;s because you might think designing hardware is as easy as coding software. There&#x27;s a world of difference. ;)<p>Decent intro to ASIC design with FPGA comparison and a pricing chart to illustrate the high costs:<p><a href="https:&#x2F;&#x2F;www.u-cursos.cl&#x2F;ingenieria&#x2F;2010&#x2F;2&#x2F;EL653&#x2F;1&#x2F;material_docente&#x2F;bajar?id_material=305352" rel="nofollow">https:&#x2F;&#x2F;www.u-cursos.cl&#x2F;ingenieria&#x2F;2010&#x2F;2&#x2F;EL653&#x2F;1&#x2F;material_d...</a><p>Note that the tooling that makes this possible, esp design synthesis, can run to $1+ million per user per year. Some are merely upper 5-digits to lower 6-digits. Really inexpensive. Mask costs have come down for older nodes in recent years because fab equpiment is finally paid off. Yet, you&#x27;re still talking millions for a full SOC with modern features. And it will be slow as hell because it&#x27;s on old stuff if it&#x27;s a CPU.<p>That the market demands more speed, more functions, less power, etc is why they keep dropping to smaller node sizes. Each one adds new effects that try to break the chip. The electrons even tend to leak out of the transistors. Can&#x27;t even assume they&#x27;ll stay in them haha. Actually, from what I&#x27;ve read, it appears chips are broken all over on latest nodes with lots of logic there just to correct that. Here&#x27;s an example of the crap they have to do at 28nm, which <i>isn&#x27;t</i> cutting-edge anymore:<p><a href="http:&#x2F;&#x2F;electronicdesign.com&#x2F;digital-ics&#x2F;understanding-28-nm-soc-design-arm-based-cores" rel="nofollow">http:&#x2F;&#x2F;electronicdesign.com&#x2F;digital-ics&#x2F;understanding-28-nm-...</a><p>So, you need specialists that make big $$$, $1+ million in EDA tools, mask costs at millions a set <i>per trial</i>, and other stuff like boards (regularly 6 digits on kickstarter). That&#x27;s for an ASIC. An FPGA&#x27;s design flow ends at the RTL simulation part, has no mask costs, free to cheap EDA, and often has pre-made boards you can use. Price you pay is lower-than-ASIC performance, higher watts, and very-high per unit price. Still a better deal on lots of systems plus can be converted to a hybrid later (see eASIC Nextreme).<p>Hope that clears up why one would choose a FPGA over an ASIC. All that said, the difficulties they&#x27;re facing in this case is largely due to choice to stay on Intel, Xen, and other difficult-to-secure crap. If one forgoes those software, then one can use Cobham-Gaisler&#x27;s SPARC SOC&#x27;s since they&#x27;re designed for easy modification &amp; already at quad-core. Academics made many secure CPU&#x27;s out of his stuff. Just gotta license it, modify it, and run it through later parts of ASIC flow. FPGA still cheaper, but you can FPGA it too. :)