<i>I&#x27;m still optimistic that FPGAs will gradually gather more software engineers into the fold</i><p>That would require a lot of retraining, at least that&#x27;s my personal experience. Before I wrote any Verilog, I had a software background. I wrote lots of code in asm and C. I also did hardware board design and ASIC design (using schematic capture).<p>The problem is that Verilog tempts people with software experience into using techniques they&#x27;re familiar with. E.g. some of my first Verilog looked like this (not proper syntax):<p><pre><code>   if condition-expression1
      do something block
   else if condition-expression2
      do something block
   else if condition-expression3
      do something block
   else
      do something block
</code></pre>
That&#x27;s easy to understand software, but it synthesizes into horrible hardware. The problem is that the sequential tests are, necessarily, synthesized into a priority encoder. Which means that the comparison chain becomes a critical timing path. There are lots of traps like that which await software people.<p>Good hardware design requires a lot more parallelism than what software engineers are typically used to.