With fixed width instruction sets there are similar tricks that trip up IDA&#x27;s style of analysis. For example, this MIPS code:<p><pre><code>        bal 1f
        nop
        .word DATA      &#x2F;* some data *&#x2F;
     1: lw REG, 0(ra)   &#x2F;* some destination register *&#x2F;
</code></pre>
Despite it being unreachable, it will attempt to disassemble the word after the branch&#x2F;nop rather than recognizing it as data.