You mainly use cache for two reasons: speed and latency.  Here, they eliminated the cache and used the die space for a really fast and wide bus to memory instead.  So speed (total throughput) is covered.  And from the article, it shows that the latency is actually better except within a narrow range of fetch sizes (~3000 to 8000 KiB).<p>I suspect the better latency at the high end is because you no longer have to work through the caching logic (which does little in such large transfers anyway).  And I guess their bet is that you&#x27;re not going to make many transfers that happen to fall into that window.  That seems like a good bet, my intuition is that there&#x27;s a &quot;bathtub&quot; style distribution here where accesses are either reasonably random (and thus don&#x27;t involve transferring more than ~3 MiB at a time) or they&#x27;re straight-through and involve very large sequential transfers (greater than 7 MiB).<p>Like the article notes, it seems to be an interesting decision.  They speculate that the L3 cache on the A9 was actually a decision made for reasons of power efficiency (it takes less power to hit cache than to hit memory) and that wasn&#x27;t a concern here, whereas they would have needed even more cache for the extra GPU cores, and die size was getting to be a concern.  But they also note that the L3 cache didn&#x27;t consume much space anyway, which is the weird thing to me.