The complete lack of an L3 cache is fascinating if true. Not being an expert on chip design, I had thought the &quot;number of cache levels&quot; trend was monotonically increasing, especially since some of Intel&#x27;s latest chips now have L4 caches, but now this. Can someone explain how they can get away with this? Is it enough to just have a really fast and wide bus, did they possibly need to make changes on the OS level, or is it just more acceptable on a device where you&#x27;ll only be running one or two applications and very few background daemons&#x2F;services?