This is what the datasheet says [1]:<p><pre><code>    - Instruction Cache = 32kB, per core
    - Data Cache = 32kB, per core
    - 256kB Mid-Level cache, per core
    - 8MB shared among cores (up to 4)
</code></pre>
So I guess the confusion is that Intel moved the L2 cache onto each core (from Nehalem onwards,  I think?) and used that opportunity to substantially lower latency for it.<p>[1] <a href="http:&#x2F;&#x2F;www.intel.com&#x2F;content&#x2F;www&#x2F;us&#x2F;en&#x2F;processors&#x2F;xeon&#x2F;xeon-5500-vol-1-datasheet.html" rel="nofollow">http:&#x2F;&#x2F;www.intel.com&#x2F;content&#x2F;www&#x2F;us&#x2F;en&#x2F;processors&#x2F;xeon&#x2F;xeon-...</a>