The article had this to say:<p>&quot;<i>One explanation may be that Apple deemed the L3 cache no longer necessary with the A9X’s 128-bit LPDDR4 memory bus; that 51.2GB&#x2F;sec of bandwidth meant that they no longer needed the cache to avoid GPU stalls.</i>&quot;<p>And:<p>&quot;<i>Our own Andrei Frumusanu suspects that it may be a power matter, and that Apple was using the L3 cache to save on power-expensive memory operations on the A9. With A9X however, it’s a tablet SoC that doesn’t face the same power restrictions, and as a result doesn’t need a power-saving cache. This would be coupled with the fact that with double the GPU cores, there would be a lot more pressure on just a 4MB cache versus the pressure created by A9, which in turn may drive the need for a larger cache and ultimately an even larger die size.</i>&quot;<p>So, basically, while the A9&#x27;s 4 MiB L3 cache wouldn&#x27;t have been much to add to the A9X, it wouldn&#x27;t have helped much and a larger, more costly L3 cache would have been needed to help the A9X performance-wise. As the article points out, this is all speculation.