The argument is this: to an (admittedly over-simplified) approximation an ASIC and an FGPA have the same gates, it&#x27;s just the interconnects that are different.  The lower the power and space efficiency of the interconnect, the larger the incentive is to put ASIC-style interconnected gates into little islands in the FPGA fabric - hence the various complex tiles like MACs that you mention.<p>When nonvolatile nanoscale memory becomes more widespread (the demand driven by SSDs, but FPGAs get to benefit), the additional interconnect power costs get close to zero, and when things get so small that nanowires are much smaller than the smallest gate, the space requirements start being negligable as well.<p>At that point there&#x27;s no real advantage to having those complex tiles, because the equivalent configured FPGA circuit is just as efficient, so you might as well take advantage of the flexiblity of a completely uniform fabric.<p>The point of view taken in the paper I linked above is that even LUTs are an uneccessary optimization at that point.<p>I&#x27;m not saying all of this is an inevitability - but it&#x27;s my bet.