I proposed doing it differently by investing billions in I.P. development for standardized interfaces and constructions at every half of the process node. As in, most of the work is already done with process shrinks easy too. On top of that, platform ASIC&#x27;s or S-ASIC&#x27;s with mapping to FPGA&#x27;s. Anyone that used the fabs would get the I.P. free or dirt cheap with that used to make more. All the stuff that isn&#x27;t a competitive advantage is gratis.<p>The other one that would kick ass is heavy investment into EDA tooling. China itself may or may not need it with the rampant piracy. However, driving the prices of EDA synthesis, verification, etc tools down to four to five digits might make the market really interesting. Especially with lots of reference I.P. and flows. That plus inexpensive, maskless prototyping like eASIC does.<p>Someone might steal my idea with me posting it all over the place but I don&#x27;t have the capital to pull it off. So, steal away and get me EDA that&#x27;s as cheap as Windows. :)