I would guess even less than 24. Today you can write your structural Verilog implementation, run an automatic mapping to a PDK standard cell library, and simulate to verify. The hardest part might be floor planning for something like that today. The placement and routing can all be automagical, and you won&#x27;t have any timing closure issues at these speeds. I&#x27;d guess a single student could do it if sufficiently motivated. And, with CMP or MOSIS you could have it manufactured on a 350nm CMOS process by AMS for $2200 (20-25 pcs).