Good write-up as well. I remember there were two things in the past that excited the heck out of me wrt FPGA&#x27;s. The first were papers in the late 90&#x27;s or so showing semi-automatic partitioning of an application between a CPU and a FPGA w&#x2F; HLS for the FPGA. Their results were pretty cool. I envisioned something like that would be great for the day the FPGA was practically sitting right on the CPU.<p>The other thing came from my old, favorite, supercomputing vendor: SGI. They used to blow my mind repeatedly with how they did hardware. On the Altix NUMA systems, they had an option called RASC nodes that basically added 2 FPGA&#x27;s plus QDR RAM to the system. Like everything else, the FPGA&#x27;s attached to the <i>shared memory bus</i> to operate on whole memory directly with microseconds latency and several GB&#x2F;s bandwidth. Not sure if modern FPGA&#x27;s are sitting on the memory bus inexpensively but RASC&#x27;s performance&#x2F;integration showed it&#x27;s a great idea.<p>So, those were my two fun points on the subject. The next will probably be if I land a Pico Computing desktop w&#x2F; some high-end FPGA&#x27;s or if Archipelago gets closer to mature FPGA architecture. Either have much potential. :)