I am an EE. I have designed fully-synthesized ASICs in Verilog for money. If you ignore the simulation constructs of Verilog (which you should, if you&#x27;re designing something to be synthesizable), Verilog is a purely declarative reactive language, and a damn good one at that. (Verilog, BTW, has stratified programming-in-the-large constructs.)<p>You can&#x27;t synthesize &quot;functional programs&quot;; there&#x27;s no analogue of recursion in hardware. You can only synthesize things that happen to look like functional programs because they&#x27;re written using sexprs and macros and expand out to a static circuit graph which is exactly what Verilog is.