I have not published the language yet, have to produce some nice looking examples first. But you can take a look at my approach to extensibility in general (the HDL language is using exactly the same thing) and some of the earlier mixing Verilog with C experiments here: <a href="https:&#x2F;&#x2F;github.com&#x2F;combinatorylogic" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;combinatorylogic</a>