EDIT to add examples for your professional curiosity:<p><a href="http:&#x2F;&#x2F;scheme2006.cs.uchicago.edu&#x2F;05-saint-mleux.pdf" rel="nofollow">http:&#x2F;&#x2F;scheme2006.cs.uchicago.edu&#x2F;05-saint-mleux.pdf</a><p><a href="http:&#x2F;&#x2F;citeseerx.ist.psu.edu&#x2F;viewdoc&#x2F;download;jsessionid=E5380DBA3DE7B118B018A7CAAEF0ACBD?doi=10.1.1.57.736&amp;rep=rep1&amp;type=pdf" rel="nofollow">http:&#x2F;&#x2F;citeseerx.ist.psu.edu&#x2F;viewdoc&#x2F;download;jsessionid=E53...</a><p>Note: DDD scheme also supported call&#x2F;cc. :P It wasn&#x27;t in the final circuit, though, except as an execution feature.<p>&quot;You can only synthesize things that happen to look like functional programs because they&#x27;re written using sexprs and macros and expand out to a static circuit graph which is exactly what Verilog is.&quot;<p>Oh, come on, that&#x27;s kind of cheating as you could say the same about almost any level of abstraction. You might as well say you can&#x27;t synthesize the Verilog constructs: you just synthesize something that looks like it into a connection of analog transistors that it actually is. Yet, if you can use that model and it works, then it&#x27;s a meaningful thing to say you can synthesize&#x2F;use such a model to get X done with Y benefits instead of hand-stitching cell libraries and gates. Likewise, the more functional (or other) alternatives to Verilog with their advantages so long as they deliver on them in the field.<p>For my examples, SHard is a research prototype that works on some, limited examples. DDD was used on numerous real-world projects while the spin-off was still in business. Gone now. Bluespec is still kicking ass in industry. So, Bluespec at the least proves out the concept and its advantages over Verilog.