.. while keeping in mind that for some workloads GC is a large chunk of the app&#x27;s work. For example, 10 Xeon cores worth of GC throughput (out of say 24) would be a pretty tall order for a FPGA, and as a fixed resource it easily becomes an Amdahl&#x27;s law bottleneck.<p>It would be a cool thing to try still, and maybe doable with COTS hw:
<a href="https:&#x2F;&#x2F;www-ssl.intel.com&#x2F;content&#x2F;www&#x2F;us&#x2F;en&#x2F;embedded&#x2F;technology&#x2F;quickassist&#x2F;documentation.html" rel="nofollow">https:&#x2F;&#x2F;www-ssl.intel.com&#x2F;content&#x2F;www&#x2F;us&#x2F;en&#x2F;embedded&#x2F;technol...</a> + <a href="http:&#x2F;&#x2F;www.hotchips.org&#x2F;wp-content&#x2F;uploads&#x2F;hc_archives&#x2F;hc21&#x2F;3_tues&#x2F;HC21.25.500.ComputingAccelerators-Epub&#x2F;HC21.25.532.Cantle-Nallatech-Xeon-Socket-FPGA.pdf" rel="nofollow">http:&#x2F;&#x2F;www.hotchips.org&#x2F;wp-content&#x2F;uploads&#x2F;hc_archives&#x2F;hc21&#x2F;...</a>