The most interesting to me is that Intel apparently stopped publishing transistor counts starting with the 14nm node.<p>This is significant because as structure sizes become smaller, the restrictions on possible layouts (so called DRCs, design rule constraints) become ever stricter. For example, you can&#x27;t just place wires wherever you want; you have to take into account the relationship to other wires. With stricter rules, the end result <i>may</i> be that the effective scaling achieved is worse than what the structure size suggests, because the rules force a lower density of transitors.<p>So what are Intel hiding? Are they far ahead of the competition in terms of DRCs and don&#x27;t want others to know how much, or are they struggling (like apparently everybody else) and want to hide a less-than-ideal effective scaling? Obviously, your guess is as good as mine, but it&#x27;s certainly fascinating to watch the competition as Moore&#x27;s law is coming to an end.