&gt; You say to Oracle, Yeah T3 SPARC64 RISC chips look nice. But coding against non-symetric asychronous cores is hard.<p>But… the T3 is symmetric? And not from the 90s, it was launched in 2010?<p>&gt; Intel, Nvidia, AMD (formerly ATI) solved this problem a long time ago just by putting the binary logic between the scalar processors and only exposing 1 scheduler to pipeline these smaller weaker cores but make them pretend to be a single processor to the OS&#x2F;User.<p>That&#x27;s the original use case for big.LITTLE actually, either cluster-switching between the low-power (A7&#x2F;A53) cluster and the high-power (A15&#x2F;A57) cluster, or presenting groups of low power and high-power cores (1&#x2F;1, 2&#x2F;1) as a single virtual core.