It is targeted to ARM uC&#x27;s and also works on AVRs with enough RAM and program space (yes I&#x27;ve tested it). Write support requires a significant amount of RAM; I think about six 512-byte blocks. When compiled in read-only mode, it should need no more than two.<p>One reason for the RAM needs is that I use a block cache and I take care do to &quot;atomically&quot; certain related operations (on the block cache level). These are things like marking a cluster as allocated, decrementing the number of free clusters in FsInfo, and linking the allocated cluster to the end of a chain. These things require multiple blocks to all be present in the block cache at the same time.<p>I suppose the asynchronous design also contributes to the code and RAM size (though I did not actually measure the code size or compare it to other drivers). It may look like more that it really compiles to. Anyway would be very surprised if you show me another asynchronous driver - I couldn&#x27;t find any!<p>Also consider that my code supports VFATs (decoding only, file creation is not supported anyway).<p>The design is intentional, I have sacrificed some RAM&#x2F;program size for asynchronous operation and better reliability in case of random write failures (because of the block cache, all writes can reliably be retried later, avoiding corruption as long as they eventually complete).<p>Update: I estimate the code compiles to about 10kB with gcc for Coretex-M3 using -Os. This is certainly within limits of most ARM uCs and many AVRs.