We&#x27;re at a crossroads in CPU design. The hardware guys implement heuristics to make ordinary code work &quot;pretty good&quot;, with cache lines and multiple layered caches and register calculus and stalling pipelines.<p>Then compiler folks reverse-engineer all that to get &quot;really good&quot; performance. But they can&#x27;t make one code for every model of CPU because this stuff changes with each release.<p>How about, CPU leaves these decisions up to the compiler? Flatten and simplify, and make (allow) compiler writers to know exactly what&#x27;s going on, and even control it!