1. I expect, if we use standard OS, that a modification might be needed where the FPGA will know the real address. The FPGA might be given enough info to figure it out with DMA or it might be something like a custom, syscall that gives FPGA details.<p>2. Barriers are one method. They&#x27;re among the most expensive. An IBM prototype used careful lock management (supported by lock registers) and scheduling to avoid barriers. There&#x27;s actually quite a few ways in the literature to avoid barriers in concurrency. I figure a team would have to leverage them plus asynchronous I&#x2F;O from CPU to FPGA for optimal performance. I see it as a series of hand-offs to FPGA which, once it has necessary information, acts on those hand-offs with CPU assuming it completed after certain time, seeing a part of memory saying so, or receiving an interrupt.<p>That&#x27;s a rough sketch.