E.g. the Mill architecture, which has no register-collision issues at all. At the cost of the compiler keeping track of the address of results as they pass through the mill.<p>And hardware doesn&#x27;t do it well at all, at least not in the super-optimization cases discussed in the OP. They&#x27;re working hard to reverse-engineer around the hardware; which is at least as hard as the compiler programming caches and pipelines explicitely.