Memory bus is just for speed. You don&#x27;t want it doing stuff like that lol. See these two LISP machines for where my inspiration of putting it on memory bus came from:<p><a href="http:&#x2F;&#x2F;diyhpl.us&#x2F;~bryan&#x2F;papers2&#x2F;paperbot&#x2F;Design%20of%20a%20LISP-based%20microprocessor.pdf" rel="nofollow">http:&#x2F;&#x2F;diyhpl.us&#x2F;~bryan&#x2F;papers2&#x2F;paperbot&#x2F;Design%20of%20a%20L...</a><p>(See section 7 for a radical... err realy old... way to do concurrent GC. Full paper available at ACM&#x2F;IEEE or if you Google LISP processors Guy Steele enough.)<p>Scheme machine by Burger 1995<p><a href="http:&#x2F;&#x2F;citeseerx.ist.psu.edu&#x2F;viewdoc&#x2F;download;jsessionid=569B0A6FC0F670004BB323ADB5D75C9E?doi=10.1.1.73.590&amp;rep=rep1&amp;type=pdf" rel="nofollow">http:&#x2F;&#x2F;citeseerx.ist.psu.edu&#x2F;viewdoc&#x2F;download;jsessionid=569...</a><p>(See the main graphic and specifics in storage section later. Once again, GC-like stuff is handled in memory management part of the processor. This processor knows that, though, to assist GC a bit. Also different in that it was specified and then synthesized to heterogenous hardware with DDD &quot;correct-by-construction&quot; toolkit.)<p>So, have fun with those. Plus, Google hardware-assisted or hardware garbage collection to get lots of interesting results already done.