Verilog which is loosely based on C also blindly followed this trend, but created a big mess.<p>In Verilog you can say:<p><pre><code>    module foo(a);
    parameter width = 20;
    input [width-1:0] a;
</code></pre>
But &quot;ANSI&quot; Verilog is &quot;improved&quot;:<p><pre><code>    module foo(input [19:0] a);
</code></pre>
Oops.. no place to put the parameter.. so later on they amended:<p><pre><code>    module #(parameter width=20) foo(input [width-1:0] a);
</code></pre>
They should have just removed the argument list:<p><pre><code>    module foo;
    input a;
</code></pre>
This would have worked for C as well:<p><pre><code>    int foo()
    int a, b, c;
    {</code></pre>