&quot; You know that the VHDL code for UltraSPARC T1 and T2 has been open sourced?&quot;<p>That was exciting. It could do well even on a 200MHz FPGA given threading performance. Then, use eASIC&#x27;s Nextreme&#x27;s to convert it to structured ASIC for better speed, power-usage, and security from dynamic attacks on FPGA. That it&#x27;s Oracle and they&#x27;re sue-happy concerns me. I&#x27;d read that &quot;GPL&quot; license very carefully just in case they tweaked it. If it&#x27;s safe, then drop one of those badboys (yes, the T2) on the best node we can afford with key I&#x2F;O. Can use microcontrollers on the board for the rest as they&#x27;re dirt cheap. Same model as Raptor&#x27;s as I explained in another comment.<p>Alternatively, use Gaisler as Leon3 is GPL and designed for customization. Simple, too. Leon4 is probably inexpensive compared to ARM, etc.<p>&quot;SPARC ISA compliant processor only costs $50, the SPARC will never really, truly be gone, especially not for those people capable of synthesizing their own FPGA&#x27;s,&quot;<p>Yep.<p>&quot;Too bad they didn&#x27;t turn their designs into ready-to-buy servers.&quot;<p>Not quite a server but available and illustrates your point:<p><a href="http:&#x2F;&#x2F;www.gaisler.com&#x2F;index.php&#x2F;products&#x2F;systems&#x2F;gr-rasta?task=view&amp;id=280" rel="nofollow">http:&#x2F;&#x2F;www.gaisler.com&#x2F;index.php&#x2F;products&#x2F;systems&#x2F;gr-rasta?t...</a><p>Btw, I found this accidentally while looking for a production version of OpenSPARC:<p><a href="http:&#x2F;&#x2F;palms.ee.princeton.edu&#x2F;node&#x2F;381" rel="nofollow">http:&#x2F;&#x2F;palms.ee.princeton.edu&#x2F;node&#x2F;381</a>