Do you strive for continuous improvement? Would you like to work at the pulse of technology? As a Senior Engineer in Physical Verification Development, you can bring our physical verification to the next level. You will join a dynamic environment with various internal interfaces and directly contribute to our products’ challenging physical verification tasks. Apply now to join our Global team and work in an exciting, multinational environment. In your new role you will: · Develop physical verification and parasitic extraction methods in cooperation with technology experts · Handle complex electrical circuits requirements · Support the PDK team to develop automated checks for electrical, ESD and reliability verification, including parasitic extraction · Ensure high quality standards · Collaborate closely with the reliability competence center, align with physical implementation teams, and support the design departments as well as the Infineon physical verification community with your expert-knowledge · Analyze existing and new CAD software solutions in cooperation with the design flow development team · Provide specification documents and trainings as part of the design flow and methodology development · Lead and implement Calibre DRC, ERC, LVS and PERC Physical Verification runsets for our in-house wafer technologies Your Profile You are dedicated to quality and efficiency and have the passion to develop new, innovative ideas. As a team player, you quickly establish successful cooperation, appreciate the contribution of others, and support your colleagues proactively. You are best equipped for this task if you have: · A degree in Electrical Engineering, Physics or a related discipline · Ideally 1-3 years of relevant professional experience in one of these following fields: Physics, Electronics, ESD and reliability verification area, including development of verification methodologies for electronic circuits · You bring an advantage, if you have experience in the following areas: parasitic extraction, voltage dependent design rules, electrical and ESD design verification · Interest in industry standard CAD tools/flows for IC designs such as Cadence Virtuoso, Cadence Quantus, Siemens Calibre tool suite and Synopsys ICV · An understanding of semiconductor device physics · 1-3 years of relevant experience in programming and scripting languages Calibre PERC, TCL, Python, SKILL · Good communications skills in English, German language is not mandatory but beneficial
Senior Engineer Physical Verification Methodology (f/m/div)* (Ingenieur/in - Elektrotechnik)