Summary Posted: 1. Jun 2023 Role Number:200482957 Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no what you could accomplish. Multifaceted, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the outstanding and exciting opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Join us! You will be taking part in the Physical Design team as a backend focal point for timing analysis and convergence, working in sophisticated technologies and interacting closely both with RTL designers, Physical Designers and other top level integration teams. Key Qualifications - Detailed knowledge of the ASIC design timing closure flow and methodology. - Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others. - Hands on experience in timing/SDC constraints generation and management - Proficient in scripting languages (TCL and Perl) - Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools - Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired. - Strong background in Constraint analysis and debug, using industry standard tools as well as backend STA closure. - Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing. - Familiar with ECO techniques and implementation. - Experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow. - Familiarity with hierarchical design approach, top-down design, timing and physical convergence. - Good communication and interaction with Front End teams and Physical Design teams. - Ability to fluently speak and write in English Description Responsibilities include especially, but are not limited to: - Work with Physical Design team, highlighting issues and best practices. - Help build timing ECO’s for project tapeout. - Build/maintain scripts and methodologies for analysis and runs. You will be responsible for constraints and timing checkups development, including their delivery for synthesis, PnR and signoff STA. Working in parallel on blocks and chip level STA modes. Education & Experience Bachelors's or Master's Degree in a technical field is required.
Experienced SoC Physical Design STA / Timing Engineer (m/w/d) (Ingenieur/in - Elektrotechnik)Experienced SoC Physical Design STA / Timing Engineer (m/w/d) (Ingenieur/in - Elektrotechnik)