ENGINEERING PROJECT MANAGER Summary Eleven years experience Analog, RF Mixed Signal Layout Design module Chip levels 180nm, 65nm, 45nm, 28nm TSMC, 14FF Samsung foundry 10nm Intel. Experienced planning, tracking executing tasks meet desired deadlines. Skills Aware Analog Layout fundamentals like Device matching, shielding, Isolation, ESD, Latchup, Antenna, EM, DFM Physical verification layout using tools like K2Ver, Hercules, Caliber, Assura Used auto routers tools like ICCT, Chip Assembly router, Aprisa, VSR various blocks reduce manual effort Used post layout parasitic extraction tools Used Nucleus (TI internal tool ESD Latchup), SPIRE (TI internal tool EMIR analysis), Voltrace (TI internal tool High voltage checks Used data management tools like Synchronicity IC manage Relevant Experience Current Company: Aricent Inc. Client: Intel USA I currently trained Genesys tool 10nm Intel flow. I working blocks like LDO begin with. Client: Qualcomm Pvt Ltd India WTR-RX/TX SYNTH 14FF (Samsung foundry) Duration project 6 months I managed team 6 worked WTR synth project done 14FF Samsung foundry. This one challenging tasks career, first RF task I worked FF technologies. To overcome challenges I undergone various FinFet related trainings understand process impact layout. Experience Engineering Project Manager 12/2012 06/2017 Company Name I used Gantt chart schedule tasks individual. I also used XL sheet track progress issues micro level. These sheets certainly helped us plan next project much better. WTR-RX/TX SYNTH 28nm (TSMC) Duration project 6 months I lead team 4 supported project done Qualcomm USA. My role project regular discussion US designers understand requirements, later communicate requirements team also track deliverables. I also handled portion TOP level layout tasks. I worked blocks like HFVCO, Regulator, VCO Buffer LPF project. I used Gantt chart schedule tasks individual. I also used XL sheet track progress issues micro level. WTR QLNA Daisy Chain 180nm (TSMC) Duration project 0.5 months For particular project I regular discussions Packaging team create best Daisy Chain structures WLP CHIP I work previously. I also went entire process Tape Out CHIP included uploaded Tapeout related files database reviewing eJV sent FAB. WTR QLNA Metal Variants Tapeout 180nm (TSMC) Duration project 0.5 months We needed metal variants QLNA chip I previously worked on. In design leave scope meal options used study certain features better testing. Here I worked creating four chips different metal variant options. I also went entire process Tape Out CHIP included uploaded Tapeout related files database reviewing eJV sent FAB. WTR QLNA 180nm (TSMC) Duration project 5 months This first project 180nm TSMC process. In project I mentored one junior team worked MBIAS block I worked creating LNA. WTR RX BBF 28nm (TSMC/UMC) Duration project 4 months I lead team 4 supported project done Qualcomm USA. My role project regular discussion US designers understand requirements, later communicate requirements team also track deliverables using Gantt chart XL sheet. I worked top level sub-blocks BBF project. WTR FBRX 28nm (TSMC) Duration project 4 months This task working FBRX module previously done. There issues seen blocks performance post silicon verifications. My role task identify IQ imbalance caused performance issues fix them. I able meet designers requirements task much appreciated task done. WTR Low Band Low Noise Amplifier 28nm (TSMC) Duration project 3 months This Low Band LNA operates 860 900 Mhz frequencies. Here layout constraints like coupling, inductance symmetry taken care layout. Majorly input devices RF_IN signal given extra care w.r.t coupling symmetry. WTR Mixer, Attenuator 28nm (TSMC) Duration project 10 months This first project I worked RF domain I wonderful experience working project. The blocks I worked project product chip hence amount learning tremendous project. The blocks ready time good quality. Senior Analog Layout Engineer 10/2011 12/2012 Company Name Member Technical Staff 06/2006 09/2011 Company Name Education Training Bachelor Engineering Electrical Electronics 2006 Visvesvaraya Technological University － City India Electrical Electronics Skills Cadence, Data management, database, debugging, features, IQ, layout, layout design, LINUX, meetings, mentor, Windows, migration, next, Operating Systems, Packaging, progress, project management, quality, Real Time, Router, Routers, Sun-Solaris