CWE Code: 362
Vulnerability Type: privilege_escalation
CVSS Score: 7.2
CWE Name:  Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
Summary: a statement in the system programming guide of the intel 64 and ia-32 architectures software developer's manual (sdm) was mishandled in the development of some or all operating-system kernels, resulting in unexpected behavior for #db exceptions that are deferred by mov ss or pop ss, as demonstrated by (for example) privilege escalation in windows, macos, some xen configurations, or freebsd, or a linux kernel crash. the mov to ss and pop ss instructions inhibit interrupts (including nmis), data breakpoints, and single step trap exceptions until the instruction boundary following the next instruction (sdm vol. 3a; section 6.8.3). (the inhibited data breakpoints are those on memory accessed by the mov to ss or pop to ss instruction itself.) note that debug exceptions are not inhibited by the interrupt enable (eflags.if) system flag (sdm vol. 3a; section 2.3). if the instruction following the mov to ss or pop to ss instruction is an instruction like syscall, sysenter, int 3, etc. that transfers control to the operating system at cpl < 3, the debug exception is delivered after the transfer to cpl < 3 is complete. os kernels may not expect this order of events and may therefore experience unexpected behavior when it occurs.
Access Authentication: NONE
Access Complexity: LOW
Access Vector: LOCAL
Impact (C/I/A): COMPLETE/COMPLETE/COMPLETE
Published Date: 2018-05-08
Last Modified Date: 2019-10-03
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system
Please provide details about this vulnerability:  Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition').
user
CWE Code: 362
Vulnerability Type: privilege_escalation
CVSS Score: 7.2
CWE Name:  Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
Summary: a statement in the system programming guide of the intel 64 and ia-32 architectures software developer's manual (sdm) was mishandled in the development of some or all operating-system kernels, resulting in unexpected behavior for #db exceptions that are deferred by mov ss or pop ss, as demonstrated by (for example) privilege escalation in windows, macos, some xen configurations, or freebsd, or a linux kernel crash. the mov to ss and pop ss instructions inhibit interrupts (including nmis), data breakpoints, and single step trap exceptions until the instruction boundary following the next instruction (sdm vol. 3a; section 6.8.3). (the inhibited data breakpoints are those on memory accessed by the mov to ss or pop to ss instruction itself.) note that debug exceptions are not inhibited by the interrupt enable (eflags.if) system flag (sdm vol. 3a; section 2.3). if the instruction following the mov to ss or pop to ss instruction is an instruction like syscall, sysenter, int 3, etc. that transfers control to the operating system at cpl < 3, the debug exception is delivered after the transfer to cpl < 3 is complete. os kernels may not expect this order of events and may therefore experience unexpected behavior when it occurs.
Access Authentication: NONE
Access Complexity: LOW
Access Vector: LOCAL
Impact (C/I/A): COMPLETE/COMPLETE/COMPLETE
Published Date: 2018-05-08
Last Modified Date: 2019-10-03
assistant