In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, "properties re-use" and "properties refinement", are described and compared in terms of refinement effort and simulation speed delay
['Nicola Bombieri', 'Andrea Fedeli', 'Franco Fummi']
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling