In this paper, we propose a parameterized crypto co-processor based on Advanced Encryption Standard (AES). This parameterized AES module is combined with a 32-bit general purpose 5-stage pipelined MIPS processor. The AES module used in this paper is fully pipelined. The processor fetches an instruction from the instruction memory and sends it to the decode stage. If the instruction is the crypto instruction it is pushed into the AES module during the decode stage. However if the instruction belongs to the MIPS processor, the remaining cycles will be completed on the MIPS processor. The parameterized AES module has different latencies on different rounds of AES according to the application requirements. The effects of different number of rounds on latency, memory, and area are studied and reported.
['Hassan Anwar', 'Masoud Daneshtalab', 'Masoumeh Ebrahimi', 'Juha Plosila', 'Hannu Tenhunen', 'Sergei Dytckov', 'Giovanni Beltrame']
Parameterized AES-Based Crypto Processor for FPGAs