In this work, the implementation of the PRESENT-80 block cipher in a 40nm CMOS technology, and its vulnerability to Side Channel Attacks Exploiting Static Power is investigated. In the last two decades, several countermeasures to thwart DPA/CPA attacks based on the exploitation of dynamic power consumption have been proposed. In particular, WDDL logic style is a gate-level countermeasure, to Power Analysis Attacks exploiting dynamic Power. It has been demonstrated that, in deep sub-micron technologies, the static power consumption is no more negligible as in the past and malicious attackers can benefit from the dependability of the static power consumption on the processed data: Leakage Power Analysis (LPA) has been proposed to recover sensible information. The possibility to recover the secret key from a protected secure implementation exploiting static power is not a minor threat, and we analyze this vulnerability with actual security metrics and with an information theoretic approach, showing that gate level countermeasures such as WDDL can be successfully attacked exploiting static power instead of dynamic power.
['Davide Bellizia', 'Giuseppe Scotti', 'Alessandro Trifiletti']
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power