High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As multiprocessor systems become necessary to satisfy the computational requirements, interconnection network design will become subject to similar constraints. This paper focuses on the design of multiprocessor interconnection networks under power constraints. We analyze and study the relationship between the no-load message latency and system parameters such as network dimension, channel width, distance, and available power to determine guidelines for multiprocessor interconnection network designs. This study is an extension and application of the model developed in [8], and provides a number of interesting results: i) we have observed that under a fixed power constraint, the network dimension which achieves minimal latency is a slowly growing function of system size, ii) as we increase the available power per node for a fixed system size, the dimension at which message latency is minimized increases, iii) the overall message latency is very sensitive to the distribution of power between driving inter-router channels and switching data through the intra-router datapaths. The paper concludes with a summary of trade-offs predicted by the model and proposals for validating the model.
['Chirag S. Patel', 'Sek M. Chai', 'Sudhakar Yalamanchili', 'David E. Schimmel']
Power/performance trade-offs for direct networks