This paper proposed an approximate adder to accelerate computation and reduce energy consumption for error-resilient applications with a moderate output quality losses. The computation acceleration comes from the predictionscheme for the adder circuit, where the critical path is divided into multiple short fragments and a paralleling addition progress is enabled. The energy consumption is reduced as the result of trimming the registers from the lower predictors of the design. Furthermore, a simple module for error compensation is inserted into the approximate part of the circuit to decrease the relative error with very little hardware cost. Being simulated with 65nm CMOS process, 2.82X speedups and 57.8% energy-efficiency improvements have been achieved compared with traditional adders. Compared with the currenthigh performance approximate adders, the proposed addershows 6.9% energy-savings with 2 orders of reduction inrelative error using random test data. At last, the proposedapproximate adder is adopted in DCT processing, where more than 10dB PSNR increase can be achieved, compared with the current counterpart designs.
['Xinghua Yang', 'Yue Xing', 'Fei Qiao', 'Qi Wei', 'Huazhong Yang']
Approximate Adder with Hybrid Prediction and Error Compensation Technique