During the early design phases of software development, many developers use floating point data types and libraries but often convert these applications into fixed point representations in later design phases - a time consuming process often requiring significant designer effort. While various approaches have been proposed to automate the floating to fixed point conversion process, these approaches are mainly targeted at creating optimized software implementations and do not directly support partitioning floating point implementation to hardware. We present an approach to optimize the number of bits required for a dynamically adaptable fixed-point representation using SNR analysis methods targeting computationally intensive floating-point kernels. We present a hardware/software partitioning methodology that leverages this SNR analysis to partition application kernels to custom hardware coprocessors implemented within a field-programmable gate array. Using several case study applications, we highlight the performance benefits and area requirements of the resulting hardware implementations.
['Varadaraj Kamath Nileshwar', 'Roman L. Lysecky']
SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation