With small device features in sub-micron technologies, interconnection delays play a dominant part in cycle time. Therefore, it is important to consider the impact of physical design during high level synthesis. In this paper, an efficient floorplanning algorithm which takes into account the effect of interconnect delays on the overall cycle time of a given schedule is presented. A simultaneous scheduling, binding and floorplanning algorithm is also presented. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower latency and area. In addition, a detailed model is considered, taking into account multiplexer and register areas and delays.
['Pradeep Prabhakaran', 'Prithviraj Banerjee']
Simultaneous scheduling, binding and floorplanning in high-level synthesis