In this paper, a novel CAD-based approach is presented for defect tolerance of QCA circuits. This approach is based on using QCA tiles and provides defect tolerance at circuit level with, in most cases, no area overhead. A ranking methodology is introduced to determine the tile configurations and logic functions that are optimal for logic synthesis of QCA circuits. Simulations on benchmark circuits show that the proposed methodology provides significant improvements in defect tolerance compared with QCA gate-based designs.
['Vamsi Vankamamidi', 'Fabrizio Lombardi']
Design of defect tolerant tile-based QCA circuits