As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPGAs CAD flow to mitigate leakage power dissipation through the use of multi-threshold CMOS technologies to pack and place logic blocks that exhibit similar idleness close to each other so they can be turned off during their idle time. The modifications are integrated into the VPR flow and tested on several FPGA benchmarks using a CMOS 0.13/spl mu/m dual-V/sub th/ technology, resulting in an average leakage power savings of at least 20%.
['Hassan Hassan', 'Mohab Anis', 'Mohamed I. Elmasry']
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs