The quality of placement and routing on gate arrays is commonly measured by  average wire length.  With regard to wire length, placement and routing are mutually competing tasks and the solution space for both is exponential. Estimates of measures of placement such as average wire length or, total wiring tracks prior to routing give some indication of the routability of the placement and, can be used to select another placement and repeat.   The nature of these problems necessitates a probabilistic approach to the wirability analysis of integrated circuits. Stochastic models for wiring space estimation and the relation between wire length distribution and placement optimization have received attention recently [1], [6], [2], [5], [7], [3] and [4]. Much of the reported work on wire length distributions and placement of logic rests on empirical evidence that indicates that “well placed” chips exhibit Rent's Rule between the number of components and the number of corresponding external connections. Rent's Rule has been the basis of the heuristic arguments used to derive upper bounds on the average wire length and the form of the wire length distribution. Rent's Rule has the form   T e KC  p  (1)   where T is the average number of external connections, C is the average number of components, K is number of connections per component and p is a positive constant. In [1], [2] and [4] the effect of placement on wire length distribution was introduced by assuming that a hierarchical partitioning scheme aimed at minimizing the average wire length results in a configuration that exhibits Rent's Rule. In [2] an upper bound r
['Sarma Sastry', 'Alice C. Parker']
On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICs