We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1∶1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <−65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.
['Vishnu Ravinuthula', 'William J. Bright', 'Mark Weaver', 'Kenneth George Maclean', 'Scott Kaylor', 'Sidharth Balasubramanian', 'Jesse Coulon', 'Robert Keller', 'Bao Nguyen', 'Ebenezer Dwobeng']
A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz