Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework achieves this by: (1) providing a means for choosing suitable custom instruction selection heuristics, (2) leveraging FPGA-aware merging of custom instructions to maximize the reconfigurable logic block utilization in each configuration, and (3) incorporating a hierarchical loop partitioning strategy to reduce runtime reconfiguration overhead. We show that the performance gain can be improved by employing suitable custom instruction selection heuristics that, in turn, depend on the reconfigurable resource constraints and the merging factor (extent to which the selected custom instructions can be merged). The hierarchical loop partitioning strategy leads to an average performance gain of over 31p and 46p for full and partial runtime reconfiguration, respectively. Performance gain can be further increased to over 52p and 70p for full and partial runtime reconfiguration, respectively, by exploiting FPGA-aware merging of custom instructions.
['Siew Kei Lam', 'Christopher T. Clarke', 'Thambipillai Srikanthan']
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration