In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/pFinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the layout area of the eDRAM cells (>10%).
['Esteve Amat', 'Antonio Calomarde', 'Francesc Moll', 'Ramon Canal', 'Antonio Rubio']
Feasibility of Embedded DRAM Cells on FinFET Technology