In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.
['V. R. Devanathan']
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage