This poster presents Very-Low-Voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin-film (a-Si TFT) transistor technology as an economic alternative to burn-in. A total number of 140 CUT implemented in 8µm a-Si TFT technology are tested at nominal voltage and very-low-voltage. The results indicate that VLV testing is effective in screening out unreliable a-Si TFT circuits.
['Shiue-Tsung Shen', 'Wei-Hsiao Liu', 'James Chien-Mo Li', 'I-Chun Cheng']
Very-Low-Voltage testing of amorphous silicon TFT circuits