In this paper we describe the architecture of MTASC, a multithreaded associative SIMD processor, and a cycle-accurate instruction set simulator for that architecture. We show, through simulations of a set of five associative benchmarks, that this architecture is capable of significantly improving the performance of associative code over a single-threaded architecture, especially for processors with a large number of PEs. Furthermore, we show that the amount of improvement in performance is highly dependent on the frequency of reduction instructions in the code being executed.
['Kevin Schaffer', 'Robert A. Walker']
MTASC: A Multithreaded Associative SIMD Processor