The exponential increase in leakage, the device parameter variations, and the aggressive power management techniques will severely impact IC testing methods. Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. In this article, we explore test considerations for scaled CMOS circuits in the nanometer regime and describe possible solutions to many of these challenges, including statistical timing and delay test, I/sub DDQ/ test under exponentially increasing leakage, and power or thermal management architectures.
['Kaushik Roy', 'T. M. Mak', 'Kwang-Ting Cheng']
Test consideration for nanometer-scale CMOS circuits