The main goal of this paper is to study the delay evolution for future technology nodes (32 nm and beyond) using electrical circuit predictive simulations. With this aim, two SPICE predictive models, directly based on ITRS data, are developed for devices and for interconnect respectively. The predictive spice models generation is presented and validated versus 45 nm silicon data. The predictive delay evaluation is performed with buffered interconnect lines simulations. The simulation results show that the critical interconnect length should be in the order of 10 mum for the 2020 generation. Moreover, in forthcoming technologies, driver resizing and systematic buffer insertion will no longer be sufficient to systematically limit wire delay increase.
['Manuel Sellier', 'Jean Michel Portal', 'B. Borot', 'Steve Colquhoun', 'Richard Ferrant', 'F. Boeuf', 'A. Farcy']
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework