This paper presents a technique to enhance the throughput of the Binary Search Analog to Digital Converter (BSADC) without increasing the analog circuits complexity. The presented technique is able to increase the output throughput to Fsample using a new sample and hold combination. The number of comparators is decreased using a reference prediction technique. We present a proof of concept 5-bit ADC, using only six passive Track- and-Hold circuits (T-H), 9 comparators, reference ladder, switches and digital gates. This ADC consumes 1.3mW from a 0.8 V supply at 1GS/s, the effective number of bits (ENOB) is 5-bits, the achieved figure of merit (FOM) is 50fJ/conversion-step.
['Ahmed Badawy', 'Emad Hegazi']
A low voltage low power and high speed binary search analog to digital converter