This paper describes a robust scan pattern mismatch debugger for the scan pattern validation process. Simulation mismatches observed during scan pattern validation process need to be resolved before scan pattern can be used in silicon. In this framework, we use efficient structural cone to create VCD values from a timing-based simulator. The VCD values are then used to trace the mismatches from failing observation points to the mismatch sources. Root-cause analysis is then performed by combining all mismatch source instances to conclude the most likely mismatch reasons. Comparing to existing solutions, the proposed mismatch debug flow doesnpsilat require VCD values of all signals in the designs, nor does it require multiple simulation of the test patterns in the Verilog simulator. Experimental results show the effectiveness and efficiency of the proposed scan pattern mismatch debug flow.
['Kun-Han Tsai', 'Ruifeng Guo', 'Wu-Tung Cheng']
A Robust Automated Scan Pattern Mismatch Debugger