We investigated the dynamic nature of a highspeed CMOS comparator, and present a comparator frequency-response model based on small-signal linear analysis of a latch. The analytical frequency model offers good insight into the linearity of the quantizer utilized in CTDeltaSigma modulators. In addition, a novel design guideline for a high-speed CMOS comparator to ensure the quantizer linearity is presented.
['Shunsuke Okura', 'Tetsuro Ohkura', 'Kenji Taniguchi', 'Hajime Shibata']
Frequency Response Analysis of Latch Utilized in High-Speed Comparator