Design and simulation results of CMOS winner-take-all circuit are presented. A 16-cell test circuit has been designed for intended implementation in 0.18 /spl mu/m CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances. The WTA is a very versatile network. The circuit has the potential to exhibit multiple winners under certain circumstances. This study investigates the dynamics of a WTA network's behaviour which lead to multiple winner selection.
['Ganesh Kothapalli']
Excitation modes and transient response of a winner-take-all circuit