a Abstract: Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below.
['M. R. Karthikeyan', 'S. K. Nandy']
An asynchronous architecture for digital signal processors