High Level Synthesis (HLS) is a promising technology where algorithms described in high level languages are automatically transformed into a hardware design. Although many HLS tools exist, they are mainly targeting developers who want to use a high level programming language to design hardwaremodules. They are not designed to automatically compile a complete software system, such as a network packet processing application, into a hardware design.#R##N##R##N#In this paper, we describe a compiler toolchain that automatically transforms existing software in a limited domain to a functional hardware design. We have selected the Click Modular Router as the input system, and the Stanford NetFPGA as the target hardware platform. Our toolchain uses LLVM to transform Click C++ code into a form suitable for hardware implementation and then uses AHIR, a high level synthesis toolchain, to produce a VHDL netlist.#R##N##R##N#The resulting netlist has been verified with actual hardware on the NetFPGA platform. The resulting hardware can achieve 20-50% of the performance compared to version handwritten in Verilog. We expect that improvements on the toolchain could provide better performance, but for the first prototype the results are good. We feel that one of the biggest contribution of this work is that it shows some new principles of high-level synthesis that could also be applied to different domains, source languages and targets.
['Teemu Rinta-aho', 'Mika Karlstedt', 'Madhav P. Desai']
The Click2NetFPGA toolchain