We propose an adaptive WWL pulse width and voltage modulation architecture for low voltage bit-interleaved 8T SRAMs. The 8T bitcell offers improved read/write margins but suffers from write and half select concerns when bit-interleaved [1]. Also, low voltage operation leads to a long-tailed write time distribution, requiring large timing margins and limiting V min . To minimize timing margins and reduce V min , both WWL pulse width and voltage level are adaptively modulated by monitoring written values through the read path. In a 65nm CMOS prototype chip, V min  is lowered from 700mV to 500mV using this technique, providing 2.55× leakage power reduction and 2.4× active power reduction.
['Daeyeon Kim', 'Vikas Chandra', 'Robert C. Aitken', 'David Blaauw', 'Dennis Sylvester']
An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs