In this paper, for the first time, we analyze non-quasi-static (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM4 and look-up table (LUT) simulations. We know that even for DSM transistors and circuits, the quasi-static approximation is valid for most digital applications. However, a single-event particle strike in a memory cell is capable of causing NQS effects which can result in erroneous logic-state prediction. The anomalous effect is attributed to the fast-varying transient (produced during particle-strike), which is able to initiate NQS effects in the transistors of the memory cell. Thus, it becomes important for a circuit designer to incorporate NQS effects during SEU simulation.
['Palkesh Jain', 'D.V. Kumar', 'J. Vasi', 'M.B. Patil']
Evaluation of non-quasi-static effects during SEU in deep-submicron MOS devices and circuits