The intent of the recent H.264/AVC standard is to provide high quality video at low bit-rates and work effectively on a wide variety of networks and systems. A promising application is video broadcasting on mobile terminals butin practice, increased processing power and power management are required for embedded systems. In this paper, we consider an embedded multiprocessor to answer these requirements. This platform is the ARM11 MPCore, including up to four processors to bring enough processing power with dynamic voltage and frequency scaling techniques (DVFS). We present here the parallelisation and implementation analysis of a H.264 decoder using symmetric multiprocessing. We detail the performance and power consumption of the decoder in different conditions of voltage and frequency in a way to derive information for the exploitation of DVFS techniques in multiprocessor architectures.
['Sébastien Bilavarn', 'Cécile Belleudy', 'Michel Auguin', 'Thibault Dupont', 'Anne-Marie Fouilliart']
Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations