The lack of electronic design automation tools for system-on-chip (SOC) test integration increases SOC development time and cost, so SOC test integration tools are important in the success of promoting SOC. We have stressed practical SOC test integration issues, including real problems found in test scheduling, test input/output (I/O) reduction, timing of functional test, scan I/O sharing, etc. In this paper, we further consider the requirement of integrating at-speed testing of embedded cores - to detect timing-related defects, our test architecture is equipped with at-speed test capability. Test scheduling is done based on our test architecture and test access mechanism, considering I/O resource constraints. Detailed scheduling further reduces the overall test time of the system chip. All these techniques are integrated into an automatic flow to facilitate SOC test integration. The test integration platform has been applied to both academic and industrial SOC cases. The chips have been designed and fabricated. The measurement results justify the approach - simple and efficient, i.e., short test integration cost, short test time, and small hardware and pin overhead.
['Chili-Yen Lo', 'Chen-Hsing Wang', 'Kuo-Liang Cheng', 'Jing-Reng Huang', 'Chili-Wea Wang', 'Shin-Moe Wang', 'Cheng-Wen Wu']
STEAC: A Platform for Automatic SOC Test Integration