The front-end sample-hold amplifier of a CMOS analog-digital converter can be made subranging, resulting in decreased output swing, by combining it with a residue amplifier function and directly quantizing the input. A control-loop minimizes the sampling instant mismatch by adjusting the timing to the coarse quantizer's clock input using the sign of the input signal's first order derivative. The process operates completely in the background with no specialized input signal for calibration.
['Gerry Quilligan', 'D. P. Burton']
A high-speed subranging system with background equalization of the sampling instants