In this work, the authors aim to improve the power efficiency of FPGAs by proposing two power reduction techniques: the authors present a low-penalty optimization technique to reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT utilization across different designs (Mondal and Memik, (2005)), and presents a dual-V dd -dual-V t  routing architecture to reduce interconnect power consumption by using two levels of V dd  and V t  (Mondal and Memik, (2005))
['Somsubhra Mondal', 'Seda Ogrenci Memik']
Power Optimization Techniques for SRAM-Based FPGAs