In this article, we analyze the impact of within-die thermal gradients on clock skew, considering temperature's effect on active devices and the interconnect system. This effect, along with the fact that the test-induced thermal map can differ from the normal-mode thermal map, motivates the need for a careful consideration of the impact of temperature gradients on delay during test. After our analysis, we propose a dual-V DD  clocking strategy that reduces temperature-related clock skew effects during test. Clock network design is a critical task in developing high-performance circuits because circuit performance and functionality depend directly on this subsystem's performance. When distributing the clock signal over the chip, clock edges might reach various circuit registers at different times. The difference in clock arrival time between the first and last registers receiving the signal is called clock skew. With tens of millions of transistors integrated on the chip, distributing the clock signal with near-zero skew introduces important constraints in the clock distribution network's physical implementation and affects overall circuit power and area
['S. Bota', 'José Luis Rosselló', 'C. de Benito', 'Ali Keshavarzi', 'Jaume Segura']
Impact of Thermal Gradients on Clock Skew and Testing