Double Patterning Lithography (DPL) is currently being used as part of Resolution Enhancement Technique (RET) in 45nm and 32nm technologies. DPL involves partitioning a layout into two masks to reduce interference from neighboring patterns and improve resolution. Triple pattern lithography has also been suggested as a way to continue scaling with trailing lithography technology. However, due to complexity involved with dense layouts, sometimes a polygon in a layout needs to be split into two masks, placing additional demand on precision of overlay control. These are known as stitches that may adversely impact manufacturing yield. Most of the previous layout decompositions for DPL are primarily based on using geometric rules such as minimum distance criteria. Such approaches neglect the positive effects that polygons in a mask may have on one another and may introduce unnecessary stitches. In this paper, we propose a model based layout decomposition technique that uses simulated annealing (SA) for mask assignment. The model based approach uses a fast lithography simulator to compute Edge Placement Error (EPE) which is then used as a metric for mask assignment. SA based mask assignment allows a greater solution space to be explored. We present results comparing SA based approach against greedy solution. It is shown that SA based approach converges to better quality solutions with nearly 20X reduction in runtime on average. The study reports the number of moves, stitches, EPE and runtime to illustrate the qualitative improvements offered by this solution.
['Rance Rodrigues', 'Sandip Kundu']
Model based double patterning lithography (DPL) and simulated annealing (SA)