Video coding techniques which are characterized by huge computational burden extensively consume power. Motion estimation with block matching criterion utilizing sum of absolute differences (SAD) with variable block size is the main source for such complexity and huge power consumption. In this work, we introduce a modified matching criterion in bit-level that lowers the computational complexity and hardware implementation when compared with the many SAD implementations introduced in the literature. We show that the number of hardware resources illustrated by the number of logic gates that are used in our design is much less than the number of the gates that are used in the traditional SAD and others in the literature. This leads in turn to a reduction in hardware complexity and consumed power. These are achieved by making our design rely on reusing the partial SAD values of smaller sub-blocks and then providing them to the compare and select unit as early as they are ready. Moreover, the final 41 motion vectors of motion estimation overlap in time and hence lower the number of output buses of the hardware implementation which results in a reduction in complexity as well. The video quality is only reduced by 0.17 dB while the bit-rate is increased only by 0.58 % in our simplified hardware architecture. The system logic synthesis is performed using the widely used FPGA platform. It produces 6.2 k LUT with a maximum operating frequency of 293 MHz (180 fps@CIF).
['Esam A. AlQaralleh', 'Osama M. F. Abu-Sharkh']
Low-complexity motion estimation design using modified XOR function