A 1.2 V 12 b 30 MS/s pipelined ADC, implemented in a 65 nm standard CMOS technology, achieves an SNDR of 65.1 dB with a rail-to-rail 4.7 MHz input. A capacitive reference scaling technique is proposed to alleviate the high gain requirement of the opamp and a wide input range of 2.4 Vp-p differential for low voltage operation in the nanometer domain. The prototype ADC dissipates 18 mW and occupies an active die area of 0.34 mm 2 . The measured DNL and INL are plusmn 0.44 LSB and plusmn1.33 LSB, respectively.
['Kang-Jin Lee', 'Kyoung-Jun Moon', 'Kwang-Sung Ma', 'Kyoung-Ho Moon', 'Jae-Whui Kim']
A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling