Although modeling of memory caches for the purpose of cache design and process scheduling has advanced considerably, the effects of cache sharing are still not captured by common approaches to modeling of software performance. One of the obstacles is lack of information about the relationship between cache misses, which the cache models usually describe, and the timing penalties, which the performance models require. Following earlier work that has shown how cache misses do not quite account for timing penalties, we report on extensive experiments that investigate the connection between cache sharing and observed performance in more depth on a real computer architecture.
['Vlastimil Babka', 'Lukáš Marek', 'Petr Tuma']
When Misses Differ: Investigating Impact of Cache Misses on Observed Performance