The 100-gigabit Ethernet (100GbE) was standardized as IEEE 802.3ba in 2010 [1]. The optics module must be equipped with a “gearbox” LSI-which switches between 10×10Gb/s data signals on the physical-coding-sublayer side and 4×25Gb/s data signals on the physical-media-dependent side. A gearbox LSI based on 0.13 μm SiGe BiCMOS consumes 8W of power [2], which is about half of the total power consumption of the optics module. Aiming to reduce the power consumption, a 50Gb/s 2:5 DEMUX based on CMOS technology is developed [3]. In addition, since the architecture in reference [2] consists of two LSIs (MUX and DEMUX), loop-back operation, which is required in the IEEE standard, is impossible. In response to these circumstances, we have developed a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI — implemented in 65nm CMOS — decreases power dissipation by 75% compared to that of a conventional LSI.
['Goichi Ono', 'Keiki Watanabe', 'Takashi Muto', 'Hiroki Yamashita', 'Koji Fukuda', 'Noboru Masuda', 'Ryo Nemoto', 'Eiichi Suzuki', 'Takashi Takemoto', 'Fumio Yuki', 'Masayoshi Yagyu', 'Hidehiro Toyoda', 'Masashi Kono', 'Akihiro Kambe', 'Seiichi Umai', 'Tatsuya Saito', 'Shinji Nishimura']
A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link