This paper discusses some specific circuit, and analog DFT techniques and methodologies used in integrated power management (PM) systems to overcome challenges of mixed-signal SoC qualification. They are mainly targeted at achieving the following: 1. Enabling the robust digital and system level test and burn-in (BI) with external supplies by disabling the on-chip PM with robust power-on performance, 2. Minimising external on-board active components in BI board and making the whole BI process more robust, 3. Making the I DDQ  tests more robust, increasing the I DDQ  sensitivity by less error prone design methods and enabling I DDQ  tests possible on analog supplies, and 4. Defining separate BI strategy for the whole PM modules on-chip and enabling it by targeted analog test modes.
['Lakshmanan Balasubramanian', 'Puneet Sabbarwal', 'Rajesh Mittal', 'Prakash Narayanan', 'Ranjit Kumar Dash', 'Anand Devendra Kudari', 'Srikanth Manian', 'Sudhir Polarouthu', 'Harikrishna Parthasarathy', 'Ravi Vijayaraghavan', 'Sachin Turkewadikar']
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system