In this brief, hysteresis is introduced to improve the noise margin of positive-feedback source-coupled logic (PFSCL) gates, that are a modification of MOS current-mode logic recently proposed by the same authors. To better understand the effect of hysteresis on the performance and the design of these circuits, a simple analytical model of the noise margin is developed. Extensive simulations on a 0.18-mum CMOS process confirm the adequate accuracy of the model. The noise margin improvement due to the hysteresis is then exploited to reduce the logic swing, which can be beneficial in terms of the speed performance or the power consumption. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Simulations confirm that, in some well-defined cases, hysteresis can significantly reduce the gate delay under a power constraint, or achieve a power saving under a speed constraint. As a fundamental result, hysteresis turns out to be an interesting design option to improve the power efficiency of PFSCL gates
['Massimo Alioto', 'Luca Pancioni', 'Santina Rocchi', 'Valerio Vignoli']
Exploiting Hysteresys in MCML Circuits