An "asynchronous unit delay" is an n-input n-output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of input n-tuple prior to the last input change. In this paper it is shown that such a circuit can be used as a basic building block in the design of any asynchronous circuit. It is shown that any fundamental mode flow table is realizable by a circuit of feedback index m with one asynchronous unit delay, m inertial delays, and a combinational network, where m is the smallest integer ≥ {log2 max (Si)} and Si is the number of stable states in any input column of the table. A straightforward method of realizing "asynchronous indefinite" fundamental mode tables without critical races by circuits of feedback index 1 with k asynchronous unit delays, one inertial delay, and combinational gates is also suggested. The approach suggested in this paper avoids complicated secondary assignment problems, results in circuits with simple structure, and further, brings closer the theories of synchronous and asynchronous sequential circuits.
['Shanker Singh']
Asynchronous Sequential Circuits with Feedback