A hardware/software co-processing system for speech recognition applications is proposed in this paper. The system consists of a soft-core microprocessor and a dedicated hardware accelerator implemented on an FPGA. This system is intended to be used in embedded devices. By offloading computation-intensive parts of the speech recognition system to the hardware accelerator, both faster recognition speed and lower power consumption are achieved without degrading recognition accuracy. The design is described in Verilog HDL and synthesized on a Xilinx Virtex-5 FPGA. Tests show that the proposed system runs 2.18 times faster than a pure software system.
['Tao Chen', 'Jiawei Zheng', 'Xingsi Zhang', 'Shengchang Cai', 'Yun Chen']
A hardware accelerator for speech recognition applications