The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems. However, the clock skew constrains the improvement of clock frequencies and affects the reliability of systems. One skew reduction technique is the use of clock deskew circuits. They can be classified into two methods: delay-locked loop (DLL) deskewing and synchronous mirror delay (SMD) deskewing. The DLL deskewing achieves a fine accuracy, but suffers from slow locking. Reversely, the adjustment of the SMD deskewing is fast, but suffers from a poor accuracy. In this paper, a low-power full-digital hybrid clock deskew circuit is presented. It uses a SMD as coarse delay line and a digital-DLL as a fine delay line. The SPICE simulation shows that the proposed clock deskew circuit achieves fine accuracy , fast locking, and low power.
['Rong Ji', 'Liang Chen', 'Gang Luo', 'Xianjun Zeng', 'Junfeng Zhang', 'Yingjie Feng']
A Novel Low-Power Clock Skew Compensation Circuit