This paper presents a second-order ΔΣ analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 µW. Its area is 640 µm 2 .
['Toshihiro Konishi', 'Hyeokjong Lee', 'Shintaro Izumi', 'Masahiko Yoshimoto', 'Hiroshi Kawaguchi']
A 40-nm 640-µm 2 45-dB opampless all-digital second-order MASH ΔΣ ADC