In this paper we present the collaborative routing architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay performance for a FPGA. This is done by enabling routing resource sharing between different types: (1) long interconnects can be constructed with short bypass interconnects without sacrificing delay performance. (2) switch boxes and connection boxes both are embedded in the switching core of the routing modules. Therefore routing resources such as MUXs can be shared between them on a per-mapping basis. (3) the switching core in CRA can dynamically extend its switching capability, whereas in a conventional switch box, switch matrix is predetermined and therefore static. These architectural features demonstrate significant performance improvements. Using the same logic placement, the CRA yields about 25% reduction in the minimum routing channel width, 20% improvement in overall delay performance for 20 largest MCNC benchmark circuits, when compared with a Virtex-II style baseline FPGA.
['Y. Ma', 'Mingjie Lin']
Collaborative Routing Architecture for FPGA