Hardware cache prefetching has a profound impact on the memory access pattern of ciphers which are exploited in profiled cache-timing attacks. In this paper, we formally demonstrate that memory access patterns influenced by sequential prefetching and its variant, known as even-odd prefetcher has varying information leakage dependent on the alignment of the underlying tables used in the cipher implementation. This demonstrates that a suitable architecture choice for the hardware prefetcher combined with appropriate memory alignment in software can lead to prefetching architectures which are leakage resilient.
['Sarani Bhattacharya', 'Chester Rebeiro', 'Debdeep Mukhopadhyay']
A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks