We propose a method for computing maximal sets of symmetric inputs in logic circuits, using a test generation procedure for single stuck-at faults. The method is enhanced by a heuristic that can be used to identify nonsymmetric inputs and thus reduce the number of inputs for which test generation has to be carried out. We show the relevance of the problem to input matching for design diagnosis and for technology mapping. Experimental results demonstrate the effectiveness of the proposed procedures. >
['Irith Pomeranz', 'Sudhakar M. Reddy']
On determining symmetries in inputs of logic circuits