A heterogenous processor architecture for video coding applications based on hybrid coding schemes is proposed. To support high computational power and architectural flexibility, the processor consists of function oriented and programmable modules. The key components of the architecture are a RISC core which performs control tasks and module synchronisation, a programmable module for tasks like DCT, quantization and filtering and a function oriented blockmatching module for motion estimation. Applying a 0.6 micron CMOS process, a single chip video codec for CIF-30 Hz video signals can be implemented. For higher video source rates several processors can be combined to a multiprocessor system. >
['Winfried Gehrke', 'Richard Hoffer', 'Peter Pirsch']
A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications