This paper proposes a new architecture for memory-based floating-point numeric function generators (NFGs). The design method uses piecewise-split edge-valued multi-valued decision diagrams (EVMDDs). To design NFGs with less memory size, we partition the domain of the floating-point function into segments, and represent the function using an EVMDD for each segment. By realizing each EVMDD with hardware, we obtain the floating-point NFG. This paper also presents an algorithm that partitions the domain by decomposing the edge-valued binary decision diagram(EVBDD) representing the whole floating-point function. Experimental results show that, for a single-precision floating-point function, our new NFG requires 40% to 65% less memory than any previous one. An advantage of our algorithm is that it can be applied to many different functions.
['Shinobu Nagayama', 'T. Sasao', 'Jon T. Butler']
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs