The emerging H.264 SVC (Scalable Video Coding) standard specifies an encoder solution responsible for generating a multi-layer stream, which provides extra flexibility for modern multimedia applications. The increased data dependency among different layers demands a significant overall encoder performance. Aiming the use of an SVC solution in real-time applications we propose an optimized hardware implementation of the computational forward two-dimensional discrete cosine transform module. The proposed solution introduces a fast pipelined architecture specially designed to explore hardware parallelism and to surmount memory access delays, processing efficiently up to eight pixel samples in a clock cycle. Practical results confirm the proposal as a high efficient solution able to speedup SVC encoder performance with reduced impacts in complexity.
['Ronaldo Husemann', 'Mariano Majolo', 'Valter Roesler', 'José Valdeni de Lima', 'Altamiro Amadeu Susin']
Highly efficient forward two-dimensional DCT module architecture for H.264/SVC