A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction-bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.
['Dong-Shong Liang', 'Kwang-Jow Gan', 'Jenq-Jong Lu', 'Cheng-Chi Tai', 'Cher-Shiung Tsai', 'Geng-Huang Lan', 'Yaw-Hwang Chen']
Multiple-Valued Memory Design by Standard BiCMOS Technique