The design of embedded subthreshold SRAMs for a quality-scalable H.264 video decoder IP is presented in this paper. In addition to the conventional 7T SRAM bitcell, we adopted power-gating techniques and multi-output dynamic circuits in order to achieve a low VDD min , a small area overhead, and a higher operating speed. A 256 × 32 90-nm SRAM macro was designed for verifying the proposed design techniques. The H.264 IP provides energy-efficient scalable video decoding of 42.8 pJ/cycle for QCIF and 235 pJ/cycle for HD720 at 0.3 V and 0.7 V, respectively.
['Jinn-Shyan Wang', 'Pei-Yao Chang', 'Tai-Shin Tang', 'Jia-Wei Chen', 'Jiun-In Guo']
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications