Clock buffer and wire sizing are intertwined problems that also greatly impact power consumption and skew in clock trees. Due to their complexity, they are often solved separately, leading to suboptimal solutions. In this brief, we propose a new formulation for cooptimization of buffer and wire sizes for high-performance clock trees. Using the proposed cooptimization of buffer and wire sizes, we are able to minimize a combination of   both    power and skew. The variation-aware experiments show that, by applying the proposed formulation, power and skew for all tested clock trees are improved. On average, we achieve a reduction of 57% in power and 50 ps in skew. We also show that our solutions are Pareto optimal where power and skew cannot be further reduced simultaneously and they provide a balanced tradeoff between power and skew.
['Amin Farshidi', 'Laleh Behjat', 'Logan M. Rakai', 'David T. Westwick']
A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees