This paper presents recent results on the MP1 router chip designed to implement scalable parallel computers. We survey design considerations used in order to reduce message delivery latency to a minimum. Results will be presented of simulations of the MP1 network which back up these considerations. It will be shown that there are many degrees of freedom in implementation and that implementation issues will often overwhelm other considerations, those on which simulation is focused, leading to anomalous predictions from those results. An example will be given on this. Even ultra-low latency networks will still have access times to remote data which are 10 to 100 times that for access to local data and architectures which tolerate low latency data-access must be exploited if scalable performance is to be obtained in these parallel machines based on networks.
['Chris R. Jesshope']
LATENCY REDUCTION IN VLSI ROUTERS