Cascadable, CMOS synapse chips containing a cross-bar array of 32×32 (1024) programmable synapses have been fabricated as "building blocks" for fully parallel implementation of neural networks. The synapses are based on a hybrid digital-analog design which utilizes on-Chip 7-bit data latches to store quantized weights and two-quadrant multiplying DAC's to compute weighted outputs. The synapses exhibit 6-bit resolution and excellent monotonicity and consistency in their transfer characteristics. A 64-neuron hardware incorporating four synapse chips has been fabricated to investigate the performance of feedback networks in optimization problem solving. In this study, a 7×7, one-to-one assignment net and the Hop field-Tank 8-city traveling salesman problem net have been implemented in the hardware. The network's ability to obtain optimum or near optimum solutions in real time has been demonstrated.
['A. Moopenn', 'Tuan A. Duong', 'A. P. Thakoor']
Digital-Analog Hybrid Synapse Chips for Electronic Neural Networks