This paper proposes the advanced Bluetooth SOC architecture for multimedia applications. Our design includes baseband functions in compliance with Bluetooth core specification v2.0+EDR (enhanced data rate), RF transceiver, modem, SBC codec, ESIC processor, and power management block. This chip is SIP integration with the flash memory and occupies a die size of 28 mm/sup 2/ in CMOS 0.18 /spl mu/m. The maximum current consumption of the total chip is 65 mA. The single operation voltage of the analog and the digital parts is 1.8 V.
['Jeonghun Kim', 'TaeHyeon Sim', 'Youngwhan Choi', 'Jungwon Jeong', 'Taesik Bang', 'Suki Kim']
The v2.0+EDR Bluetooth SOC architecture for multimedia