A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.
['Luc Séméria', 'Andrew Seawright', 'Renu Mehra', 'Daniel Ng', 'Arjuna Ekanayake', 'Barry Pangrle']
RTL C-based methodology for designing and verifying a multi-threaded processor