Future SOC devices make extensive use of phase locked loops to either generate gigahertz clocks on-chip or to adjust the phase of data signals in high speed IO links running at multiple gigabits per second. The high speed analog nature of the circuitry requires a dedicated test strategy to obtain fault coverage particularly for parametric defects affecting jitter performance. While traditional specification oriented test methods require a complex setup of additional instrumentation, This work describes a completely new model based approach using existing capture and compare equipment available with ATE. The methodology proposed in This work performs a test by verifying the frequency domain model of the phase regulation characteristic developed during the design phase of the circuit. The method scales in performance and accuracy with leading edge measurement equipment such as ATE and BERT.
['Bernd Laquai']
A model-based test approach for testing high speed PLLs and phase regulation circuitry in SOC devices