The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
['Vladimir Hahanov', 'Irina Hahanova', 'Ngene Christopher Umerah', 'Tiecoura Yves']
Testing and verification of HDL-models for SoC components