This paper presents the design space exploration on a multitransform architecture for the H.264/AVC video coding standard. Three different architectures were designed, exploring different pipeline configurations. The architectures were described in VHDL and synthesized to an Altera Stratix II FPGA, and also to the TSMC 0.18µm standard-cells technology. The best throughput result achieves an operation frequency of 309 MHz, processing almost 5 billion of samples per second, which allows the processing of QHDTV frames (3840×2048 pixels) in real time. This is the best result compared to all related works found in the literature.
['Felipe Sampaio', 'Robson Dornelles', 'Daniel Palomino', 'Gabriel Siedler', 'Marcel Moscarelli Corrêa', 'Luciano Volcan Agostini']
A multitransform architecture for the H.264/AVC standard and its design space exploration