FIR filtering is one of the basic operations in digital signal processing. To cope with the increasing demands on the speed of DSP processors for real-time and mobile applications, it is important to identify design techniques which help us build very high speed, low power filters. In this paper, we first investigate the effects of multiplier recoding which is a popular technique to increase the speed of multipliers. Next, we propose a method for reducing the activity factor, and hence the power consumption, of multipliers by using gated clocks. Lastly, we look at pipelining issues in multi-hundred MHz filters. In pipelined systems a large fraction of the total power is consumed by the clock circuitry. We compare the power and speed of bit, half-bit and gate level pipelining techniques in multipliers.
['Chetana Nagendra', 'Mary Jane Irwin']
Design tradeoffs in CMOS FIR filters