A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.
['Tohru Adachi', 'Hitoshi Kitazawa', 'Mitsuyoshi Nagatani', 'Tsuneta Sudo']
Hierarchical Top-Down Layout Design Method for VLSI Chip