Integrated circuits may employ many clock domains. The presence of multiple clock domains in modern circuits imposes an issue of inaccurate data transfer from one clock domain to another. Mainly, the issue takes a form of metastable state of the nets of the circuit in the receiving clock domain and corrupts appropriate operation of a consequent circuit. This paper presents a research of flip-flops' metastability phenomenon and its timing characteristics for different threshold voltages and process variations. Metastable state is researched by using master-slave flip-flops from SAED32/28 Educational Design Kit (EDK).
['Tigran Khazhakyan']
Research of metastability timing characteristics for threshold voltage and process-voltage-temperature variations