When we analyze the scaling factors of the recent technology nodes, we come to the conclusion that the geometrical scaling scenario has been replaced by the electrical scaling and hence the electrical characterization of these really challenging technologies becomes an absolute must. However, the extremely small process windows, and the 3-dimensional nature of the FinFET devices and the complicated interconnect schemes, make this characterization very difficult. Systematic failure modes and their dependence on the layout patterns are extremely complex and almost impossible to detect in-line. Moreover, soft failures become much more prevalent due to process marginalities and present not only yield but also reliability hazards. Hence, the new fault models must be created that take into account layout patterns and layout-process interactions to allow for more efficient testing and reliability risk screening. This talk will present novel approaches to electrical characterization of the dominant failure modes, its impact on the test generation and execution, and the need for tracking this information all the way from the front end process to the test and assembly stages of IC manufacturing.
['Andrzej J. Strojwas', 'Jacob A. Abraham', 'Hong Hao', 'Max M. Shulaker']
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below