Integration of isolated LDMOS transistors in smart power process is subjected to bipolar parasitics due to multi layers constructions that are needed for high voltage operation. These parasitics need to be minimized to assure proper circuit functionality. Several approaches for parasitics reduction are suggested: DTI (Deep Trench Isolation) module optimization, NLDMOS and PLDMOS device construction considerations, and lateral and vertical isolation techniques. Creating circuit level parasitic model which can be turned on and off is essential to verify circuit functionality of the improved isolation.
['Moshe Agam', 'Jaroslav Pjencak', 'Dušan Prejda', 'Agajan Suwhanov', 'Thierry Yao', 'Ladislav Seliga']
Management of parasitic bipolars in modular high power LDMOS technology