The paper explores alternatives for implementing a multiplierless implementation of linear-phase finite-impulse response (FIR) digital filters by converting coefficient values to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms. Our observation is that if one is willing to accept some deviations in the given specifications, the required number of nonzero bits becomes quite low, making multiplierless implementation feasible. Alternatively, one may start with a filter that exceeds the given criteria, at the expense of a slightly increased filter order, and then quantize the coefficient values into the desired representation forms such that the given overall criteria are still met. In many cases, this results in an overall implementation where the total number of nonzero bits is significantly less than that obtained by using the initial design. A fairly exhaustive investigation suggests that less than three nonzero bits per multiplier are quite sufficient along with a reduction in number of arithmetic operations and an attendant increase in the rate of the data throughput.
['Mrinmoy Bhattacharya', 'Tapio Saramäki']
Some observations leading to multiplierless implementation of linear phase FIR filters