Scalable high-performance routers and switches are required to provide a larger number of ports, higher throughput, and good reliability. Most of today's routers and switches are implemented using single crossbar as the switched fabric. The single crossbar complexity increases at O(N 2 ) in terms of crosspoint number, which might become unacceptable for scalability as the port number (N) increases. A delta class self-routing multistage interconnection network (MIN) with the complexity of O(N times log 2 N) has been widely used in the asynchronous transfer mode switches. However, the reduction of the crosspoint number results in considerable internal blocking. A number of scalable methods have been proposed to solve this problem. One of them uses more stages with recirculation architecture to reroute the deflected packets, which greatly increase the latency. In this paper, we propose an interleaved multistage switching fabrics architecture and assess its throughput with an analytical model and simulations. We compare this novel scheme with some previous parallel architectures and show its benefits. From extensive simulations under different traffic patterns and fault models, our interleaved architecture achieves better performance than its counterpart of single panel fabric. Our interleaved scheme achieves speedups (over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns, respectively, at maximum load (p = 1). Moreover, the interleaved fabrics show great tolerance against internal hardware failures.
['Rongsen He', 'José G. Delgado-Frias']
Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers