The Cellular Logic Memory Array (CLMA) is a parallel computing paradigm based on an array of memory elements. Each of the memory elements can be configured as a binary logic element or a piece of wiring depending on the contents written in the element. Together these memory elements form a logic circuit that is able to conduct logic operations by sending signals along the elements. The CLMA is originally designed as a synchronous system with clock signals, but it should be operated without clock signals to achieve low-power consumption and efficient computation. As a first step towards an asynchronous CLMA, we present an asynchronous updating scheme in CLMA. Binary signals in the original CLMA are extended to eight-level signals that contain temporal information, so that the resulting functions of logic and wiring resemble that of a synchronously timed scheme. We show that the presented CLMA can operate the same function as in the original CLMA, though some overhead is sustained.
['Teijiro Isokawa', 'Ferdinand Peper', 'Shoji Ishibashi', 'Toshifumi Minemoto', 'Nobuyuki Matsui']
An Asynchronous Updating Scheme for a Cellular Logic Memory Array