Battery-powered electronics rely on integration and power efficiency for size and operational life. Switched-inductor converters play a critical role in this because most portable systems depend on dc-dc converters to supply power efficiently. Understanding the collective impact of shrinking dimensions on total power losses in a switching converter is therefore important when selecting a process technology for the power-supply chip, because the optimal choice results in longer battery life. This paper analyzes and validates the effects of finer CMOS technologies (which feature shorter minimum channel lengths L MIN , higher oxide capacitance, and lower breakdown voltages) on the efficiency performance of switched-inductor dc-dc converters in continuous- and discontinuous-conduction modes (CCM and DCM). Simulation results show that conduction and gate-drive losses in switches rise with L MIN  1.5  and bias and bandwidth-critical quiescent losses with L MIN  and L MIN  3 , respectively. In other words, because parasitic components and gate-drive voltages rise with L MIN , efficiency drops with coarser technologies: E.g., the efficiencies of optimized 0.18-, 0.35-, and 0.5-µm buck converters peaked at 93%, 89%, and 79%.
['Suhwan Kim', 'Gabriel A. Rincon-Mora']
Efficiency of switched-inductor dc-dc converter ICs across process technologies