Multi-rank DRAM modules have been identifiedas a flexible option for accommodating large mixed criticalworkloads. However, because all ranks in a module share thesame multi-drop data bus, a penalty in the form of idle cyclesis necessary when alternating data transfers between differentranks. Moreover, as the data bus clock frequency of DRAMmodules becomes higher, such penalty increases significantly andcan no longer be neglected. Therefore, in this paper, we propose amixed critical real-time controller for multi-rank DRAM modulesthat minimizes rank switches. Our controller works by schedulingbatches of data transfers for each rank and performing rankswitches only in the end of each batch. We provide a detailedtiming analysis of our approach and a comparison with a state-of-the-art counterpart. For a dual-rank scenario, our approachincreases DRAM utilisation, thus reducing the latency bounds ofhard real-time applications by on average 14% and decreasingthe average request latency of soft real-time applications by onaverage 51%.
['Leonardo Ecco', 'Adam Kostrzewa', 'Rolf Ernst']
Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance