Design-manufacturing co-optimization has been earmarked as a key enabler of future technology scaling. Current manufacturing methods treat all transistors equally irrespective of their criticality in the design flow. In the presence of variations in the lithographic process, this leads to timing violations which reduces chip yield. In this paper, we develop a timing-driven process window optical proximity correction (TD-PWOPC) algorithm that tunes the mask generation for each transistor based on its electrical criticality in the design. Our method utilizes knowledge of timing information to generate delay bounds on each cell. It then develops a process variation aware OPC cost function for each cell to ensure that post-lithography delay lies within these bounds. This method uses a single image simulation coupled with simplified models for regular polysilicon layouts to predict though-process performance. We finally use a gradient-descent algorithm to minimize this cost function. Results show that the use of TD-PWOPC can reduce delay errors significantly compared to regular OPC at small runtime overheads of 4.5%.
['Shayak Banerjee', 'Kanak B. Agarwal', 'Sani R. Nassif', 'James A. Culp', 'Lars W. Liebmann', 'Michael Orshansky']
Coupling timing objectives with optical proximity correction for improved timing yield