This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined execution and cache memories of RISC processors. The main focus of this paper is on explaining the necessary steps for performing timing analysis of a given target machine within the extended timing schema framework. This paper also gives results from experiments using a timing tool for the target machine that is built based on the extended timing schema approach.
['Yerang Hur', 'Young Hyun Bae', 'Sung-Soo Lim', 'Sung-Kwan Kim', 'Byung-Do Rhee', 'Sang Lyul Min', 'Chang Yun Park', 'Minsuk Lee', 'Heonshik Shin', 'Chong Sang Kim']
Worst case timing analysis of RISC processors: R3000/R3010 case study