Scatter-gather direct memory access (DMA) transfers can be used to efficiently fetch graph memory data for onchip processing of graph applications. We present a hardware controlled graph DMA engine which can operate autonomously without the need for CPU interaction. Graph processing algorithms can asynchronously request graph data which is fetched from memory and streamed to the processing core. An implementation of Dijkstra’s shortest path algorithm operating on real-world social network graph data is used to demonstrate the operation of our hardware controlled graph DMA engine. Our system shows a 38% decrease in processing time over a standard CPU implementation and up to an 11% improvement over a hardware implementation using standard AXI4 read requests.
['Andrew Bean', 'Nachiket Kapre', 'Peter Y. K. Cheung']
G-DMA: improving memory access performance for hardware accelerated sparse graph computation