This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis, a high-performance design, in a 0.18mum CMOS process, is presented.
['Savvas Koudounas', 'Julius Georgiou']
A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit