Negative Bias Temperature Instability (NBTI) induced transistor aging has become one of the major reliability concerns in sub-micron circuit as technology scales. Transistor performance degrades over time and may eventually cause timing violations and circuit failure. Multi-Vth is known as a method to improve circuit performance with leakage and timing tradeoffs. In this paper, we propose a heuristic metric, which could be used to capture leakage and timing tradeoff during multi-Vth optimization. Our technique is an after-aging delay minimization problem under leakage power constraint. The experimental results on ISCAS85 benchmark circuits at 45nm node show up to 17% after-aging delay improvement within the predefined leakage power constraint.
['H. Luo', 'Mehrdad Heydarzadeh', 'Mehrdad Nourani']
Aging-Leakage Tradeoffs Using Multi-Vth Cell Library