To recover the timing violations due to the delay variations after fabrication, delay tuning is promising. Delay tuning inserts programmable delay elements (PDEs) to circuits before fabrication and tunes their delays to recover the timing violations after fabrication. However, the yield of the circuits obtained by existing delay tuning methods is not improved enough and their power consumptions become high. Besides, technology mapping which assigns a cell in some cell libraries to each gate to minimize the clock period and the power consumption has been proposed. In this paper, a design method applying delay tuning and technology mapping for high yield improvement and low power consumption is proposed. The experimental results show the effectiveness of the proposed method.
['Hayato Mashiko', 'Yukihide Kohira']
Yield and power improvement method by post-silicon delay tuning and technology mapping