This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.
['Laung-Terng Wang', 'Xiaoqing Wen', 'Po-Ching Hsu', 'Shianling Wu', 'Jonhson Guo']
At-speed logic BIST architecture for multi-clock designs