This paper outlines the development of a rapid prototype methodology used to implement a new communications decoding architecture and a channel simulator to evaluate that decoder's performance. In addition, we describe the subsequent refinement of a key computational component of the decoder using a semicustom approach; namely, a CMOS standard cell implementation. Both these project tasks have relied extensively on the use of design automation (DA) tools and Field Programmable Gate Array (FPGA) technology. Herein, we describe our rapid prototype methodology, some lessons learned, and highlight our experiences using DA tools (specifically, Mentor Graphics and Xilinx) encountered in the progress of our work.
['Patrick H. Kelly', 'Kevin J. Page', 'Paul M. Chau']
Rapid prototyping of ASIC based systems