Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as −146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from −115 to −135dBc/Hz, injection spurs from −40.5dB to −57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm 2  and consuming 19.8mW from a 0.85V supply resulting in FoM and FoM Jitter  of −163dB and −223.6dB respectively.
['Alvin Siu-chi Li', 'Yue Chao', 'Xuan Chen', 'Liang Wu', 'Howard C. Luong']
An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique