This paper presents an ultra-low-voltage and power-efficient 10 bit hybrid successive approximation register (SAR) analog-to-digital converter (ADC). For reducing the digital-to-analog converter (DAC) capacitance and comparator requirement, we propose a hybrid architecture comprising a coarse 7 bit SAR ADC and fine 3.5 bit time-to-digital converter (TDC). The Vcm-based switching method is adopted for coarse conversion to reduce DAC power and maintain common mode. The residual voltage after coarse conversion is converted to time domain, and the fine TDC detects the least three bits with 0.5 bit redundancy by using a Vernier delay structure. Offset calibration and delay time locking are implemented to guarantee the ADC performance under process variation. The test chip, fabricated in 90 nm CMOS technology, occupied a core area of   ${0.04}\;{{\text{m}}{\text{m}}^{2}}$  . With a 0.4 V supply and a Nyquist rate input, the prototype consumed 200 nW at 250 kS/s and achieved an ENOB of 8.63 bits and a SFDR of 78.5 dB. The operation frequency was scalable from 250 kS/s to 4 MS/s. The converter had a power supply range of 0.4–0.7 V, and the figure of merit (FoM) were 2.02–5.16 fJ/conversion step.
['Yan-Jiun Chen', 'Kwuang-Han Chang', 'Chih-Cheng Hsieh']
A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS