In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis shown how the timing diagrams for the unit network verificationare easily derived from the timing diagrams specified for theunits. The multiprocessor hardware test showed the effectivenessof the proposed verification approach.
['Jörg A. Walter', 'Jens Leenstra', 'Gerhard Döttling', 'Bernd Leppla', 'Hans-Jürgen Münster', 'Kevin W. Kark', 'Bruce Wile']
Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors