In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. Regarding the device technique, we utilize asymmetric halo implant MOSFETs, which enables to enhance both the static noise margin and write margin of SRAM, simultaneously. As for the design technique, dynamic body-bias scheme which operates body bias dynamically is introduced to overcome the speed degradation due to lower supply voltage. Showing measured data fabricated on 45nm CMOS technology, we demonstrate a plausible scenario for achieving 0.5V operating SoC products.
['Makoto Yabuuchi', 'Yasumasa Tsukamoto', 'Hidehiro Fujiwara', 'Shigeki Tawa', 'Koji Maekawa', 'Motoshige Igarashi', 'Koji Nii']
A dynamic body-biased SRAM with asymmetric halo implant MOSFETs