A 4.5 mW, 0.01148 mm 2  frequency multiplier based on mixed-mode delay-locked-loop (DLL) in 65 nm CMOS technology is presented in this paper. The operating frequency range is between 100 and 150 MHz which enables to produce output signals in the frequency range from 4 to 6 GHz. NAND-based delay cells are used in the digital part of the delay line due to their wide operating frequency range and small intrinsic delay. The analogue part of the delay line is based on the inverter delay chain with biasing circuit. It was added into the system to overcome the resolution problem and improve jitter performance. The total locking time changes from 10 to 14 clock cycles based on the operating frequency. The simulated peak-to-peak jitter is 21 ps and 1.95 ps for the generated clock operating at 5 GHZ and output clock of DLL operating at 125 MHz respectively.
['Erkan Bayram', 'Oner Hanay', 'Renato Negra']
A 4.5 mW, 0.01148 mm 2 frequency multiplier based on DLL with output frequency from 4 to 6 GHz