The digit-recurrence division relies on a sequence of addition/subtraction and shift operations in a manner similar to the paper-and-pencil approach, that gives a very regular structure suitable for efficient VLSI implementation. Speed is obtained through the use of redundant number notation allowing carry-propagation-free addition/subtraction with a delay independent of the size of the divisor. Since the quotient digits are obtained sequentially, the delay can theoretically be further reduced by recurring to higher-order radixes to obtain several quotient bits at once. This paper compares the synthesis of radix-2 and radix-4 dividers.
['Alain Guyot', 'Luis A. Montalvo', 'A. Houelle', 'Habib Mehrez', 'Nicolas Vaucher']
Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers