3D integration of functions such as sensors and circuit elements enables miniaturized and cost-effective smart systems. Wirebonds are replaced by Through Silicon Vias (TSVs) and Wafer Level Packaging (WLP) for shorter conductive paths and reduced form factor. This paper reviews prior art and presents a comprehensive set of data from volume manufacturing of 3D integrated optical sensors and circuits using a “via last” manufacturing flow. 3D specific yield detracting processes such as patterning of open TSVs, wafer bonding, and etching are analyzed and discussed. Functional test yields equivalent to standard CMOS process yields can be achieved.
['Martin Schrems', 'Joerg Siegert', 'Peter Dorfi', 'Jochen Kraft', 'Ewald Stueckler', 'Franz Schrank', 'Siegfried Selberherr']
Manufacturing of 3D integrated sensors and circuits