The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.
['Lirida A. B. Naviner', 'Kaikai Liu', 'Hao Cai', 'Jean-François Naviner']
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix