Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over "long" distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks. >
['Jiao Fan', 'David Zaleta', 'Chung-Kuan Cheng', 'Sing H. Lee']
Physical models and algorithms for optoelectronic MCM layout