We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control circuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology.
['Jo C. Ebergen', 'Jonathan Gainsley', 'Jon Lexau', 'Ivan E. Sutherland']
GasP control for domino circuits