A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method. >
['Yusuke Matsunaga', 'Masahiro Fujita', 'Takeo Kakuda']
Multi-level logic minimization across latch boundaries