A low power CMOS voltage reference circuit was designed and implemented by TSMC 0.18-mum CMOS process. The voltage reference circuit uses the V GS  difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining the weighted V GS  difference with weak-inversion V GS  voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/degC in [-20degC~120degC] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm 2  and dissipates 17.25 muW at room temperature. By connecting a 0.22 muF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 muV/radicHz and 22.2 muV/radicHz, respectively.
['Chia-Wei Chang', 'Tien-Yu Lo', 'Chia-Min Chen', 'Kuo-Hsi Wu', 'Chung-Chih Hung']
A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation