A 600-Mb/s rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder was implemented in a 90-nm CMOS process. The encoder operates at 1.1 GHz and includes built-in all-phase termination. The decoder design maximizes throughput while minimizing the number of memory banks and delivering an information throughput of 1 bit per clock cycle. The size of the decoder controller is minimized by sharing it among an arbitrary number of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2.0 and a throughput of 600 Mb/s. An integrated test system enables accurate power measurements for various SNR settings.
['Tyler L. Brandon', 'John C. Koob', 'L. van den Berg', 'Zhengang Chen', 'Amirhossein Alimohammad', 'Ramkrishna Swamy', 'J. Klaus', 'Stephen Bates', 'Vincent C. Gaudet', 'Bruce F. Cockburn', 'Duncan G. Elliott']
A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes