We present an accurate model for compact implementations of Rayleigh and Rician fading channels. Verification of the proposed fading simulator is performed by comparing the simulated statistics with those of the ideal reference models. A parameterizable field-programmable gate array (FPGA) implementation of the channel simulator is presented. The design is readily scalable to support multipath fading channels and multiple-input multiple-output (MIMO) systems. A 16-path fading channel, providing either Rician or Rayleigh fading, uses 41% of the configurable slices, 33% of the dedicated multipliers, and 32% of the on-chip block memories of a Xilinx Virtex-II Pro XC2VP100-6 FPGA while generating over 200 million complex- valued fading coefficients per second.
['Amirhossein Alimohammad', 'Saeed Fouladi Fard', 'Bruce F. Cockburn', 'Christian Schlegel']
A single-FPGA multipath MIMO fading channel simulator