Digital and mixed circuits performance are affected and limited by the simultaneous switching power and ground noise. For accurately selecting the number of power/ground pins to overcome switching noise, it is very important to accurately estimate the worst case simultaneous switching power and ground noise. In this paper we propose a heuristic that helps to estimate this worst case. >
['Abdessatar Abderrahman', 'Bozena Kaminska', 'Yvon Savaria']
Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits