In this paper we present efficient Mesochronous and Plesiochronous interfaces targeting low-latency and low-overhead links. Our source-synchronous scheme can easily be integrated in traditional design flows, supports maximal throughput, has low latency and has an overhead of only three flip flops per data line. With one additional flip-flop per data line, the Plesiochronous interface allows the synchronizer to cope with clock drifts. The simple synchronization scheme is validated through formal analysis and simulation.
['Jean Michel Chabloz', 'Ahmed Hemani']
Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers