This paper proposes dependable flip-flop design, dual edge triggered flip-flops, taking into account of noise induced on data signal lines. The clock signal has two edges in nature. If an edge triggered flip-flop can sample data by using two clock edges of both rising and falling, the flip-flop has the highly ability to prevent sampling a noise signal on the data line.
['Yukiya Miura']
Dual Edge Triggered Flip-Flops for Noise Aware Design