A high performance back-traced deductive-parallel (BDP) fault simulation method based on the superposition procedure is oriented on using large digital designs processing. Evaluation of RT and gate level design description is proposed in this work. The data structure and program are developed for algorithms realization of the proposed method and integration with automatic test pattern generation systems.
['Vladimir Hahanov', 'Raimund Ubar', 'Stanley Hyduke']
Back-traced deductive-parallel fault simulation for digital systems