A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18/spl mu/ CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling time is 300/spl mu/sec. Synthesizer consumes 22mW of power at supply voltage of 1.8 V and occupies an active area of mm/sup 2/.
['Saurabh Kumar Singh', 'T. K. Bhattacharyya', 'Ashudeb Dutta']
Fully integrated CMOS frequency synthesizer for ZigBee applications