Networks-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal-based NoC pursuit offers limited scalability with the relentless technology scaling especially in global communications. To meet the scalability demand, this study proposes a new hybrid architecture empowered by both metal interconnect and Zenneck surface waves interconnects (SWIs). This architecture reduces the NoC average hop count between any communication pairs, which has been reflected as a better average delay and throughput. Furthermore, SWI enables more efficient power dissipation and faster cross the chip signal propagation. The authors' initial results based on a cycle-accurate simulator demonstrate the effectiveness of the proposed system architecture, such as significant power reduction (23%), large average delay reduction (34%) and higher throughput (35%) compared with regular NoC. These results are achieved with negligible hardware and area overhead. This study explores promising potentials of SWI for future complex global communication. © The Institution of Engineering and Technology 2013.
['Ammar Karkar', 'Janice Turner', 'Kenneth Tong', "Ra'ed AI-Dujaily", 'Terrence S. T. Mak', 'Alex Yakovlev', 'Fei Xia']
Hybrid wire-surface wave interconnects for next-generation networks-on-chip