This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an lntel/spl reg/ Pentium/spl reg/ 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.
['Srikanth Venkataraman', 'S. Sivaraj', 'Enamul Amyeen', 'Sangbong Lee', 'Ajay Ojha', 'Ruifeng Guo']
An experimental study of N-detect scan ATPG patterns on a processor