In response to the current requirements of energy efficiency and high performance in computing systems, architects have turned towards customization. General purpose computing however remains a challenge as processors must adhere to a variety of applications, on-chip resources, and increased performance without solely relying on transistor scaling and additional cache levels. For this reason, the concept of Reconfigurable Computing Unit (RCU) processors have been proposed which redesign the conventional processor on the microarchitectural and architectural level. RCUs are extended in this work to support a multi-task workload using OmpSs, where task and instruction placement algorithms are thoroughly assessed for effects of performance and energy efficiency. Experimental results demonstrate that a single RCU processor with a double engine configuration is able to exceed single-core performance on average by 1.48x and achieve/exceed dual-core performance. The various inter-and intra-task placement algorithms tested also display up to 16.7% and 23% fluctuation in performance and energy efficiency, respectively, depending on the method and RCU engine combination employed.
['Anita Tino', 'Kaamran Raahemifar']
Assessing Multi-task Placement Algorithms in RCUs