Scan design is a powerful Design-for-Testability (DFT) technique that enhances controllability and observability of internal nodes of the circuit under test. However, it can increase system vulnerability being a back door to access secret information of a secure chip. In this paper, we present a scan-based design which is robust against scan-based side channel attacks. We use SHA256 secure hash and Blum Blum Shub pseudo random number generator to create a simple challenge/response scheme. The system can be used to enable JTAG instructions for authorized user or control access to IEEE 1687 on-chip instruments. The effectiveness of the proposed method has been verified using NIST statistical test suite.
['Elnaz Koopahi', 'Shahram Etemadi Borujeni']
Secure scan-based design using Blum Blum Shub algorithm