Test quality requires the ability of test patterns to cover realistic faults originated by physical defects induced during IC manufacturing. Recent progress in a methodology for physical testability analysis is reported in this paper. A refined bridging faults classification provides evidence that reconvergent fan-out areas should be carefully designed to avoid hard to detect faults. Moreover, the concept of selective decompaction is introduced, to show that with reduced area overhead, testability can significantly be increased. As a result, guidelines for cell library development, and for refined routing algorithms, are presented. The results are il1ustra.ted with several design examples. These examples also show that the realistic fault coverage can be higher or lower than the Line Stuck-At (LSA) fault coverage depending on the relative incidence of bridging and open faults, and the topological characteristics of the surrounding circuit.
['M. Saraiva', 'Pilar González Casimiro', 'M. B. Santos', 'José T. de Sousa', 'Fernando M. Gonçalves', 'Isabel C. Teixeira', 'João Paulo Teixeira']
Physical DFT for High Coverage of Realistic Faults