Typical approaches to solve Dynamic Programming algo- rithms explore data level parallelism by relying on specialized vector instructions. However, the fully-parallelizable scheme is often not com- pliant with the memory organization of general purpose processors, lead- ing to a less optimal parallelism exploitation, with worse performance. The proposed processor architecture overcomes this issue by relying on a data stream loader and a set of especially designed instructions. Further- more, to make it compliant with the strict power and energy limitations of embedded systems, it maximizes resource utilization by exploiting both data and instruction level parallelism, by statically scheduling a bundle of instructions to several vector execution units. To evaluate the proposed architecture, we compare it with two embedded processors, an ARM Cortex-A9 and an application-specific processor with SIMD extensions, using two benchmarks from the sequence alignment domain, namely Smith-Waterman and Viterbi. The obtained results show that the proposed architecture achieves up to 5.16x and 2.19x better performance- energy efficiency and up to 5.44x and 1.25x better energy efficiency than the ARM Cortex-A9 and the dedicated processor, respectively.
['Miguel Tairum Cruz', 'Pedro Tomás', 'Nuno Roma']
Energy-Efficient Architecture for DP Local Sequence Alignment: Exploiting ILP and DLP