In this paper, an embedded SRAM architecture of Video application is proposed to reduce the power consumption. By analyzing the general read and write access patterns, the embedded memory is customized to reduce power consumption while achieving general FIFO operations. Some of the signal activations and the Pseudo-read operations are removed in FIFO. According to the simulation results with 65nm CMOS process, the proposed embedded memory for line buffer achieves 17.62% power savings with 3.72% overhead compared to the conventional embedded SRAM approaches.
['Sangkyu Lee', 'Hoyoung Tang', 'Kyungrak Choi', 'Jongsun Park']
Customized SRAM design for low power video code applications