Reducing the power dissipation associated with the clock network in a sequential circuit can result in significant dynamic power saving. In this work, an efficient technique of autonomous clock gating (CG) has been proposed for finite state machines (FSMs). The CG logic is based on the idea of dynamically disabling the clock signal to the sequential blocks of the FSM during periods of inactivity. The inactive state is decided by the occurrence of self-loops within the FSM. The proposed gating technique operates at a fine level of granularity and can be generally implemented to any FSMs. A technique of partitioning the registers of the FSM is introduced in this work in order to avoid functional errors and signal losses during gating. The logic of registers partitioning for CG in large FSMs containing few or no self-loops is also presented in this work. The simulation results obtained shows up to 38% (max) dynamic power reduction of the FSM with a little penalty in area. The timing slack associated with the gated and non-gated FSMs is also analyzed for varying clock frequencies. The results indicate a minimal increase in delay after gating. The technique for CG in large FSMs containing few or no self-loops has yield up to 58% (max) power reduction.
['Abhishek Nag', 'Sambhu Nath Pradhan']
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning