Silicon bring-up aims to achieve validation across a desired spread of power and performance for an integrated circuit product such as a microprocessor, and manufacturing test aims to screen out defects and classify parts into a range of performance bins. Both these steps are increasingly becoming complex due to shrinking device dimensions causing circuit performance to become highly sensitive to voltage variations such as high/low frequency voltage droops and IR drop. During bring-up, the sensitivity of performance to voltage behavior is also not consistent and correlated across different validation platforms such as a system (board) or a tester, or across different test methodologies such as functional testing or scan testing. This voltage sensitivity coupled with lack of sufficient silicon observability of voltage behavior in a cycle-by-cycle manner adversely impacts silicon debug efficiency during bring-up both on the system and on the tester. This can lead to sub-optimal fixes in each silicon iteration and increased iterations. This can increase time-to-market, and also significantly reduce yield during manufacturing test. The downward pressure on product cost necessitates that test cost scales proportionally. The high cost of functional test development to achieve a desired coverage, the relatively high functional tester costs vis-a-vis the costs of structural testers, and increased complexity of low-yield analysis and failure analysis (FA) with functional tests due to large number of cycles that need to be simulated to reason about failures, all conspire to render production testing with functional tests increasingly infeasible. To address the need for adequate defect coverage at a desired operating frequency using scan-based tests that is at par with that provided by functional tests, at-speed application of scan tests becomes necessary. Recently published literature has indicated increased voltage sensitivity to at-speed scan test application and increased power dissipation during at-speed test. To avoid yield loss and test escapes due to these issues, it becomes necessary to match or correlate the dynamic voltage and current profiles of scan tests to those of functional tests which have been accepted so far as a de facto standard (though not golden). However, for scan-based testing to replace functional tests effectively, it is imperative that voltage/power profiles during functional tests be characterized adequately. Scan test application schemes and scan test content that can provide voltage/power profiles that match those of functional tests can then be developed to reduce product test cost without compromising quality. This session explores characterization of power delivery network on a silicon die, its impact on silicon bring-up, and on effectiveness of functional and at-speed scan-based manufacturing test.
['Suriyaprakash Natarajan']
Innovative practices session 9C: Implications of power delivery network for validation and testing