This paper proposes a novel high level synthesis methodology for optimal linear analog systems in a formal and systematic way. It takes as an input, a high level description as well as the desired specifications of the system and gives as an output, an optimal sized architecture as well as certain constraints. This facilitates hierarchical analog system design and reduces circuit designers' effort by providing block level sizes with appropriate tolerance level. The methodology defines an abstract description of the system, selects an optimal architecture by exploring the entire architecture space and finally performs a behavioral sizing of the architecture. The entire methodology is illustrated with the case study of a state variable filter and the benefits of the approach are clearly brought out.
['Soumya Pandit', 'Chittaranjan A. Mandal', 'Amit Patra']
A formal approach for high level synthesis of linear analog systems