Many of the nanometer CMOS challenges are seriously compromising the gains attained with technology scaling, mainly impacting the yield and the circuit reliability. To cope with these problems, new design methodologies are necessary to improve the robustness of the circuits. Given the overheads associated with the traditional fault-tolerant approaches, alternative solutions, based on partial fault tolerance and fault avoidance, are also being considered as possible solutions to the reliability problem. These approaches are based on the application of fault tolerance to a restricted part of the circuits or hardening of individual cells, allowing reliability improvements and limiting the associated overheads. In this context, a fast and accurate evaluation of circuit's reliability is fundamental, to allow a reliability-aware automated design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. This work presents a methodology to calculate circuit reliability, based on the Probabilistic Transfer Matrix (PTM) method, and using a probabilistic model for stuck-on faults that considers a fault probability for each input vector. The work shows that considering the same error probability for all input vectors underestimates the input influence on the overall circuit reliability. The proposed model of gate reliability associated with the PTM method can provide results that are more accurate in terms of circuit reliability. Results obtained with the proposed approach show a difference up to 15% when compared with the traditional application of the PTM method with equal input vector probabilities, when applied to a set of combinational circuits.
['Rafael B. Schivittz', 'Rafael Fritz', 'Denis Teixeira Franco', 'Lirida A. B. Naviner', 'Cristina Meinhardt', 'Paulo F. Butzen']
Inserting permanent fault input dependence on PTM to improve robustness evaluation