We define and investigate the problem of electromigration faults caused by spot defects during the VLSI manufacturing process. Analysis is given for a simple layout, and simulations are presented and discussed for a more complicated case. It is shown that in some cases, electromigration-dependent parametric faults can make a significant contribution to the total yield estimation.
['Roman Barsky', 'Israel A. Wagner']
Electromigration-dependent parametric yield estimation