This paper proposes multi-domain quantization for a partially-parallel QC-LDPC decoder, which allows efficient memory bandwidth utilization. The change of quantization during decoding is dynamic. In addition to this, the proposed decoder targets speedup and energy efficient processing, with negligible error correction capability degradation. From the message storage perspective, it uses 2 quantization modes: a high resolution based q-bit messages, and a low resolution q/2-bit messages. Regarding the lower quantization domain, the variable node units operate on q/2+1 resolution, while check node units process q/2-bit messages. In order to evaluate the efficiency of this approach, we have analyzed the decoding performance for both AWGN and BSC channel models. In addition to this, we have implemented the proposed units and evaluated the overhead with respect to the baseline.
['Oana Boncalo']
QC-LDPC Gear-Like Decoder Architecture with Multi-domain Quantization