Spectral generation of patterns, to excite the natural frequencies of a digital circuit, is highly effective in testing sequential circuits. We have created a hardware embodiment of the spectral test-pattern generator for built-in self-test (BIST). We present five new spectral response compactors SRC1-5 for BIST. Each analyzes the spectral content of circuit output responses, and accumulates their spectrum in one or more counters. The method has astonishing results. SRC1 never aliased for any faults in the ISC AS '89 benchmarks. SRC2, a low-overhead version of SRC1, aliased slightly more than the multiple-input signature register (MISR), but used less hardware than the MISR. This new spectral BIST system has a 91.26% shorter test sequence than for a conventional LFSR pattern generator and MISR system, with at least 8.42% higher fault coverage. The benefits of this are drastically shorter test sequences, the elimination of scan-shifting sequences, much lower test power dissipation, and higher fault coverage.
['Omar I. Khan', 'Michael L. Bushnell']
Spectral analysis for statistical response compaction during built-in self-testing