An error-detecting 32-b reduced instruction set computer (RISC) designed in a 1.2- mu m CMOS technology with an on-chip watchdog using embedded signature monitoring is presented. It was evaluated through simulation-based fault injection, using a register level model written in VHDL (very high-speed IC (VHSIC) description language). A chip area increase of 4.7% was caused by the watchdog. Two application programs were executed to study workload dependencies. The insertion of watchdog instructions resulted in a memory overhead of between 13% and 25% as well as a performance overhead of between 9% and 19%. A total of 2779 faults were injected into the processor during execution of the application programs. Only 23% of these resulted in effective errors. A minimum detection coverage of 95% was reached for effective errors classified as control flow errors with a median latency of one clock cycle. Few effective data errors, between 22% and 50%, were detected. >
['Joakim Ohlsson', 'Marcus Rimén', 'Ulf Gunneflo']
A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog