A novel DPS integrator scheme for fast CMOS imagers is presented, which combines the advantages of analog APS and DPS circuits. The reset-insensitive integrator proposal improves the linearity of the ADC curve, while it allows both low-power consumption for the active blocks and low-voltage operation for the switching devices even at high frame rates. In this sense, a comparative study is presented in 0.18 mum 1-poly 6-metal 1.8 V CMOS technology to demonstrate the advantages of this novel solution.
['Josep Maria Margarit', 'Justo Sabadell', 'Lluis Teres', 'Francisco Serra-Graells']
A novel DPS integrator for fast CMOS imagers