The threshold voltage (V th ) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient  SPICE simulation method and statistical transistor model  that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of V th  from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to V th  and (c) propose a  compact model of V th  variation  that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of V th  variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.
['Yun Ye', 'Frank Liu', 'Sani R. Nassif', 'Yu Cao']
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness