A highly concurrent second-generation RISC (reduced-instruction-set computer) that combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio is described. Like earlier RISC processors, this design uses a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, however, several advanced architectural and implementation features are used, including separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. The CPU has a full 64-b floating-point engine, and thirty-two 64-b floating point registers in addition to thirty-two 32-b fixed-point registers. In a single cycle, four instructions can be executed simultaneously. >
['H. B. Bakoglu', 'Greg Grohoski', 'L. E. Thatcher', 'James Allan Kahle', 'Charles R. Moore', 'David Tuttle', 'Warren E. Maule', 'William R Hardell', 'Dwain A. Hicks', 'M. Nguyenphu', 'Robert K. Montoye', 'W.T. Glover', 'Sudhir Dhawan']
IBM second-generation RISC machine organization