The proposed output buffer circuit uses 1.8V transistors in 90nm CMOS process to develop I/Os for 2.5V and 3.3V interfaces. A voltage clamp circuit, bias generators, and a feedback circuit are used to ensure reliability and noise decoupling. Use of these circuits enables achieving low power (130/spl mu/A) and high performance (up to 275MHz) in a comparative area of an equivalent I/O in 90nm 3.3V process.
['Rajat Chauhan', 'Karthik Rajagopal', 'Vinod Menezes', 'H M Roopashree', 'Sanish Koshy Jacob']
A high performance, high voltage output buffer in a low voltage CMOS process