A technique for deskewing a pair of terminated, differential PCB traces has been developed and fabricated in 0.25 /spl mu/m CMOS technology. The deskewing system utilizes a delay-locked-loop with a digital counter-controlled delay line to match the delay through the positive and negative traces. Time domain reflectometry is used to measure the delay from the terminating resistor to the transmitting chip. The core circuitry occupies 588 /spl mu/m/spl times/235 /spl mu/m. Simulation results indicate that skews of over 1 ns can be eliminated using this technique.
['Amer Hani Atrash', 'Brian Butka']
A technique to deskew differential PCB traces