In this paper, a fully digital frequency-tracking clock and data recovery circuit is presented. The circuit is implemented in a commercial USB 2.0 transceiver platform, and adopts a new clock phase selection feedback approach rather than the conventional feed-forward blind oversampling methodology. This allows for frequency-tracking capability. In spite of the feedback loop used, the circuit is implemented in an entirely digital design flow, allowing for a minimized gate count and power consumption. Formal analysis of the circuit paths allows for ease-of-reuse and retargeting, and is also presented in detail.
['José Henrique Alves Sarmento', 'John T. Stonick']
A minimal-gate-count fully digital frequency-tracking oversampling CDR circuit