We propose a three-dimensional architecture using post-silicon devices, such as nano-mechanical electrical switches, carbon nanotube FETs, and nanowire FETs, for future networks-on-chip (NoC). Based on such a new 3D architecture, extremely high bandwidth with very low latency can be realized. These promising features are very useful for future NoCs.
['Shinobu Fujita', 'Kumiko Nomura', 'Keiko Abe', 'Thomas H. Lee']
3D on-chip networking technology based on post-silicon devices for future networks-on-chip