A CORDIC-based, unified systolic architecture for sliding window applications of the discrete Fourier transform (DFT), the discrete Hartley transform (DHT), the discrete cosine transform (DCT), and the discrete sine transform (DST) is proposed. Compared to earlier works, the proposed scheme offers significant reduction in hardware, particularly for DHT. For an N-point DHT, it requires only [N/2]+1 processing elements, each consisting of one CORDIC processor and two adders.
['Dulal C. Kar', 'V.V. Bapeswara Rao']
A CORDIC-based unified systolic architecture for sliding window applications of discrete transforms