A high accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for USB2.0 application, is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) combined with a Current Controlled Oscillator (ICO). Sigma- Delta (ΣΔ) dithering is used on the DAC for improved frequency accuracy. To reduce noise due to ΣΔ dithering and to allow for passive filtering of this noise, the ΣΔ section of the DAC is limited to a small range. This range, however, is not sufficient to account for frequency drifts due to temperature: a novel temperature compensation scheme is used for this purpose. The DPLL is built in 65nm technology, and provides a 480MHz output, with a phase noise of −103.5dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports a list of input frequencies: 13MHz, 12MHz, 19.2MHz, 24MHz and 48MHz, occupies a die area of 0.21 sq mm, and does not require external components.
['Anant Shankar Kamath', 'Biman Chattopadhyay', 'Gopalkrishna Nayak']
A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0