This paper introduces the first high-level (task-level)model of hierarchical memories and describes a scheduling andallocation algorithm for system-level synthesis of heterogeneousmultiprocessors. Caches are essential for modern RISC embeddedcores to obtain sustained high performance. However, caches havereceived limited use in priority-driven preemptive real-time systemsdue to the unpredictability of caches-average-case improvementsare of no use in systems with hard deadlines. Program-levelcache models do not take into account preemptions between multipletasks running at multiple rates on embedded cores. Our task-levelmodel of performance in the presence of memory hierarchiesprovides an efficient means to bound the guaranteed memory performanceof tasks running in a multi-rate, multi-tasking environment.Our system synthesis algorithm uses software-based cachepartitioning and reservation techniques to guarantee cache hitsfor some tasks and therefore improve task schedulability. Experimentalresults show that our model significantly improves schedulabilityof real-time tasks and can be evaluated efficiently duringsystem-level synthesis.
['Yanbing Li', 'Wayne H. Wolf']
A task-level hierarchical memory model for system synthesis of multiprocessors