Multi-core processor architectures, also known as chip-multiprocessors (CMPs), have become a predominant technology for applications demanding both the high bandwidth and the low power. A typical CMP architecture integrates multiple processor cores, one or more memory controllers, a multi-level cache hierarchy, and an interconnection network on a single chip. Sharing of large size cache among multi-cores poses a number of new challenges to be addressed in terms of cache-coherence and power management. This paper investigates the integration of a directory-based cache coherence protocols for the last level shared cache (L2/L3) for power-aware CMP architectures. We propose a scalable directory-based cache coherence protocol with minimal hardware overhead. The protocol supports the “sleep” mode for one or more cores without running into issues of data inconsistencies of shared data. The paper also presents the framework of an analytical model to evaluate the performance of the proposed protocol.
['Rana Ejaz Ahmed', 'Muhammad Dhodhi']
Directory-based cache coherence protocol for power-aware chip-multiprocessors