This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (V CS ) in the active mode. A digitally controllable retention circuit regulates V CS  in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.
['Keiichi Kushida', 'Fumihiko Tachibana', 'Osamu Hirabayashi', 'Yasuhisa Takeyama', 'Miyako Shizuno', 'Atsushi Kawasumi', 'Azuma Suzuki', 'Yusuke Niki', 'Shinichi Sasaki', 'Tomoaki Yabe', 'Yasuo Unekawa']
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit