This paper analyses the receiver of 40GBASE PCS Sub layer specified by IEEE 802.3ba CSMA/CD standards. Based on the analysis, possible optimization parameters for the receiver FIFO are identified. Proper functionality of the proposed design is verified with simulation results. The optimization of receiver FIFO design may lead to reduce the gate count, area and power consumption in ASIC design.
['A G A N Nanayakkara', 'Subramaniam Thayaparan']
Optimization of receiver FIFO for IEEE 802.3ba 40GBASE PCS Sub layer