In many wire-limited VLSI digital systems the time delay of the longest global interconnect can be a significant percentage of the clock period. However, because semi-global and global wires with shorter wire lengths can have a much smaller time delay, they can remain idle (i.e. not switching) for a significant portion of the clock period even after their data has been transmitted. To capitalize on this phenomenon, this paper proposes that a low-overhead 2-slot Time Division Multiplexing (TDM) network should be incorporated into the multilevel interconnect architectures of future GSI systems to help reduce the escalating manufacturing costs that are primarily due to the projected increase in the number of metal layers. Using system-level interconnect prediction (SLIP) techniques, it is shown that a 20% reduction in the number of metal levels could be achieved for a 100M transistor VLSI system with only a 5-10% increase in power dissipation.
['Ajay Joshi', 'Jeffrey A. Davis']
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)