This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm 2 . From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and HF FOM is 19 fJ/conversion-step.
['Ying-Zu Lin', 'Chih-Hou Tsai', 'Shan-Chih Tsou', 'Chao-Hsin Lu']
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS