High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach
['George Athanasiou', 'Chara I. Chalkou', 'Dimitrios Bardis', 'Harris E. Michail', 'George Theodoridis', 'Costas E. Goutis']
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach