A custom chip set implementing a Single Instruction Multiple Data (SIMD) architecture has been designed bringing the benefits of massively parallel processing to the embedded systems domain. A scaled, rapid prototype was first implemented providing an exact duplicate of the functionality and interfaces of the custom chips, but using off the shelf technology. This scaled version was specified to allow development and debugging of software, and provide early feedback for verification of the interfaces and instruction operations. The rapid prototype provides full functionality, allowing any design errors or beneficial modifications to the design to be identified. >
['D. L. Andrews', 'Andrew Wheeler', 'B. Wealand', 'Cliff Kancler']
Rapid prototype of a hardware emulator for a SIMD processor array