Block matching motion estimation algorithms are useful in many video applications such as the block-based video coding scheme employed in MPEG1/2. A single-chip implementation of a motion estimator (ME) for high quality video compression domains has been the goal of many ongoing research projects. There are several complementary directions along which we can reduce hardware complexity, for example, (1) reduction of search points, and (2) simplification of criterion functions. The last category is what this paper focuses on. We study the algorithmic and architectural potentials of the pixel difference classification (PDC) method and propose a generalisation called multi-level PDC (MPDC). The goal is to examine different hardware-complexity vs performance trade-offs. Moreover, we identify a subset of MPDC, the bit-truncation (BT) method which has the most potential for hardware saving. Experimental results show that it offers attractive trade-offs. Under fixed bit rate constraints, it gives picture quality degradation of less than 0.5 dB, which is non-perceivable, for up to 6-bit truncation. BT results in no complicated data or control flows. Hence the consequent hardware reduction is straightforward. The estimated overall encoder hardware saving ranges from 12% to 35% for 6-bit truncation.
['Yin Chan', 'Sun-Yuan Kung']
Multi-level pixel difference classification methods