Three-dimensional (3-D) chip stacking is considered as the silver bullet technology to preserve Moore’s momentum and fuel the next wave of consumer electronics. However, the benefits of such an integration technology have not yet been explored due to limitations posed mostly by the lack of efficient tools to support application mapping onto these devices. This letter introduces a framework based on a genetic algorithm for netlist partitioning targeting 3-D reconfigurable platforms. Experimental results prove the efficiency of our solution, as we achieve average reduction of the number of utilized through-silicon vias (TSVs) up to 17% for comparable performance metrics against relevant state-of-the-art algorithms.
['Konstantinos Maragos', 'Kostas Siozios', 'Dimitrios Soudris']
An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs