An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13µm CMOS process. The operation frequency range is from 770MHz to 1.05GHz. The locking time of AIPWCL is less than 40ns within the operation frequency band. The power dissipation is 4.38mW at 1.2V voltage supply. The peak-to-peak jitter is less than 1ps at an input clock frequency of 1GHz while adjusting various duty cycles.
['Ro-Min Weng', 'Yun-Chih Lu', 'Chun-Yu Liu']
A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment