This paper presents a complete BIST architecture for FPGA look-up tables. This architecture can detect multiple faults, and can be configured to detect a fault in as few as five LUTs. Unlike an earlier work, our method places the output response analyzer (ORA) within the FPGA.
['Mahnaz Sadoughi Yarandi', 'Armin Alaghi', 'Zainalabedin Navabi']
An optimized BIST architecture for FPGA look-up table testing