This paper develops pipeline architecture of particle swarm optimization with random time-varying inertia weight and acceleration coefficients (PSO-RTVIWAC) based on existing serial architecture. The proposed architecture incorporated two features to reduce calculation error and keep high speed calculation with acceptable chip area cost. First, actual hardware design is simplified. Then the pipeline mechanism is introduced. The developed system is implemented in field programmable gate array (FPGA) and achieves high stability with slightly increased speed.
['Xiao Cai', 'Syahrulanuar Ngah', 'Hui Zhu', 'Yuji Tanabe', 'Takaaki Baba']
Pipeline Architecture of Particle Swarm Optimization