A digital low dropout regulator (D-LDO) manages to operate at low voltage and scale with process. But, the tradeoff between current efficiency and transient response speed limits its applications. In this work, a coarse-fine-tuning technique with burst-mode operation is employed to advance this trade-off. Once the output voltage under/overshoot is detected, the power MOS array changes with x16 unit size at 500 MHz sampling frequency for a fixed time, comparing with x1 size and 50 MHz in steady state. The limit cycle oscillation (LCO) in steady state is reduced by a feed-forward compensation zero with negligible power and area overheads. The proposed D-LDO is simulated in a 65 nm CMOS process, achieving a 60 mV voltage undershoot and 0.36 ps FOM of speed with a 60 μA quiescent current, and mode-1 LCO in steady state.
['Mo Huang', 'Yan Lu', 'Seng-Pan U', 'Rui Paulo Martins']
A digital LDO with transient enhancement and limit cycle oscillation reduction