As a result of the increasing requirements of present and future computation intensive applications, there have been many fundamentally divergent approaches such as the Blue-Gene, TRIPS, HERO, Cascade spurred in order to provide increased performance at node level in supercomputing clusters. The design of the node architecture should be such that 'Cost-Effective Supercomputing' is realized without compromising on the requirements of the ever-performance hungry grand challenge applications. However, to increase performance at the cluster level, scalability and likewise tackling the mapping complexity across the large cluster of nodes becomes critical. The potential of such a node architecture can be fully exploited only with an appropriate cluster architecture. In an attempt to address these issues for efficient and Cost-Effective Supercomputing, we propose a novel paradigm for designing High Performance Clusters, in two papers. In paper-II, we discuss the design of operating system and cluster architecture. In this paper, we present a node architecture model based on the Memory In Processor paradigm and discuss the related architectural aspects (ISA, compiler, network interconnection etc). We provide a design space based on the proposed model for which a simulator is developed, with the help of which the performance of such a node architecture is outlined.
['Nagarajan Venkateswaran', 'Deepak Srinivasan', 'Madhavan Manivannan', 'T. P. Ramnath Sai Sagar', 'Shyamsundar Gopalakrishnan', 'Vinoth Krishnan Elangovan', 'Karthik Chandrasekar', 'Prem Kumar Ramesh', 'Viswanath Venkatesan', 'Arvindakshan Babu', 'Sudharshan']
Future generation supercomputers I: a paradigm for node architecture