A high performance and low power node architecture becomes crucial in the design of future generation supercomputers. In this paper, we present a generic set of cells for designing complex functional units that are capable of executing an algorithm of reasonable size. They are called Algorithm Level Functional Units (ALFUs) and a suitable VLSI design paradigm for them is proposed in this paper. We provide a comparative analysis of many core processors based on ALFUs against ALUs to show the reduced generation of control signals and lesser number of memory accesses, instruction fetches along with increased cache hit rates, resulting in better performance and power consumption. ALFUs have led to the inception of the Super Computer On Chip (SCOC) IP core paradigm for designing high performance and low power supercomputing clusters. The proposed SCOC IP cores are compared with the existing IP cores used in supercomputing clusters to bring out the improved features of the former.
['Venkateswaran Nagarajan', 'Rajagopal Hariharan', 'Vinesh Srinivasan', 'Ram Srivatsa Kannan', 'Prashanth Thinakaran', 'Vigneshwaren Sankaran', 'Bharanidharan Vasudevan', 'Ravindhiran Mukundrajan', 'Nachiappan Chidambaram Nachiappan', 'Aswin Sridharan', 'Karthikeyan Palavedu Saravanan', 'Vignesh Adhinarayanan', 'Vignesh Veppur Sankaranarayanan']
SCOC IP Cores for Custom Built Supercomputing Nodes