This brief presents a technique for compensating the bandwidth variation of digital phase-locked loops (PLLs) arising due to process, voltage and temperature (PVT) variation induced changes in loop parameters. For a digital PLL with a bang-bang phase detector, the bandwidth also depends on the phase noise level present at the input of the phase detector. The presented technique also compensates for the bandwidth variations induced by variations in phase noise power. The compensation technique is verified by a MATLAB model and transistor-level transient noise simulations.
['Archit Joshi', 'Gagan Midha']
Bandwidth Compensation Technique for Digital PLL