An improved CMOS buffer for high-speed ADC testing is presented. It is based on the circuit means to stabilize the dc output voltage of source-follower test buffer through the replica circuit and amplifier in a feedback loop to generate a regulated biasing voltage. With this biasing arrangement, the proposed test buffer maintains high-speed characteristics whilst yet preserving the headroom for test input signal and providing a defined dc output with immunity to variations of process, supply and temperature. In addition, the third-order harmonic distortion of the buffer is analyzed based on a large signal simplified BSIM3 model. The HSPICE simulation results validate the proposed work and correlate well with the distortion analysis on the basis of a standard 0.35 ?m CMOS process at a single 3V supply.
['Xian Ping Fan', 'Pak Kwong Chan']
Improving Source-Follower Buffer for High-Speed ADC Testing