Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include inter-and intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various  RC  structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.
['Xiaoning Qi', 'Alex Gyure', 'Yansheng Luo', 'Sam C. Lo', 'Mahmoud Shahram', 'Kishore Singhal']
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies