In the physical design of VLSI circuits, routing is one of the most important tasks. Usually done towards the end of the design process, especially the detailed routing phase has to obey virtually all design rules. As the feature size become ever smaller, shifts towards gridless design paradigms are necessary and a formerly trivial task, namely pin access, now becomes difficult.   This work presents and discusses gridless pin access. In particular, we show how to create a feasible and efficient gridless routing approach that can be fit into existing gridded routing flows, creating a practical overall routing solution. As a key ingredient, our approach explicitly addresses design rule conform (shortest) paths among geometric obstacles, also taking violations within the paths themselves into consideration. Furthermore, redundancy exploiting structures called circuitclasses are introduced, and based on these, further improvements are described.   We evaluated the approach on current gridless designs and present respective results: the routing performance is improved greatly both with respect to runtime and quality of the results.
['Tim Nieberg']
Gridless pin access in detailed routing