This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first 2/sup k/ vectors cover all adjacent k-bit spaces exhaustively. It requires substantially less hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.
['Prabir Dasgupta', 'Santanu Chattopadhyay', 'Parimal Pal Chaudhuri', 'Indranil Sengupta']
Cellular automata-based recursive pseudoexhaustive test pattern generator