We present a design technique for providing test access to 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The associated optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs.
['Xiaoxia Wu', 'Yibo Chen', 'Krishnendu Chakrabarty', 'Yuan Xie']
Test-Access Solutions for Three-Dimensional SOCs