Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs. We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7/spl times/, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4/spl times/, compared to a traditional network of PLA design. Our approach is quite general, and can be applied to traditional circuits as well.
['Nikhil Jayakumar', 'Rajesh Garg', 'Bruce Gamache', 'Sunil P. Khatri']
A PLA based asynchronous micropipelining approach for subthreshold circuit design