This paper presents an architecture which is equally efficient at computing both the discrete wavelet transform (the DWT) and the inverse discrete wavelet transform (the IDWT). Given the seemingly fundamental difference between the structure of a DWT filter bank and the structure of an IDWT filter bank, it is somewhat surprising that such an architecture can be derived. Our architecture allows the building of a single chip which can efficiently compute both transforms. Tandem use of the architecture (/spl rarr/DWT/spl rarr/IDWT/spl rarr/) is simplified by the fact that the j'th octave is generated by the architecture when it is in DWT mode at the sane rate at which it is consumed by the architecture when it is in IDWT mode.
['Mohan Vishwanath', 'Robert Michael Owens']
A common architecture for the DWT and IDWT