A description is presented of efforts applying mixed-mode simulation techniques to two other areas of research. In incremental simulation, techniques are presented to perform fast incremental circuit simulation based on a modified incremental-in-space approach and event-driven techniques. In fault simulation, a mixed-mode fault simulator is presented that allows the user to specify any type of electrical level fault at the transistor level, as opposed to one of the simple stuck-at faults used in logic simulators. The program performs fault simulation, using mixed-mode techniques, and provides the fault coverage of a set of input patterns. To improve efficiency, concurrent fault simulation with a table look-up scheme is used. The merits of both algorithms are demonstrated with simulation results that show significant speed-ups over standard approaches. >
['Yun-Cheng Ju', 'Fred L. Yang', 'Resve A. Saleh']
Mixed-mode incremental simulation and concurrent fault simulation