A new cyclic Analog-to-Digital conversion algorithm with embedded digital error correction is proposed to reduce the linearity errors caused by the comparator inaccuracy and the offset of the S/H operations. New low-voltage fully-balanced current-mode circuits performing the sample/hold, signal-amplification, and current comparison functions are developed to realize a low-voltage current-mode cyclic Analog-to-Digital converter (ADC). With 1.5 V supply voltage and 0.8 /spl mu/m CMOS device parameters, the HSPICE simulation results show that the designed ADC can achieve 12-bit resolution at 10 k/s conversion rate with the power dissipation of the analog circuits less than 2 mW.
['Chih-Cheng Chen', 'Chung-Yu Wu', 'Jyh-Jer Cho']
A 1.5 V CMOS current-mode cyclic analog-to-digital converter with digital error correction