An advantage of a RLD (Reconfigurable logic device) such as an FPGA (Field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using it in SoC used in embedded systems. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead — data hibernation and reconfiguration time — and SRAM being volatile. In this paper, we describe a chip that we developed — are configurable logic chip based on FeRAM (Ferroelectric random access memory) technology. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, aFF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. Thus, chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18 x 18 logic blocks and an area of 54.76 mm2.
['Masahiro Koga', 'Masahiro Iida', 'Motoki Amagasaki', 'Yoshinobu Ichida', 'Mitsuro Saji', 'Jun Iida', 'Toshinori Sueyoshi']
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells