Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence® Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply.
['Anil Singh', 'Ayushi Goel', 'Alpana Agarwal']
A Digital-Based Low-Power Fully Differential Comparator