This paper presents a design flow for an improved selective multi-threshold (selective-MT) circuit. The selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL (register transfer level) to final layout with optimizing switch transistor structure.
['Takeshi Kitahara', 'Naoyuki Kawabe', 'Fimihiro Minami', 'Katsuhiro Seta', 'Toshiyuki Furusawa']
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction