A 1.5V 10-b 4MS/s pipeline ADC for sensor interfacing is described. Amplifiers are efficiently shared between stages and low-voltage techniques are used to reduce the power supply down to 1.4V. The selected resolution-per-stage greatly simplifies the implementation of a low-power design. Simulated results using a standard digital 0.18 /spl mu/m CMOS technology exhibit 9.5 effective bits at Nyquist-rate. The chip occupies 0.6 mm/sup 2/ and dissipates only 3 mW at maximum conversion-rate.
['Bruno Vaz', 'J. Goes', 'Ramón Piloto', 'J. Neto', 'R. Monteiro', 'Nuno F. Paulino']
A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing