This paper presents a new approach to analysis and design of ADC-based random number generators. To this end, different full-bit and half-bit redundant stages of algorithmic converter are used to design chaotic maps. It is shown that, in the redundant and nonredundant structures, output probability density function of the converter stages and their related chaotic functions always converge to uniformity. It is demonstrated that residues become independent and uniformly distributed. This fact leads to the randomness and uniformity of distribution of the random number generator output bits. Moreover, it is shown that some common chaotic maps that are employed in chaotic random number generators can be implemented using nonredundant and half-bit redundant stages of algorithmic converter. In this way, the capability of ADC-based generators in designing chaotic maps and producing random number sequences is illustrated. The validity of the proposed chaos-based random number generator is confirmed using NIST statistical tests even in the presence of nonidealities in algorithmic converter. Since the ADCs are mixed-signal integrated circuits and can be used in high-speed applications, the ADC-based random number generator has high throughput and is easily embeddable in all analog and digital circuits.
['Esmaeil Fatemi-Behbahani', 'Karim Ansari-Asl', 'Ebrahim Farshidi']
A New Approach to Analysis and Design of Chaos-Based Random Number Generators Using Algorithmic Converter