A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm 2 . A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101 dB and THD is -94 dB.
['Moo-Yeol Choi', 'Sung-No Lee', 'Seung-Bin You', 'Wang-Seup Yeum', 'Ho-Jin Park', 'Jae-Whui Kim', 'Hae-Seung Lee']
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control