In this paper we discuss board test coverage of opens for power pins of large ASICs soldered to electronic boards. Multiple power pin connections cannot be tested by typical electrical testing techniques because they are connected in parallel between the package and the board. We present in this paper an estimate of the probability of these power pin opens, outline the impact of the lack of test coverage in system performance, and offer possible solutions to the problem,.
['Mick Tegethoff', 'Kenneth P. Parker', 'Ken Lee']
Opens board test coverage: when is 99% really 40%?