It is now widely recognised that Built-in Self-Test (BIST) techniques and Design-for-Testability (DfT) will be mandatory to meet test and quality specifications in next generation mixed signal ICs. For evaluating, verifying, and comparing testability improvements, a more detailed understanding of circuit specific failure modes is essential. This paper presents fault simulation results for a 6-bit ADC and identifies typical failure modes the converter is likely to exhibit and hence must be tested for.
['A. Lechner', 'Andrew Richardson', 'B. Hermes']
Towards a better understanding of failure modes and test requirements of ADCs