Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Prior work on GPC synthesis using FPGAs has focused on utilizing the fast carry chain and mapping the logic onto LUTs. This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. Modern day Xilinx FPGAs support 6-input LUTs that can be used in the dual mode for achieving high logic density. In this work we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs reported in literature and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx Virtex-5 FPGAs show a considerable reduction in resources utilized and dynamic power dissipation for almost same critical path delay.
['Burhan Khurshid', 'Roohie Naaz Mir']
High Efficiency Generalized Parallel Counters for Xilinx FPGAs