CMOS bridge faults have very complex behavior and make the testing difficult. This paper proposes a new technique to model all types of bridges as faulty boolean expressions. The modeling is based on analyzing the affected subcircuits using a simplified transistor model. Experiments show that this way of modeling is a good tradeoff of accuracy versus efficiency and allows fast evaluation of test patterns for large circuits. >
['Chennian Di', 'Jochen A. G. Jess']
On CMOS bridge fault modeling and test pattern evaluation