We propose a testable decimal multiplication circuit under the single cell fault model. The multiplier consists of iterative logic arrays of partial product generators and adders. We also give a set of test patterns to detect single faults in the circuit. The number of test patterns is proportional to that of the input digits of the multiplier, which is significantly smaller than the exponential number of test patterns required in non-testable circuits. This efficient testability is achieved only by as light change of the function in the partial product generators and an insertion of some testing inputs in the adders. No additional hardware modules are required in the proposed realization.
['Takashi Hirayama', 'Yasuaki Nishitani', 'Seiji Kitamura']
A Testable Realization for Decimal Multipliers