Previous researchers in logic testing focused on shorts in MOS gate oxides that have zero-resistance. However, most shorts are resistive and may cause delay faults. In this paper, we propose a simple and realistic delay fault model for gate oxide shorts. A reasonably accurate method is proposed to compute delay change due to resistive shorts. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG.
['Xiang Lu', 'Zhuo Li', 'Wangqi Qiu', 'D.M.H. Walker', 'Weiping Shi']
A circuit level fault model for resistive shorts of MOS gate oxide