In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.
['Igor Keller', 'King Ho Tarn', 'Vinod Kariat']
Challenges in gate level modeling for delay and SI at 65nm and below