A novel voltage tripler using 4 clocks with different phases is present in this work. Both the positive and negative polarities of the voltage are generated to serve as the boosted voltage and the back bias voltage. The proposed design is carried out by pass transistors and switched capacitors. The largest generated voltages which the proposed design can provide is +11.09 V and -10.62 V given VDD=3.3 V when the circuit is implemented by TSMC 0.35 /spl mu/m 1P4M CMOS technology.
['Chua-Chin Wang', 'Ya-Hsin Hsueh', 'Ting-Wan Kuo', 'Ron Hu']
A boosted wordline voltage generator for low-voltage memories