This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ−Δ) Modulator to measure and assess its performance. The CT Σ−Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ−Δ modulator hence measuring in real-time and fully assessing the modulator's performance.
['Sevket Cetinsel', 'Richard C. S. Morling', 'Izzet Kale']
An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation