Describes research activities, the goal of which is to develop a methodology that solves the problem of RT (register transfer) level (RTL) testability analysis in a complex way. On the basis of the RTL testability analysis, a substantial reduction in test application time can be achieved. A new model of RTL element classification for the purposes of RTL testability analysis is described. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in a PROLOG environment are presented. The methodology for the RTL testability analysis and the principles of its implementation are described.
['Zdenek Kotasek', 'Frantisek Zboril']
RT level testability analysis to reduce test application time