In this paper, we present a variable node clock network and a power model to estimate leakage power in CMOS processor. Design of clock delivery network is a constrained optimization problem. A variable rate clock network is provided to reduce unwanted switching as well as to limit active clock routing network. We propose two power models to estimate processor performance under variable rate clock signal. Overall this optimization method provides improved in power and performance in current CMOS processor.
['T. Joby Titus', 'V. Vijayakumari', 'B. Saranya', 'V.S. Sanjana Devi']
Power model analysis using variable rate clock network in CMOS processor