Institut TELECOM, TELECOM ParisTech, CNRS LTCIEcole Nationale Sup´erieure des T´el´ecommunicationsD´epartement Communications et Electronique46 rue Barrault, 75634 Paris CEDEX 13, France{lirida.naviner, jean-francois.naviner}@telecom-paristech.frAbstract. This paper deals with digital VLSI design aspects relatedto reliability. The focus is on the problem of reliability evaluation incombinational logic circuits. We present some methods for this evaluationthat can be easily integrated in a tradidional design ﬂow. Also we describesuitable metrics for performance estimation of concurrent error detectionschemes.Keywords. Reliability, fault tolerance, combinational logic.
['Lirida A. B. Naviner', 'Jean-François Naviner', 'Denis Teixeira Franco', 'Maí Correia Vasconcelos']
Methods and Metrics for Reliability Assessment