As a result of our research so far, our placement tool achieved temperature reductions of over 10degC while the adaptive FPGA architectures generate timely responses to bring down temperature by about 14degC. Since routing accounts for a bulk of the power generated, exploiting the temporal and spatial variation in interconnect utilization to minimize their thermal contributions would be an interesting future extension to our work.
['Shilpa Bhoj']
Thermal aware FPGA architectures and CAD