This paper describes the architecture of the transport stream processor system for the digital HDTV receiver with HDD recording capability. The transport stream processor consists of a RISC processor, a content protection circuit, an IDE controller, and a bus interface. The transport stream processor generates the low clock rate partial transport streams by utilizing the bit rate control algorithm with the recording information table and the modulo algorithm. This system realizes a high-speed signal processing of multiple HDTV transport streams for HDD recording and playback for the storage digital broadcasting.
['Masaru Sakurai', 'Hidefumi Nagata', 'Masahiro Yamada', 'Noriya Sakamoto']
A transport stream processor for HDD recording and playback of HDTV signal