This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.
['Dawood Alnajiar', 'Younghun Ko', 'Takashi Imagawa', 'Hiroaki Konoura', 'Masayuki Hiromoto', 'Yukio Mitsuyama', 'Masanori Hashimoto', 'Hiroyuki Ochi', 'Takao Onoye']
Coarse-grained dynamically reconfigurable architecture with flexible reliability