In this paper, the CDM logic style has been analyzed and compared with the Conventional CMOS (C-CMOS) logic style with the FinFET devices in super-threshold operation. Standard cell library with FinFET logic gates in CDM and C-CMOS logic style has been developed in various selected technologies (7nm, 10nm, 14nm, 16nm & 20nm) and used to synthesize the ISCAS'85 benchmark designs to evaluate the performance improvement. Synopsys silicon smart and library compiler tool has been used to generate the standard cell libraries using FinFET device models from PTM and design compiler to synthesize the designs with developed standard cell libraries. The Simulation results shows that CDM based standard cell library achieve the average power improvement of 17-21% and average PDP improvement of 7-26% for all benchmark designs compared with C-CMOS standard cell library in 7nm, 10nm, 14nm, and 16nm & 20nm technology node respectively.
['Ashish Joshi', 'Thejaswani Putta', 'Tooraj Nikoubin']
Power and Energy Efficient Standard Cell Library Design in CDM Logic Style with FinFET Transistors