Odin II is a high-level Verilog Hardware Description Language synthesis tool. This tool is a significant improvement on the original Odin for a number of reasons including Odin II does both front-end parsing and netlist flattening, Odin II interfaces with VPR architecture description of an FPGA to help identify and use available hard circuits, and Odin II can read in netlists from downstream stages in the VPR 5.0 CAD flow into its netlist data-structure. Odin II is open source and is released under the MIT License. Odin II source code, regression benchmarks, and more documentation can be found at http://www.users.muohio.edu/jamiespa/ODIN II/.
['Peter Jamieson', 'Kenneth B. Kent']
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only)