Partial reconfiguration (PR) enhances traditional FPGA-based system-on-chips (SoCs) by providing additional benefits such as reduced area and increased functionality as compared to non-PR SoCs. However, since leveraging these additional benefits requires specific designer expertise and increased development time, PR has not yet gained widespread usage. In this paper, we present an integrated development toolset that automates the implementation of PR SoCs on FPGA devices and leverage this tool in a rapid design space exploration case study.
['Abelardo Jara-Berrocal', 'Ann Gordon-Ross']
An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips