The formal analysis of parallelism and pipelining is performed on an 8-bit add-compare-select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and parallelism are characterized in connection to their corresponding depth and degree, showing clear advantages of pipelining over parallelism.
['Hoang Q. Dao', 'Bart R. Zeydel', 'Vojin G. Oklobdzija']
Architectural considerations for energy efficiency