As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.
['Sungyoul Seo', 'Yong Lee', 'Hyeonchan Lim', 'Joohwan Lee', 'Hongbom Yoo', 'Yojoung Kim', 'Sungho Kang']
Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction