To justify the designs, we demonstrate that each component we design exhibits correct behaviour. Considering as an example the C-element, this amounts to working with an informal specification of the C-element in terms of high/low signals as in Fig. 5, and then showing that our (continuous) CRN empirically satisfies that specification according to appropriate thresholding for high/low signals, as normally done in electronics for transistor logic. To this end, we explore the time evolution of the components under the deterministic and stochastic semantics, including also LNA for scalability. We additionally employ probabilistic model checking with PRISM, where temporal logic is used to express the temporal ordering of events. We remark that, although we validate the components for all possible input configurations, this does not amount to full verification of the correctness of the designs. We discuss the challenges of achieving full verification in Sect. 6.