Next, the cross-linked hybrid (X-ASiO-PVPNP) films were examined as a gate-insulating layer for the transistor structure as illustrated in Fig. 1d. As shown in the output curves (Fig. 4a), all devices exhibited typical p-type transistor characteristics and could be operated at low voltages (−1~−5 V in absolute value). Interestingly, a hysteresis was measured in the output curves for the devices with the X-ASiO-PVPNP layers, which became more pronounced as the content of PVP increased. In addition, the drain current (ID) at the same voltage condition was higher for the devices with the X-ASiO-PVPNP layers (10 mol.% PVP) than those with the pristine X-ASiO layers or the pristine PVP layers. Note that the devices with the pristine PVP layers showed high leakage currents even at zero gate voltage (VG = 0 V). As observed from the transfer curves in Fig. 4b, the current hysteresis between forward and backward sweeps in the devices with the pristine X-ASiO layers was quite small and not improved even by increasing the drain voltage (VD) from −1 V to −5 V. However, the hysteresis became certainly pronounced when 5 mol.% PVP was added. Further addition of PVP (10 mol.%) led to more improved hysteresis in the transfer curves (see Fig. S3 for the gradual hysteresis change with the drain voltage). In addition, the on/off ratio at VD = −5 V was noticeably improved from 1.2 × 103 (0 mol.%) to 1.1 × 104 (5 mol.%) and 4.4 × 105 (10 mol.%) by addition of PVP. The PVP addition contributed to the improved hole mobility from 2.89 × 10−3 (0 mol.%) to 2.28 × 10−2 (5 mol.%) and 1.3 × 10−1 (10 mol.%) (see Fig. S4).