In particular, we have simulated a double gate FET (sketched in Figure 1). Its channel is an armchair graphene ribbon with width W= 3.81 nm (corresponding to 32 dimer lines) and length L variable between 10 nm and 70 nm. The channel is substitutionally doped with randomly located boron atoms, and connects the source and drain contacts. Two 1-nm-thick silicon oxide layers, located above and under the ribbon, separate it from the top gate and the bottom gate. The two gates are kept at the same potential and bias the transport channel. In our simulations, performed at room temperature, we applied a voltage VDS= 0.1 V between the source and the drain, and we computed the current ID flowing through the channel as a function of the voltage VGS applied between the gates and the source. In this way, we obtained the transfer characteristic ID(VGS) of the device.