The input and output ports for the target spin are represented by the first j=1 and last j=N sites of the chain, see Fig. 1a. The inner sites j=2,…, N−1 constitute the gate which may be open (Fig. 1b) or closed (Fig. 1c) for the target spin transfer depending on the absence, , or presence, , of a single control spin excitation. One might think that the shortest possible spin chain to accommodate a gate between the input and output ports would consist of just N=3 spins. As we show in Supplementary Note 1, however, the three-spin chain cannot implement a reusable spin transistor even in the Ising limit >>1 since the control spin excitation at the gate site j=2 is not protected from leakage. We will therefore illustrate the scheme using a chain of N=4 spins, with the gate consisting of spins j=2,3 coupled to each other via the strong exchange constant .