Timing properties of asynchronous circuits Asynchronous circuits can be classified as being self-timed, speed independent or delay-insensitive, depending upon delay assumptions that are made. Assume a circuit is composed of gates and wires. A self-timed circuit operates correctly if both gates and wires experience measurable and fixed delays. A speed independent circuit operates correctly if gates exhibit some unknown time delay within gates but exhibits no time delay on wires. A delay-insensitive circuit operates correctly if there is both unknown delay within gates but also unknown delay within wires. The set of delay insensitive circuits is small, essentially those built from the Muller C-element and NOT gates, and so a broader class of quasi-delay insensitive circuits are identified. Quasi-delay insensitive circuits, which can be composed of purely C-elements, NOT-gates and forks, are Turing complete Manohar and Martin (1996). They are not possible to achieve without an isochronous fork.