Since this system was mechanical, and therefore prone to failure, the 7600 was redesigned into a large "C" shape to allow access to the modules on either side of the cooling piping by walking into the inside of the "C" and opening the cabinet. The 7600 was an architectural landmark, and most of its features are still standard parts of computer design. It is a reduced-instruction-set computer with a 15-bit instruction word containing a 6-bit operation code. There are only 64 machine codes, including a no-operation code, with no fixed-point multiply or divide operations in the central processor. The 7600 has two main core memories. Small core memory holds the instructions currently being executed and the data currently being processed. It has an access time of 10 of the 27.5-ns minor cycles and a 60-bit word length. Large core memory holds data ready to transfer to small core memory. It has an access time of 60 of the 27.5-ns minor cycles and a word length of 480 bits (512 bits with parity). Accesses are fully pipelined and buffered, so the two have the same sequential transfer rate of 60 bits every 27.5 ns. The two work in parallel, so the sequential transfer rate from one to the other is 60 bits per 27.5 ns minor-cycle. On an operating system call, the contents of the small core memory are swapped out and replaced from the large core memory by the operating system, and restored afterward. There is a 12-word instruction pipeline, called instruction word stack in CDC documentation. All addresses in the stack are fetched, without waiting for the instruction field to be processed. Therefore, the fetch of the target instruction of a conditional branch precedes evaluation of the branch condition. During the execution of a 10-word (up to 40 instruction) loop, all the needed instructions remain in the stack, so no instructions are fetched, leaving small core memory free for data transfers. There are eight 60-bit registers, each with an address register. Moving an address to an address register starts a small core memory read or write. Arithmetic and logic instructions have these registers as sources and destinations. The programmer or compiler tries to fetch data in time to be used and store data before more data needs the same register, but if it is not ready, the processor goes into a wait state until it is. It also waits if one of the four floating-point arithmetic units is not ready when requested, but due to pipelining, this does not usually happen.