NAND logic  The NAND Boolean function has the property of functional completeness. This means, any Boolean expression can be re-expressed by an equivalent expression utilizing only NAND operations. For example, the function NOT(x) may be equivalently expressed as NAND(x,x). In the field of digital electronic circuits, this implies that we can implement any Boolean function using just NAND gates. The mathematical proof for this was published by Henry M. Sheffer in 1913 in the "Transactions of the American Mathematical Society" (Sheffer 1913). A similar case applies to the NOR function, and this is referred to as NOR logic. A NAND gate is an inverted AND gate. It has the following truth table:  A NAND gate is a universal gate, meaning that any other gate can be represented as a combination of NAND gates. A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate. An AND gate is made by inverting the output of a NAND gate as shown below. If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output. A NOR gate is an OR gate with an inverted output. Output is high when neither input A nor input B is high. An XOR gate is made by connecting four NAND gates as shown below. This construction entails a propagation delay three times that of a single NAND gate. Alternatively, an XOR gate is made by considering the disjunctive normal form formula_1, noting from de Morgan's Law that a NAND gate is an inverted-input OR gate. This construction uses five gates instead of four. An XNOR gate is made by considering the disjunctive normal form formula_2, noting from de Morgan's Law that a NAND gate is an inverted-input OR gate. This construction entails a propagation delay three times that of a single NAND gate and uses five gates. Alternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction has a propagation delay four times (instead of three times) that of a single NAND gate.