These instructions supported on the 990/12. Type 17 instructions The first word is the opcode; the first part of the second word is the value field and the second part is the register and the third part is the relative offset. These instructions supported on the 990/12. Type 18 instructions The first part of the word is the opcode and the second part is the register specification. These instructions supported on the 990/12. Type 19 instruction The first word is the opcode; the first part of the second word is the destination operand and the second part is the source operand. This instruction supported on the 990/12. Type 20 instructions The first word is the opcode; the first part of the second word is the condition code field, the second part is the destination operand and the third part is the source operand. These instructions supported on the 990/12. Type 21 instruction The first part of the first word is the opcode, the second part of the first word specifies the destination length; the first part of the second word specifies the source length, the second part is the destination operand and the third part is the source operand. This instruction supported on the 990/12. A complete "Hello, world!" program in TI-990 assembler, to run under DX10:  You can try out the above for yourself on a TI-990 simulator. Dave Pitts's sim990 simulates the TI-990 and includes software kits for native operating systems (including DX10). The following program is a standalone version that prints on the serial terminal connected to CRU address 0. It illustrates the CRU I/O and workspace linkage for the PRINT subroutine. The TI-990 processors fell into several natural groups depending on the original design upon which they are based and which I/O bus they used. All models supported the Communications Register Unit (CRU) which is a serial bit addressable I/O bus. Also, supported on higher end models was the TILINE I/O bus which is similar to DEC's popular UNIBUS. The TILINE also supported a master/slave relationship that allowed multiple CPU boards in a common chassis with arbitration control. The following models used the TILINE as their principal mass storage bus:  The following models used the CRU as their principal bus:  Several operating systems were available for the TI-990  From TI:  From third parties: