Binary counters, for example, need a fast carry architecture because they essentially add one to the previous counter value. A solution is using a hybrid counter architecture. A Johnson counter, for example, is a fast non-binary counter. It can be used to count very quickly the low order count; a more conventional binary counter can be used to accumulate the high order count. The fast counter is sometime called a prescaler. The speed of counters fabricated in CMOS-technology is limited by the capacitance between the gate and the channel and by the resistance of the channel and the signal traces. The product of both is the cut-off-frequency. Modern chip technology allows multiple metal layers and therefore coils with a large number of windings to be inserted into the chip. This allows designers to peak the device for a specific frequency, which may lie above the cut-off-frequency of the original transistor. A peaked variant of the Johnson counter is the traveling-wave counter which also achieves sub-cycle resolution. Other methods to achieve sub-cycle resolution include analog-to-digital converters and vernier Johnson counters. In most situations, the user does not want to just capture an arbitrary time that an event occurs, but wants to measure a time interval, the time between a start event and a stop event. That can be done by measuring an arbitrary time both the start and stop events and subtracting. The measurement can be off by two counts. The subtraction can be avoided if the counter is held at zero until the start event, counts during the interval, and then stops counting after the stop event. Coarse counters base on a reference clock with signals generated at a stable frequency formula_1. When the start signal is detected the counter starts counting clock signals and terminates counting after the stop signal is detected. The time interval formula_2 between start and stop is then  with formula_4, the number of counts and formula_5, the period of the reference clock. Since start, stop and clock signal are asynchronous, there is a uniform probability distribution of the start and stop signal-times between two subsequent clock pulses. This detuning of the start and stop signal from the clock pulses is called quantization error. For a series of measurements on the same constant and asynchronous time interval one measures two different numbers of counted clock pulses formula_6 and formula_7 (see picture). These occur with probabilities  with formula_10 the fractional part of formula_11. The value for the time interval is then obtained by  Measuring a time interval using a coarse counter with the averaging method described above is relatively time consuming because of the many repetitions that are needed to determine the probabilities formula_13 and formula_14.