10 nm process  In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm. All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10nm chips in 2018. Since 2009, however, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors. Egyptian-American engineer Mohamed Atalla and Korean-American engineer Dawon Kahng (the original inventors of the MOSFET in 1959) in 1962 demonstrated a device that has a metallic layer with nanometric thickness sandwiched between two semiconducting layers, with the metal forming the base and the semiconductors forming the emitter and collector. They deposited metal layers (the base) on top of single crystal semiconductor substrates (the collector), with the emitter being a crystalline semiconductor piece with a top or a blunt corner pressed against the metallic layer (the point contact). With the low resistance and short transit times in the thin metallic nanolayer base, the devices were capable of high operation frequency compared to bipolar transistors. The device demonstrated by Atalla and Kahng deposited gold (Au) thin films with a thickness of 10 nm on n-type germanium (n-Ge) and the point contact was n-type silicon (n-Si).