We = I + Xilinx (HW+SW developers)
We are interested in the graph mode.
The most common scenario we can imagine it is a model that has been designed and trained; however,  part of it will be executed on a fixed point precision device. This opens a lot of interesting questions.
Please, consider to use us not only as Guinea Piggys but we can help you in giving you test cases, suggestions, and also “me” the worst coder in the west world I will need to figure this out for the purpose to then plug in a specialized partitioner and compiler.
Please, consider to come down (if you are in the Bay Area) and visit Xilinx and see what we can do for you as well.
thank you