Wasn’t aware of that. Thanks! Just checked the main bits and they look pretty similar, only very minor differences like that one reflection pads res blocks instead of cropping the residual connection like mine and the original paper. Also it seems that I forgot to set affine=True on the instancenorm blocks but I’m not convinced either of these things could cause such strange artifacts. I’ll make the changes and run it again in the morning just to make sure. I suppose I should just swap out PIL as well. Trying to wrap by head around how those outliers could even happens with how the optimization is set up is giving me a headache