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"Despite the amount of proposed works for the verification of diverse model properties  understanding the root cause of latency requirements violation in execution traces is still an open-issue especially for complex HW SW system-level designs  is it due to an unfavorable real-time scheduling  to contentions on buses  to the characteristics of functional algorithms or hardware components  This identification is particularly at stake when adding new features in a model  e g   a new security countermeasure  The paper introduces PLAN  a new trace analysis technique whose objective is to classify execution transactions according to their impact on latency  To do so  we rely first on a model transformation that builds up a dependency graph from an allocation model  thus including hardware and software aspects of a system model  Then  from this graph and an execution trace  our analysis can highlight how software or hardware elements contributed to the latency violation  The paper first formalizes the problem before applying our approach to simulation traces of SysML models  A case study defined in the AQUAS European project illustrates the interest of our approach "
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